A method, device and medium for configuring the PCIe bandwidth of a 112G retimer chip

Abstract

The application discloses a PCIe bandwidth configuration method and device of a 112G retimer chip and a medium, relates to the technical field of intelligent integrated circuits, and comprises the following steps: extracting an effective configuration from a PCIe bandwidth configuration basic state according to a verified PCIe bandwidth configuration package and backing up the effective configuration as a fallback configuration; loading a target configuration to perform PCIe link training; collecting a link state and a double-node signal purity code word after switching; performing effectiveness verification; confirming the target configuration when the effectiveness verification is passed; loading the fallback configuration and re-executing the PCIe link training when the effectiveness verification is not passed; and generating a PCIe bandwidth configuration state. The application reduces the risk of link interruption caused by different synchronization and abnormal configurations, and improves switching reliability.

Description

Technical Field

[0001] This invention relates to the field of intelligent integrated circuit technology, and in particular to a PCIe bandwidth configuration method, device and medium for an 112G retimer chip. Background Technology

[0002] As data centers, AI computing platforms, and high-performance servers continue to evolve towards high-speed interconnection, PCIe links are gradually adopting higher transmission rates and wider channel combinations. The 112G retimer chip, as a high-speed signal reshaping device in intelligent integrated circuits, can improve signal attenuation and inter-symbol interference in long-distance transmission through continuous-time linear equalization, decision feedback equalization, clock recovery, and link training. Regarding PCIe link status awareness, channel resource organization, equalization parameter adjustment, and bandwidth configuration management, related technologies have gradually evolved from fixed register configuration to data processing mechanisms that dynamically configure based on link monitoring information.

[0003] Existing PCIe bandwidth configuration technologies mostly rely on preset rates, widths, and equalization control words to directly train links, lacking joint processing of dual-node signal purity, channel locking continuity, and real-time service bandwidth requirements. This easily leads to mismatches between configuration parameters and current link quality. During configuration switching, candidate channel activation, inter-channel latency verification, configuration effectiveness verification, and anomaly rollback are usually separate processes, making it difficult to complete the verification of channels to be activated without interrupting current service transmission. Configuration failures may also cause extended link retraining times and fluctuations in service capacity. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, this invention provides a PCIe bandwidth configuration method for an 112G retimer chip to solve the problems of insufficient PCIe link configuration adaptation and insufficient reliability of configuration switching.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] In a first aspect, the present invention provides a PCIe bandwidth configuration method for a 112G retimer chip, comprising: collecting PCIe link operation information and service transmission information; organizing the link operation information into channels, extracting rate, bandwidth, channel mapping, and locking status to form a link status; monitoring the continuous-time linear equalizer and decision feedback equalizer to obtain dual-node signal purity codewords; statistically analyzing service transmission load and verifying bandwidth occupancy to determine service bandwidth requirements and compiling them into a basic PCIe bandwidth configuration status; based on the basic PCIe bandwidth configuration status, selecting adjustable channels according to the link status; briefly fine-tuning the control parameters of the continuous-time linear equalizer and the decision feedback equalizer; comparing the changes in dual-node signal purity codewords before and after fine-tuning and verifying the locking status to form a channel equalization perturbation sequence; and combining the service bandwidth requirements to perform bandwidth carrying screening to generate candidate channels. PCIe bandwidth configuration package; Based on the candidate PCIe bandwidth configuration package, keep the current channel group running in the link state, start the channel group to be enabled and write the equalization control word, perform candidate channel isolation training and stability maintenance verification, check the lock status, dual-node signal purity codeword and arrival time difference, screen the channel group that meets the bandwidth carrying requirements, and generate a verified PCIe bandwidth configuration package; According to the verified PCIe bandwidth configuration package, extract the effective configuration from the PCIe bandwidth configuration base state and back it up as a fallback configuration, load the target configuration and perform PCIe link training, collect the link state and dual-node signal purity codeword after switching, perform validity verification, confirm the target configuration when the validity verification passes, and load the fallback configuration and re-execute PCIe link training when the validity verification fails, and generate the PCIe bandwidth configuration state.

[0008] As a preferred embodiment of the PCIe bandwidth configuration method for the 112G retimer chip of the present invention, the aggregation of the PCIe bandwidth configuration basic state comprises the following steps:

[0009] The PCIe link operation information is timestamped and the channel affiliation is verified according to the channel mapping and acquisition sequence. The rate, bandwidth and lock status are attached to the corresponding channel. The continuity of each channel is checked and breakpoints are marked to generate the PCIe channel operation sequence.

[0010] Based on the PCIe channel operation sequence, the continuous-time linear equalizer end and the decision feedback equalizer end of the same channel are located. The dual-end sampling time calibration and channel position mapping are performed according to the same acquisition period to obtain the dual-node signal purity codeword. The codewords at both ends are time-series correlated with the lock state of the corresponding channel to generate the dual-node signal purity state.

[0011] The service transmission information is attached to the corresponding transmission period in the PCIe channel operation sequence. The transmission period is divided, the service load is statistically analyzed, and the bandwidth usage is checked. The link carrying capacity is calculated in combination with the rate and width to determine the service bandwidth requirements. At the same time, it is collected with the signal purity status of the two nodes to generate the basic status of PCIe bandwidth configuration.

[0012] As a preferred embodiment of the PCIe bandwidth configuration method for the 112G retimer chip of the present invention, the steps for forming the channel equalization perturbation sequence are as follows:

[0013] Extract the locking status, dual-node signal purity codewords, and bandwidth usage of each channel from the basic PCIe bandwidth configuration status. Perform lock continuity verification and full-load continuous segment identification, filter out channels with lock interruption and continuous full load, and fine-tune the available time period of the remaining channels to form an adjustable channel set.

[0014] For the adjustable channel set, short-term fine-tuning windows are divided, and the link rate and width are frozen to a baseline. The control parameters of the continuous-time linear equalizer and the decision feedback equalizer are changed sequentially in a single-parameter step manner. The dual-node signal purity codewords and locking status before and after each fine-tuning window are collected, and the status before and after fine-tuning is reverted to generate a channel equalization perturbation sequence.

[0015] In a preferred embodiment of the PCIe bandwidth configuration method for the 112G retimer chip described in this invention, the steps for generating candidate PCIe bandwidth configuration packets are as follows:

[0016] The channel equalization perturbation sequence is time-sequentially processed according to the channel identifier and fine-tuning window. The direction and degree of change of the dual-node signal purity codeword are extracted. The codeword change amplitude is normalized. The equalization response gain value is calculated by combining the dual-node codeword improvement and the proportion of locked continuous segments. The control parameter change is associated with the equalization response gain value to form the equalization perturbation response.

[0017] Based on the balanced perturbation response, the control parameters of the codewords that can maintain lock and improve the purity of dual-node signals are screened for stability, collected into the corresponding channels, and combined with the service bandwidth requirements and the factory bandwidth carrying capacity calibration table to perform carrying capacity mapping and configuration item sorting, screening rate, width, channel group and balanced control words, and encapsulating to generate candidate PCIe bandwidth configuration packages.

[0018] As a preferred embodiment of the PCIe bandwidth configuration method for the 112G retimer chip of the present invention, the steps of starting the channel group to be enabled and writing the equalization control word are as follows:

[0019] The configuration fields of the candidate PCIe bandwidth configuration packets are parsed to extract the channel group to be enabled, target rate, target width and equalization control word. The channel affiliation is located according to the channel mapping in the link status, the channel group currently participating in the link transmission is determined, and channel switching preparation information is generated.

[0020] Based on the channel switching preparation information, the current channel group participating in the link transmission is kept running. The service transmission path of the current channel group and the candidate training path of the channel group to be activated are established through the channel selection unit. The clock activation, signal path connection and equalization control word writing are executed sequentially for the channel group to be activated. The service data gating position is used to restrict the channel group to be activated from receiving service data and generate the channel pre-configuration state.

[0021] In the pre-configured channel state, the training sequence generation unit sends the training sequence and idle ordered set to the channel group to be activated along the candidate training path, keeps the current channel group carrying service data along the service transmission path, performs dual-node sampling synchronization and signal arrival time marking on the channel group to be activated, collects the locking status of each channel, dual-node signal purity codeword and signal arrival time, and forms candidate channel training response information.

[0022] In a preferred embodiment of the PCIe bandwidth configuration method for the 112G retimer chip described in this invention, the steps for generating the verified PCIe bandwidth configuration package are as follows:

[0023] Based on the candidate channel training response information, the locking continuity segment is extracted and the codeword change trend is determined. The locking continuity and dual-node signal purity codeword of each channel are checked. The channel delay is sorted according to the signal arrival time. The channel arrival time difference is calculated. Channels with locking interruption, decreased signal purity, and channel arrival time difference that do not meet the synchronization requirements are eliminated to generate a verification channel group.

[0024] The number of channels in the verification channel group is counted, the bandwidth capacity is calculated, and the rate, width, number of channels and bandwidth capacity are compared with the service bandwidth requirements to determine the target channel group that meets the bandwidth capacity requirements. The configuration integrity is checked and the fields are encapsulated for the target rate, target width, target channel group and corresponding load balancer control word to generate a verified PCIe bandwidth configuration package.

[0025] In a preferred embodiment of the PCIe bandwidth configuration method for the 112G retimer chip described in this invention, the steps of loading the target configuration and performing PCIe link training are as follows:

[0026] The configuration fields of the verified PCIe bandwidth configuration package are validated, the target rate, target width, target channel group and equalization control word are extracted, and the channel group currently participating in the link transmission is located according to the basic status of the PCIe bandwidth configuration. The current rate, width, channel group and equalization control word are backed up and the backup consistency is checked, and the rollback configuration is generated.

[0027] Based on the verified PCIe bandwidth configuration package, the target rate, target width and equalization control word are loaded in order and written to the target channel group. Configuration write readback and training status tracking are performed. Channel switching and PCIe link training are performed according to the target channel group to form the configuration switching execution status.

[0028] Based on the configuration switching execution status, the training completion time is aligned and the configuration field is read back according to the channel identifier and training sequence. The rate, width, channel mapping, locking status and dual-node signal purity codeword of the target channel group are collected. The collected content is summarized and time-series linked according to the corresponding channel to generate configuration switching response information.

[0029] In a preferred embodiment of the PCIe bandwidth configuration method for the 112G retimer chip of the present invention, the steps for generating the PCIe bandwidth configuration state are as follows:

[0030] The configuration switching response information is compared with the verified PCIe bandwidth configuration package to check the consistency of configuration fields, the negotiation between the target rate and the target width is checked, the target channel group is checked for locked continuous segments and dual-node codeword stability, and the service bandwidth adaptation is determined in combination with the actual bandwidth capacity and service bandwidth requirements to generate the configuration validity verification status.

[0031] When the configuration validity verification status meets the target configuration requirements, the target configuration is confirmed to be effective and the configuration status is solidified. When the configuration validity verification status does not meet the target configuration requirements, the fallback configuration is written, the link is retrained, and the fallback status is verified. The final effective rate, bandwidth, channel group, equalization control word, and lock status are collected to generate the PCIe bandwidth configuration status.

[0032] In a second aspect, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program, wherein: when the computer program is executed by the processor, it implements any step of the PCIe bandwidth configuration method for the 112Gretimer chip as described in the first aspect of the present invention.

[0033] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, it implements any step of the PCIe bandwidth configuration method for the 112G retimer chip as described in the first aspect of the present invention.

[0034] The beneficial effects of this invention are as follows: By monitoring dual-node codewords, equalizing perturbations, and filtering gains, channel signal response identification is achieved, which is used for balanced configuration adaptation of intelligent integrated circuits, reducing link mismatch caused by fixed parameters, and improving configuration accuracy and channel utilization. By pre-training the channel to be used, checking the time difference, filtering bandwidth, and backing up to failure, configuration is verified before switching, which is used to maintain continuous service transmission, reduce the risk of link interruption caused by asynchrony and abnormal configuration, and improve switching reliability. Attached Figure Description

[0035] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A flowchart illustrating the PCIe bandwidth configuration method for a 112G retimer chip.

[0037] Figure 2 The graph shows the changes in codeword purity of the dual-node signal under different fine-tuning rounds.

[0038] Figure 3 The relationship between the equalization response gain value and the codeword of the average signal purity of the two nodes after switching is shown in the figure.

[0039] Figure 4 This is a comparison chart of the overall performance indicators of the baseline group and the complete solution group. Detailed Implementation

[0040] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0041] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0042] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0043] Reference Figures 1-4 As one embodiment of the present invention, this embodiment provides a PCIe bandwidth configuration method for a 112G retimer chip, including the following steps:

[0044] S1: Collect PCIe link operation information and service transmission information, organize the link operation information into channels, extract the rate, bandwidth, channel mapping and locking status to form the link status, monitor the continuous time linear equalizer end and the decision feedback equalizer end, obtain the dual-node signal purity codeword, and count the service transmission load and check the bandwidth usage to determine the service bandwidth requirements and collect them into the basic status of PCIe bandwidth configuration.

[0045] S1.1: According to the channel mapping and acquisition timing, the PCIe link operation information is timestamped and the channel ownership is verified. The rate, bandwidth and lock status are attached to the corresponding channel. The continuous operation of each channel is checked for continuity and breakpoints are marked to generate the PCIe channel operation sequence.

[0046] Furthermore, the timestamps, channel identifiers, and channel mapping relationships in the PCIe link operation information are uniformly organized. Independent data receiving positions are established using the channel identifier as an index, and operation records belonging to the same channel and with similar acquisition times are arranged on the same timeline. For records with different acquisition frequencies or timestamp offsets, the time position is corrected using adjacent valid sampling times as references. Duplicate reports are eliminated, and records that cannot be matched with the channel mapping relationship are marked as having abnormal attribution. Time alignment is completed, and the rate, width, and lock status formed at each acquisition time are written to the corresponding channel position, giving each operation record a clear channel attribution and timing position.

[0047] Following the operational trajectory of each channel, the time intervals and status continuity between adjacent records are examined from earliest to latest according to the acquisition time. This identifies operational interruptions caused by missing acquisitions, channel unlocking, rate switching, and width changes. Records with stable states and continuous time continuity are grouped into continuous operational segments. Breakpoints are marked at locations where the time intervals exceed the normal acquisition range or where the states before and after cannot be directly connected, preserving the channel states and occurrence times on both sides of the breakpoint. Continuous operational segments and breakpoint locations are summarized according to channel number to form a PCIe channel operational sequence reflecting the operational order, status continuity, and interruption boundaries of each channel.

[0048] S1.2: Based on the PCIe channel operation sequence, locate the continuous-time linear equalizer end and the decision feedback equalizer end of the same channel, perform dual-end sampling time calibration and channel position mapping according to the same acquisition period, obtain the dual-node signal purity codeword, and time-correlate the codewords at both ends with the lock state of the corresponding channel to generate the dual-node signal purity state.

[0049] Furthermore, based on the channel identifier and continuous running segments in the PCIe channel operation sequence, the sampling positions corresponding to the continuous-time linear equalizer and the decision feedback equalizer are located respectively, and node pairing relationships are established for dual-end sampling records belonging to the same channel. The sampling range is limited by the start and end times of the continuous running segments, and the dual-end sampling times are corrected according to a unified acquisition period. Records with similar time positions are grouped into the same sampling period, and records falling on both sides of the breakpoint, with inconsistent channel affiliation, or with deviations in sampling time are separated and marked. After completing the dual-end time calibration, the sampling positions of the continuous-time linear equalizer and the decision feedback equalizer are mapped to the corresponding channels, and the dual-end signal purity codewords within each sampling period are obtained.

[0050] Organize the dual-end signal purity codewords of the same channel from morning to night according to the sampling period. Link the codewords from the continuous-time linear equalizer end to the codewords from the decision feedback equalizer end to the same time position, and verify the lock status corresponding to that time position. Continuously merge time periods where the dual-end codewords are fully sampled and the channel remains locked. Set state boundaries for positions with missing codewords, where dual-end timing cannot be inherited, or where the lock status changes, to avoid establishing associations across different operating stages. Using the channel identifier as the collection unit, retain the time order, node source, lock inheritance status, and state boundaries of the dual-end codewords to form a dual-node signal purity status.

[0051] It should be noted that the signal purity codeword is a dimensionless state value formed by the internal signal monitoring unit of the chip through quantization encoding of the signal stability, noise disturbance level, and decision reliability during the sampling period. It is used to characterize the signal quality of the corresponding node. A larger codeword value indicates higher signal purity, while a decrease in codeword value indicates increased signal attenuation, interference, and decision fluctuations. The continuous-time linear equalizer and decision feedback equalizer respectively generate corresponding codewords, which are then linked to the sampling time, channel identifier, and lock status for subsequent equalization fine-tuning response comparison and control parameter selection.

[0052] S1.3: Connect the service transmission information to the corresponding transmission period in the PCIe channel operation sequence, perform transmission period division, service load statistics and bandwidth usage verification, and calculate the link carrying capacity in combination with rate and width to determine the service bandwidth requirements. At the same time, collect the signal purity status of the two nodes to generate the basic status of PCIe bandwidth configuration.

[0053] Furthermore, using consecutive segments within the PCIe channel's operational sequence as the time frame, service transmission information is linked to the corresponding channel and transmission location according to the time of occurrence, excluding transmission records that fall outside operational breakpoints or have inconsistent channel affiliations. The continuity of service transmission is examined along the acquisition time sequence, dividing transmission periods into segments based on service start, transmission pause, and load change locations, grouping records that are temporally continuous and have stable transmission states into the same segment. The actual transmission volume and duration are compiled around each transmission segment, identifying transmission processes with continuously increasing load, stable occupancy, and short-term surges, forming a set of service transmission segments that maintain temporal continuity with the PCIe channel's operational sequence.

[0054] The service load for each time period is statistically analyzed based on the service transmission time period set. The actual bandwidth occupied is then linked to the corresponding channel to verify the connection between changes in bandwidth occupation and the channel's operational status. Based on the rate, bandwidth, and effective operating channels within the corresponding time period, the link's capacity bandwidth is determined. The service load is compared with the capacity bandwidth to determine the service bandwidth requirements needed to maintain current service transmission. Using the channel identifier and transmission time period as a common index, the service bandwidth requirements are linked back to the dual-node signal purity status, ensuring that link operation, signal purity, and service bandwidth requirements are reflected simultaneously at the same time point, thus generating the basic PCIe bandwidth configuration status.

[0055] S2: Based on the basic state of PCIe bandwidth configuration, select adjustable channels according to link status, make short-term fine adjustments to the control parameters of the continuous-time linear equalizer and the decision feedback equalizer, compare the changes in the codeword purity of the dual-node signal before and after fine adjustment and check the lock status, form a channel equalization perturbation sequence, and perform bandwidth carrying screening in combination with service bandwidth requirements to generate candidate PCIe bandwidth configuration packages.

[0056] S2.1: Extract the locking status, dual-node signal purity codewords, and bandwidth usage of each channel from the PCIe bandwidth configuration basic status, perform lock continuity verification and full-load continuous segment identification, filter out channels with lock interruption and continuous full load, and fine-tune the available time period of the remaining channels to form an adjustable channel set.

[0057] Furthermore, using the channel identifier in the PCIe bandwidth configuration basic status as an index, the locking status, dual-node signal purity codeword, and bandwidth occupancy of each channel are linked to a unified time axis, and the continuity between adjacent states is checked according to the acquisition time. Locked segments are merged around the time range in which the locked state remains unchanged, and lock interruption boundaries are defined for the unlocking marker, repeated switching of the locked state, and the location corresponding to the acquisition breakpoint. The time range in which the bandwidth occupancy changes continuously approaches the link capacity limit is identified along the bandwidth occupancy change trajectory, separating short-term load increases from continuous full-load processes, and marking the full-load continuous segment of each channel.

[0058] The channel runtime periods are filtered based on lockout interruption boundaries and continuous full-load segments, eliminating channels that cannot maintain stable lockout and those with insufficient margin for parameter fine-tuning under continuous full load. The sampling integrity and timing continuity of the dual-node signal purity codewords are checked for the remaining channels, and the time range where lockout is stable, load does not reach continuous full load, and dual-end codewords can be continuously acquired is retained as candidate fine-tuning periods. The start and end positions of the candidate fine-tuning periods are marked, excluding boundary ranges near lockout switching, sudden traffic surges, and runtime breakpoints, and the corresponding channels and available time periods are grouped into an adjustable channel set.

[0059] It should be noted that the time range, for example: the stable locking time range can be set to 20-100 milliseconds continuously; the full-load continuous segment can be set to a bandwidth utilization rate of over 90% for 10-50 milliseconds; the candidate fine-tuning period can be set to 5-20 milliseconds, and should maintain an interval of 2-5 milliseconds from the lock switching, service surge, and operation breakpoint boundaries; it should be calibrated according to the link status sampling period, the effective delay of the equalization control parameters, the channel lock recovery time, and the duration of service bursts, and determined on the premise of ensuring that codeword changes can be observed without affecting normal service transmission.

[0060] S2.2: Divide the adjustable channel set into short-term fine-tuning windows, freeze the link rate and width at the baseline, change the control parameters of the continuous-time linear equalizer and the decision feedback equalizer in a single-parameter stepping manner, collect the dual-node signal purity codewords and locking status before and after each fine-tuning window, and revert the status before and after fine-tuning to generate a channel equalization perturbation sequence.

[0061] Furthermore, within the available time periods of the adjustable channel set, independent short-term fine-tuning windows are defined according to channel identifiers, with the start and end positions of these windows avoiding sudden increases in service load, lockout transitions, and operational interruptions. Upon entering a fine-tuning window, the current link rate and bandwidth are fixed, and the continuous-time linear equalizer control parameters, decision feedback equalizer control parameters, and dual-node signal purity codewords are recorded as fine-tuning benchmarks. Keeping the decision feedback equalizer control parameters unchanged, the continuous-time linear equalizer control parameters are changed sequentially at adjacent control levels. After each change, a brief response period is retained, and the corresponding dual-node signal purity codeword and lockout status are collected. Finally, the parameters are restored to the fine-tuning benchmark.

[0062] Complete the step acquisition of the continuous-time linear equalizer control parameters, keeping their reference values ​​unchanged. Sequentially change the decision feedback equalizer control parameters using the same method, ensuring that only one control parameter changes within each fine-tuning window. Organize the fine-tuning process according to the parameter writing time, response acquisition time, and recovery time. Associate the dual-node signal purity codewords and lock status before and after fine-tuning with the corresponding channels and parameter levels. Mark fine-tuning records with lock interruptions, missing samples, or window out-of-bounds errors as invalid. Collect valid records according to the fine-tuning execution order, retaining the direction and order of control parameter changes and corresponding signal responses to generate a channel equalization perturbation sequence.

[0063] It should be noted that the continuous-time linear equalizer is used to continuously compensate for high-frequency attenuation in the received signal. By adjusting the gain and frequency response, it reduces inter-symbol interference caused by channel loss and provides a more stable input for subsequent signal decision.

[0064] The decision feedback equalizer compensates for the current signal based on the historical symbols that have been decided. By adjusting the coefficients of each tap, it cancels out residual inter-symbol interference and improves the decision accuracy and signal purity at the receiver.

[0065] S2.3: The channel equalization perturbation sequence is time-sequentially processed according to the channel identifier and fine-tuning window. The direction and degree of change of the dual-node signal purity codeword are extracted. The codeword change amplitude is normalized. The equalization response gain value is calculated by combining the improvement of the dual-node codeword and the proportion of locked continuous segments. The control parameter change is associated with the equalization response gain value to form the equalization perturbation response.

[0066] Furthermore, using the channel identifier as the aggregation index, the fine-tuning records belonging to the same channel in the channel equalization perturbation sequence are arranged according to the window start time, and the parameter writing, response acquisition, and parameter recovery order of adjacent records are checked. The dual-node signal purity codeword formed before fine-tuning is used as the comparison benchmark for the corresponding window. The codeword offsets at the continuous-time linear equalizer end and the decision feedback equalizer end during parameter changes are extracted separately, and the improvement, descent, and maintenance directions are marked according to the offset sign. The codeword offset is normalized using the variable range of each node's codeword, and the equalization response gain value is calculated by combining the jointly improved portion at both ends with the proportion of the locked continuous segment to the response time period.

[0067] The lockout status is checked for changes during the response period corresponding to each parameter change. Records of unlocking, repeated locking switching, and disconnection of status acquisition are marked as invalid perturbations. Effective control parameter changes are linked to the corresponding equalization response gain value according to parameter type, direction of change, and control level, preserving the dual-node response direction and lockout relationship. The control parameter changes, signal responses, and equalization response gain values ​​of each channel are summarized according to the execution order of the fine-tuning window to form the equalization perturbation response.

[0068] The formula for calculating the equalization response gain is: ;

[0069] in, Indicates the first The first channel in the The equalization response gain value within each fine-tuning window, index Indicates the channel number, subscript Indicates the fine-tuning window number. Indicates the first The first channel in the The amount of normalized codeword improvement at the continuous-time linear equalizer end within a fine-tuning window. Indicates the first The first channel in the The amount of normalized codeword improvement at the decision feedback equalizer end within a fine-tuning window. Indicates the first The first channel in the Within each fine-tuning window, the proportion of a continuous segment to the corresponding response time period is locked. This represents the smallest positive number that prevents the denominator from being zero.

[0070] It should be noted that the formula collaboratively aggregates the normalized codeword improvements of the two sampling nodes. A higher equalization response gain value is only formed when both the continuous-time linear equalizer and the decision feedback equalizer show positive improvements, thus preventing the improvement of one node from masking the decline of the other. Harmonic aggregation can highlight the weaker part of the improvement in the two nodes, limiting the gain value when the difference in improvement between the two ends widens. Furthermore, the aggregation result is corrected by the proportion of locked continuous segments, so that fine-tuning records with significant codeword improvement but discontinuous locking process receive lower gains, comprehensively reflecting the degree of signal improvement and link operation stability.

[0071] The normalized codeword improvement in the formula is formed based on the difference between the codewords before and after fine-tuning and the range of variation of the corresponding node codewords. It is used to eliminate differences in node range and initial level. Negative changes and no improvement states are aggregated as zero values. The proportion of locked continuous segments is formed based on the duration of continuous locking and the total duration of the response period, and is multiplied by the aggregated result of the two-node improvement. The minimum positive number is set according to the calculation accuracy and written into the aggregation denominator to avoid invalid calculations when neither node is improved.

[0072] Figure 2Using the number of fine-tuning rounds as the horizontal axis and the normalized signal purity codeword as the vertical axis, the codeword changes at the continuous-time linear equalizer and decision feedback equalizer ends are compared between the baseline group and the complete solution group. The baseline group, using fixed equalization control parameters, shows relatively small overall changes in the dual-node signal purity codeword, indicating that a fixed configuration is difficult to continuously adapt to different channel states. The complete solution group, performing single-parameter step fine-tuning based on an adjustable channel set, shows that the dual-node signal purity codeword gradually increases during the fine-tuning process and remains relatively stable in subsequent rounds. This change demonstrates that the channel equalization perturbation sequence can reflect the actual impact of the continuous-time linear equalizer control parameters and the decision feedback equalizer control parameters on the signal states of different nodes. The equalization response gain value screening can retain control parameters that are collaboratively improved by both nodes and have continuous locked states, thereby reducing link mismatch caused by fixed parameters and improving the equalization configuration adaptation accuracy and channel signal stability.

[0073] Reference group—continuous-time linear equalizer end: This indicates the change in signal purity codewords generated by the continuous-time linear equalizer end when using fixed equalization control parameters.

[0074] Reference group—Decision feedback equalizer end: This indicates the change in signal purity codewords generated at the decision feedback equalizer end when using fixed equalization control parameters.

[0075] Complete Solution Group - Continuous Time Linear Equalizer End: This indicates the change in signal purity codewords at the continuous time linear equalizer end after performing adjustable channel filtering, single-parameter step fine-tuning, and equalization response gain value filtering.

[0076] Complete Solution Group - Decision Feedback Equalizer End: This indicates the change in signal purity codewords at the decision feedback equalizer end after performing adjustable channel filtering, single-parameter step fine-tuning, and equalization response gain value filtering.

[0077] S2.4: Based on the balanced perturbation response, the control parameters of the codewords that can maintain lock and improve the purity of dual-node signals are stable and screened, collected into the corresponding channels, and combined with the service bandwidth requirements and the factory bandwidth carrying capacity calibration table, the carrying capacity is mapped and the configuration items are sorted. The rate, width, channel group and balanced control word are screened and encapsulated to generate candidate PCIe bandwidth configuration packages.

[0078] Furthermore, using the channel identifier in the equalization perturbation response as an index, the perturbation records for each iteration are organized according to the control parameter type and change level. The lock-in continuity status and the changes in the dual-node signal purity codewords during parameter changes are checked. Parameters that experience lock-in interruption, synchronous decrease in dual-node codewords, or repeated changes in the response direction of adjacent fine-tuning windows are removed. Parameters with continuously locked channels and improving dual-node codewords are retained. The response continuity relationship between consecutive levels is checked around the retained parameters. Records that show improvement only in a single sampling and whose improvement cannot be maintained after parameter recovery are filtered out. Control parameters with stable response directions and continuous degree of change are aggregated into the corresponding channels to form effective equalization parameter entries.

[0079] Using service bandwidth requirements as the lower limit, the system locates rate and bandwidth combinations that can cover these requirements from the factory bandwidth capacity calibration table. Each combination is mapped to a channel with valid balancing parameter entries. Configuration entries are sorted according to channel locking stability, dual-node codeword improvement, and bandwidth capacity margin. The sorted entries are then checked for channel quantity, channel mapping relationships, and the completeness of the balancing control word. Configurations with insufficient capacity or missing control words are removed, retaining those that form complete channel groups. The corresponding rate, bandwidth, channel group, and balancing control word are written into a unified configuration structure, with configuration order and channel affiliation tags added, and encapsulated to generate candidate PCIe bandwidth configuration packages.

[0080] S3: Based on the candidate PCIe bandwidth configuration package, keep the current channel group running in the link state, start the channel group to be enabled and write the equalization control word, perform candidate channel isolation training and stability maintenance verification, check the lock status, dual-node signal purity codeword and arrival time difference, filter the channel group that meets the bandwidth carrying requirements, and generate the verified PCIe bandwidth configuration package.

[0081] S3.1: Parse the configuration fields of the candidate PCIe bandwidth configuration packet, extract the channel group to be enabled, target rate, target width and equalization control word, and locate the channel affiliation according to the channel mapping in the link status, determine the channel group currently participating in the link transmission, and generate channel switching preparation information.

[0082] Furthermore, the configuration structure in the candidate PCIe bandwidth configuration package is parsed layer by layer. The channel group identifier and leveling control field are identified according to the encapsulation order of the configuration entries, and entries that form complete configuration relationships are retained in their corresponding configuration locations. Channel members are expanded around the channel group identifier, and each channel is checked for clearly defined rate, bandwidth, and leveling control word affiliation. Configuration entries with missing fields, duplicate channels, or conflicting mapping relationships are eliminated. The parsed candidate channels are then associated with the target transmission parameters and organized into channels to be enabled according to the channel identifier, retaining the enabling order and control word writing location of each channel in the candidate configuration.

[0083] Based on the channel mapping in the link status, locate the channels already participating in link transmission along the current valid transmission path, and verify the channel identifiers against the channels to be activated group item by item. Channels existing in both are marked as continuously running channels, while channels belonging only to candidate configurations are marked as newly activated channels, avoiding misclassification of channels currently carrying services as pending activation. Verify channel affiliation according to physical location and logical mapping relationship to confirm the channel group currently participating in link transmission. Aggregate the current channel group, channels to be activated, target rate, target bandwidth, equalization control word, and corresponding write locations in switching order to generate channel switching preparation information.

[0084] It should be noted that the equalization control word is a configuration field formed by encoding the gain level of the continuous-time linear equalizer, the tap coefficients of the decision feedback equalizer, and related compensation parameters. It is used to write to the corresponding channel and control the signal equalization state.

[0085] S3.2: Based on the channel switching preparation information, keep the channel group currently participating in the link transmission running, establish the service transmission path of the current channel group and the candidate training path of the channel group to be enabled through the channel selection unit, and sequentially perform clock enable, signal path connection and equalization control word writing for the channel group to be enabled, and restrict the channel group to be enabled from receiving service data through the service data gating position, and generate the channel pre-configuration state.

[0086] Furthermore, taking the current channel group and the channel group to be activated in the channel switching preparation information as objects, service transmission paths, candidate training paths, and channel selection units are configured between the link management controller and each channel. The service data gating position corresponding to the current channel group is kept in an open state, and the training sequence input position is kept in a closed state, so that the current channel group continues to carry service data along the original service transmission path; the service data gating position corresponding to the channel group to be activated is set to a closed state, and the training sequence input position is set to an open state, so that the channel group to be activated is isolated from the current service transmission path and only accesses the candidate training path.

[0087] The startup sequence is arranged according to the physical location, logical mapping relationship, and shared clock relationship of the channels to be activated. First, the clock of the corresponding channel is activated, then the signal path between the channel to be activated and the candidate training path is connected, and the equalization control word is written to the corresponding channel configuration position. After each control word is written, the configuration position is read back according to the channel identifier, and the read-back content is checked against the equalization control word in the channel switching preparation information item by item. Positions with incomplete writing or inconsistent channel affiliation are rewritten. The service gating status of the current channel group, the training gating status of the channel group to be activated, the path isolation status, the clock status, the signal path status, and the control word verification status are collected to generate the channel pre-configuration status.

[0088] S3.3: In the pre-configured channel state, the training sequence generation unit sends the training sequence and idle ordered set to the channel group to be enabled along the candidate training path, keeps the current channel group carrying service data along the service transmission path, performs dual-node sampling synchronization and signal arrival time marking on the channel group to be enabled, collects the locking status of each channel, dual-node signal purity codeword and signal arrival time, and forms candidate channel training response information.

[0089] Furthermore, based on the path isolation and gating states in the pre-configured channel state as training prerequisites, it is checked that the service data gating position of the current channel group remains open, the service data gating position of the channel group to be activated remains closed, and it is confirmed that the training sequence input position of the channel group to be activated has been connected to the candidate training path. A training sequence sending window and an idle ordered set sending window are divided around the channel group to be activated. The training sequence generation unit continuously injects training sequences into the corresponding channel within the training sequence sending window and injects idle ordered sets within the idle ordered set sending window. The training content does not enter the current channel group or the service data interface.

[0090] Synchronous sampling is initiated at the continuous-time linear equalizer and decision feedback equalizer according to the training sequence transmission time window. The first valid response time of the training sequence at the two sampling nodes is marked, and the lock establishment, lock holding, and changes in the dual-node signal purity codeword are recorded along the sampling time sequence. Anomaly markers are set for locations with missing sampling, lock interruption, training content crossing candidate training paths, and changes in service data gating status, maintaining isolation between abnormal channels and service transmission paths. The training time window, gating status, lock status, dual-node signal purity codeword, and signal arrival time are collected according to the channel identifier to form candidate channel training response information.

[0091] S3.4: Based on the candidate channel training response information, extract the lock-on continuous segment and determine the codeword change trend. Verify the lock-on continuity and dual-node signal purity codeword of each channel. Sort the inter-channel delay according to the signal arrival time, calculate the channel arrival time difference, and remove channels with lock-on interruption, decreased signal purity, and channel arrival time difference that does not meet the synchronization requirements to generate a verification channel group.

[0092] Furthermore, using the channel identifier in the candidate channel training response information as an index, the response records within the training sequence transmission window and the idle ordered set transmission window are arranged on a unified time axis. The lock establishment time is located along the lock state change trajectory, and records that continuously maintain lock without sampling breakpoints are grouped into lock duration segments, marking the locations of unlocking and repeated lock switching. Dual-node signal purity codewords are organized around the lock duration segments, and codeword changes during the training start, lock establishment, and idle holding phases are compared to eliminate short-term offsets caused by single-point jumps, determining codeword stability, improvement, and downward trends, thus forming channel lock and codeword verification records.

[0093] The channels are arranged from earliest to latest according to their signal arrival times. The earliest arrival time is used as the starting point for time delay comparison, and the arrival time difference of other channels relative to the earliest arriving channel is calculated. The channel arrival time difference is checked against the channel synchronization allowable range, and channels that exceed the synchronization requirements are marked. Based on the channel locking and codeword verification records, channels with incomplete locking persistence segments, continuously decreasing dual-node signal purity codewords, and channel arrival time differences exceeding the channel synchronization allowable range are removed. Channels with continuous locking, stable codewords, and arrival time sequences that can be synchronously accepted are retained, and they are re-merged according to the channel mapping relationship to generate a verification channel group.

[0094] It should be noted that the allowable range for channel synchronization (example range 50-500 picoseconds) is determined based on the link unit interval, board-level trace delay difference, clock recovery tracking capability, and channel alignment buffer depth.

[0095] The formula for calculating the time difference of arrival of a channel is: ;

[0096] in, Indicates the first The arrival time difference of each channel after dual-node difference compensation Indicates the first The arrival times of the signals at the continuous-time linear equalizer for each channel. Indicates the first The arrival time of the signal at the decision feedback equalizer of each channel. This represents the channel number that is traversed in the candidate channel set. This represents the set of candidate channels participating in the delay sorting. This represents the dual-node delay compensation coefficient, used to adjust the impact of the arrival deviation between two sampling nodes in the same channel on the channel's arrival time difference. This means taking the minimum value from multiple candidate values.

[0097] It should be noted that the dual-node delay compensation coefficient (example range: 0.1 to 0.5) is specifically calibrated based on the dual-node sampling clock deviation, board-level propagation path differences, clock recovery stability, and channel synchronization calibration results.

[0098] The formula averages the signal arrival times of the same channel at two sampling nodes to reduce the impact of single-node sampling offset on inter-channel delay comparison. It then uses the earliest average arrival time among candidate channels as a unified comparison benchmark to obtain the propagation offset of the current channel relative to the earliest channel. The formula also includes a dual-node arrival time difference compensation term to reflect the intra-node propagation difference between the continuous-time linear equalizer and the decision feedback equalizer, ensuring that the channel arrival time difference simultaneously reflects both inter-channel synchronization offset and the degree of asynchrony between dual nodes within a channel, thus improving the accuracy of channel synchronization selection.

[0099] The candidate channel set in the formula consists of channels that have completed the acquisition of arrival times of both nodes and remain locked, which is used to limit the search range of the earliest average arrival time; the channel traversal number is assigned sequentially according to the channel identifier in the candidate channel set, which is used to compare the average arrival times of both nodes one by one; the dual-node delay compensation coefficient is calibrated based on the dual-node sampling clock deviation, board-level propagation path difference and synchronization calibration record.

[0100] S3.5: Perform channel number statistics on the verification channel group, calculate the bandwidth capacity, verify the rate, width, number of channels and bandwidth capacity against the service bandwidth requirements, determine the target channel group that meets the bandwidth capacity requirements, and perform configuration integrity checks and field encapsulation on the target rate, target width, target channel group and corresponding load balancer control word to generate a verified PCIe bandwidth configuration package.

[0101] Furthermore, based on verifying the channel mapping relationship in the channel group, the system checks whether adjacent channels can form a continuous transmission combination according to the channel identifier. Channels with stable locking and satisfactory synchronization are assigned to the same bearer node, and the number of effective channels in each bearer node is counted. Based on the rate and width corresponding to the candidate PCIe bandwidth configuration packets, the effective transmission capacity of a single channel is extended to all effective channels. After deducting the portion occupied by training, maintenance, and protocol transmission, the bandwidth capacity of each bearer node is calculated. Using the service bandwidth requirement as the benchmark for bandwidth capacity requirements, the bandwidth capacity of each bearer node is compared with the service bandwidth requirement. Channel combinations with bandwidth capacity lower than the service bandwidth requirement are eliminated. Channel combinations whose bandwidth capacity can cover the service bandwidth requirement are determined as candidate combinations that meet the bandwidth capacity requirements. The target channel group is then determined according to the minimum number of channels and bandwidth margin required to meet the service bandwidth requirements.

[0102] For the target channel group that meets the bandwidth requirements, check the correspondence between the number of channel members and the target width, verify whether the target rate falls within the verified operating range of each channel, and reattach the load balancing control word to the corresponding channel position. Mark incomplete channels, misaligned control words, and incompatible configuration fields with incomplete flags, and replenish the verified channel group with stable locking, synchronization requirements, and the ability to maintain bandwidth requirements. When the configuration is complete and the recalculated bandwidth capacity still covers the service bandwidth demand, organize the fields according to the writing order of rate configuration, width configuration, channel mapping, and load balancing control, write the configuration version and verification flag, and encapsulate to generate a verified PCIe bandwidth configuration package.

[0103] It should be noted that the bandwidth capacity requirement refers to the actual bandwidth capacity of the channel combination after deducting the bandwidth occupied by training, maintenance, and protocol transmission, which is sufficient to cover the current service bandwidth demand. This is used to determine whether a channel group has the ability to continuously carry service data and serves as the basis for selecting target channel groups.

[0104] The formula for calculating bandwidth capacity is: ;

[0105] in, This represents the bandwidth capacity of any given node. Indicates the single-channel transmission rate. This indicates the number of channels corresponding to the configured width. This indicates the number of valid channels in the verification channel group. Indicates encoding and protocol transmission efficiency. This indicates the percentage of time allocated for training and maintenance.

[0106] The formula first determines the theoretical carrying capacity based on the single-channel transmission rate and the actual number of channels available for transmission. It takes the smaller value between the number of channels corresponding to the configured width and the number of effective channels to avoid inflated carrying capacity when the configured width exceeds the number of available channels. Then, it introduces encoding and protocol transmission efficiency to effectively convert the nominal transmission capacity of the line into data, and finally deducts the transmission share occupied during training and maintenance. This ensures that the calculation result reflects the effective bandwidth available for service transmission by the bearer node under the current configuration and actual operating conditions.

[0107] The encoding and protocol transmission efficiency in the formula are statistically calibrated based on the encoding method used, protocol message overhead, flow control occupancy, and effective payload ratio. During calculation, it is used to convert the theoretical transmission capacity into effective service transmission capacity. The training and maintenance occupancy ratio is determined based on the occupancy time of the training sequence, idle ordered set, and link maintenance content within the statistical period and the total transmission time. During calculation, it is deducted from the available transmission ratio to avoid including non-service transmission in the bandwidth capacity.

[0108] S4: Based on the verified PCIe bandwidth configuration package, extract the effective configuration from the PCIe bandwidth configuration base state and back it up as a fallback configuration. Load the target configuration and perform PCIe link training. Collect the link status and dual-node signal purity codewords after the switchover and perform validity verification. If the validity verification passes, confirm the target configuration. If the validity verification fails, load the fallback configuration and re-execute PCIe link training to generate the PCIe bandwidth configuration state.

[0109] S4.1: Perform configuration field validation on the verified PCIe bandwidth configuration package, extract the target rate, target width, target channel group and equalization control word, locate the channel group currently participating in link transmission based on the basic status of PCIe bandwidth configuration, perform backup and backup consistency checks on the current rate, width, channel group and equalization control word, and generate rollback configuration.

[0110] Furthermore, the configuration hierarchy, field boundaries, and channel mapping relationships in the verified PCIe bandwidth configuration package are validated. Configuration identifiers, field lengths, and verification flags are checked according to the encapsulation order, eliminating configuration content with missing fields, duplicate channels, and conflicting control words. Channel members are expanded around the target channel group, and the target rate and target width are attached to the complete channel range. The leveling control field is located according to the channel identifier, and it is checked whether each channel has a complete leveling control word configured. Field connection verification is completed, and the target rate, target width, target channel group, and leveling control word are extracted to form the target configuration content to be loaded.

[0111] Based on the locked state and channel mapping in the PCIe bandwidth configuration baseline, the channels currently carrying service data are identified along the current effective transmission path and grouped into the current channel group participating in link transmission. The effective rate, bandwidth, and equalization control words for the current channel group are collected and written to an independent backup location according to the channel identifier, preserving the configuration collection time and channel affiliation. The backup content is repeatedly read back, and the read-back fields are checked against the currently effective fields item by item. Missing, misaligned, or inconsistent fields are re-collected and overwritten in the backup location. When the backup content passes the consistency check, the fields are encapsulated according to the write order required for configuration recovery, generating the rollback configuration.

[0112] It should be noted that the complete channel range (example range: 1 to 16 consecutive channels corresponding to the target width) is determined based on the target width, the number of available channels on the chip, the continuity of channel mapping, and the number of effective channels in the verification channel group.

[0113] S4.2: Based on the verified PCIe bandwidth configuration package, the target rate, target width, and equalization control word are loaded in a specific order and written to the target channel group. Configuration write-back and training status tracking are performed. Channel switching and PCIe link training are executed according to the target channel group to form a configuration switching execution status.

[0114] Furthermore, using the target channel group in the verified PCIe bandwidth configuration package as the execution target, the loading order is arranged according to channel startup dependencies and configuration activation relationships. First, the load balancing control word is written to the corresponding channel configuration location, then the channel enable flag corresponding to the target width is written, and finally the target rate control field is written. After each configuration write is completed, the same configuration location is read back according to the channel identifier, and the read-back content is checked against the target fields in the verified PCIe bandwidth configuration package item by item. For locations with missing fields, misaligned control words, or inconsistent channel affiliation, subsequent writing is paused, the corresponding configuration is reloaded, and read back again until all configuration fields within the target channel group are consistent.

[0115] Configuration writing is verified via readback to restrict new service data from entering the current channel group, while preserving currently transmitting data to complete existing transmission processes. Signal transmission paths are switched according to the channel mapping of the target channel group. PCIe link training is triggered, tracking the detection, polling, configuration, and link activation phases sequentially along the training state changes. The time each channel enters its corresponding training phase is recorded, and the continuity of training phases is checked. Execution anomaly flags are set for training pauses, phase rollbacks, and channel unlocking locations. For channels that have completed link training, the target rate and target width are confirmed to be effective. The configuration writing, readback verification, channel switching, and link training processes are aggregated to form a configuration switching execution state.

[0116] S4.3: Based on the configuration switching execution status, the training completion time is aligned and the configuration field is read back according to the channel identifier and training sequence. The rate, width, channel mapping, locking status and dual-node signal purity codeword of the target channel group are collected. The collected content is summarized and time-series linked according to the corresponding channel to generate configuration switching response information.

[0117] Furthermore, based on the training phase records in the configuration switch execution state, the time when each channel in the target channel group enters the link activation phase is located according to the channel identifier, and the time of the channel that finishes training latest is used as the unified alignment position. For channels that finish training early, the stable running segment between the completion time and the unified alignment position is retained, and training anomaly markers are set for channels that have training stalled, phase rolled back, or have missing completion markers. The configuration fields are read back around the unified alignment position, and the read-back content is attached to the corresponding channel to verify the channel affiliation relationship between the configuration effective scope and the target channel group, so as to avoid temporary fields during the training process from entering the switch response scope.

[0118] The target channel group status acquisition is initiated according to a unified alignment position. The actual effective rate and width are recorded along the continuous sampling time sequence. It is checked whether the channel mapping covers the target channel group, and the locking duration of each channel and the changes in the dual-node signal purity codeword are extracted. Time correction and anomaly marking are performed on positions where the acquisition time deviates, the dual-node sampling is asynchronous, and the configuration field is missing. Using the channel identifier as a summary index, the configuration field readback content, training completion status, locking status, and dual-node signal purity codeword are linked to the same time position. The status succession relationship is preserved according to the order of training completion, and configuration switching response information is generated.

[0119] S4.4: Compare the configuration switching response information with the verified PCIe bandwidth configuration package to check the consistency of configuration fields, check the negotiation between the target rate and the target width, perform continuous segment locking verification and dual-node codeword stability check on the target channel group, and determine the service bandwidth adaptation based on the actual bandwidth capacity and service bandwidth requirements to generate a configuration validity verification status.

[0120] Furthermore, using the channel identifier in the configuration switch response information as an index, the readback content of the configuration fields is linked to the target fields in the verified PCIe bandwidth configuration package to the same channel location, and the written values, channel affiliation, and field activation order are checked item by item. Around the stable running segment after training, it is confirmed whether the actual rate and actual width reach the target rate and target width, and the locations of rate reduction negotiation, bandwidth reduction negotiation, and ineffective fields are marked. Continuous lock records are merged along the lock state time trajectory of the target channel group, lock interruption boundaries are defined, short-term state fluctuations occurring at the end of training are eliminated, and a target configuration consistency check record is formed.

[0121] The codewords for the dual-node signal purity are organized around the continuously locked sections. The direction and degree of change of the dual-end codewords during continuous sampling are examined, and channels with continuously decreasing codewords, inconsistent changes between the two ends, and sampling interruptions are marked as unstable codeword channels. The actual bandwidth capacity is calculated based on the actual effective rate, width, and number of effective locked channels. The actual bandwidth capacity is then compared with the service bandwidth requirements using the same statistical caliber to check whether the target channel group can cover the bandwidth required for service transmission. Locations with insufficient capacity are marked as having insufficient service bandwidth mismatch. Verification tags are set according to target configuration consistency, locking continuity, dual-node codeword stability, and service bandwidth compatibility, and these are aggregated to form a configuration validity verification status.

[0122] The target rate (example: 32GT / s) is set based on the discrete rate levels supported by the PCIe protocol, the capabilities of the Retimer chip, and the stable training rate of the verification channel group.

[0123] The target bandwidth (example: 8 channels) is set based on service bandwidth requirements, the number of effective channels, board-level channel mapping relationships, and the synchronous carrying capacity of the verification channel group.

[0124] Figure 3 Using the equalization response gain value as the horizontal axis and the average signal purity codeword of the two nodes after the switch as the vertical axis, configuration entries after the target configuration loading is marked as valid or invalid. Valid configuration samples are mainly distributed in the region with higher equalization response gain values ​​and higher average signal purity codewords of the two nodes, and show an overall upward trend with increasing equalization response gain values. Invalid configuration samples are mainly concentrated in the low gain and low codeword region; some samples, even if the codeword improves in a single operation, are still excluded due to insufficient lock continuity, inconsistent changes in the two nodes, or failure to adapt to service bandwidth. This distribution indicates that the equalization response gain value not only reflects the degree of codeword improvement during fine-tuning but also forms a stable correspondence with the actual signal state after configuration switching, proving that gain screening of candidate PCIe bandwidth configuration packages can improve the hit rate of valid configurations and provide a reliable screening basis for configuration validity verification.

[0125] Valid Configuration: This indicates a configuration sample that meets the requirements of configuration field consistency, lock continuity, dual-node codeword stability, and service bandwidth adaptation after the target configuration is switched.

[0126] Invalid configuration: This indicates that after the target configuration is switched, there are at least some configuration fields that are inconsistent, lock interruption, unstable dual-node codewords, and incompatible service bandwidth.

[0127] The trend line represents the overall fit between the equalization response gain value and the average signal purity codeword of the two nodes after switching, reflecting the overall trend that both increase synchronously as the gain value increases.

[0128] S4.5: When the configuration validity verification status meets the target configuration requirements, confirm the target configuration effectiveness and solidify the configuration status. When the configuration validity verification status does not meet the target configuration requirements, perform configuration writing, link retraining and fallback status verification on the fallback configuration, collect the final effective rate, bandwidth, channel group, equalization control word and lock status, and generate PCIe bandwidth configuration status.

[0129] Furthermore, based on the verification flag in the configuration validity verification status, if the target configuration consistency, lock continuity, dual-node codeword stability, and bandwidth carrying difference all meet the target configuration requirements, the currently effective fields of the target channel group are read back, and the read-back content is verified to be consistent with the verified PCIe bandwidth configuration package. It is confirmed that the target channel group continues to carry service data, the service transmission restrictions set during training are lifted, and the target configuration is written to the configuration retention location, including the configuration version, channel correspondence, and effectiveness flag. The configuration retention location is read back again, and the field integrity is verified, completing the target configuration effectiveness confirmation and configuration status solidification.

[0130] When the configuration validity verification status contains verification flags that do not meet the target configuration requirements, new service data is restricted from entering the target channel group. The system waits for data already on the link to complete transmission, and then writes the equalization control word, channel group, bandwidth, and rate according to the recovery order in the fallback configuration. Each recovery field is read back to confirm that the written content matches the fallback configuration, triggering PCIe link retraining and tracking the status changes of each channel from training startup to link activation. After training is complete, the actual effective configuration, lock continuity, and dual-node signal purity codewords are checked to confirm that the fallback status can stably carry services. The final effective configuration and corresponding lock status are aggregated according to channel identifiers to generate the PCIe bandwidth configuration status.

[0131] Figure 4 A normalized evaluation was conducted between the baseline group and the complete solution group on six indicators: configuration accuracy, channel utilization, bandwidth fulfillment rate, handover success rate, rollback success rate, and service continuity. The complete solution group outperformed the baseline group in all dimensions. Specifically, improvements in configuration accuracy and channel utilization correspond to dual-node codeword monitoring, channel equalization perturbation sequence, and equalization response gain value selection; improved bandwidth fulfillment rate corresponds to verifying the bandwidth capacity of the verification channel group against service bandwidth requirements; improved handover success rate and service continuity correspond to pre-training of channels to be activated, channel arrival time difference verification, and configuration validity verification; and improved rollback success rate corresponds to rollback configuration backup, configuration writing, link retraining, and rollback status verification. The significantly increased overall profile area indicates that this invention not only improves single signal parameters but also simultaneously enhances PCIe bandwidth configuration adaptability, channel resource utilization, and reliability of abnormal configuration recovery.

[0132] Baseline group: This refers to a standard configuration scheme that uses fixed equalization control parameters and directly performs PCIe bandwidth configuration switching.

[0133] Complete solution group: This refers to a complete configuration scheme that adopts dual-node codeword monitoring, equalization perturbation, gain filtering, pre-training of channels to be enabled, time difference verification, bandwidth filtering, and failure fallback.

[0134] This embodiment also provides a computer device applicable to the PCIe bandwidth configuration method of an 112G retimer chip, comprising: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the PCIe bandwidth configuration method of the 112G retimer chip as proposed in the above embodiment.

[0135] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0136] This embodiment also provides a storage medium storing a computer program that, when executed by a processor, implements the PCIe bandwidth configuration method for the 112G retimer chip as proposed in the above embodiments. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0137] In summary, this invention achieves channel signal response identification through dual-node codeword monitoring, equalization perturbation, and gain filtering, which is used for balanced configuration adaptation of intelligent integrated circuits, reducing link mismatch caused by fixed parameters and improving configuration accuracy and channel utilization. Through pre-training of channels to be used, time difference verification, bandwidth filtering, and failure fallback, configuration is verified before switching, which is used to maintain continuous service transmission, reduce the risk of link interruption caused by asynchrony and abnormal configuration, and improve switching reliability.

[0138] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for configuring PCIe bandwidth for a 112G retimer chip, characterized in that, include: Collect PCIe link operation information and service transmission information, organize the link operation information into channels, extract the rate, bandwidth, channel mapping and locking status to form the link status, monitor the continuous time linear equalizer end and the decision feedback equalizer end, obtain the dual-node signal purity codeword, and count the service transmission load and check the bandwidth usage to determine the service bandwidth requirements and collect them into the basic status of PCIe bandwidth configuration. Based on the basic PCIe bandwidth configuration status, adjustable channels are selected according to link status. The control parameters of the continuous-time linear equalizer and the decision feedback equalizer are then fine-tuned in a short period. The changes in the codeword purity of the dual-node signal before and after the fine-tuning are compared, and the lockout status is checked. This forms a channel equalization perturbation sequence. Combined with service bandwidth requirements, bandwidth carrying capacity is screened to generate candidate PCIe bandwidth configuration packages. The steps are as follows: The channel equalization perturbation sequence is time-sequentially processed according to the channel identifier and fine-tuning window. The direction and degree of change of the dual-node signal purity codeword are extracted. The codeword change amplitude is normalized. The equalization response gain value is calculated by combining the dual-node codeword improvement and the proportion of locked continuous segments. The control parameter change is associated with the equalization response gain value to form the equalization perturbation response. Based on the balanced perturbation response, the control parameters of the codewords that can maintain lock and improve the purity of dual-node signals are screened for stability, collected into the corresponding channels, and combined with the service bandwidth requirements and the factory bandwidth carrying capacity calibration table, the carrying capacity is mapped and the configuration items are sorted. The rate, width, channel group and balanced control word are screened and encapsulated to generate candidate PCIe bandwidth configuration packages. Based on the candidate PCIe bandwidth configuration package, keep the current channel group running in the link state, start the channel group to be enabled and write the equalization control word, perform candidate channel isolation training and stability maintenance verification, check the lockout state, dual-node signal purity codeword and arrival time difference, filter the channel group that meets the bandwidth carrying requirements, and generate a verified PCIe bandwidth configuration package. The steps are as follows: The configuration fields of the candidate PCIe bandwidth configuration packets are parsed to extract the channel group to be enabled, target rate, target width and equalization control word. The channel affiliation is located according to the channel mapping in the link status, the channel group currently participating in the link transmission is determined, and channel switching preparation information is generated. Based on the channel switching preparation information, the current channel group participating in the link transmission is kept running. The service transmission path of the current channel group and the candidate training path of the channel group to be activated are established through the channel selection unit. The clock activation, signal path connection and equalization control word writing are executed sequentially for the channel group to be activated. The service data gating position is used to restrict the channel group to be activated from receiving service data and generate the channel pre-configuration state. In the pre-configured channel state, the training sequence generation unit sends the training sequence and idle ordered set to the channel group to be activated along the candidate training path, keeps the current channel group carrying service data along the service transmission path, performs dual-node sampling synchronization and signal arrival time marking on the channel group to be activated, collects the locking status of each channel, dual-node signal purity codeword and signal arrival time, and forms candidate channel training response information; According to the verified PCIe bandwidth configuration package, extract the effective configuration from the PCIe bandwidth configuration base state and back it up as a fallback configuration. Load the target configuration and perform PCIe link training. Collect the link status and dual-node signal purity codewords after the switch and perform validity verification. If the validity verification passes, confirm the target configuration. If the validity verification fails, load the fallback configuration and re-execute PCIe link training to generate the PCIe bandwidth configuration state.

2. The PCIe bandwidth configuration method for the 112G retimer chip as described in claim 1, characterized in that, The aggregation of PCIe bandwidth configuration basic status involves the following steps: The PCIe link operation information is timestamped and the channel affiliation is verified according to the channel mapping and acquisition sequence. The rate, bandwidth and lock status are attached to the corresponding channel. The continuity of each channel is checked and breakpoints are marked to generate the PCIe channel operation sequence. Based on the PCIe channel operation sequence, the continuous-time linear equalizer end and the decision feedback equalizer end of the same channel are located. The dual-end sampling time calibration and channel position mapping are performed according to the same acquisition period to obtain the dual-node signal purity codeword. The codewords at both ends are time-series correlated with the lock state of the corresponding channel to generate the dual-node signal purity state. The service transmission information is attached to the corresponding transmission period in the PCIe channel operation sequence. The transmission period is divided, the service load is statistically analyzed, and the bandwidth usage is checked. The link carrying capacity is calculated in combination with the rate and width to determine the service bandwidth requirements. At the same time, it is collected with the signal purity status of the two nodes to generate the basic status of PCIe bandwidth configuration.

3. The PCIe bandwidth configuration method for the 112G retimer chip as described in claim 1, characterized in that, The steps for forming the channel-equalized perturbation sequence are as follows: Extract the locking status, dual-node signal purity codewords, and bandwidth usage of each channel from the basic PCIe bandwidth configuration status. Perform lock continuity verification and full-load continuous segment identification, filter out channels with lock interruption and continuous full load, and fine-tune the available time period of the remaining channels to form an adjustable channel set. For the adjustable channel set, short-term fine-tuning windows are divided, and the link rate and width are frozen to a baseline. The control parameters of the continuous-time linear equalizer and the decision feedback equalizer are changed sequentially in a single-parameter step manner. The dual-node signal purity codewords and locking status before and after each fine-tuning window are collected, and the status before and after fine-tuning is reverted to generate a channel equalization perturbation sequence.

4. The PCIe bandwidth configuration method for the 112G retimer chip as described in claim 1, characterized in that, The steps for generating the verified PCIe bandwidth configuration package are as follows: Based on the candidate channel training response information, the locking continuity segment is extracted and the codeword change trend is determined. The locking continuity and dual-node signal purity codeword of each channel are checked. The channel delay is sorted according to the signal arrival time. The channel arrival time difference is calculated. Channels with locking interruption, decreased signal purity, and channel arrival time difference that do not meet the synchronization requirements are eliminated to generate a verification channel group. The number of channels in the verification channel group is counted, the bandwidth capacity is calculated, and the rate, width, number of channels and bandwidth capacity are compared with the service bandwidth requirements to determine the target channel group that meets the bandwidth capacity requirements. The configuration integrity is checked and the fields are encapsulated for the target rate, target width, target channel group and corresponding load balancer control word to generate a verified PCIe bandwidth configuration package.

5. The PCIe bandwidth configuration method for the 112G retimer chip as described in claim 1 or 4, characterized in that, The steps for loading the target configuration and performing PCIe link training are as follows: The configuration fields of the verified PCIe bandwidth configuration package are validated, the target rate, target width, target channel group and equalization control word are extracted, and the channel group currently participating in the link transmission is located according to the basic status of the PCIe bandwidth configuration. The current rate, width, channel group and equalization control word are backed up and the backup consistency is checked, and the rollback configuration is generated. Based on the verified PCIe bandwidth configuration package, the target rate, target width and equalization control word are loaded in order and written to the target channel group. Configuration write readback and training status tracking are performed. Channel switching and PCIe link training are performed according to the target channel group to form the configuration switching execution status. Based on the configuration switching execution status, the training completion time is aligned and the configuration field is read back according to the channel identifier and training sequence. The rate, width, channel mapping, locking status and dual-node signal purity codeword of the target channel group are collected. The collected content is summarized and time-series linked according to the corresponding channel to generate configuration switching response information.

6. The PCIe bandwidth configuration method for the 112G retimer chip as described in claim 5, characterized in that, The steps for generating the PCIe bandwidth configuration status are as follows: The configuration switching response information is compared with the verified PCIe bandwidth configuration package to check the consistency of configuration fields, the negotiation between the target rate and the target width is checked, the target channel group is checked for locked continuous segments and dual-node codeword stability, and the service bandwidth adaptation is determined in combination with the actual bandwidth capacity and service bandwidth requirements to generate the configuration validity verification status. When the configuration validity verification status meets the target configuration requirements, the target configuration is confirmed to be effective and the configuration status is solidified. When the configuration validity verification status does not meet the target configuration requirements, the fallback configuration is written, the link is retrained, and the fallback status is verified. The final effective rate, bandwidth, channel group, equalization control word, and lock status are collected to generate the PCIe bandwidth configuration status.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the PCIe bandwidth configuration method for the 112G retimer chip according to any one of claims 1 to 6.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the PCIe bandwidth configuration method for the 112G retimer chip according to any one of claims 1 to 6.

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