A micro-electro-mechanical system device and a method of manufacturing the same

Abstract

The present application relates to a kind of micro electro mechanical system devices and preparation method thereof, the micro electro mechanical system device includes device layer, top layer silicon, buried oxygen layer, bottom layer silicon and substrate layer in thickness direction thereof in sequence, multiple cavities are in the micro electro mechanical system device, multiple described cavities are located bottom layer silicon and are set in thickness direction and pass through bottom layer silicon, the depth D of the cavity in thickness direction is less than the thickness H of substrate layer.In the technical scheme of the present application, support strength is provided by thicker substrate layer, and bottom layer silicon with cavity does not need to provide support strength, solve the problem that substrate strength and cavity size are easily in conflict when cavity is set in bottom layer silicon.

Description

Technical Field

[0001] This invention relates to the field of semiconductor process technology, and more specifically to a microelectromechanical system (MEMS) device and its fabrication method. Background Technology

[0002] With the increasing application of microelectromechanical systems (MEMS) devices in fields such as 5G communication, artificial intelligence, and the Internet of Things, the requirements for device performance, integration, and reliability are becoming increasingly stringent. As a key structural element of MEMS sensors, actuators, and radio frequency devices, the performance of cavities has a significant impact on core indicators such as device sensitivity, resonant frequency, and isolation.

[0003] Currently, industry and academia primarily fabricate MEMS cavity structures through pre-forming cavities during substrate manufacturing (Cavity-SOI technology) and sacrificial layer release-based approaches. Cavity-SOI technology requires pre-forming cavities on the substrate. In this approach, the size and depth of the cavity are strictly limited by the remaining mechanical strength of the underlying silicon. To obtain a larger or deeper cavity, the effective support thickness of the underlying silicon must be reduced, exacerbating wafer warping and significantly increasing the risk of fragmentation. Conversely, if the cavity size is reduced to ensure substrate strength, core performance characteristics such as device sensitivity and resonant frequency will be constrained. Therefore, this technology struggles to simultaneously achieve both cavity size and high mechanical strength. Sacrificial layer release-based approaches utilize the buried oxide layer of the MEMS device as a sacrificial layer to define the cavity region. In this technology, the cavity gap height is fixed by the thickness of the buried oxide layer, making it impossible to freely adjust according to device performance requirements, resulting in insufficient design flexibility. Meanwhile, the etching medium used in the release process can easily damage sensitive materials in the device (such as metal electrodes, piezoelectric films, etc.), affecting the long-term reliability and yield of the device. This approach has high requirements for the selective release of the buried oxide layer, and is prone to incomplete release or over-corrosion, affecting the airtightness of the cavity or the device performance. In addition, the cavity is fabricated after the front-side device process (such as electrode fabrication, piezoelectric layer deposition), and relies on pre-designed etching holes or release channels to remove sacrificial materials. The complex release process may damage or contaminate the already completed delicate front-side structure. For MEMS devices such as pressure sensor diaphragms and ultrasonic transducer elements that require complete and sealed thin films as functional areas, the top silicon layer itself does not allow for the existence of release holes or channels for the flow of etching media. Therefore, the applicability of this approach is limited.

[0004] In summary, in the aforementioned prior art, the cavity is directly formed inside the silicon-on-insulator substrate, causing the cavity function to mutually restrict and influence the performance of the bottom or top silicon layers within the silicon-on-insulator substrate. This contradiction severely restricts further improvements in the sensitivity, integration, and reliability of high-performance MEMS devices. Summary of the Invention

[0005] Based on the above description, the present invention provides a microelectromechanical system (MEMS) device and its fabrication method, and a MEMS device, aiming to solve the problem of mutual constraint between the cavity function and the performance of the bottom or top silicon inside the silicon-on-insulator substrate.

[0006] The technical solution of the present invention to solve the above-mentioned technical problems is as follows: The present invention provides a microelectromechanical system (MEMS) device, which includes, along its thickness direction, a device layer, a top silicon layer, a buried oxide layer, a bottom silicon layer, and a substrate layer. The MEMS device has multiple cavities located in the bottom silicon layer and penetrating the bottom silicon layer in the thickness direction. The multiple cavities are spaced apart, and the depth D of the cavity in the thickness direction is less than the thickness H of the substrate layer.

[0007] Furthermore, the cavity has a depth D of 1μm to 100μm in the thickness direction, and the substrate layer has a thickness H greater than 10mm.

[0008] Furthermore, multiple cavities are spaced apart in the substrate layer, with the spacing between two adjacent cavities being greater than 100 μm.

[0009] Furthermore, the substrate layer is made of at least one of silicon, glass, silicon carbide, gallium nitride, sapphire, ceramic, polymer, and metal.

[0010] This invention also proposes a method for fabricating the above-mentioned microelectromechanical system (MEMS) device, comprising the following steps: S1. Provide a silicon-on-insulator substrate and a carrier substrate, wherein the silicon-on-insulator substrate comprises, in its thickness direction, a top silicon layer, a buried oxide layer and a bottom silicon layer in sequence; S2. A groove of depth D is formed on the side of the underlying silicon that is away from the buried oxide layer by etching pretreatment; S3. Bond the side of the silicon-on-insulator substrate with the groove to the carrier substrate. After the groove is bonded to the carrier substrate, a cavity is formed to obtain a microelectromechanical system device.

[0011] Furthermore, in step S1, the material of the underlying silicon includes monocrystalline silicon, and the material of the buried oxide layer includes silicon dioxide.

[0012] Furthermore, step S2 includes: S21. Thin the underlying silicon layer to a predetermined thickness; S22. Perform etching pretreatment on the side of the bottom silicon layer that is away from the buried oxide layer to form an initial groove of the target depth; S23. Using deep reactive ion etching technology, the surface of the bottom silicon away from the buried oxide layer is etched as a whole, so that the bottom of the initial groove and the unetched surface of the bottom silicon away from the buried oxide layer are etched inward at the same thickness in the thickness direction, so as to form a groove of the target depth on the bottom silicon.

[0013] Furthermore, step S3 includes: bonding one side of the silicon-on-insulator substrate with a groove to a carrier substrate in a vacuum or controlled atmosphere environment, wherein the groove and the carrier substrate form a sealed cavity after bonding, thereby obtaining a microelectromechanical system device.

[0014] Furthermore, the material of the substrate includes at least one selected from silicon, glass, silicon carbide, gallium nitride, sapphire, ceramic, polymer, and metal.

[0015] Furthermore, prior to step S3, the method further includes: fabricating a device layer on the side of the top silicon layer opposite to the buried oxide layer.

[0016] Compared with the prior art, the technical solution of this application has the following beneficial technical effects: (1) In the technical solution of the present invention, the support strength is provided by a thicker substrate layer, and the support strength is not provided by the bottom silicon with cavity. This solves the problem that the substrate strength and cavity size are prone to conflict when the cavity is set in the bottom silicon.

[0017] (2) Since the cavity is set in the bottom silicon and penetrates the bottom silicon, the cavity and the top silicon are located on opposite sides of the buried oxide layer, and there is no direct contact between them. This achieves the decoupling of the cavity preparation process from the structure of the top silicon, and significantly reduces the risk of the cavity preparation process affecting the top silicon. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of an embodiment of the microelectromechanical system device in this application; Figure 2 This is a schematic flowchart of an embodiment of the fabrication method of microelectromechanical system devices in this application.

[0019] Explanation of icon numbers: 100. Microelectromechanical systems (MEMS) devices; 1. Top silicon layer; 2. Buried oxide layer; 3. Bottom silicon layer; 4. Substrate layer; 5. Cavity. Detailed Implementation

[0020] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0022] Currently, industry and academia primarily fabricate MEMS cavity structures through pre-forming cavities during substrate manufacturing (Cavity-SOI technology) and sacrificial layer release-based approaches. Cavity-SOI technology requires pre-forming cavities on the substrate. In this approach, the size and depth of the cavity are strictly limited by the remaining mechanical strength of the underlying silicon. To obtain a larger or deeper cavity, the effective support thickness of the underlying silicon must be reduced, leading to increased wafer warping and a significantly higher risk of fragmentation. Conversely, if the cavity size is reduced to ensure substrate strength, core performance characteristics such as device sensitivity and resonant frequency will be constrained. Therefore, this technology struggles to simultaneously achieve both cavity size and high mechanical strength. Sacrificial layer release-based approaches utilize the buried oxide layer of the MEMS device as a sacrificial layer to define the cavity region. In this technology, the cavity gap height is fixed by the thickness of the buried oxide layer and cannot be freely adjusted according to device performance requirements, resulting in insufficient design flexibility. Meanwhile, the etching medium used in the release process can easily damage sensitive materials in the device (such as metal electrodes, piezoelectric films, etc.), affecting the long-term reliability and yield of the device. This approach has high requirements for the selective release of the buried oxide layer, and is prone to incomplete release or over-corrosion, affecting the airtightness of the cavity or the device performance. In addition, the cavity is fabricated after the front-side device process (such as electrode fabrication, piezoelectric layer deposition), and relies on pre-designed etching holes or release channels to remove sacrificial materials. The complex release process may damage or contaminate the already completed delicate front-side structure. For MEMS devices such as pressure sensor diaphragms and ultrasonic transducer elements that require complete and sealed thin films as functional areas, the top silicon layer itself does not allow for the existence of release holes or channels for the flow of etching media. Therefore, the applicability of this approach is limited.

[0023] In summary, in the aforementioned prior art, the cavity is directly formed inside the silicon-on-insulator substrate, causing the cavity function to mutually restrict and influence the performance of the bottom or top silicon layers within the silicon-on-insulator substrate. This contradiction severely restricts further improvements in the sensitivity, integration, and reliability of high-performance MEMS devices.

[0024] In view of this, please refer to Figure 1The present invention provides a microelectromechanical system (MEMS) device 100, which includes, along its thickness direction, a device layer, a top silicon layer 1, a buried oxide layer 2, a bottom silicon layer 3, and a substrate layer 4. The MEMS device 100 has a plurality of cavities 5, which are located on the bottom silicon layer 3 and penetrate the bottom silicon layer 3 in the thickness direction. The plurality of cavities 5 are spaced apart, and the depth D of the cavity 5 in the thickness direction is less than the thickness H of the substrate layer 4.

[0025] In the technical solution of the present invention, the support strength is provided by a thicker substrate layer 4, eliminating the need for the bottom silicon 3 with cavity 5 to provide support strength. This solves the problem that the substrate strength and the size of cavity 5 are prone to conflict when cavity 5 is set in bottom silicon 3. In addition, since cavity 5 is set in bottom silicon 3 and penetrates bottom silicon 3, cavity 5 and top silicon 1 are located on opposite sides of buried oxide layer 2, and the two have no direct contact. This achieves structural decoupling between cavity 5 fabrication process and top silicon 1 (and even device layer on top silicon 1), significantly reducing the risk of cavity 5 fabrication process affecting top silicon 1.

[0026] Furthermore, the depth D of the cavity 5 in the thickness direction is 1 μm to 100 μm, and the thickness H of the substrate layer is greater than 10 mm. A depth D of the cavity 5 within the above range can improve the performance of the device. A thickness of the substrate layer 4 within the above range can provide sufficient support, thereby improving the mechanical strength of the microelectromechanical system device 100.

[0027] Furthermore, the distance between two adjacent cavities 5 is greater than 100 μm.

[0028] Furthermore, the material of the substrate layer 4 includes at least one of silicon, glass, silicon carbide, gallium nitride, sapphire, ceramic, polymer, and metal.

[0029] Please see Figure 2 The present invention also proposes a method for fabricating the above-mentioned microelectromechanical system device, comprising the following steps: S1. Provide a silicon-on-insulator (SOI) substrate and a carrier substrate, wherein the SOI substrate comprises, in its thickness direction, a top silicon layer, a buried oxide layer and a bottom silicon layer. S2. A groove is formed on the side of the bottom silicon that is away from the buried oxide layer by etching pretreatment, with the buried oxide layer as the etching stop layer. S3. Bond the side of the silicon-on-insulator substrate with the groove to the carrier substrate. After the groove is bonded to the carrier substrate, a cavity is formed to obtain a microelectromechanical system device.

[0030] In the technical solution of the present invention, the buried oxide layer in the silicon-on-insulator substrate is used as a natural etching stop layer, which can prepare a target cavity with a depth equal to the thickness of the bottom silicon layer. At the same time, a supporting substrate is used to enhance the mechanical strength, which solves the problem that the substrate strength and cavity size are prone to conflict when the cavity is set in the bottom silicon layer.

[0031] This application uses readily available and low-cost standard silicon-on-insulator (SOI) wafers. By etching the bottom silicon surface of the silicon-on-insulator substrate and supplementing it with bonded independent substrates to provide support strength, it is possible to achieve the same effect as in the past, which required silicon-on-insulator wafers with customized thickness or complex Cavity-SOI processes, using the cheapest materials and the most common laboratory equipment.

[0032] Furthermore, in the technical solution of this application, since the groove is etched from the side of the bottom silicon away from the top silicon to form the cavity, the relative position of the groove and the top silicon on the front side is determined. That is, the relative position of the groove and the top silicon can be determined in the etching step, so that the bonding step does not need to consider the problem of alignment error.

[0033] Furthermore, after the groove fabrication is completed, the present invention can integrate the functional chip with the carrier substrate using low-temperature (<300°C) plasma-activated bonding or polymer adhesion bonding (e.g., using BCB, with a curing temperature <250°C). The thermal budget of this process is much lower than that of traditional silicon direct bonding or certain metal eutectic bonding. For cases where the front side (top silicon) of the silicon-on-insulator substrate already integrates high-temperature sensitive functional materials (such as lead zirconate titanate piezoelectric films) or pre-processed circuits, the functional integrity of the front-side sensitive materials is perfectly protected, making it possible to realize high-performance cavity structures on MEMS devices containing advanced functional materials such as PZT.

[0034] In some implementations, step S2 includes: S21. Thin the underlying silicon to a predetermined thickness; S22. Perform etching pretreatment on the side of the bottom silicon layer that is away from the buried oxide layer to form an initial groove of the target depth; S23. Using deep reactive ion etching (DRIE) technology, the surface of the underlying silicon away from the buried oxide layer is etched as a whole, so that the bottom of the initial groove and the unetched surface of the underlying silicon are etched inward at the same thickness in the thickness direction, so as to form a groove of the target depth on the underlying silicon.

[0035] It should be noted that in the above technical solution, the underlying silicon is thinned to a predetermined thickness, which is greater than the target depth. This operation can reduce the thickness required for subsequent etching. The method used is a thinning scheme commonly used in the art. For example, at least one of mechanical polishing, wet spin etching, and dry plasma etching can be used to thin the underlying silicon.

[0036] In step S22, a pre-etching process can be performed on the side of the underlying silicon opposite to the buried oxide layer using methods known in the art to form an initial groove of the target depth. For example, this initial groove can be fabricated using patterned photolithography or a hard mask process.

[0037] In step S23, deep reactive ion etching (DRIE) is used to etch the surface of the bottom silicon layer away from the buried oxide layer in a holistic downward direction. This means that the upper surface planar area is not masked for protection, allowing the etching reaction to act simultaneously on the bottom of the initial groove and the unetched upper surface of the bottom silicon layer. In this process, a high-density plasma is generated using an inductively coupled plasma (ICP) source, and an RF bias voltage perpendicular to the substrate surface is applied to control the ion bombardment direction. Simultaneously, by introducing passivation gases such as O2, a SiOxFy-type passivation protective layer is formed on the silicon sidewall surface during the etching process. This passivation layer effectively suppresses the chemical etching of the sidewalls by fluorine radicals, resulting in a physical bombardment-enhanced etching rate along the thickness direction (i.e., perpendicular to the buried oxide layer) that is much greater than the lateral chemical etching rate. This achieves highly anisotropic etching, resulting in a sidewall verticality of 88°~92° and a flat bottom, forming a groove structure with a good morphology. However, during this global maskless etching process, the loading effect caused by the difference in pattern density—that is, the etching rate of the open area (unetched upper surface) and the densely patterned area (bottom of the groove)—objectively differs to some extent. To minimize this difference, process parameters can be optimized (such as appropriately reducing chamber pressure, adjusting gas ratio, and bias power) to ensure that the bottom of the initial groove and the unetched surface advance inward at essentially similar etching rates to achieve the same or similar thickness. Since the downward advancement thickness of both is the same or similar, the overall remaining thickness of the underlying silicon is correspondingly reduced by this advancement thickness. However, the height difference between the bottom of the initial groove and the unetched upper surface (i.e., the groove depth) is always numerically equal to or approximately equal to the target depth formed in step S22. When etching reaches the buried oxide layer, the extremely high selectivity of the buried oxide layer (SiO2) for fluorine-based etching gases (the selectivity of silicon to silicon dioxide can reach over 200:1) enables automatic and precise etching stop. However, upon reaching the buried oxide layer interface, the accumulation of surface charge in the insulating layer may cause ion deflection, resulting in a "notching effect" at the bottom of the silicon sidewalls. To address this issue, the bottom lateral undercut can be effectively suppressed by strictly controlling the over-etching time (e.g., keeping the over-etching time within 10% of the main etching time) or by employing a pulsed bias etching mode, thus ensuring the integrity of the trench sidewall morphology. Ultimately, this global etching method achieves further reduction in the overall thickness of the underlying silicon and maintenance of the trench depth without the need for additional masks. It fully utilizes the high etching rate and good uniformity of DRIE, improving the consistency of the thickness reduction of the underlying silicon.

[0038] In an optional embodiment, the DRIE process in step S23 above can employ the following typical parameters (based on a laboratory-grade ICP-DRIE device): ICP source power of 600 W (for generating high-density plasma), RF bias power of 15 W (corresponding to a self-bias voltage of approximately -100 V, used to control the vertical bombardment energy of ions), and chamber pressure of 15 mTorr (approximately 2.0 Pa); the etching gas is a mixture of SF6 and O2, with an SF6 flow rate of 40 sccm and an O2 flow rate of 5 sccm (O2 accounts for approximately 11%, used for sidewall passivation); the substrate temperature is maintained at room temperature (20~25°C). Under the above process conditions, the longitudinal etching rate of silicon can reach 0.8~1.2 μm / min, and it has an etching selectivity ratio for silicon dioxide higher than 200:1; simultaneously, through the above over-etching control strategy, a groove structure with vertical sidewalls, a flat bottom, a depth of the target depth D, and penetrating the underlying silicon can be reliably obtained.

[0039] In the technical solution of this application, the device layer can be prepared either before or after bonding the carrier substrate.

[0040] In some embodiments, prior to step S3, a device layer is fabricated on the side of the top silicon layer opposite to the buried oxide layer.

[0041] In the technical solution of this application, the device layer can be prepared either before or after the groove etching, thus making it more widely applicable to the process.

[0042] In some embodiments, in step S1, the material of the underlying silicon includes monocrystalline silicon, and the material of the buried oxide layer includes silicon dioxide.

[0043] This invention does not limit the carrier substrate and allows for selection based on needs. For example, when using the method provided in this application during the R&D phase, the carrier substrate can be a "universal test carrier board" with standardized alignment marks, enabling rapid replacement and testing of chips with different functions and improving R&D efficiency. Similarly, when using the method provided in this application during the mass production phase, the carrier substrate can be a multifunctional interposer or packaging substrate integrating redistribution layers, through-silicon vias (TSVs), or passive components. In this case, the bonding step provides mechanical support while directly completing system-level packaging and electrical interconnection, significantly improving device performance and integration. Furthermore, during wafer-level packaging, the carrier substrate can directly serve as a cap wafer, completing the cavity sealing and protection of all chips on the entire wafer in one step. Since the recess is located in the bottom silicon layer, and the positional relationship between the bottom and top silicon layers is already determined, there is no need to align the cavities with the top silicon layer when packaging the carrier substrate (cap wafer).

[0044] In some embodiments, step S3 includes: bonding one side of the silicon-on-insulator substrate with a groove to a carrier substrate in a vacuum or controlled atmosphere, wherein the groove and the carrier substrate form a sealed cavity to obtain a microelectromechanical system device.

[0045] For devices such as resonators and infrared detectors that require a vacuum or specific atmosphere, the airtightness of the cavity is crucial. In this embodiment, the bonding of a grooved silicon-on-insulator substrate to a carrier substrate is completed in a bonding apparatus under vacuum or a controlled atmosphere. By pre-baking and degassing before bonding and maintaining a vacuum environment during bonding, a high-vacuum sealed cavity can be directly formed. The carrier substrate simultaneously acts as a sealing cover, completing structure formation and vacuum encapsulation in one step.

[0046] In the technical solution of this application, the bonding between the groove and the substrate can be permanent or temporary. For example, in the manufacturing of standardized sensors, actuators, and other products, plasma-activated bonding or metal thermo-pressing bonding can be used to form a strong, airtight, and thermomechanically stable permanent bond. Alternatively, during research and testing, photoresist, special wax, or commercial temporary bonding films can be used for bonding. After testing, the substrate can be non-destructively peeled off by heating, laser irradiation, or chemical dissolution, facilitating the recycling of expensive functional chips or failure analysis, and greatly reducing research and development iteration costs.

[0047] In embodiments of this application, the silicon-on-insulator (SiI) substrate can be one or more. That is, one carrier substrate can be bonded to one SiI substrate, or one carrier substrate can be bonded to multiple SiI substrates. When one carrier substrate is bonded to multiple SiI substrates, the groove sealing and cavity formation of multiple SiI substrates on one carrier substrate (e.g., a wafer) can be completed in one go, which is more efficient.

[0048] This application does not impose any restrictions on the material of the carrier substrate, and it can be selected as needed. In some embodiments, the material of the carrier substrate includes at least one selected from silicon, glass, silicon carbide, gallium nitride, sapphire, ceramic, polymer, and metal.

[0049] Specifically, a designable prestress state can be introduced at the bonding interface by selecting a substrate material with a coefficient of thermal expansion (CTE) that matches or is specifically mismatched with silicon. When near-zero stress is required, a CTE that matches silicon (2.6 × 10⁻⁶) can be selected. -6Materials with similar CTE (such as silicon carbide and gallium nitride) can be selected to minimize thermal mismatch stress. When tensile prestress is required, a carrier substrate with a CTE greater than that of silicon (such as a metal material) can be selected, and the functional chip will bear tensile stress after cooling. When compressive prestress is required, a carrier substrate with a CTE less than that of silicon (such as Invar alloy and quartz glass) can be selected, and the functional chip will bear compressive stress after cooling.

[0050] This application does not impose any limitation on the bonding temperature. The bonding temperature (T-bond) is the stress zero-point temperature. In some embodiments, by controlling the bonding temperature at 200~300°C through low-temperature bonding, the temperature difference between the device operating temperature (e.g., room temperature to 85°C) and the stress zero point can be reduced, keeping the thermal stress at a controllable low level. This stress regulation method can be used to compensate for residual process stress, tune resonator frequencies, and improve the diaphragm's resistance to breakage. It can not only improve device reliability but also be extended to actively tuning resonator frequencies, optimizing piezoelectric transducer performance, and manufacturing high-performance, high-reliability heterogeneous integrated microsystems for flexible electronics and wearable devices.

[0051] In addition, when the top silicon layer contains heat-sensitive piezoelectric materials such as PZT and AlN or when CMOS circuits have been completed, a low-temperature bonding process is used, with a bonding temperature below 300°C; when the top silicon layer does not contain heat-sensitive materials, any one of high-temperature bonding, eutectic bonding, or polymer adhesion bonding can be used; the low-temperature bonding process includes plasma-activated bonding, surface-activated bonding (SAB), and polymer adhesion bonding.

[0052] The present invention also proposes a MEMS device comprising the above-described MEMS device structure, wherein the MEMS device is a sensor or an actuator.

[0053] Since this MEMS device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be repeated here.

[0054] In one specific implementation, multiple miniature silicon-based MEMS "functional islands" (silicon-on-insulator substrates) containing high-performance cavity structures (groove structures) can be arrayed and bonded onto a flexible polymer substrate such as polyimide. These islands are responsible for high-precision sensing and computing, while the flexible substrate is responsible for deformation and system connectivity. This provides a highly promising heterogeneous solution that combines rigidity and flexibility to address the pain points of insufficient performance and reliability in flexible electronics.

[0055] In summary, the technical solution of this application has the following beneficial technical effects: (1) In the technical solution of the present invention, the buried oxide layer in the silicon-on-insulator substrate is used as a natural etching stop layer to prepare a target cavity with a depth equal to the thickness of the bottom silicon layer. At the same time, a carrier substrate is used to enhance the mechanical strength, which solves the problem that the substrate strength and cavity size are prone to conflict when the cavity is set in the bottom silicon layer.

[0056] (2) This application uses readily available and low-cost standard silicon-on-insulator wafers (silicon-on-insulator substrates), and etches the bottom silicon surface of the silicon-on-insulator substrate, and provides support strength by bonding independent substrates. Thus, it can achieve the effect that previously required silicon-on-insulator wafers with customized thickness or complex Cavity-silicon-on-insulator processes with the cheapest materials and the most common laboratory equipment.

[0057] (3) In the technical solution of this application, since the groove is obtained by etching from the side of the bottom silicon away from the top silicon and finally forming a cavity, the relative position of the groove and the top silicon on the front side has been determined. That is, the relative position of the groove and the top silicon can be determined in the etching step, so that the bonding step does not need to consider the alignment error.

[0058] (4) After the groove is prepared, the present invention can use low-temperature (<300℃) plasma activation bonding or polymer adhesion bonding (e.g., using BCB, curing temperature <250℃) to integrate the functional chip with the carrier substrate. The thermal budget of this process is much lower than that of traditional silicon direct bonding or some metal eutectic bonding. For cases where the front side (top silicon) of the silicon-on-insulator substrate has integrated high-temperature sensitive functional materials (such as lead zirconate titanate piezoelectric films) or pre-processed circuits, the functional integrity of the front sensitive materials is perfectly protected, making it possible to realize high-performance cavity structures on MEMS devices containing advanced functional materials such as PZT.

[0059] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A microelectromechanical system (MEMS) device, characterized in that, The microelectromechanical system device includes, along its thickness direction, a device layer, a top silicon layer, a buried oxide layer, a bottom silicon layer, and a substrate layer. The microelectromechanical system device has multiple cavities, which are located in the bottom silicon layer and penetrate the bottom silicon layer in the thickness direction. The multiple cavities are spaced apart, and the depth D of the cavity in the thickness direction is less than the thickness H of the substrate layer.

2. The microelectromechanical system device as described in claim 1, characterized in that, The cavity has a depth D of 1μm to 100μm in the thickness direction, and the substrate layer has a thickness H greater than 10mm.

3. The microelectromechanical system device as described in claim 1, characterized in that, The distance between two adjacent cavities is greater than 100 μm.

4. The microelectromechanical system device as described in claim 1, characterized in that, The substrate layer is made of at least one of silicon, glass, silicon carbide, gallium nitride, sapphire, ceramic, polymer, and metal.

5. A method for fabricating a microelectromechanical system device as described in any one of claims 1 to 4, characterized in that, Includes the following steps: S1. Provide a silicon-on-insulator substrate and a carrier substrate, wherein the silicon-on-insulator substrate comprises, in its thickness direction, a top silicon layer, a buried oxide layer and a bottom silicon layer in sequence; S2. A groove of depth D is formed on the side of the underlying silicon that is away from the buried oxide layer by etching pretreatment; S3. Bond the side of the silicon substrate on the insulator with the groove to the carrier substrate. After the groove is bonded to the carrier substrate, a cavity with a depth of D is formed, thus obtaining a microelectromechanical system device.

6. The method for fabricating a microelectromechanical system device as described in claim 5, characterized in that, In step S1, the material of the bottom silicon layer includes monocrystalline silicon, and the material of the buried oxide layer includes silicon dioxide.

7. The method for fabricating a microelectromechanical system device as described in claim 5, characterized in that, Step S2 includes: S21. Thin the underlying silicon layer to a predetermined thickness; S22. Perform etching pretreatment on the side of the bottom silicon layer that is away from the buried oxide layer to form an initial groove of the target depth; S23. Using deep reactive ion etching technology, the surface of the bottom silicon away from the buried oxide layer is etched as a whole, so that the bottom of the initial groove and the unetched surface of the bottom silicon away from the buried oxide layer are etched inward at the same thickness in the thickness direction, so as to form a groove of the target depth on the bottom silicon.

8. The method for fabricating a microelectromechanical system device as described in claim 5, characterized in that, Step S3 includes: bonding the side of the silicon-on-insulator substrate with the groove to a carrier substrate in a vacuum or controlled atmosphere environment, wherein the groove and the carrier substrate form a sealed cavity after bonding, thereby obtaining a microelectromechanical system device.

9. The method for fabricating a microelectromechanical system device as described in claim 5, characterized in that, The material of the substrate includes at least one of silicon, glass, silicon carbide, gallium nitride, sapphire, ceramic, polymer, and metal.

10. The method for fabricating a microelectromechanical system device as described in claim 5, characterized in that, Before step S3, the method further includes: fabricating a device layer on the side of the top silicon layer opposite to the buried oxide layer.

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