A method for manufacturing a MEMS double-layer mass inertial device and the inertial device

Abstract

The application discloses a MEMS double-layer mass block inertial device preparation method and an inertial device, relates to the micro-nano manufacturing technical field, and adopts a three-wafer bonding scheme to take an SOI wafer as an intermediate layer material, forms a first movable micro-mechanical structure layer and a second movable micro-mechanical structure layer on the front surface and the back surface of the SOI wafer respectively through deep silicon etching, and the comb teeth in the two layers of structure are arranged correspondingly in the vertical direction and jointly form a double-layer comb tooth capacitor structure. The first movable micro-mechanical structure layer is sealed through the bonding of a second wafer, the second movable micro-mechanical structure layer is sealed through the bonding of a third wafer, and a vacuum environment is maintained in the device. A tapered blind hole is formed on the second wafer and the third wafer, and a metal wiring layer is manufactured, so that the electrical connection with the two layers of movable micro-mechanical structure layers is realized respectively. Compared with the existing single-layer mass block MEMS inertial device, the number of comb teeth is doubled under the same chip area, the capacitance change amount is significantly improved, the device sensitivity is effectively improved, and the mechanical thermal noise is reduced, and the application is suitable for the batch preparation of MEMS high-performance gyroscopes and accelerometers.

Description

Technical Field

[0001] This invention relates to the field of micro-nano manufacturing technology, and more specifically to a method for fabricating a MEMS double-layer mass block inertial device and the field of inertial device technology. Background Technology

[0002] Micro-Electro-Mechanical Systems (MEMS) based inertial sensors are an important hardware branch of inertial navigation devices. Compared with traditional precision mechanical inertial devices, MEMS inertial devices have significant advantages such as excellent shock resistance, small size, light weight, low power consumption, easy integration with microelectronic circuits, and high-precision mass production capabilities. They have been widely used in automotive electronics, consumer electronics, aerospace, weaponry, and industrial control.

[0003] As unmanned intelligent control systems continue to demand higher navigation accuracy and reliability, the market's need for high-performance MEMS inertial devices is becoming increasingly urgent. This places higher demands on key performance indicators of MEMS inertial devices, such as sensitivity, resolution, noise level, and long-term stability.

[0004] Micro-nano fabrication technology is a crucial component of advanced manufacturing and a key technology for fabricating MEMS inertial sensors. Currently, the fabrication of MEMS inertial devices primarily employs silicon-based micromachining processes, specifically involving the following mainstream techniques: (1) SOI wafer fabrication technology: In existing technologies, MEMS inertial devices typically use silicon-on-insulator (SOI) wafers as the starting material. An SOI wafer consists of three layers: a bottom silicon layer, a buried oxide layer (silicon dioxide), and a top silicon layer (device layer). The top silicon layer serves as the structural layer for movable micromechanical structures. By utilizing the characteristic of the buried oxide layer in the SOI wafer as an etch stop layer, precise control of the thickness of the micromechanical structure can be achieved.

[0005] (2) Anisotropic Chemical Etching and Deep Silicon Etching: Anisotropic chemical etching (such as KOH wet etching) and deep reactive ion etching (DRIE, also known as deep silicon etching) can be used to fabricate microstructures with high aspect ratio vertical sidewalls. DRIE technology uses the Bosch process, which alternates etching and passivation steps to etch trenches and holes hundreds of micrometers deep in silicon materials. It is a core technology for fabricating movable parts such as MEMS comb structures, mass blocks, and elastic beams.

[0006] (3) Self-stop etching technology: Using the buried oxide layer of SOI wafer as the stop layer for electrochemical or chemical etching, the etching process can be precisely stopped at the buried oxide layer position, ensuring the uniformity of device layer thickness and the accuracy of etching depth, and avoiding damage to the device structure caused by over-etching.

[0007] (4) Wafer bonding technology: Through technologies such as silicon-silicon direct bonding, silicon-glass anodic bonding, or silicon-metal eutectic bonding, two or more wafers are permanently connected in a vacuum or controlled atmosphere environment to achieve three-dimensional integration and wafer-level vacuum packaging of MEMS devices. Wafer-level packaging can maintain a stable vacuum level in the working cavity of the device, thereby reducing the impact of air damping on the movement of movable structures and improving the quality factor of the device.

[0008] By combining the above technologies, existing processes can manufacture MEMS micromechanical structures with micron-level precision, and at the same time realize high-precision, high-efficiency, and mass production of MEMS devices at the wafer level.

[0009] In terms of specific device structure, existing MEMS inertial devices (including gyroscopes and accelerometers) typically employ a single-layer movable mass structure. In this structure, the mass, comb teeth, and elastic support beams are formed in one step within the same plane from the same structural layer (i.e., the top silicon layer of the SOI wafer) through deep silicon etching. The mass is connected to anchor points via the elastic beams and suspends above the substrate. Under external inertial forces, it can displace along the sensitive direction, causing a change in the capacitance gap between the movable and fixed comb teeth. Inertial signals are obtained by detecting the change in capacitance. The fixed comb teeth are typically fixed to the substrate via anchor points, and their electrical signals are led out through metal wiring in the anchor point area.

[0010] Although the existing MEMS inertial device fabrication technologies mentioned above are relatively mature and have achieved industrial application to a certain extent, the following obvious technical defects and shortcomings still exist when facing high-performance navigation applications: Firstly, sensitivity improvement is limited by the highly uniform nature of single-layer structures. In existing inertial devices, the movable micromechanical structure has a uniform height (i.e., the thickness of the top silicon layer), typically ranging from 3 micrometers to 100 micrometers. Given a specific chip area, the number of comb teeth that can be arranged in a single-layer mass block structure is limited by the thickness of the structural layer and the aspect ratio capability of the etching process. With the ever-increasing performance requirements of inertial devices, existing single-layer structures cannot significantly increase the number of comb teeth within a limited area, leading to a bottleneck in improving capacitance variation and limiting further improvements in device sensitivity.

[0011] Secondly, increasing the mass size to enhance sensitivity comes at an excessive cost. To increase device sensitivity and reduce mechanical and thermal noise, current technologies often use mass sizes of hundreds or even thousands of micrometers. However, simply increasing the mass size significantly increases the area occupied by a single chip, reducing the number of chips that can be cut from each wafer, thus increasing material costs and hindering mass production and cost control. Furthermore, excessively large mass sizes are prone to generating significant stress during movement, affecting the long-term reliability and overload resistance of the device.

[0012] Thirdly, the mechanical thermal noise suppression capability is insufficient. According to thermodynamic principles, the mechanical thermal noise of MEMS inertial devices is inversely proportional to the equivalent mass of the mass block and directly proportional to the damping coefficient and operating temperature. In existing single-layer mass block structures, the effective mass of the mass block is limited by the product of the structural layer thickness and the planar area, making it difficult to effectively increase the mass without increasing the chip area. This results in the difficulty of further reducing the mechanical thermal noise level, limiting the application of the device in high-precision navigation scenarios.

[0013] Fourthly, the electrical connection scheme introduces additional parasitic effects. In existing technologies, the electrical signals of movable micromechanical structures typically need to be led out during the packaging stage after chip dicing through methods such as wire bonding or gold wire ball bonding. The wires themselves introduce parasitic inductance and capacitance, affecting the quality of high-frequency signals. At the same time, the electrical connection process during the packaging stage increases packaging costs and process complexity, which is not conducive to reducing overall costs.

[0014] Fifthly, the single-layer structure limits the improvement of device integration. As MEMS inertial devices continue to develop towards miniaturization and integration, single-layer micromechanical structures can no longer meet the dual requirements of functional integration and performance improvement within a limited area. There is an urgent need to develop new three-dimensional structures to break through the limitations of the existing technological framework.

[0015] In summary, existing MEMS inertial device fabrication technologies have significant shortcomings in terms of sensitivity improvement, noise suppression, cost control, and electrical connectivity. There is an urgent need for a new device structure and fabrication method to achieve a significant increase in the number of comb teeth and a significant improvement in sensitivity within a limited chip area, thereby meeting the urgent needs of high-performance inertial navigation applications for MEMS inertial devices. Summary of the Invention

[0016] The purpose of this invention is to provide a method for fabricating a MEMS double-layer mass block inertial device and the inertial device itself in order to solve the above-mentioned technical problems.

[0017] To achieve the above objectives, the present invention specifically adopts the following technical solution: One aspect of the present invention provides a method for fabricating a MEMS double-layer mass block inertial device, comprising the following steps: S1. A first wafer is provided, which includes a bottom silicon layer, a buried oxide layer and a top silicon layer from bottom to top. The first wafer is cleaned and a first oxide layer is formed on the surface of the top silicon layer. S2. Photolithographically define the first microstructure pattern on the first oxide layer, etch away part of the first oxide layer to form the first etching window, and perform deep silicon etching on the top silicon layer through the first etching window to the buried oxide layer to form the first movable micromechanical structure layer. S3. Remove the remaining first oxide layer from the top silicon surface; S4. Provide a second wafer, etch a first cavity on one surface of the second wafer, and arrange a first metal wiring layer on the unetched surface of the first cavity on the same side of the second wafer. S5. Align the first wafer processed by steps S1 to S3 with the second wafer processed by step S4, so that the top silicon side faces the side of the second wafer with the first cavity and the first metal wiring layer, and perform vacuum bonding to seal the first movable micromechanical structure layer inside the first cavity. S6. Polish the bonded wafer from the bottom silicon side of the first wafer to thin the bottom silicon to a first predetermined thickness. S7. A third oxide layer is formed on the thinned bottom silicon surface. A first electrical connection pattern is defined by photolithography on the second wafer. Part of the second wafer is etched away to form a first window. The second wafer is etched through the first window to form a first tapered blind hole. The first tapered blind hole penetrates the second wafer and exposes the first metal wiring layer. S8. Deposit metal in the first tapered blind via and on the bottom silicon surface to form a second metal wiring layer. The second metal wiring layer is electrically connected to the first metal wiring layer through the first tapered blind via. S9. Photolithographically define the second microstructure pattern on the third oxide layer, etch away part of the third oxide layer to form a second etching window, and perform deep silicon etching on the bottom silicon through the second etching window to the buried oxide layer to form a second movable micromechanical structure layer. S10. Then remove the remaining third oxide layer and partially etch the buried oxide layer to release the second movable micromechanical structure layer, so that the second mass block and the second comb structure can move freely. S11. A second cavity is etched on one surface of the third wafer, and a third metal wiring layer is arranged on the unetched surface of the second cavity on the same side of the third wafer. S12. Align and bond the bottom silicon side of the wafer obtained in step S10 with the third wafer to seal the second movable micromechanical structure layer in the second cavity. S13. Polish the bonded wafer from one side of the third wafer to thin the third wafer to a second predetermined thickness, and form a second tapered blind hole on the thinned third wafer. The second tapered blind hole penetrates the third wafer and exposes the third metal wiring layer. S14. Deposit metal in the second tapered blind via and on the surface of the third wafer to form a fourth metal wiring layer. The fourth metal wiring layer is electrically connected to the third metal wiring layer through the second tapered blind via.

[0018] In one embodiment, in step S2, the first movable micromechanical structure layer includes a first mass block and a first comb structure connected to the first mass block; In step S9, the second movable micromechanical structure layer includes a second mass block and a second comb structure connected to the second mass block; The first and second comb tooth structures are arranged vertically in a direction perpendicular to the wafer surface, forming a double-layer comb tooth capacitor structure. When external inertia occurs, the first and second mass blocks are displaced simultaneously, and the capacitance changes of the upper and lower comb teeth are in the same direction and superimposed on each other.

[0019] In one embodiment, the first oxide layer in step S1 and the third oxide layer in step S7 are both silicon dioxide layers formed by thermal oxidation or deposition processes, and the thickness of the silicon dioxide layer is 100 nanometers to 3 micrometers.

[0020] In one embodiment, in step S6, the first predetermined thickness is 10 micrometers to 100 micrometers; in step S9, when deep silicon etching is performed on the bottom silicon to the buried oxide layer, the etching depth of the bottom silicon is equal to the first predetermined thickness.

[0021] In one embodiment, in steps S8 and S14, both the second metal wiring layer and the fourth metal wiring layer are multilayer metal layers. The multilayer metal layer includes a diffusion barrier layer located at the bottom and a conductive layer located on the diffusion barrier layer. The material of the diffusion barrier layer is selected from one or more of Ta, TaN / Ta, TiN, TiW, Cr, and Ti, and the material of the conductive layer is selected from one or more of Au, Cu, and Al.

[0022] In one embodiment, in steps S5 and S12, the alignment bonding method is silicon-metal eutectic bonding or silicon-silicon melt bonding, and the bonding interface is subjected to plasma activation treatment or wet activation treatment before bonding.

[0023] In one embodiment, in step S7, the sidewall of the first tapered blind hole is inclined at an angle of 45° to 85° to the surface of the underlying silicon; in step S13, the sidewall of the second tapered blind hole is inclined at an angle of 45° to 85° to the surface of the third wafer.

[0024] In one embodiment, in step S7, the process of etching the bottom silicon to form the first tapered blind hole is deep silicon etching or wet etching; in step S13, the process of etching the third wafer to form the second tapered blind hole is deep silicon etching or wet etching.

[0025] The second aspect of this invention provides a MEMS double-layer mass block inertial device, which is fabricated using the above-described MEMS double-layer mass block inertial device fabrication method.

[0026] In one implementation, the MEMS dual-layer mass block inertial device is a MEMS gyroscope or a MEMS accelerometer.

[0027] The beneficial effects of this invention are as follows: 1. Significantly Improved Sensitivity: This invention forms a first movable micromechanical structure layer and a second movable micromechanical structure layer in the top and bottom silicon layers of an SOI wafer, respectively. These two layers are stacked vertically, with the first and second comb-tooth structures corresponding vertically to form a double-layer comb-tooth capacitor structure. When subjected to external inertial forces, the first and second mass blocks displace simultaneously, and the capacitance changes of the upper and lower comb layers are in the same direction and superimposed. Compared to a single-layer mass block structure, this invention achieves a multiple increase in the number of comb teeth within the same chip area, and the total capacitance change is approximately twice that of a single-layer structure, thereby effectively improving the device's sensitivity. It is particularly suitable for applications requiring high detection capabilities for weak inertial signals.

[0028] 2. Significantly Reduced Noise Level: This invention employs a dual-layer mass block structure. The two mass blocks are mechanically independent but jointly respond to external inertial forces, significantly increasing the equivalent total mass. Based on the mechanical thermal noise formula (the thermal noise acceleration spectral density is inversely proportional to the square root of the equivalent mass), the mechanical thermal noise level of the device is significantly reduced. The lower noise floor allows the device to resolve finer inertial signals, facilitating high-precision, low-noise inertial signal detection and meeting the stringent requirements of high-performance inertial navigation systems.

[0029] 3. High chip area utilization and high integration: This invention stacks two layers of movable micromechanical structures in the vertical direction (wafer thickness direction), achieving a doubling of comb tooth quantity and sensitivity without needing to increase chip area in the horizontal direction. Compared with the traditional approach of increasing the number of comb teeth by increasing chip area in a single-layer plane, this invention fully utilizes the wafer thickness space, significantly improving device performance while maintaining or reducing chip size, which is beneficial for device miniaturization and high-density integration.

[0030] 4. High self-stop etching precision using SOI wafers: This invention uses SOI wafers as the first wafer and leverages the extremely high etching selectivity between the buried oxide layer (silicon dioxide) and silicon material in deep reactive ion etching to achieve precise self-stop control of the etching depth of the top and bottom silicon layers. This method avoids the inconsistency in device performance caused by uneven etching depth in traditional processes, ensuring high uniformity and consistency of etching depth within and between wafers, significantly improving device manufacturing yield and performance consistency.

[0031] 5. Vacuum bonding ensures high device quality factor: In this invention, the first and second movable micromechanical structure layers are sealed inside the first and second cavities respectively in a vacuum environment through silicon-metal eutectic bonding. The vacuum sealing environment effectively reduces air damping during the movement of the movable structure, enabling the device to achieve a high quality factor (Q value), further reducing mechanical thermal noise, and improving the frequency response characteristics and stability of the device.

[0032] 6. Reasonable electrical lead layout and convenient signal extraction: This invention bonds a second and third wafer to both sides of a first wafer (SOI wafer), and utilizes a tapered blind via structure penetrating the second and third wafers in conjunction with a multilayer metal wiring layer to guide the electrical signals of the first and second movable micromechanical structure layers to the back sides of the second and third wafers, respectively. The inclined sidewalls (45°~85°) of the tapered blind vias facilitate uniform coverage of the metal layers, ensuring the continuity and reliability of the electrical connections. The signals from the upper and lower layers can be extracted independently, facilitating superposition or differential processing by external differential detection circuits to achieve common-mode noise suppression and signal multiplication.

[0033] 7. Strong process compatibility, suitable for mass production: Each step of this invention adopts mature semiconductor microfabrication processes (such as RCA cleaning, thermal oxidation, photolithography, deep reactive ion etching, physical vapor deposition / magnetron sputtering, silicon-metal eutectic bonding, polishing, etc.), which are highly compatible with the process capabilities of existing MEMS foundry production lines. There is no need to purchase special equipment or develop new process modules, which has good industrialization feasibility and economic efficiency for mass production.

[0034] 8. Mechanical independence and electrical isolation of the two-layer mass blocks: In this invention, the first mass block and the second mass block are independently suspended and supported by their respective elastic beam systems. The two do not interfere with each other mechanically, avoiding cross interference caused by mechanical coupling. At the same time, the two-layer structure achieves electrical isolation through the intermediate buried oxide layer (silicon dioxide insulating layer), and is electrically independent of each other. Signal detection can be performed separately, or differential or superimposed combinations can be achieved through external circuits as needed, which provides high design flexibility.

[0035] 9. Wide range of applications: The MEMS double-layer mass block inertial device prepared by this invention can be widely used in the manufacture of MEMS gyroscopes and MEMS accelerometers. It is especially suitable for high-performance inertial navigation, attitude measurement, autonomous positioning of unmanned systems, precision industrial control and other high-end application scenarios with strict requirements for sensitivity and noise level. It has broad market prospects and important engineering application value. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained from these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the structure of the first wafer in step S1 of Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the structure of the first movable micromechanical structure layer formed in step S2 of embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the structure after removing the oxide layer in step S3 of embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the structure of the second wafer forming the first cavity in step S4 of embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the structure of the second wafer forming the first metal wiring layer in step S5 of embodiment 1 of the present invention; Figure 6 This is a schematic diagram of the structure after the first wafer and the second wafer are bonded in step S6 of embodiment 1 of the present invention; Figure 7 This is a schematic diagram of the structure for thinning and forming the first conical blind hole in steps S7 and S8 of Embodiment 1 of the present invention; Figure 8 This is a schematic diagram of the structure for forming the second metal wiring layer in step S9 of embodiment 1 of the present invention; Figure 9 This is a schematic diagram of the structure after the oxide layer is deposited in step S10 of Embodiment 1 of the present invention; Figure 10 This is a schematic diagram of the structure in step S11 of embodiment 1 of the present invention for forming the second movable micromechanical structure layer; Figure 11 This is a schematic diagram of the structure for releasing the second movable micromechanical structure layer in step S12 of embodiment 1 of the present invention; Figure 12 This is a schematic diagram of the structure of the third wafer in step S13 of Embodiment 1 of the present invention; Figure 13 This is a schematic diagram of the structure after bonding in step S14 of embodiment 1 of the present invention; Figure 14 This is a schematic diagram of the structure forming the electrical connection in steps S15 and S16 of Embodiment 1 of the present invention.

[0038] Figure label: 101—Top layer silicon; 102—Buried oxygen layer; 103a—First oxide layer; 103b—Second oxide layer; 103c—Third oxide layer; 104a—First comb tooth structure; 104b—Second comb tooth structure; 201—Second wafer; 202—First cavity; 203—First metallic wiring layer; 204—First conical blind hole; 205—Second metal wiring layer; 301—Third wafer; 302—Second cavity; 303—Third metal wiring layer; 304—Second conical blind hole; 305—Fourth metal wiring layer. Detailed Implementation

[0039] To make the technical problems, technical solutions, and technical effects of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0040] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0041] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0042] In the description of the embodiments of the present invention, it should be noted that the terms "inner", "outer", "upper", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting the present invention.

[0043] Example 1 This embodiment provides a method for fabricating a MEMS double-layer mass block inertial device, including the following steps: S1. Cleaning and oxidation of the first wafer: like Figure 1 As shown, a first wafer is selected, which is an SOI type wafer. The SOI wafer consists of three layers: a bottom silicon layer (i.e., the bottom bulk silicon), a buried oxide layer 102, and a top silicon layer 101 (i.e., the top device layer). The top silicon layer 101 serves as the structural material layer for subsequent movable micromechanical structures. In this embodiment, the total thickness of the SOI wafer is 300 micrometers to 400 micrometers, and the thickness of the top silicon layer 101 is 10 micrometers to 100 micrometers. The specific thickness is adjusted according to the comb height required by the device design.

[0044] First, the SOI wafer is cleaned using the standard RCA cleaning procedure in semiconductor processes to remove organic contaminants, metal ions, and particulate impurities from the wafer surface, resulting in a clean wafer surface. After cleaning, the SOI wafer undergoes thermal oxidation, simultaneously forming silicon dioxide oxide layers (i.e., the first oxide layer) on both the top silicon 101 surface and the bottom silicon back side, as shown in the figure: first oxide layer 103a (top silicon 101 surface) and second oxide layer 103b (bottom silicon back side). The thicknesses of the first oxide layer 103a and the second oxide layer are 100 nanometers to 3 micrometers, respectively. These first oxide layers 103a and 103b serve as hard masks in subsequent deep silicon etching processes, exhibiting good etching selectivity for silicon. Depending on the required oxide layer thickness, the oxidation process can employ dry oxidation, wet oxidation, or a combination of both.

[0045] S2: Front-side photolithography and deep silicon etching form the first movable micromechanical structure layer: like Figure 2 As shown, the oxidized SOI wafer is cleaned, and then photoresist is coated on the first oxide layer 103a on the surface of the top silicon 101. The first microstructure pattern is defined by photolithography. The thickness of the photoresist is generally more than 1 micrometer to ensure sufficient pattern transfer protection for the oxide layer during subsequent etching.

[0046] After development, the silicon dioxide in the patterned area is removed using dry etching (such as reactive ion etching, RIE) or wet etching (such as BOE buffered oxide etchant) to form the first etching window, exposing the surface of the top silicon layer 101 in the etching window area. Subsequently, using the remaining first oxide layer 103a as a hard mask, deep reactive ion etching (DRIE, also known as deep silicon etching) is performed on the exposed top silicon layer 101 through the first etching window. The etching depth penetrates the entire thickness of the top silicon layer 101 until it reaches the buried oxide layer 102 and stops. Since the buried oxide layer 102 is made of silicon dioxide, it has an extremely high etching selectivity with silicon. The deep silicon etching terminates naturally when it reaches the buried oxide layer, thus precisely ensuring the uniformity and consistency of the etching depth.

[0047] This step forms a first movable micromechanical structure layer in the top silicon layer 101. This structure layer includes a first mass block, a first comb tooth structure 104a connected to the first mass block, and microstructures such as elastic beams and fixed anchor points for supporting the mass block. The first mass block is suspended and supported by the elastic beams and can be displaced along the sensitive direction under the action of inertial force; the movable comb teeth in the first comb tooth structure 104a move together with the mass block and form a variable capacitance gap with the fixed comb teeth.

[0048] S3. Remove the front oxide layer: like Figure 3 As shown, after deep silicon etching is completed, the photoresist on the surface of the first wafer is removed and cleaned. Then, wet etching (such as BOE solution) or dry etching (such as fluorine-based gas RIE) is used to remove the remaining first oxide layer 103a on the surface of the top silicon 101. In this step, it is only necessary to completely remove the silicon dioxide on the surface of the top silicon 101. The buried oxide layer 102 located between the top silicon 101 and the bottom silicon can be partially etched or completely retained. In this embodiment, it is preferable to retain the full thickness of the buried oxide layer 102 so that it can continue to serve as an etching stop layer in subsequent back-side processes, while protecting the first movable micromechanical structure from damage during subsequent processing.

[0049] S4, Cavity etching of the second wafer 201: like Figure 4As shown, a second wafer 201 is selected, which is a single-crystal silicon wafer. First, the second wafer 201 is cleaned using a standard RCA cleaning procedure. After cleaning, photoresist is coated on the surface of the second wafer 201, and the cavity pattern is defined by photolithography. Then, deep silicon etching technology is used to etch the second wafer 201 to form the first cavity 202. The depth of the first cavity 202 is determined based on the thickness of the first movable micromechanical structure layer and the required movement stroke, generally set to 10 micrometers to 150 micrometers, ensuring that the first mass block and the first comb structure 104a do not contact the bottom of the first cavity 202 during movement. The planar pattern dimensions of the first cavity 202 match the contour of the first movable micromechanical structure layer to ensure that the subsequent first movable micromechanical structure is completely accommodated inside the first cavity 202.

[0050] S5. Fabrication of the 201 metal wiring layer on the second wafer: like Figure 5 As shown, the second wafer 201, on which the first cavity 202 is etched, is cleaned, and then photoresist is coated on the surface of the second wafer 201 to define the metal wiring pattern by photolithography. Metal material is deposited in the patterned area using processes such as physical vapor deposition (PVD), magnetron sputtering, atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), or electroplating to form the first metal wiring layer 203.

[0051] In this embodiment, the first metal wiring layer 203 is a multilayer metal structure. First, a diffusion barrier layer or adhesion layer is deposited on the silicon surface. This layer can be made of metals such as tantalum (Ta), tantalum nitride / tantalum composite (TaN / Ta), titanium nitride (TiN), titanium-tungsten alloy (TiW), chromium (Cr), or titanium (Ti). Its function is to enhance the adhesion between the metal layer and the silicon substrate and to prevent subsequent conductive metal from diffusing into the silicon substrate. Then, a conductive layer is deposited on the diffusion barrier layer. The conductive layer material can be made of metals with good conductivity, such as gold (Au), copper (Cu), or aluminum (Al). The multilayer metal structure ensures the reliability of the electrical connection and low resistance characteristics.

[0052] S6. First bonding between the first wafer and the second wafer 201: like Figure 6 As shown, the first wafer processed through steps S1 to S3 and the second wafer 201 processed through steps S4 to S5 are cleaned respectively to remove surface particles and contaminants. Then, the two wafers are precisely aligned so that the top silicon 101 side of the first wafer faces the patterned surface of the second wafer 201 (i.e., the side where the first cavity 202 and the first metal wiring layer 203 are formed).

[0053] After alignment, silicon-metal bonding is performed. In this embodiment, a silicon-metal eutectic bonding process is preferably used to form a eutectic alloy layer at the bonding interface to achieve permanent connection. Before bonding, the bonding surfaces of the two wafers are pretreated, for example, by surface activation treatment using oxygen plasma or nitrogen plasma, or by surface activation treatment using a wet chemical solution, to improve the surface activity and bonding strength of the bonding interface. Bonding is performed in a vacuum environment, ensuring a stable vacuum environment in the first cavity 202 after bonding and sealing. After bonding, the first movable micromechanical structure layer is sealed inside the first cavity 202, isolated from the external environment, ensuring low-damping and high-quality factor characteristics of the device operation.

[0054] S7, Underlying silicon thinning: like Figure 7 As shown, the bonded wafer assembly is cleaned, and then polished from the bottom silicon side of the first wafer (i.e., the back side of the SOI wafer). The polishing process consists of three steps: rough grinding, fine grinding, and polishing, reducing the thickness of the bottom silicon layer from an initial approximately 300-400 micrometers to a first predetermined thickness. In this embodiment, the first predetermined thickness is 10-100 micrometers, which determines the thickness of the subsequent second movable micromechanical structure layer. The specific value is determined based on the device design requirements for the height of the second layer's comb teeth.

[0055] During the polishing process, the flatness of the wafer must be strictly controlled to ensure that the wafer does not develop defects such as warping, sagging, surface damage, or edge chipping after processing, thus guaranteeing the accuracy of subsequent photolithography and etching processes. After polishing, the thinned bottom silicon will serve as the structural material for the second movable micromechanical structure layer.

[0056] S8, Backside tapered blind via etching (first through-silicon via): like Figure 7 As shown, the polished wafer is cleaned, and then photoresist is coated on the surface of the second wafer 201. The first electrical connection pattern (i.e., the through-silicon via (TSV) location pattern) is defined by photolithography. Deep silicon etching or wet etching is used to etch the underlying silicon, forming the first tapered blind via 204. Etching continues until the first tapered blind via 204 penetrates the second wafer 201 and exposes the first metal wiring layer 203 on the surface of the second wafer 201.

[0057] In this embodiment, the sidewall of the first tapered blind via 204 is inclined at an angle to the surface of the second wafer 201, preferably between 45° and 85°. The inclined sidewall facilitates the uniform coverage of the subsequent metal layer on the blind via sidewall, ensuring the continuity of electrical connections and avoiding open circuit defects caused by poor step coverage.

[0058] S9. Fabrication of the second metal wiring layer on the back side: like Figure 8As shown, the wafer with the first tapered blind via 204 etched on it is cleaned, and then photoresist is coated on the surface of the second wafer 201 and the inner wall of the first tapered blind via 204. The pattern of the second metal wiring layer is defined by photolithography. Metal material is deposited in the patterned area using processes such as PVD, magnetron sputtering, ALD, PECVD or electroplating to form the second metal wiring layer 205.

[0059] The second metal wiring layer 205 also employs a multilayer metal structure. First, a diffusion barrier layer or adhesion layer (materials selected from Ta, TaN / Ta, TiN, TiW, Cr, Ti, etc.) is deposited, followed by a conductive layer (materials selected from Au, Cu, Al, etc.). The second metal wiring layer 205 directly contacts the first metal wiring layer 203 through the opening region at the bottom of the first tapered blind via 204, thereby achieving electrical conduction. Thus, the electrical signal from the first movable micromechanical structure layer is led to the back side of the second wafer via the first metal wiring layer 203, the metal filling layer within the first tapered blind via 204, and the second metal wiring layer 205, facilitating subsequent connection to external circuits.

[0060] S10, Backside oxide layer deposition: like Figure 9 As shown, the wafer with the second metal wiring layer 205 is cleaned, and then a third oxide layer 103c (silicon oxide layer) is deposited on the bottom silicon surface of the first wafer as a hard mask for subsequent deep silicon etching on the back side. In this embodiment, the deposition thickness of the third oxide layer 103c is 100 nanometers to 3 micrometers, and the specific thickness is determined according to the depth and etching selectivity of the subsequent deep silicon etching. The deposition process can be plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or thermal oxidation, etc.

[0061] S11. Backside photolithography and deep silicon etching form the second movable micromechanical structure layer: like Figure 10 As shown, photoresist is coated on the surface of the deposited third oxide layer 103c, and a second microstructure pattern is defined by photolithography. Dry etching or wet etching is used to remove silicon oxide within the patterned area, forming a second etching window that exposes the underlying silicon surface in the etching window region. Subsequently, using the remaining third oxide layer 103c as a hard mask, deep reactive ion etching (DRIE) is performed on the underlying silicon through the second etching window. The etching depth is the remaining thickness of the underlying silicon after thinning in step S7 (i.e., the first predetermined thickness), until it stops at the buried oxide layer 102.

[0062] This step forms a second movable micromechanical structure layer in the underlying silicon. This layer includes a second mass block, a second comb structure 104b connected to the second mass block, and corresponding elastic beams and anchor points. The second mass block is also suspended and supported by elastic beams, allowing it to displace along the sensitive direction under external inertial forces. Notably, the first comb structure 104a and the second comb structure 104b are arranged vertically in a direction perpendicular to the wafer surface, together forming a double-layer comb capacitor structure. When the first and second mass blocks simultaneously displace under external inertial forces, the capacitance changes of the upper and lower comb layers are superimposed, resulting in a multiplication of the signal output.

[0063] S12, Release the second movable micromechanical structure layer: like Figure 11 As shown, after deep silicon etching is completed, the photoresist on the wafer surface is removed and the wafer is cleaned. Then, wet etching (such as BOE solution) or dry etching (such as gaseous hydrogen fluoride) is used to remove the third oxide layer 103c on the bottom silicon surface, while simultaneously partially etching the buried oxide layer 102. In this step, the etching time needs to be precisely controlled to ensure that the buried oxide layer located below the second movable micromechanical structure layer is completely removed, allowing the second mass block and the second comb structure 104b to be released from the bottom silicon substrate and move freely under external inertia. At the same time, a certain thickness of the buried oxide layer in the region of the first movable micromechanical structure layer can be selectively retained to maintain the supporting stability of the first layer structure.

[0064] After release, both the first movable micromechanical structure layer and the second movable micromechanical structure layer are in a state of free movement. They are isolated from each other by the residual part of the buried oxide layer in the middle or directly by silicon material, and are electrically independent, allowing for signal detection separately.

[0065] Preparation of S13 and the third wafer 301: like Figure 12 As shown, a third wafer 301 is selected, which is a single-crystal silicon wafer. Steps S4 and S5 are repeated, i.e., a second cavity 302 is etched onto the third wafer 301, and a third metal wiring layer 303 is formed on the surface of the third wafer 301. The depth and planar dimensions of the second cavity 302 match the thickness and travel of the second movable micromechanical structure layer. The structure and material of the third metal wiring layer 303 are the same as those of the first metal wiring layer 203, and it is also a multilayer metal structure.

[0066] S14, Second Bonding: like Figure 13As shown, the wafer obtained in step S12 (i.e., the wafer assembly with a double-layer movable micromechanical structure) and the third wafer 301 are cleaned respectively. Then, the bottom silicon side of the wafer obtained in step S12 (i.e., the side with the second movable micromechanical structure layer) is aligned with the patterned side of the third wafer 301 (i.e., the side with the second cavity 302 and the third metal wiring layer 303) and bonded.

[0067] The bonding process is the same as step S6, preferably using silicon-metal eutectic bonding. Before bonding, the bonding surfaces undergo plasma or wet activation pretreatment. Bonding is performed in a vacuum environment, sealing the second cavity 302 to create a vacuum. After bonding, the second movable micromechanical structure layer is sealed inside the second cavity 302, isolated from the external environment, ensuring that both the upper and lower movable structures of the device operate under low-damping vacuum conditions.

[0068] Step S15, Etching of the tapered blind via on the back of the third wafer (second through-silicon via): like Figure 14 As shown, the wafer assembly after the second bonding is polished from one side of the third wafer 301, thinning the third wafer 301 to a second predetermined thickness (typically 50 micrometers to 200 micrometers). After polishing and cleaning, photoresist is coated on the back side of the third wafer 301, and the second electrical connection pattern is defined by photolithography. A second tapered blind via 304 is formed using deep silicon etching or wet etching until the third metal wiring layer 303 is exposed. The sidewall tilt angle of the second tapered blind via 304 is also preferably 45° to 85° to ensure the continuity of the metal layer coverage.

[0069] S16, Fabrication of the fourth metal wiring layer on the back side of the third wafer: like Figure 14 As shown, metal is deposited within the second tapered blind via 304 and on the surface of the third wafer 301 to form a fourth metal wiring layer 305. The fourth metal wiring layer 305 is electrically connected to the third metal wiring layer 303 through the second tapered blind via 304, thereby guiding the electrical signals of the second movable micromechanical structure layer to the back side of the third wafer, realizing an external electrical interface. The material and structure of the fourth metal wiring layer 305 are the same as those of the second metal wiring layer 205.

[0070] Device working principle: Through the processing steps S1 to S16 described above, a MEMS dual-layer mass block inertial device is finally formed. The core structural feature of this device is that a first movable micromechanical structure layer and a second movable micromechanical structure layer are formed in the top silicon 101 and bottom silicon of the SOI wafer, respectively. The two structures are stacked in the vertical direction (i.e., the wafer thickness direction) and electrically isolated by the buried oxide layer in between. The first mass block and the second mass block are suspended and supported by their respective elastic beam systems. They are mechanically independent of each other, but both are displaced by external inertial forces.

[0071] When an external acceleration or angular velocity is applied to the device, the first and second mass blocks are displaced along the sensitive direction under the action of inertial force. The first mass block causes the movable comb teeth in the first comb structure 104a to displace relative to the fixed comb teeth, resulting in a change in the gap of the first layer of comb teeth capacitors, and thus a change in the capacitance value of the first layer. At the same time, the second mass block causes the movable comb teeth in the second comb structure 104b to displace relative to the fixed comb teeth, causing a change in the capacitance value of the second layer. Since the first comb structure 104a and the second comb structure 104b are arranged correspondingly in the vertical direction, the direction of their capacitance changes is the same. After being led out through the first metal wiring layer 203, the second metal wiring layer 205, the third metal wiring layer 303, and the fourth metal wiring layer 305, they can be superimposed or differentially processed by an external differential detection circuit.

[0072] Compared to a single-layer mass block structure, the dual-layer mass block structure of this invention achieves a multiple increase in the number of comb teeth within the same chip area, and the total capacitance change is approximately twice that of the single-layer structure, thereby effectively improving the device's sensitivity. Simultaneously, the equivalent total mass of the dual-layer mass block is significantly increased, and according to the mechanical thermal noise formula, the device's mechanical thermal noise level is significantly reduced, which is beneficial for achieving high-precision, low-noise inertial signal detection.

[0073] The MEMS dual-layer mass block inertial device prepared by this invention can be widely used in the fabrication of MEMS gyroscopes and MEMS accelerometers, and is especially suitable for high-performance inertial navigation applications with stringent requirements for sensitivity and noise levels.

Claims

1. A method for fabricating a MEMS double-layer mass block inertial device, characterized in that, Includes the following steps: S1. A first wafer is provided, which includes a bottom silicon layer, a buried oxide layer and a top silicon layer from bottom to top. The first wafer is cleaned and a first oxide layer is formed on the surface of the top silicon layer. S2. A first microstructure pattern is defined by photolithography on the first oxide layer, and a portion of the first oxide layer is etched away to form a first etching window. The top silicon layer is then deeply etched through the first etching window to the buried oxide layer to form a first movable micromechanical structure layer. The first movable micromechanical structure layer includes a first mass block and a first comb structure connected to the first mass block. S3. Remove the remaining first oxide layer from the surface of the top silicon layer; S4. Provide a second wafer, etch a first cavity on one surface of the second wafer, and arrange a first metal wiring layer on the unetched surface of the first cavity on the same side of the second wafer. S5. Align the first wafer processed in steps S1 to S3 with the second wafer processed in step S4, so that the top silicon side faces the side of the second wafer with the first cavity and the first metal wiring layer, and perform vacuum bonding so that the first movable micromechanical structure layer is sealed inside the first cavity. S6. Polish the bonded wafer from the bottom silicon side of the first wafer to thin the bottom silicon to a first predetermined thickness. S7. A third oxide layer is formed on the thinned bottom silicon surface, a first electrical connection pattern is defined by photolithography on the second wafer, a portion of the second wafer is etched away to form a first window, and the second wafer is etched through the first window to form a first tapered blind hole, which penetrates the second wafer and exposes the first metal wiring layer. S8. Deposit metal in the first tapered blind via and on the surface of the bottom silicon layer to form a second metal wiring layer. The second metal wiring layer is electrically connected to the first metal wiring layer through the first tapered blind via. S9. A second microstructure pattern is defined by photolithography on the third oxide layer, and a portion of the third oxide layer is etched away to form a second etching window. The underlying silicon is then deeply etched through the second etching window to the buried oxide layer to form a second movable micromechanical structure layer. The second movable micromechanical structure layer includes a second mass block and a second comb structure connected to the second mass block. The first comb structure and the second comb structure are arranged vertically in a direction perpendicular to the wafer surface to form a double-layer comb capacitor structure. S10. Then remove the remaining third oxide layer and partially etch the buried oxide layer to release the second movable micromechanical structure layer, so that the second mass block and the second comb structure can move freely. S11. A second cavity is etched on one surface of the third wafer, and a third metal wiring layer is disposed on the surface of the second cavity that is not etched on the same side of the third wafer. S12. Align and bond the bottom silicon side of the wafer obtained in step S10 with the third wafer to seal the second movable micromechanical structure layer in the second cavity. S13. Polish the bonded wafer from one side of the third wafer to thin the third wafer to a second predetermined thickness, and form a second tapered blind hole on the thinned third wafer. The second tapered blind hole penetrates the third wafer and exposes the third metal wiring layer. S14. Deposit metal in the second tapered blind via and on the surface of the third wafer to form a fourth metal wiring layer, wherein the fourth metal wiring layer is electrically connected to the third metal wiring layer through the second tapered blind via.

2. The method for fabricating a MEMS double-layer mass block inertial device according to claim 1, characterized in that, In step S2, when external inertia occurs, the first mass block and the second mass block are displaced simultaneously, and the capacitance changes of the upper and lower comb teeth are in the same direction and superimposed on each other.

3. The method for fabricating a MEMS double-layer mass block inertial device according to claim 1, characterized in that, The first oxide layer in step S1 and the third oxide layer in step S7 are both silicon dioxide layers formed by thermal oxidation or deposition processes, and the thickness of the silicon dioxide layer is 100 nanometers to 3 micrometers.

4. The method for fabricating a MEMS double-layer mass block inertial device according to claim 1, characterized in that, In step S6, the first predetermined thickness is 10 micrometers to 100 micrometers; in step S9, when the bottom silicon is deep etched to the buried oxide layer, the etching depth of the bottom silicon is equal to the first predetermined thickness.

5. The method for fabricating a MEMS double-layer mass block inertial device according to claim 1, characterized in that, In steps S8 and S14, the second metal wiring layer and the fourth metal wiring layer are both multilayer metal layers. The multilayer metal layer includes a diffusion barrier layer at the bottom and a conductive layer on the diffusion barrier layer. The material of the diffusion barrier layer is selected from one or more of Ta, TaN / Ta, TiN, TiW, Cr, and Ti. The material of the conductive layer is selected from one or more of Au, Cu, and Al.

6. The method for fabricating a MEMS double-layer mass block inertial device according to claim 1, characterized in that, In steps S5 and S12, the alignment bonding method is silicon-metal eutectic bonding or silicon-silicon melt bonding, and the bonding interface is subjected to plasma activation treatment or wet activation treatment before bonding.

7. The method for fabricating a MEMS double-layer mass block inertial device according to claim 1, characterized in that, In step S7, the sidewall of the first tapered blind hole is inclined at an angle to the surface of the underlying silicon, and the inclined angle is 45°~85°; in step S13, the sidewall of the second tapered blind hole is inclined at an angle to the surface of the third wafer, and the inclined angle is 45°~85°.

8. The method for fabricating a MEMS double-layer mass block inertial device according to claim 1, characterized in that, In step S7, the process of etching the bottom silicon to form the first tapered blind hole is deep silicon etching or wet etching; in step S13, the process of etching the third wafer to form the second tapered blind hole is deep silicon etching or wet etching.

9. A MEMS dual-layer mass block inertial device, characterized in that, It is fabricated using the MEMS double-layer mass block inertial device fabrication method described in any one of claims 1 to 8.

10. The MEMS dual-layer mass block inertial device according to claim 9, characterized in that, The MEMS dual-layer mass block inertial device is a MEMS gyroscope or a MEMS accelerometer.

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