Membrane device and method for manufacturing a membrane device, electronic device

Abstract

The application relates to the technical field of micro electro mechanical system, and discloses a MEMS device, a preparation method thereof, and an electronic device, and the preparation method of the MEMS device comprises the following steps: providing a target structure, wherein the target structure comprises, from bottom to top, a handle substrate layer, an insulating oxide layer and a device layer which are stacked in sequence; forming an opening pattern in a predetermined area on the surface of the device layer, and based on the opening pattern, etching downward from the surface of the device layer to form an etching channel, wherein the etching channel penetrates through the device layer, the insulating oxide layer and the handle substrate layer to expose the handle substrate layer; and filling the etching channel with conductive material to form a longitudinal conductive path. The application improves the reliability of the MEMS device.

Description

Technical Field

[0001] This application relates to the field of microelectromechanical systems (MEMS) technology, specifically to a MEMS device and its fabrication method, and electronic devices. Background Technology

[0002] In the field of MEMS device manufacturing, with the continuous improvement of device integration and increasingly stringent performance requirements, the electrical management between functional layers in the substrate structure has become one of the key factors affecting device performance. In MEMS device substrates with back cavities, reference layers, shielding layers, or mechanical support layers, the buried oxide layer naturally blocks the electrical connection between the device layer and the substrate layer. While this insulating isolation characteristic provides convenience for electrical isolation in device design, it also brings problems related to the potential control of the underlying conductive layer. In many accelerometers, pressure sensors, resonators, and other capacitive MEMS devices, if the substrate potential is left floating, it can easily introduce problems such as parasitic capacitance drift, uncertain electrostatic boundary conditions, unstable bottom shielding potential, and deteriorated test repeatability.

[0003] In related technologies, one approach is to fabricate independent pads on the substrate layer and connect the layer to an external fixed potential via wire bonding. While this achieves potential fixation, it requires additional chip area, increases packaging processes and costs, and the parasitic inductance introduced by the wires may also affect the performance of high-frequency devices. Summary of the Invention

[0004] In view of this, this application provides a MEMS device and its fabrication method, as well as an electronic device, to solve the aforementioned technical problems.

[0005] In a first aspect, embodiments of this application disclose a method for fabricating a MEMS device, including: A target structure is provided, the target structure comprising, from bottom to top, a handle substrate layer, an insulating oxide layer and a device layer, stacked sequentially; An opening pattern is formed in a predetermined area on the surface of the device layer, and based on the opening pattern, an etching channel is formed by etching downward from the surface of the device layer. The etching channel penetrates the device layer and the insulating oxide layer to the handle substrate layer to expose the handle substrate layer. The etched channel is filled with conductive material to form a longitudinal conductive path.

[0006] In one possible example, a predetermined region on the surface of the device layer is an inactive region of the device layer that is far from the movable structure.

[0007] In one possible example, the predetermined area on the surface of the device layer is an anchoring area on the device layer, an outer region of the sealing ring on the device layer, or a reserved connection area.

[0008] In one possible example, the etching downwards from the surface of the device layer based on the opening pattern includes: The device layer is etched using dry etching or deep reactive ion etching until the insulating oxide layer is reached, at which point the etching is stopped. The insulating oxide layer is etched using dry etching, wet etching, or a combination of dry and wet etching until the handle substrate is exposed. The etching channels are formed in the form of grooves or through holes.

[0009] In one possible example, after the etching channel penetrates the device layer and the insulating oxide layer, the handle substrate layer continues to be etched to a predetermined over-etch depth to improve ohmic contact.

[0010] In one possible example, the target structure is a standard SOI substrate, an SOI substrate with a pre-defined cavity, an equivalent substrate with an intermediate silicon oxide isolation layer, or a composite substrate in which the standard SOI substrate and the SOI substrate with the pre-defined cavity are fused together.

[0011] In one possible example, the conductive material comprises a metallic material or in-situ heavily doped polycrystalline silicon; and the metallic material comprises at least one of tungsten, copper, aluminum, titanium, titanium nitride, nickel, cobalt, or ruthenium.

[0012] In one possible example, when the conductive material is a metallic material, the structure of the longitudinal conductive path is a multilayer structure consisting of a barrier layer, a seed layer, and a metal layer; and There are multiple longitudinal conductive paths, and the multiple longitudinal conductive paths are arranged in parallel.

[0013] Secondly, embodiments of this application disclose a MEMS device, which is fabricated by the MEMS device fabrication method described in any one of the above embodiments, comprising: The handle substrate layer, insulating oxide layer and device layer are stacked in sequence; The device layer has a movable structure, and a predetermined area on the surface of the device layer has an etching channel. The etching channel is filled with a conductive material to serve as a longitudinal conductive path for potential locking of the handle substrate layer.

[0014] Thirdly, this application discloses an electronic device, which is an accelerometer, gyroscope, pressure sensor or resonator, and the electronic device includes a MEMS device fabricated by the MEMS device fabrication method described in any of the above embodiments.

[0015] In summary, compared with the prior art, this application discloses a MEMS device and its fabrication method, as well as an electronic device. The MEMS device fabrication method includes providing a target structure, which includes a handle substrate layer, an insulating oxide layer, and a device layer stacked sequentially from bottom to top; forming an opening pattern in a predetermined area on the surface of the device layer, and based on the opening pattern, etching downwards from the surface of the device layer to form an etching channel, the etching channel penetrating the device layer and the insulating oxide layer to the handle substrate layer to expose the handle substrate layer; filling the etching channel with a conductive material to form a vertical conductive path.

[0016] By implementing the above configuration, the handle substrate layer, which was originally suspended due to the buried oxide layer isolation, is made equipotentially locked to the reference potential of the device layer. This allows for the establishment of a low-resistance permanent conductive path within the chip without relying on external leads, fundamentally eliminating the physical mechanism of handle substrate layer potential drift. This significantly reduces the impact of parasitic capacitance changes and electrostatic boundary condition uncertainties on device performance. Simultaneously, the vertical conductive structure is built into the inactive area, eliminating the need for additional pad areas on the substrate surface and the need for additional wire bonding processes. This saves chip area, simplifies the packaging process, and reduces manufacturing costs. Furthermore, the internal vertical conductive path replaces external lead connections, significantly shortening the electrical connection path and eliminating parasitic parameters such as lead inductance and capacitance, thereby improving the overall performance of the MEMS device. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of the MEMS device fabrication method of this application; Figure 2 This is a schematic diagram of the structure of the MEMS device in the fabrication process of this application; Figure 3 This is another structural schematic diagram of the MEMS device in the fabrication process of this application; Figure 4 This is a schematic diagram of the structure of the MEMS device in this application. Detailed Implementation

[0019] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the claims.

[0020] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0021] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0022] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0023] In the description of this application, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0024] The technical solutions shown in this application will be described in detail below through specific embodiments. It should be noted that the order of description of the following embodiments is not intended to limit the priority of the embodiments.

[0025] Please refer to Figure 1 This application provides a method for fabricating a MEMS device, including: S101 provides a target structure, which includes a handle substrate layer, an insulating oxide layer and a device layer stacked sequentially from bottom to top.

[0026] S102, an opening pattern is formed in a predetermined area on the surface of the device layer, and based on the opening pattern, an etching channel is formed by etching downward from the surface of the device layer. The etching channel penetrates the device layer and the insulating oxide layer to the handle substrate layer to expose the handle substrate layer.

[0027] S103, fills the etched channel with conductive material and forms a longitudinal conductive path.

[0028] This allows for equipotential locking between the handle substrate, which was previously suspended due to the buried oxide layer isolation, and the device layer reference potential. A low-resistance, permanent conductive path can be established within the chip without relying on external leads, fundamentally eliminating the physical mechanism of handle substrate potential drift. This significantly reduces the impact of parasitic capacitance changes and electrostatic boundary condition uncertainties on device performance. Furthermore, the vertical conductive structure is entirely integrated into the inactive area, eliminating the need for additional pads on the substrate surface and wire bonding processes, thus saving chip area, simplifying the packaging process, and reducing manufacturing costs. The internal vertical conductive path replaces external lead connections, significantly shortening the electrical connection path and eliminating parasitic parameters such as lead inductance and capacitance, thereby improving the overall performance of the MEMS device.

[0029] The following is combined with Figures 2 to 4 The following provides a detailed description of each fabrication step in the MEMS device fabrication method according to the embodiments of this application.

[0030] refer to Figure 2 A target structure is provided, comprising, from bottom to top, a handle substrate layer 1, an insulating oxide layer 2, and a device layer 3, stacked sequentially.

[0031] In the specific implementation process, device layer 3 can be a single crystal silicon layer, and its thickness can be selected in the range of 10μm to 100μm according to the design requirements of MEMS device; insulating oxide layer 2 is silicon dioxide layer (i.e., BOX layer), and its thickness can be selected in the range of 0.5μm to 3μm, for example, to achieve electrical isolation between device layer 3 and handle substrate layer 1; handle substrate layer 1 is a silicon substrate, which serves as both the mechanical support layer of the whole wafer and the back cavity layer or reference potential layer of MEMS device.

[0032] In one example, a cavity may be pre-formed on the side of the handle substrate 1 near the device layer 3 to provide physical space for the subsequently released movable structure. This cavity can be formed by photolithography and deep reactive ion etching (DRIE) on the surface of the handle substrate 1 before bonding, and then bonded to the device layer 3 via fusion bonding. In other alternative embodiments, the target structure can also be a standard SOI substrate, where the side of the handle substrate 1 near the device layer 3 is a flat surface without a pre-formed cavity.

[0033] Continue to refer to Figure 2 An opening pattern is formed in a predetermined area on the surface of device layer 3, and based on the opening pattern, etching is performed downward from the surface of device layer 3 to form an etching channel 4. The etching channel 4 penetrates through device layer 3 and insulating oxide layer 2 to handle substrate layer 1 to expose handle substrate layer.

[0034] In the specific implementation process, a photoresist mask or hard mask (such as a silicon oxide mask or a silicon nitride mask) can be formed in a predetermined area on the surface of device layer 3, and the opening pattern can be defined by photolithography.

[0035] Optionally, the shape of the opening pattern can be any of the following: circular hole, strip groove, annular groove, trench array, or multi-hole parallel structure, and its width or diameter can be selected in the range of, for example, 5 μm to 50 μm, according to the layout space and conductivity requirements of the MEMS device.

[0036] Then, based on the opening pattern, etching is performed downwards from the surface of device layer 3. In a preferred example, this etching step specifically includes: First, device layer 3 is etched using a dry etching method. Preferably, deep reactive ion etching (DRIE) can also be used to etch device layer 3 with a high aspect ratio until the insulating oxide layer 2 is reached, at which point the etching stops. DIE can create an etching morphology with steep sidewalls and a high aspect ratio, which is beneficial for the uniform filling of subsequent conductive materials. The etching gas can be SF6 / O2 or C4F8 / SF6, etc., which are etching / passivation gases based on alternating sidewall passivation deep silicon etching processes.

[0037] Next, the insulating oxide layer 2 is etched using dry etching, wet etching, or a combination of dry and wet etching to remove at least a portion of the insulating oxide layer 2 within a predetermined area, thereby exposing the surface of the handle substrate layer 1. In this embodiment, the removal of the insulating oxide layer 2 can be achieved using a selective silicon oxide etching process. Specifically, dry etching, such as reactive ion etching based on a fluorocarbon system (e.g., CF4 or CHF3), can be used to precisely remove the insulating oxide layer 2 in the exposed area by utilizing the high etching selectivity between silicon oxide and silicon (typically, the silicon oxide to silicon etching selectivity ratio is greater than 10:1).

[0038] In another alternative embodiment, wet etching may also be used, for example, etching with liquid phase HF solution or buffered oxide etchant (BOE), or a vapor phase HF etching process.

[0039] After etching is completed, an etching channel 4 is formed that penetrates the device layer 3 and the insulating oxide layer 2, and the bottom of the etching channel 4 exposes the surface of the handle substrate layer 1. The etching channel 4 can be in the form of a trench structure or a through-hole structure.

[0040] Preferably, the etched channel 4 adopts a narrow groove or multiple parallel narrow groove structures to reduce the risk of voids in the subsequent conductive filling process and optimize the conductivity reliability.

[0041] In one example, after etching away the insulating oxide layer 2 and exposing the handle substrate layer 1, a slight over-etching can be performed on the surface of the handle substrate layer 1, i.e., the handle substrate layer 1 can be etched to a preset over-etching depth to improve ohmic contact.

[0042] The preset over-etching depth can be, for example, from 0.05 μm to 2 μm, preferably from 0.1 μm to 1 μm. This over-etching step can remove the natural oxide layer and / or etching residue on the surface of the handle substrate 1, exposing a fresh silicon surface, thereby significantly reducing the contact resistance between the subsequent conductive material and the handle substrate 1 and improving the reliability of the ohmic contact. The over-etching depth can be precisely adjusted by controlling the etching time to ensure good contact without excessively damaging the structural strength of the handle substrate 1.

[0043] refer to Figure 3 Conductive material 5 is filled into the etched channel 4 to form a longitudinal conductive path 6.

[0044] Conductive material 5 is filled into the etched channel 4. This conductive material 5 forms physical contact and electrical connection with the sidewall of the device layer 3 and the exposed surface of the handle substrate layer 1, thereby forming a longitudinal conductive path 6. This longitudinal conductive path 6 locks the handle substrate layer 1, which was originally suspended due to isolation by the insulating oxide layer 2, to the reference potential on the device layer 3 side at the same potential.

[0045] Therefore, the reference potential of the handle substrate layer 1, which was originally suspended due to the buried oxide layer isolation, is locked to the reference potential of the device layer 3. A low-resistance permanent conductive path can be established inside the chip without relying on external leads. This fundamentally eliminates the physical mechanism of potential drift of the handle substrate layer 1, significantly reduces the impact of parasitic capacitance changes and electrostatic boundary condition uncertainties on device performance, and the vertical conductive structure (vertical conductive path 6) is completely built into the inactive area, without occupying additional pad area on the substrate surface or adding wire bonding process, thereby saving chip area, simplifying the packaging process, and reducing manufacturing costs. Moreover, the internal vertical conductive path replaces the external lead connection, greatly shortens the electrical connection path, eliminates parasitic parameters such as lead inductance and capacitance, thereby improving the overall performance of MEMS devices.

[0046] Regarding the selection of conductive material 5, this embodiment provides several examples. In one optional embodiment, conductive material 5 is doped polycrystalline silicon, preferably in-situ heavily doped polycrystalline silicon.

[0047] In-situ doping refers to the simultaneous introduction of a dopant gas (such as PH3 or B2H6) during polycrystalline silicon deposition, allowing dopant atoms to be uniformly incorporated into the polycrystalline silicon thin film. Compared to post-deposition diffusion doping, in-situ doping ensures a uniform doping concentration distribution within high aspect ratio etched channels, thereby guaranteeing low and stable resistivity throughout the entire vertical conductive path. The advantages of doped polycrystalline silicon include its high compatibility with silicon-based CMOS and MEMS front-end processes, its ability to withstand subsequent high-temperature processes (such as annealing and oxidation), and its well-matched thermal expansion coefficient with the silicon substrate, reducing the likelihood of interface cracking caused by thermal stress.

[0048] In this embodiment, the conductive material 5 is in-situ heavily doped polycrystalline silicon. The specific filling process is as follows: First, after forming the etched channel 4, the exposed surface of the handle substrate 1 is cleaned to remove etching residues and the native oxide layer. Second, a low-pressure chemical vapor deposition process is used to deposit polycrystalline silicon within the etched channel 4. The deposition temperature can be selected, for example, between 580°C and 650°C, and the reaction gas is silane or dichlorosilane, while a doping gas is introduced simultaneously. For N-type doping, phosphine can be introduced; for P-type doping, borane can be introduced. The doping concentration can be adjusted according to the target resistivity to achieve low resistivity. During the deposition process, since the etched channel 4 has a high aspect ratio, to ensure sufficient filling, a multi-step deposition and etching retreat process (i.e., deposition-etching-deposition cycle) can be used to avoid the formation of voids or gaps inside the channel. Finally, an etching rollback or chemical mechanical polishing process is used to remove excess polysilicon from the surface of device layer 3, restoring the surface of device layer 3 to flatten it, so that subsequent photolithography and MEMS structure release processes can be carried out.

[0049] In another alternative embodiment, the conductive material 5 is a metallic material. The metallic material may include at least one of tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), nickel (Ni), cobalt (Co), and ruthenium (Ru), or a combination layer composed of multiple of the above metals.

[0050] When using metallic materials for filling, chemical vapor deposition or physical vapor deposition combined with electroplating is preferred. Since direct contact between metal and silicon may cause metal contamination or form high-resistivity silicides, in some embodiments, a barrier layer (such as TiN, TaN) and / or a seed layer (such as Ti, Cu) can be formed on the sidewalls and bottom of the etched channel 4 before filling with metal, and then the main metal layer (such as W, Cu) is filled, forming a multilayer composite conductive structure of "barrier layer / seed layer / metal layer".

[0051] That is, when the conductive material 5 is a metallic material, a preferred structure for the longitudinal conductive path 6 is a multi-layer structure consisting of a barrier layer, a seed layer and a metal layer.

[0052] Tungsten, with a thermal expansion coefficient close to that of silicon, is the preferred high-reliability metal filler material in this embodiment.

[0053] In one example, after forming the longitudinal conductive path 6, the movable structure 7 (such as a cantilever beam, spring beam, mass block, diaphragm, comb electrode, etc.) within the device layer 3 is released. That is, after filling the etching channel 4 with conductive material 5 and forming the longitudinal conductive path 6, the movable structure 7 within the device layer 3 is released. This "releases" the movable structure 7 from the substrate, making it a suspended movable mechanical structure. Therefore, releasing the movable structure 7 within the device layer 3 after filling the etching channel 4 with conductive material 5 and forming the longitudinal conductive path 6 reduces the risk of damage to the movable structure 7 and ensures the reliability of the conductive path.

[0054] It is particularly important to note that the formation of the longitudinal conductive path 6 (filling of the conductive material 5) is completed before the release of the movable structure 7. This process sequence has significant advantages: before release, the movable structure 7 is constrained to the target structure, possessing high mechanical strength and capable of withstanding the high-energy plasma bombardment during etching in step S102 and the high-temperature process of conductive material deposition in step S103 (e.g., polysilicon deposition is typically performed at 580℃~650℃, and metal CVD may also be performed at higher temperatures). Releasing the structure after the longitudinal conductive path 6 has been formed avoids damaging the established longitudinal conductive structure, thus achieving seamless process integration. This sequence reduces the risk of damage to the movable structure while ensuring the reliability of the conductive structure.

[0055] In one example, the predetermined region is the inactive area on device layer 3 that is far from the movable structure 7. The "inactive area" refers to the region in device layer 3 that does not participate in MEMS mechanical movement or signal detection, such as the edge region of the chip or a blank area where no movable structure is located. Placing the etching channel 4 in the inactive area ensures that the etching and filling processes do not affect the mechanical characteristics and degrees of freedom of the MEMS movable structure, achieving a decoupled design between electrical optimization and mechanical structure.

[0056] Alternatively, the predetermined area can be the anchoring region on device layer 3. The anchoring region refers to the connection point area where the movable structure 7 is fixed to the handle substrate layer 1. The structure of this region remains fixed during the operation of the MEMS device and is not affected by the movement of the movable structure. By placing the longitudinal conductive path 6 near the anchoring region, the "fixed" characteristic of this region is utilized to ensure that the conductive structure is not subjected to repeated mechanical stress, and the connection path to the reference potential of the device layer is shortened.

[0057] Alternatively, the designated area is the region outside the sealing ring on device layer 3. The sealing ring is typically a closed ring structure surrounding the core functional area of ​​the chip, used to form a hermetically sealed or vacuum-sealed cavity together with the capped wafer to protect the internal movable MEMS structures. The region outside the sealing ring refers to the annular area from the sealing ring outwards to the chip dicing track. This region usually has external interface structures such as electrode pads. Placing the longitudinal conductive path 6 in the region outside the sealing ring avoids compromising the hermetically sealed nature of the sealing ring and facilitates electrical connection with the ground potential region or the preset bias potential region on the device layer.

[0058] Alternatively, the predetermined area can be a reserved connection area. A reserved connection area refers to an area specifically reserved for this vertical conductive structure 6 during the MEMS layout design phase, which does not perform other functions. This implementation facilitates standardized process module design and makes it easier to integrate the conductive structure of this application into the layout of various MEMS devices in the form of standard units.

[0059] The various methods of selecting predetermined regions are not mutually exclusive. In the same MEMS device, one or more vertical conductive paths 6 can be set in one or more predetermined regions according to the chip area and layout. Preferably, multiple vertical conductive paths 6 are arranged in parallel to reduce the total on-resistance and improve the reliability and redundancy of potential locking.

[0060] In one example, the target structure is a standard SOI substrate. The handle substrate layer 1 of the standard SOI substrate is a solid, flat silicon substrate without pre-fabricated cavities. This substrate can be widely used in the fabrication of various MEMS devices. For this type of substrate, the etching channel 4 of this application sequentially etches through the device layer 3 and the insulating oxide layer 2 from the surface of the device layer 3 downwards, exposing the surface of the solid handle substrate layer 1. After filling with conductive material 5, the handle substrate layer 1 can be locked to the reference potential, thereby achieving stable potential control of the shielding layer.

[0061] In one example, the target structure is a Cavity SOI substrate with a pre-defined cavity. The handle substrate layer 1 of this type of substrate has a pre-defined cavity on the side near the device layer 3, which provides physical space for the subsequently released movable structure 7. For this type of substrate, the etching channel 4 of this application needs to be arranged in a solid area not occupied by the cavity (i.e., the support area of ​​the handle substrate layer 1) to ensure that the bottom of the etching channel 4 can expose the solid silicon surface of the handle substrate layer 1, thereby achieving reliable ohmic contact.

[0062] Alternatively, the target structure is a composite substrate formed by fusion bonding a silicon wafer with a cavity (such as an SOI substrate with a pre-defined cavity) to another device silicon wafer (such as a standard SOI substrate). The bonding interface of this type of substrate consists of atomically dense Si-O-Si covalent bonds, exhibiting extremely high bonding strength and hermeticity. The etching and filling processes in this embodiment are fully compatible with this type of substrate, and since it does not require penetrating the bonding interface, it does not affect the bonding quality or the hermeticity of the cavity.

[0063] Alternatively, the target structure is an equivalent substrate structure containing an intermediate silicon oxide isolation layer and upper and lower layers primarily composed of silicon or semiconductor materials. Although this type of substrate differs from standard SOI or Cavity SOI in its specific manufacturing process, it has a three-layer electrical structure consisting of a "device layer—insulating oxide layer—conductive support layer," and therefore is equally applicable to the technical solution of this embodiment.

[0064] In this application, the aforementioned "equipotential locking" can be implemented in various specific ways. In one embodiment, the vertical conductive path 6 can directly lock the handle substrate layer 1 to the silicon body potential of the device layer 3. This method eliminates the potential difference between the handle substrate layer 1 and the device layer 3 by shorting them together, thereby eliminating the electrostatic attraction caused by the potential difference. In another embodiment, the vertical conductive path 6 locks the handle substrate layer 1 to the ground potential region (GND) on the device layer 3. This method forcibly anchors the handle substrate layer 1 to a 0V potential, making it a stable shielding layer that effectively shields against electric field interference from the bottom of the chip, improving the purity of the MEMS detection signal. In yet another embodiment, the vertical conductive path 6 locks the handle substrate layer 1 to a preset bias potential region (such as Vbias). This method is suitable for applications that require a bias voltage to be applied to the bottom electrode, such as frequency tuning of resonators (adjusting mechanical stiffness through bottom bias voltage) and sensitivity optimization of capacitive MEMS.

[0065] For example, see reference Figure 4 In this embodiment of the application, the MEMS device is used in a capacitive MEMS accelerometer or gyroscope, and the MEMS device is flip-chip connected to the integrated chip 8 of the accelerometer or gyroscope. The longitudinal conductive path 6 is arranged in a region away from the mass block, spring beam, comb electrode, and sealing ring. Through this conductive structure, the lower handle substrate layer 1 can be locked to ground potential or a preset bias potential, reducing the impact of the bottom shielding layer potential drift on the detection capacitance, parasitic coupling, and zero-bias stability.

[0066] refer to Figure 3 and Figure 4 This application also discloses a MEMS device, which can be fabricated by any of the MEMS device fabrication methods described in the above embodiments, including: a handle substrate layer 1, an insulating oxide layer 2, and a device layer 3 stacked sequentially; a movable structure 7 is provided in the device layer 3, and an etching channel 4 is provided in a predetermined area on the surface of the device layer 3. The etching channel 4 is filled with a conductive material 5 to serve as a longitudinal conductive path 6 for potential locking of the handle substrate layer 1. The handle substrate layer 1 is electrically connected to the device layer 3 or a reference potential region on the device layer 3.

[0067] The MEMS device can be any of the following: accelerometer, gyroscope, pressure sensor or resonator, and is especially suitable for high-precision capacitive MEMS sensors.

[0068] This application also discloses an electronic device, which is an accelerometer, gyroscope, pressure sensor or resonator, and a MEMS device fabricated by any of the above embodiments using the MEMS device fabrication method.

[0069] The electronic device can be a standalone sensor chip or a system-in-package module integrating the aforementioned MEMS device and integrated chip 8. That is, the MEMS device can be flip-chip connected to integrated chip 8. Due to the MEMS device fabrication method employed in this embodiment, the bottom shielding layer of this electronic device exhibits stable potential, low parasitic capacitance drift, and high zero-bias stability, making it particularly suitable for applications in automotive electronics, industrial control, aerospace, and consumer electronics where high sensor accuracy and long-term reliability are required.

[0070] The present application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only for the purpose of helping to understand the core ideas of the present application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present application. Therefore, the content of this specification should not be construed as a limitation of the present application.

Claims

1. A method for fabricating a MEMS device, characterized in that, include: A target structure is provided, the target structure comprising, from bottom to top, a handle substrate layer, an insulating oxide layer and a device layer, stacked sequentially; An opening pattern is formed in a predetermined area on the surface of the device layer, and based on the opening pattern, an etching channel is formed by etching downward from the surface of the device layer. The etching channel penetrates the device layer and the insulating oxide layer to the handle substrate layer to expose the handle substrate layer. The etched channel is filled with conductive material to form a longitudinal conductive path.

2. The MEMS device fabrication method according to claim 1, characterized in that, The predetermined area on the surface of the device layer is the inactive area of ​​the device layer that is far away from the movable structure.

3. The MEMS device fabrication method as described in claim 1, characterized in that, The predetermined area on the surface of the device layer is the anchoring area on the device layer, the outer area of ​​the sealing ring on the device layer, or the reserved connection area.

4. The MEMS device fabrication method according to claim 1, characterized in that, The etching downwards from the surface of the device layer based on the opening pattern includes: The device layer is etched using dry etching or deep reactive ion etching until the insulating oxide layer is reached, at which point the etching is stopped. The insulating oxide layer is etched using dry etching, wet etching, or a combination of dry and wet etching until the handle substrate is exposed. The etching channels are formed in the form of grooves or through holes.

5. The MEMS device fabrication method according to claim 1, characterized in that, After the etching channel penetrates the device layer and the insulating oxide layer, it continues to etch the handle substrate layer to a preset over-etching depth to improve ohmic contact.

6. The MEMS device fabrication method according to claim 1, characterized in that, The target structure is a standard SOI substrate, an SOI substrate with a preset cavity, an equivalent substrate with an intermediate silicon oxide isolation layer, or a composite substrate in which the standard SOI substrate and the SOI substrate with the preset cavity are fused and bonded.

7. The MEMS device fabrication method according to claim 1, characterized in that, The conductive material includes a metallic material or in-situ heavily doped polycrystalline silicon; and the metallic material includes at least one of tungsten, copper, aluminum, titanium, titanium nitride, nickel, cobalt or ruthenium.

8. The MEMS device fabrication method according to claim 7, characterized in that, When the conductive material is a metallic material, the structure of the longitudinal conductive path is a multilayer structure consisting of a barrier layer, a seed layer, and a metal layer; and There are multiple longitudinal conductive paths, and the multiple longitudinal conductive paths are arranged in parallel.

9. A MEMS device, said MEMS device being fabricated by the MEMS device fabrication method according to any one of claims 1 to 8, characterized in that, include: The handle substrate layer, insulating oxide layer and device layer are stacked in sequence; The device layer has a movable structure, and a predetermined area on the surface of the device layer has an etching channel. The etching channel is filled with a conductive material to serve as a longitudinal conductive path for potential locking of the handle substrate layer.

10. An electronic device, said electronic device being an accelerometer, gyroscope, pressure sensor, or resonator, characterized in that, The electronic device includes a MEMS device fabricated by the MEMS device fabrication method according to any one of claims 1 to 8.

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