Process for improving edge lift-off of single-sided plated edges

Abstract

The present application discloses a process for improving edge lift-off of single-sided plating, comprising: providing a substrate having a first surface on which a first metal layer is to be formed and a second surface on which a second metal layer is to be formed; forming the first metal layer on the first surface of the substrate by single-sided plating; depositing the second metal layer on the second surface of the substrate, the material of the second metal layer also forming on the side surface of the substrate; and performing a plating process before the forming process of the second metal layer to prevent the material of the first metal layer from forming on the material of the second metal layer on the side surface of the substrate, thereby preventing edge lift-off of the single-sided plating. The present application can prevent edge lift-off of the single-sided plating film layer and thus prevent particle contamination.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor integrated circuits, and more particularly to a process method for improving edge peeling of single-sided plating. Background Technology

[0002] Chemical plating is a process that uses the displacement and reduction reactions of intermetallic ions to deposit metals onto the surface of a wafer by means of the gain and loss of electrons in the solution. Due to its low process cost and the fact that it does not require current or a conductive substrate, it has been actively researched and applied to chip manufacturing in recent years.

[0003] Single-sided plating of 12-inch IGBT products can improve the packaging reliability of the products. Currently, after plating of thin-film IGBT products, there is a peeling problem in the edge area of ​​the wafer. Peeling is prone to forming particle contamination in subsequent processes, which affects the product circulation.

[0004] like Figure 1 The diagram shows a schematic of the single-sided coating layer structure of an existing IGBT product; a metal interconnect structure is formed on the front side of the semiconductor substrate 101, and the metal interconnect structure includes a metal pad (PAD) 102 formed by the top metal layer. Figure 1 In this design, the metal interconnect structure at the bottom of the metal pad 102 is omitted. The metal pad 102 is typically an Al pad.

[0005] A back metal layer 103 is formed on the back side of the semiconductor substrate 101. The back metal layer 103 includes an Al layer, a Ti layer, a Ni layer, and an Ag layer stacked sequentially. Figure 1 The expression is also represented as Al+Ti+Ni+Ag.

[0006] A metal layer 104 formed by single-sided electroplating is formed on the front side of the semiconductor substrate 101 on which the metal pad 102 is formed. The metal layer 104 includes a Ni layer, a Pd layer and an Au layer stacked sequentially. Figure 1 In this context, the metal layer 104 is also represented as Ni+Pd+Au.

[0007] like Figure 2 The diagram shown is a flowchart of an existing single-sided electroplating process; as shown... Figures 3 to 6 The diagram shown is a schematic representation of the device structure in each step of an existing single-sided electroplating process; the existing single-sided electroplating process includes: Step S101: Perform backside metallization, including: like Figure 3As shown, a semiconductor substrate 101 with a front-side metal layer formed is provided. A semiconductor device is formed in the semiconductor substrate 101. A metal interconnect structure is formed on the front side of the semiconductor substrate 101, the metal interconnect structure including a metal pad (PAD) 102, such as an Al pad, formed from the topmost metal layer.

[0008] The semiconductor substrate 101 is thinned by Taiko and includes a support ring and a thinned region located inside the support ring.

[0009] Backside metal deposition, as indicated by arrow 105, forms a backside metal layer 103 on the back side of the semiconductor substrate 101. Typically, metal material 103a is also formed on the side surfaces of the edge regions of the semiconductor substrate 101 during backside metal deposition.

[0010] Step S102, as follows Figure 4 As shown, a back-side film is applied to form a protective film 106 on the back side of the semiconductor substrate 101 on which the back-side metal layer 103 is formed.

[0011] Step S103, as follows Figure 5 As shown, chemical plating of NiPdAu is performed to form a metal layer 104 composed of a Ni layer, a Pd layer, and an Au layer. Since the semiconductor substrate 101 has a metal material 103a on its side, a metal material 104a corresponding to the metal layer 104 will also be formed on the surface of the metal material 103a during the chemical plating process.

[0012] Step S104, as follows Figure 6 As shown, a back-side peeling process is performed to remove the protective film 106. It can be seen that the metal material layer 104a is located in the edge region of the wafer and is easily peeled off to form a peeling layer 104b, which becomes a source of particulate contamination.

[0013] Step S105: Perform subsequent wafer testing (CP) and wafer fabrication testing (WMT) tape-out. Summary of the Invention

[0014] The technical problem to be solved by the present invention is to provide a process method to improve the edge peeling of single-sided electroplating, which can prevent the edge peeling of the single-sided electroplating film layer, thereby preventing particulate contamination caused by the edge peeling of the film layer.

[0015] To solve the above-mentioned technical problems, the present invention provides a process method for improving edge peeling of single-sided electroplating, which includes the following steps: A substrate is provided having a first surface for forming a first metal layer and a second surface for forming a second metal layer.

[0016] A first-sided metal layer is formed on the first surface of the substrate by single-sided electroplating.

[0017] The second metal layer is deposited on the second surface of the substrate, and the material of the second metal layer is simultaneously formed on the side surface of the substrate; the single-sided plating is placed before the formation process of the second metal layer to prevent the material of the first metal layer from forming on the material of the second metal layer on the side surface of the substrate, thereby preventing the single-sided plating edge peeling.

[0018] A further improvement is that the substrate includes a semiconductor substrate in which semiconductor devices are formed, and a metal interconnect structure is formed on the front side of the semiconductor substrate, the metal interconnect structure including a metal pad formed by the topmost metal layer.

[0019] The first surface of the substrate is the front side of the metal pad.

[0020] The second surface of the substrate is the back side of the semiconductor substrate.

[0021] A further improvement is that the metal gasket includes an Al gasket.

[0022] A further improvement is that the semiconductor substrate is thinned by Taiko, including a support ring and a thinned region located inside the support ring.

[0023] A further improvement is that the first metal layer comprises a Ni layer, a Pd layer, and an Au layer stacked sequentially.

[0024] A further improvement is that the second metal layer is formed using a PVD process.

[0025] A further improvement is that the second metal layer comprises an Al layer, a Ti layer, a Ni layer, and an Ag layer stacked sequentially.

[0026] A further improvement is that the temperature of the process for forming the second metal layer is less than 320°C.

[0027] A further improvement is that the thickness of the thinned region is less than 100 micrometers.

[0028] A further improvement is that the thickness of the Ni layer in the first metal layer is 1.0 micrometer to 3.0 micrometers, the thickness of the Pd layer is 0.05 micrometers to 0.25 micrometers, and the thickness of the Au layer is 0.03 micrometers to 0.07 micrometers.

[0029] A further improvement is that the semiconductor device includes an IGBT device.

[0030] A further improvement is that the single-sided plating includes the following steps: A protective film is attached to the second surface of the substrate; A chemical plating process is performed to form the first surface metal layer on the first surface of the substrate; Remove the protective film; Before single-sided electroless plating, this invention comprehensively considers the formation process of the second-sided metal layer, which can affect the single-sided electroless plating. Unlike existing methods that first form the second-sided metal layer and then use single-sided electroless plating to form the first-sided metal layer, this invention first forms the first-sided metal layer using single-sided electroless plating and then forms the second-sided metal layer. This eliminates the possibility of the second-sided metal layer forming material on the side of the substrate edge during the formation process of the second-sided metal layer, and also eliminates the possibility of the first-sided metal layer forming material on the side of the substrate during the electroless plating process. This prevents the edge of the single-sided electroless plating film, i.e., the first-sided metal layer, from peeling, thereby preventing particle contamination caused by edge peeling. Attached Figure Description

[0031] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a schematic diagram of the single-sided coating layer structure of existing IGBT products; Figure 2 This is a flowchart of an existing single-sided electroplating process; Figures 3-6 This is a schematic diagram of the device structure in each step of the existing single-sided electroplating process; Figure 7 This is a flowchart of a process method for improving edge peeling of single-sided electroplating according to an embodiment of the present invention; Figure 8 This is a flowchart of a preferred embodiment of the process for improving edge peeling of single-sided electroplating according to the present invention; Figures 9-12 This is a schematic diagram of the device structure in each step of the process method for improving edge peeling of single-sided electroplating according to an embodiment of the present invention. Detailed Implementation

[0032] like Figure 7 The diagram shown is a flowchart of a process method for improving edge peeling of single-sided electroplating according to an embodiment of the present invention; as shown... Figure 8 The diagram shown is a flowchart of a preferred embodiment of the present invention for improving edge peeling of single-sided electroplating; as shown Figures 9 to 12 The diagram shown is a schematic representation of the device structure in each step of the process method for improving edge peeling of single-sided plating according to an embodiment of the present invention. The process method for improving edge peeling of single-sided plating according to an embodiment of the present invention includes the following steps: Step S201: Provide a substrate having a first surface for forming a first metal layer 204 and a second surface for forming a second metal layer 206.

[0033] In embodiments of the present invention, such as Figure 9 As shown, the substrate includes a semiconductor substrate 201 in which semiconductor devices are formed. A metal interconnect structure is also formed on the front side of the semiconductor substrate 201, and the metal interconnect structure includes a metal pad 202 formed by the topmost metal layer. Figure 9 In this context, the metal interconnect structure at the bottom of the metal pad 202 is omitted.

[0034] The first surface of the substrate is the front side of the metal pad 202.

[0035] The second surface of the substrate is the back side of the semiconductor substrate 201.

[0036] In some embodiments, the metal liner 202 includes an Al liner.

[0037] The semiconductor substrate 201 is thinned by Taiko and includes a support ring and a thinned region located inside the support ring.

[0038] In some embodiments, the semiconductor device includes an IGBT device.

[0039] The thickness of the thinned region is less than 100 micrometers.

[0040] Step S202: Perform single-sided electroplating to form the first-side metal layer 204 on the first surface of the substrate.

[0041] In a preferred embodiment of the present invention, such as Figure 8 As shown, the single-sided plating includes the following steps: Step S202a, as follows Figure 9 As shown, a protective film 203 is applied to the second surface of the substrate, i.e., back-side film application is performed.

[0042] Step S202b, as follows Figure 10 As shown, a chemical plating process is performed to form the first surface metal layer 204 on the first surface of the substrate.

[0043] The first metal layer 204 includes a Ni layer, a Pd layer and an Au layer stacked sequentially. Figure 8 In this process, step S202b is also known as electroless NiPdAu plating. The electroless plating process is short for electroless plating process.

[0044] In some embodiments, the thickness of the Ni layer in the first surface metal layer 204 is 1.0 micrometer to 3.0 micrometer, the thickness of the Pd layer is 0.05 micrometer to 0.25 micrometer, and the thickness of the Au layer is 0.03 micrometer to 0.07 micrometer.

[0045] Step S202c, as follows Figure 11 As shown, the protective film 203 is removed. Figure 8 In step S202c, the film is peeled off from the back.

[0046] Step S203, as follows Figure 12 As shown, a second surface metal layer 206 is deposited on the second surface of the substrate. The deposition process of the second surface metal layer 206 is indicated by arrow line 205.

[0047] The material 206a of the second metal layer 206 is simultaneously formed on the side of the substrate; the single-sided plating is placed before the formation process of the second metal layer 206 to prevent the material of the first metal layer 204 from forming on the material of the second metal layer 206 on the side of the substrate, thereby preventing the single-sided plating edge peeling.

[0048] In this embodiment of the invention, the second surface metal layer 206 is formed using a PVD process. The second surface of the substrate is typically the back side. Figure 8 In step S203, the back side is metallized.

[0049] In some embodiments, the second surface metal layer 206 includes an Al layer, a Ti layer, a Ni layer and an Ag layer stacked sequentially.

[0050] The temperature of the process for forming the second metal layer 206 is less than 320°C.

[0051] In a preferred embodiment of the present invention, such as Figure 8 As shown, the following also includes: Step S204: Perform subsequent wafer testing (CP) and wafer fabrication testing (WMT) tape-out.

[0052] In this embodiment of the invention, the formation process of the second metal layer 206, which would affect the single-sided electroplating, is comprehensively considered before the single-sided electroplating. Unlike the existing method, which first forms the second metal layer 206 and then forms the first metal layer 204 using single-sided electroplating, this embodiment of the invention first forms the first metal layer 204 using single-sided electroplating and then forms the second metal layer 206. This eliminates the possibility that the formation process of the second metal layer 206 will also form material on the side of the substrate edge, and thus eliminates the possibility that the material of the first metal layer 204 will also form on the side of the substrate during the electroplating process. This prevents the edge of the single-sided electroplated film layer, i.e., the first metal layer 204, from peeling, thereby preventing particle contamination caused by edge peeling.

[0053] Existing IGBT single-sided plating products are prone to peeling in the wafer edge area, which affects product circulation. The embodiments of the present invention can avoid peeling by optimizing the process.

[0054] The existing IGBT single-sided metallization process involves first plating the back side with Al-Ti-Ni-Ag, followed by Ni-Pd-Au plating on the front side. During back-side metal sputtering, a small amount of metal sputtering occurs at the wafer edge, forming peeling in the wafer edge area during the metallization process. This invention optimizes the process by performing metallization first, followed by back-side metallization (BSM), thus eliminating the source of peeling. Therefore, this invention improves the peeling situation in the wafer edge area, reduces PD sources in the product fabrication process, and ensures product quality.

[0055] In addition, the existing process for single-sided plating of thin-film IGBTs is to first metallize the back side and then perform electroplating. In this embodiment of the invention, the adjusted process is to perform electroplating first and then metallize the back side to avoid wafer edge peeling. While adopting the electroplating -> back gold plating process, this embodiment of the invention also further controls the back metallization temperature to ensure that the back metallization temperature is <320°C, which can prevent the electroplating layer from cracking due to high temperature.

[0056] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A process method for improving edge peeling of single-sided electroplating, characterized in that, Includes the following steps: A substrate is provided, the substrate having a first surface for forming a first metal layer and a second surface for forming a second metal layer; A first-side metal layer is formed on the first surface of the substrate by single-sided electroplating. A second side metal layer is deposited on the second surface of the substrate, and the material of the second side metal layer is simultaneously formed on the side surface of the substrate; The single-sided electroplating is performed before the formation process of the second metal layer to prevent the material of the first metal layer from forming on the material of the second metal layer on the side of the substrate, thereby preventing the single-sided electroplating edge peeling.

2. The process method for improving edge peeling of single-sided electroplating as described in claim 1, characterized in that: The substrate includes a semiconductor substrate in which a semiconductor device is formed. A metal interconnect structure is also formed on the front side of the semiconductor substrate, the metal interconnect structure including a metal pad formed by the topmost metal layer. The first surface of the substrate is the front side of the metal pad; The second surface of the substrate is the back side of the semiconductor substrate.

3. The process method for improving edge peeling of single-sided electroplating as described in claim 2, characterized in that: The metal gasket includes an Al gasket.

4. The process method for improving edge peeling of single-sided electroplating as described in claim 2, characterized in that: The semiconductor substrate is thinned by Taiko and includes a support ring and a thinned region located inside the support ring.

5. The process method for improving edge peeling of single-sided electroplating as described in claim 3, characterized in that: The first metal layer comprises a Ni layer, a Pd layer, and an Au layer stacked sequentially.

6. The process method for improving edge peeling of single-sided electroplating as described in claim 3, characterized in that: The second metal layer is formed using PVD (Polydioxanone) technology.

7. The process method for improving edge peeling of single-sided electroplating as described in claim 6, characterized in that: The second metal layer comprises an Al layer, a Ti layer, a Ni layer, and an Ag layer stacked sequentially.

8. The process method for improving edge peeling of single-sided electroplating as described in claim 6, characterized in that: The temperature of the process for forming the second metal layer is less than 320°C.

9. The process method for improving edge peeling of single-sided electroplating as described in claim 4, characterized in that: The thickness of the thinned region is less than 100 micrometers.

10. The process method for improving edge peeling of single-sided electroplating as described in claim 5, characterized in that: The thickness of the Ni layer in the first metal layer is 1.0 micrometer to 3.0 micrometer, the thickness of the Pd layer is 0.05 micrometer to 0.25 micrometer, and the thickness of the Au layer is 0.03 micrometer to 0.07 micrometer.

11. The process method for improving edge peeling of single-sided electroplating as described in claim 2, characterized in that: The semiconductor device includes an IGBT device.

12. The process method for improving edge peeling of single-sided electroplating as described in claim 1, characterized in that: The single-sided electroplating process includes the following steps: A protective film is attached to the second surface of the substrate; A chemical plating process is performed to form the first surface metal layer on the first surface of the substrate; Remove the protective film.

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