A rapid quality detection method for PVD seed layer based on TGV

CN122879667APending Publication Date: 2026-10-09SHENZHEN ARRAYED MATERIALS TECH CO LTD
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Patent Information

Application Number
CN202610940761.8
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-06-27
Publication Date
2026-10-09

AI Technical Summary

Technical Problem

[0004]生产过程中,一般只能通过裂片的方式,通过SEM或者FIB方式测试TGV通孔内的PVD种子层厚度,SEM和FIB测试比较烦琐,速度慢,成本高,且裂片后对应的大板不能继续进行生产导致生产成本增加

Benefits of technology

[0016]本发明整体方案简单,能够快速地完成对TGV种子层薄膜工艺是否合格的检测,且不影响基板的后续加工使用。

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Abstract

The application discloses a kind of PVD seed layer rapid quality detection methods based on TGV, belong to the field of semiconductor processing technology, including the following steps: in the effective area of TGV big board, at least one test pattern is set, the test pattern is composed of a pair of positive and negative surface misregistration rectangular continuous wave TGV blind slot, it can surround cover multiple TGV through holes, when PVD seed layer processing is completed, the impedance value of two layers of test pattern is tested directly by impedance table, whether in set range can determine whether PVD process is qualified according to, without damaging substrate, rapid quality detection is completed.This application overall scheme is simple, can quickly complete the detection of whether TGV seed layer film process is qualified, and does not affect the subsequent processing use of substrate.
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Description

Technical Field

[0001] This invention belongs to the field of semiconductor processing technology, specifically relating to a rapid quality inspection method for PVD seed layers based on TGV. Background Technology

[0002] Through Glass Via (TGV) technology, leveraging the high-frequency, insulating, and thermally stable advantages of glass substrates, is becoming a disruptive solution for 5G communications, optoelectronics, and advanced packaging. Large-size TGV glass substrates, through material performance optimization, process innovation, and cost control, have become a core technology for overcoming the bottlenecks in computing chip packaging. Their advantages in high-density interconnects, high-frequency signal transmission, and ultra-large-size packaging will accelerate the upgrading of computing power in fields such as AI and data centers, while simultaneously driving the extension of China's domestic semiconductor industry chain into the high-end packaging field.

[0003] The core process of TGV technology lies in via metallization, which requires depositing a continuous metal seed layer film within the TGV via using PVD magnetron sputtering. During the PVD process, an RF bias is typically applied to the substrate stage, forming a plasma sheath above the stage. This allows ionized metal target particles to be deposited more rapidly on the sidewalls of the TGV via. In optimizing the TGV PVD process, the optimal process conditions are generally assessed based on step coverage. TGV via PVD seed layer deposition requires double-sided deposition; the seed layer thickness is thinnest on the middle sidewall of the via and thickest on the outer side of the via opening. Therefore, step coverage = seed layer thickness on the middle sidewall / seed layer thickness on the outer side of the via opening. With a fixed seed layer thickness on the outer side of the via opening, a thicker seed layer on the middle sidewall results in better step coverage.

[0004] During production, the thickness of the PVD seed layer within the through-holes of TGV PVD equipment is typically tested using a sharding method and SEM or FIB. However, SEM and FIB testing are cumbersome, slow, and costly. Furthermore, the corresponding large board cannot be further processed after sharding, increasing production costs. Therefore, industry professionals urgently need a rapid method to test whether the PVD seed layer completely covers the through-holes during TGV PVD equipment production, and a method that allows for random checks of the PVD seed layer on TGV large boards during production to ensure its quality. Summary of the Invention

[0005] To address the above problems, this invention provides a rapid quality detection method for PVD seed layers based on TGV, comprising the following steps:

[0006] Within the effective area of ​​the TGV large board, at least one test pattern is set. The test pattern consists of a pair of rectangular continuous wave-shaped TGV blind grooves with staggered front and back sides, which can surround and cover multiple TGV through holes. After the PVD seed layer is processed, the impedance values ​​of the two layers of the test pattern are directly tested by an impedance meter. Whether the impedance values ​​are within the set range can determine whether the PVD process is qualified or not. Rapid quality inspection is completed without damaging the substrate.

[0007] Furthermore, the test pattern has a single side length of 10mm~20mm, and the central area enclosed by its four sides consists of multiple normal TGV through holes.

[0008] Furthermore, the diameter of the TGV through-hole is 10um~100um.

[0009] Furthermore, the width of the TGV blind groove is smaller than the diameter of the TGV through hole, specifically, the width of the TGV blind groove is 30% to 40% of the diameter of the TGV through hole.

[0010] Furthermore, the depth of the TGV blind slot is 60% of the thickness of the TGV plate.

[0011] Furthermore, the ratio of the depth to width of the TGV blind trench is not less than twice the ratio of the depth to width of the TGV via. After depositing the preset TGV TiCu seed layer, the sidewalls of the TGV via can be continuously covered by the seed layer, while the sidewalls of the TGV blind trench cannot be continuously covered. Therefore, the film layer within the test key area and the external area are electrically isolated. This allows for direct impedance testing of the two layers of the test key using an impedance meter. The impedance data can then be used to assess whether the TGV seed layer film continuously covers the via sidewalls and whether it meets the production requirements of subsequent processes. This approach avoids damaging the substrate and allows for rapid and effective monitoring of daily TGV PVD production.

[0012] Furthermore, if the impedance meter reading is within the set range during testing, it indicates that the PVD seed layer processing technology is qualified; if the reading exceeds the set range, it indicates that the PVD seed layer processing technology is unqualified, thus achieving the purpose of rapid detection.

[0013] Laser-induced etching (TGV) technology is currently the mainstream method for fabricating high-quality microvias in the field of advanced semiconductor packaging. A laser (usually a picosecond or femtosecond laser) is focused onto a tiny point inside the glass. The extremely high energy density induces a multiphoton ionization effect, equivalent to applying a huge amount of energy simultaneously at a single point. This energy alters the atomic structure inside the glass (e.g., silicon-oxygen bonds break and reform, forming nanogratings), generating tiny cracks and stress zones. This significantly increases the etching rate in hydrofluoric acid or strongly alkaline solutions; while near the induced spot, the un-laser-induced glass experiences a lower etching rate in the same etching solution. Therefore, the induced area can be etched to form a TGV via.

[0014] This invention aims to quickly detect the thickness of the seed layer formed by sputtering on TGV vias, avoiding traditional destructive and time-consuming testing methods. It directly delineates the test area through a set test pattern and uses the reasonable impedance range within this area to quickly reflect whether the process is qualified or not. The cleverly designed structure does not affect the subsequent processing and use of the substrate.

[0015] The present invention has the following advantages over the prior art:

[0016] The overall solution of this invention is simple and can quickly complete the detection of whether the TGV seed layer thin film process is qualified, without affecting the subsequent processing and use of the substrate. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall structure of the test pattern set in the method of the present invention.

[0018] Figure 2 This is a schematic cross-sectional view of the structure after the PVD seed layer processing is completed in the method of the present invention.

[0019] Figure 3 This is a schematic diagram of the impedance meter test in the method of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below in conjunction with the embodiments of this invention. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of the embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0021] In the embodiments, it should be noted that any processes not specifically described below are those that can be implemented or understood by those skilled in the art by referring to existing technology. Reagents or instruments whose manufacturers are not specified are considered to be conventional products that can be purchased commercially. Example 1

[0022] A rapid quality detection method for PVD seed layers based on TGV includes the following steps:

[0023] In this embodiment, the substrate thickness is 500µm, the TGV via diameter is 50µm, and the TGV via aspect ratio is designed to be 10:1. Two test keys are then placed on the substrate, each with a side length of 20mm. The TGV blind trenches designed on all four sides are rectangular and wavy, with the width of the blind trenches smaller than the via diameter. The central area contains multiple normal TGV vias. The width of the blind trenches is 30% of the via diameter, specifically 15µm, and the depth is 60% of the substrate depth, i.e., 300µm. Therefore, the aspect ratio of the blind trenches is 20:1. The blind trenches encircle the TGV vias of the test keys. Blind trenches are designed on both the front and back sides of the test keys, with the front and back positions staggered. The specific structure is shown in the attached figure. Figure 1 As shown.

[0024] When the TGV seed layer TiCu film is deposited, because the aspect ratio of the blind trench is much larger than that of the TGV via, the film thickness of the normally designed TGV via cannot cover and connect the sidewalls of the blind trench. Therefore, the TGV seed layer film inside the blind trench is disconnected. Figure 2 As can be seen, the yellow part is the seed layer deposited by TGV TiCu, and the film in the blind trench is broken.

[0025] After completing the TGV TiCu seed layer, use an impedance meter to test its impedance by placing the two probes on the front and back sides of the test key, respectively. The procedure is as follows: Figure 3 As shown. If the impedance data is within the production requirement range, it indicates that the TGV seed layer covering this TGV board meets the production requirements. In this embodiment, the vias with a depth-to-width ratio of 10:1 are designed with a film thickness of Ti 100nm and Cu 900nm, and the step coverage is calculated at 3%. The thinnest TiCu seed layer film thickness in the middle of the via is 30nm. The TGV TiCu seed layer covering the sidewalls of the 30 TGV vias in the test key is electrically connected on both sides. The impedance of each via is R1, R2...R30, and the impedance R on both sides of the test key is the parallel combination of the via impedances within its range, i.e., R = 1 / (1 / R1 + 1 / R2 + ... + 1 / R30). In this embodiment, the defined impedance standard is <0.12Ω, which meets the requirements for subsequent electroplating and via filling. If the impedance is found to be within the standard range after testing, it indicates that production is normal and can meet the requirements of subsequent processes.

[0026] Following this embodiment, the impedance of 10 production substrates is randomly sampled daily to monitor the production process, ensuring the continuity of the TGV via sidewall seed layer film and meeting the requirements for subsequent electroplating. Online monitoring is possible without slicing. No additional costs are required.

[0027] If conventional methods are used, to monitor whether the seed layer film on the sidewalls of the TGV vias meets the requirements for subsequent electroplating during the production process, only one TGV substrate with completed TGV seed layer deposition is taken per day for SEM testing. Assuming the cost of each substrate is 1,000 yuan, the annual cost is 365,000 yuan. If multiple substrates need to be tested, the cost will increase several times over. Example 2

[0028] A rapid quality detection method for PVD seed layers based on TGV includes the following steps:

[0029] In this embodiment, the substrate thickness is 500µm, the TGV via diameter is 50µm, and the TGV via aspect ratio is designed to be 10:1. A test key is then placed on the substrate, with a side length of 15mm. The TGV blind trenches on all four sides are rectangular and wavy, with the width of the blind trenches smaller than the via diameter. The central area contains multiple normal TGV vias. The width of the blind trenches is 30% of the via diameter, specifically 15µm, and the depth is 60% of the substrate depth, i.e., 300µm. Therefore, the aspect ratio of the blind trenches is 20:1. The blind trenches encircle the TGV vias of the test key. Blind trenches are designed on both the front and back sides of the test key, and their positions are staggered.

[0030] When the TGV seed layer TiCu film is deposited, the aspect ratio of the blind trench is much larger than that of the TGV via. Therefore, the film thickness of the normally designed TGV via cannot cover and connect the sidewalls of the blind trench. As a result, the TGV seed layer film inside the blind trench is disconnected.

[0031] After completing the TGV TiCu seed layer, an impedance meter is used to test the impedance by placing two probes on both sides of the front and back of the test key. If the impedance data is within the production requirement range, it indicates that the TGV seed layer covering this TGV board meets production requirements. In this embodiment, the vias with a depth-to-width ratio of 10:1 are designed with a film thickness of Ti 100nm and Cu 900nm, and the step coverage is calculated at 3%. The thinnest TiCu seed layer film thickness in the middle of the via is 30nm. The 20 TGV vias in the test key are electrically connected on both sides through the TGV TiCu seed layer covering the sidewalls of the vias. The impedance of each via is R1, R2...R20. The impedance R on both sides of the test key is the parallel sum of the via impedances within its range, i.e., R = 1 / (1 / R1 + 1 / R2 + ... + 1 / R20). In this embodiment, the defined impedance standard is <0.20Ω to meet the subsequent electroplating filling requirements. If the impedance is found to be within the standard range after testing, it indicates that production is normal and can meet the requirements of subsequent processes. Example 3

[0032] A rapid quality detection method for PVD seed layers based on TGV includes the following steps:

[0033] In this embodiment, the substrate thickness is 500µm, the TGV via diameter is 50µm, and the TGV via aspect ratio is designed to be 10:1. Three test keys are then placed on the substrate, each with a side length of 10mm. The TGV blind trenches designed on all four sides are rectangular and wavy, with the width of the blind trenches smaller than the via diameter. The central area contains multiple normal TGV vias. The width of the blind trenches is 30% of the via diameter, specifically 15µm, and the depth of the blind trenches is 60% of the substrate depth, i.e., 300µm. Therefore, the aspect ratio of the blind trenches is 20:1. The blind trenches encircle the TGV vias of the test keys. Blind trenches are designed on both the front and back sides of the test keys, and their positions are staggered.

[0034] When the TGV seed layer TiCu film is deposited, the aspect ratio of the blind trench is much larger than that of the TGV via. Therefore, the film thickness of the normally designed TGV via cannot cover and connect the sidewalls of the blind trench. As a result, the TGV seed layer film inside the blind trench is disconnected.

[0035] After completing the TGV TiCu seed layer, an impedance meter is used to test the impedance by placing two probes on the front and back sides of the test key, respectively. If the impedance data is within the production requirement range, it indicates that the TGV seed layer covering this TGV board meets production requirements. In this embodiment, the vias with a depth-to-width ratio of 10:1 are designed with a film thickness of Ti 100nm and Cu 900nm, and the step coverage is calculated at 3%. The thinnest TiCu seed layer film thickness in the middle of the via is 30nm. The 16 TGV vias in the test key are electrically connected on both sides through the TGV TiCu seed layer covering the sidewalls of the vias. The impedance of each via is R1, R2...R16, respectively. The impedance R on both sides of the test key is the parallel sum of the via impedances within its range, i.e., R = 1 / (1 / R1 + 1 / R2 + ... + 1 / R16). In this embodiment, the defined impedance standard is <0.25Ω, which meets the requirements for subsequent electroplating and via filling. If the impedance is found to be within the standard range after testing, it indicates that production is normal and can meet the requirements of subsequent processes.

[0036] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A rapid quality detection method for PVD seed layers based on TGV, characterized in that, Includes the following steps: Within the effective area of ​​the TGV large board, at least one test pattern is set. The test pattern consists of a pair of rectangular continuous wave-shaped TGV blind grooves with staggered front and back sides, which can surround and cover multiple TGV through holes. After the PVD seed layer is processed, the impedance values ​​of the two layers of the test pattern are directly tested by an impedance meter. Whether the impedance values ​​are within the set range can determine whether the PVD process is qualified or not. Rapid quality inspection is completed without damaging the substrate.

2. The rapid quality detection method for PVD seed layers based on TGV according to claim 1, characterized in that, The test pattern has a single side length of 10mm to 20mm, and the central area enclosed by its four sides contains multiple normal TGV through holes.

3. The rapid quality detection method for PVD seed layers based on TGV according to claim 2, characterized in that, The diameter of the TGV through-hole is 10um~100um.

4. The rapid quality detection method for PVD seed layers based on TGV according to claim 3, characterized in that, The width of the TGV blind groove is smaller than the diameter of the TGV through hole, specifically, the width of the TGV blind groove is 30% to 40% of the diameter of the TGV through hole.

5. The rapid quality detection method for PVD seed layers based on TGV according to claim 4, characterized in that, The depth of the TGV blind slot is 60% of the thickness of the TGV plate.

6. The rapid quality detection method for PVD seed layers based on TGV according to claim 5, characterized in that, The ratio of the depth to the width of the TGV blind slot is not less than twice the ratio of the depth to the width of the TGV through hole.

7. The rapid quality detection method for PVD seed layers based on TGV according to claim 1, characterized in that, If the impedance meter reading is within the set range during testing, it indicates that the PVD seed layer processing technology is qualified. If the reading exceeds the set range, it indicates that the PVD seed layer processing technology is unqualified, thus achieving the purpose of rapid detection.