Method for lengthening nanowires
Patent Information
- Application Number
- CN202510392868.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2026-10-09
AI Technical Summary
[0006]鉴于以上所述现有技术的缺点,本发明的目的在于提供一种纳米线的续长方法,用于解决现有技术中半导体材料的纳米线的续长工艺中均是使用一次形成的催化剂还原不同前驱体实现纳米线的连续生长,由于反应过程不能间断,实质上相当于是纳米线的一次生长,无法实现,尤其是半导体工艺加工后的续长纳米线结构等的问题
[0030]如上所述,本发明的纳米线的续长方法,先通过CMP工艺形成与直立纳米线层表面齐平的介质层;再基于介质层与直立纳米线不同的刻蚀选择比,刻蚀直立纳米线,以在直立纳米线上方形成盲孔,该盲孔建立了介质层与直立纳米线层的上表面具有不同水平高度的基础;从而使后续形成的续长金属催化剂层也为不平坦表面,因此可以方便的将介质层表面上的续长金属催化剂层去除而保留直立纳米线层上的续长金属催化剂层,实现续长金属催化剂层与直立纳米线层的精准对位;最后,基于精准对位的续长金属催化剂层实现续长纳米线在直立纳米线上原位掺杂的直立续长。该续长方法可以实现半导体工艺加工后半导体材料纳米线的两次以上生长,对于构建同质结或异质结提供基础;另外该续长方法避免二次光刻,工艺简单,易于实现;且续长纳米线的续长反应时间短、成本低廉且原材料环境友好。
Smart Images

Figure CN122879835A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor nanowire structure manufacturing technology, and in particular relates to a method for extending nanowires. Background Technology
[0002] Nanowire propagation technology has been used in both vapor-liquid-solid (VLS) and liquid-liquid-solid (SLS) growth processes and is often used to grow multi-component nanowire materials.
[0003] The preparation process of gas-phase VLS typically involves arranging catalyst particles on a substrate, placing the substrate in a CVD apparatus, heating it to a preset temperature by introducing an inert gas, injecting a precursor gas source, and then, at the desired reaction temperature, obtaining vertically grown nanowire substrates. During this process, by changing the composition or adjusting the proportion of the precursor gas source, A... x B (1-x) Composite nanowire materials, that is, achieving continuous growth of different components of nanowires.
[0004] Similarly, in low-temperature liquid-phase SLS reactions (Chem. Commun. 2018, 54, 5728), elemental Si, Ge, or Si can be obtained by continuous injection of reducing agents and precursors. x Ge (1-x) The reaction system uses Sn nanoparticles as seeds and LiBH4 as a reducing agent to continuously reduce the molecules in the precursor at 200℃~300℃ to obtain Si or Ge atoms, which are then enriched and crystallized in the metal droplets to grow nanowire (composite) materials epitaxially. The reaction time is related to the type of precursor and is about 10min~40min.
[0005] However, each nanowire material obtained by the above two methods involves the continuous growth of molecules of different precursors by reducing them with a catalyst formed in one step. The reaction process cannot be interrupted, so it is impossible to obtain a continuously growing nanowire structure. In addition, the equipment and raw materials used in the VLS / CVD method for the continuous preparation of nanowire materials of the same or different components are expensive. Summary of the Invention
[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for extending nanowires, which solves the problem that in the prior art, the extension process of nanowires in semiconductor materials all uses a catalyst formed in one step to reduce different precursors to achieve continuous growth of nanowires. Since the reaction process cannot be interrupted, it is essentially equivalent to the one-time growth of nanowires, which cannot be achieved, especially the extension of nanowire structures after semiconductor processing.
[0007] To achieve the above and other related objectives, the present invention provides a method for extending nanowires, the method comprising the following steps:
[0008] S1. A substrate is provided, on which a layer of upright nanowires of semiconductor material is formed; wherein the upright nanowire layer comprises a plurality of upright nanowires.
[0009] S2. A dielectric layer is formed on the substrate, the dielectric layer covering the upright nanowire layer and having a thickness that at least covers the upper surface of the upright nanowire layer;
[0010] S3. Grind the dielectric layer using CMP process until the upper surface of the upright nanowires is exposed;
[0011] S4. Based on the different etching selectivity ratios of the dielectric layer and the upright nanowire, the upright nanowire is etched to form a plurality of blind holes of a predetermined depth in the dielectric layer.
[0012] S5. A continuous metal catalyst layer is formed on the upper surface of the dielectric layer and the upright nanowire layer obtained in step S4.
[0013] S6. Remove the extended metal catalyst layer on the surface of the medium layer, and retain the extended metal catalyst layer on the vertical nanowire layer; wherein the upper surface of the extended metal catalyst layer on the surface of the vertical nanowire layer is not higher than the upper surface of the remaining medium layer.
[0014] S7. The extended metal catalyst layer is annealed using a rapid annealing process to form an extended alloy catalyst particle layer between the extended metal catalyst layer and the upright nanowires.
[0015] S8. The substrate with the extended alloy catalyst particle layer obtained in step S7 is placed in an extended solution, wherein the extended solution includes a semiconductor element precursor for forming extended nanowires.
[0016] S9. The substrate in the extended solution is vertically irradiated with a laser. The thermal accumulation effect of laser heating liquefies the extended alloy catalyst particle layer into extended alloy catalyst droplets. Simultaneously, the photothermal effect of the liquefied extended alloy catalyst droplets under laser irradiation accelerates the redox reaction of the precursor in the extended solution. The atoms generated by the catalytic redox reaction dissolve into the extended alloy catalyst droplets. When the atoms reach a saturation concentration in the extended alloy catalyst droplets, they crystallize and grow epitaxially, realizing the vertical extension of extended nanowires on the corresponding upright nanowires. During the vertical extension of the extended nanowires, the extended metal atoms in the extended metal catalyst layer are embedded into the lattice of the extended nanowires to achieve in-situ doping. The growth direction of the extended nanowires is consistent with the upright direction of the upright nanowires.
[0017] Optionally, the medium layer is a single-layer structure; in step S6, the extended metal catalyst layer on the surface of the medium layer is removed by CMP process.
[0018] Optionally, the dielectric layer is formed by stacking a first dielectric layer at the bottom and a second dielectric layer at the top, both made of different materials; in step S2, the upper surface of the first dielectric layer is lower than the upper surface of the upright nanowire layer, and the thickness of the second dielectric layer at least covers the upper surface of the upright nanowire layer; in step S3, the second dielectric layer is ground using a CMP process until the upper surface of the upright nanowires is exposed; in step S4, the upper surface of the upright nanowires corresponding to the blind holes is lower than the upper surface of the first dielectric layer; in step S6, the extended metal catalyst layer on the surface of the dielectric layer is removed by removing the second dielectric layer.
[0019] Furthermore, the material of the second dielectric layer is photoresist.
[0020] Optionally, the material of the extended nanowire is the same as the material of the upright nanowire.
[0021] Furthermore, the material of the extended nanowire and the material of the upright nanowire are germanium.
[0022] Furthermore, the doping atoms of the extended nanowires are one of indium, tin, gallium, bismuth and gold or their alloys; the doping atoms of the upright nanowires are one of indium, tin, gallium, bismuth and gold or their alloys.
[0023] Optionally, the extended solution in step S9 is formed by dissolving GeI2 inorganic salt in a solution formed by trioctylphosphine and / or oleylamine.
[0024] Optionally, the upright nanowires are wet-etched in step S4.
[0025] Furthermore, the etching solution used in the wet etching process in step S4 includes hydrogen peroxide.
[0026] Optionally, in step S5, a thin film deposition process is used to directly form the extended metal catalyst layer on the upper surface of the dielectric layer and the upright nanowire layer.
[0027] Furthermore, the thin film deposition process is molecular beam epitaxy, electron beam deposition, sputtering, or vapor deposition.
[0028] Optionally, the rapid annealing process in step S7 is a laser annealing process or an RTP annealing process; in step S9, the extended solution is irradiated with a continuous laser.
[0029] Optionally, the depth of the blind hole formed in step S4 is 15 nm to 80 nm; the height difference between the upper surface of the extended metal alloy catalyst layer and the upper surface of the remaining medium layer on the surface of the upright nanowire layer in step S6 is 5 nm to 10 nm.
[0030] As described above, the nanowire extension method of the present invention first forms a dielectric layer flush with the surface of the upright nanowire layer using a CMP process; then, based on the different etching selectivity ratios of the dielectric layer and the upright nanowires, the upright nanowires are etched to form blind holes above them. These blind holes establish the basis for the dielectric layer and the upper surface of the upright nanowire layer to have different horizontal heights; thus, the subsequently formed extension metal catalyst layer also has an uneven surface, allowing for easy removal of the extension metal catalyst layer on the dielectric layer surface while retaining the extension metal catalyst layer on the upright nanowire layer, achieving precise alignment between the extension metal catalyst layer and the upright nanowire layer; finally, based on the precisely aligned extension metal catalyst layer, in-situ doping of the extension nanowires on the upright nanowires is achieved, resulting in upright extension. This extension method can achieve more than two growths of semiconductor nanowires after semiconductor processing, providing a basis for constructing homojunctions or heterojunctions; furthermore, this extension method avoids secondary photolithography, is simple in process, and easy to implement; and the extension reaction time for the nanowires is short, the cost is low, and the raw materials are environmentally friendly. Attached Figure Description
[0031] Figure 1 The diagram shows a three-dimensional structure of an upright nanowire layer of semiconductor material formed on a substrate in the nanowire extension method of the present invention.
[0032] Figure 2 The diagram shows a cross-sectional structure of an upright nanowire layer of semiconductor material formed on a substrate in the nanowire extension method of the present invention.
[0033] Figures 3 to 8 The diagram shows a cross-sectional structure of each step in a nanowire extension method as an example of the present invention.
[0034] Figures 9 to 14 The diagram shows a cross-sectional structure of each step in a nanowire extension method, which is another example of the present invention.
[0035] Figure 15 The diagram shows a schematic of forming a metal catalyst layer on the substrate surface in the nanowire extension method of the present invention.
[0036] Figure 16 The diagram shows a schematic of the formation of an alloy catalyst particle layer using laser annealing in the nanowire extension method of the present invention.
[0037] Figure 17 The diagram shows a three-dimensional structure of an upright nanowire layer formed by laser irradiation of a precursor solution in the nanowire extension method of the present invention.
[0038] Figures 18 to 21 The diagram shows an example of the nanowire extension method of the present invention, illustrating the process of forming an upright nanowire layer and extending the nanowire layer.
[0039] Component designation explanation
[0040] 10 Substrates
[0041] 11 Metal catalyst layer
[0042] 12 Alloy catalyst particle layer
[0043] 13 Alloy catalyst droplets
[0044] 14 Vertical nanowire layers
[0045] 140 upright nanowires
[0046] 15-pulse laser
[0047] 16 Continuous Lasers
[0048] 17 Glove Box
[0049] 18 Catalyst droplets that have absorbed precursor atoms
[0050] 20 Dielectric Layer
[0051] 21 First dielectric layer
[0052] 22 Second dielectric layer
[0053] 23 Blind Holes
[0054] 24. Extended metal catalyst layer
[0055] 25 Continuous Alloy Catalyst Particle Layer
[0056] 26 Continuous Nanowire Layers
[0057] 260 continuous nanowire Detailed Implementation
[0058] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0059] Please see Figures 1 to 21 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0060] This invention provides a method for extending nanowires, employing secondary self-alignment of a catalyst to enable the continued in-situ, self-aligned, upright growth of the extended nanowires along the original nanowire's extension direction. This method provides a basis for constructing homojunctions or heterojunctions. The extension method includes the following steps:
[0061] S1. A substrate is provided, on which a vertical nanowire layer of semiconductor material is formed; wherein the vertical nanowire layer includes a plurality of vertical nanowires; it should be noted that the subsequently formed extended nanowires are grown in situ in the extension direction of the plurality of vertical nanowires.
[0062] S2. A dielectric layer is formed on the substrate, the dielectric layer covering the upright nanowire layer and having a thickness that at least covers the upper surface of the upright nanowire layer;
[0063] S3. Grind the dielectric layer using CMP process until the upper surface of the upright nanowires is exposed;
[0064] S4. Based on the different etching selectivity ratios of the dielectric layer and the upright nanowires, the upright nanowires are etched to form a plurality of blind holes of a predetermined depth in the dielectric layer; that is, the remaining upright nanowires are below the plurality of blind holes, and the upper surface of the remaining upright nanowires and the upper surface of the dielectric layer are exposed at different heights.
[0065] S5. A continuous metal catalyst layer is formed on the upper surface of the medium layer and the vertical nanowire layer obtained in step S4. Since the upper surface of the vertical nanowire and the upper surface of the medium layer are exposed at different heights, the formed continuous metal catalyst layer is also an uneven surface, specifically, the upper surface of the vertical nanowire and the upper surface of the medium layer are at different heights.
[0066] S6. Remove the extended metal catalyst layer on the surface of the dielectric layer, retaining the extended metal catalyst layer on the vertical nanowire layer; wherein the upper surface of the extended metal catalyst layer on the surface of the vertical nanowire layer is not higher than the upper surface of the remaining dielectric layer; it should be noted here that there is no excessive restriction on how to remove the extended metal catalyst layer on the surface of the dielectric layer. It can be removed by etching only the extended metal catalyst layer, which may cause some unintentional damage to the dielectric layer. Alternatively, the extended metal catalyst layer on the dielectric layer can be removed by etching the dielectric layer of a preset thickness, which is considered intentional damage to the dielectric layer. Regardless of the method, damage will be caused to the dielectric layer, so the dielectric layer after this step is defined as the remaining dielectric layer.
[0067] S7. The extended metal catalyst layer is annealed using a rapid annealing process to form an extended alloy catalyst particle layer between the extended metal catalyst layer and the upright nanowires.
[0068] S8. The substrate with the extended alloy catalyst particle layer obtained in step S7 is placed in an extended solution, wherein the extended solution includes a semiconductor element precursor for forming extended nanowires.
[0069] S9. The substrate in the extended solution is vertically irradiated with a laser. The thermal accumulation effect of laser heating liquefies the extended alloy catalyst particle layer into extended alloy catalyst droplets. Simultaneously, the photothermal effect of the liquefied extended alloy catalyst droplets under laser irradiation accelerates the redox reaction of the precursor in the extended solution. The atoms generated by the catalytic redox reaction dissolve into the extended alloy catalyst droplets. When the atoms reach a saturation concentration in the extended alloy catalyst droplets, they crystallize and precipitate, and epitaxial growth is achieved to realize the upright extension of extended nanowires on the corresponding upright nanowires. During the upright extension of the extended nanowires, the extended metal atoms in the extended metal catalyst layer are embedded into the lattice of the extended nanowires to achieve in-situ doping. The growth direction of the extended nanowires is consistent with the upright direction of the upright nanowires.
[0070] The nanowire elongation principle of this invention is as follows: a stable elongation alloy catalyst particle layer is formed between the elongation metal catalyst layer and the surface of the upright nanowires through a rapid annealing process. This elongation alloy catalyst particle layer has a specific contact angle with the surface of the upright nanowires. During the growth of the elongated nanowires, the elongation solution is irradiated with a laser. The laser can precisely and uniformly distribute and focus energy on a limited area. Utilizing the thermal accumulation effect of laser heating of all structures in the substrate and the photothermal effect of laser-induced metal catalyst, on the one hand, laser irradiation of the elongation solution heats the entire substrate to an extremely high temperature, thereby heating the elongation solution through heat exchange; on the other hand, laser irradiation of the elongation solution melts the elongation alloy catalyst particle layer into elongated nanowires. When the temperature of the extended alloy catalyst droplet surface and the extended solution rises to the temperature required for the redox reaction, the redox reaction in the extended solution begins to proceed rapidly, continuously forming extended nanowire atoms. Under the catalysis of the extended alloy catalyst droplet, the extended nanowire atoms are continuously absorbed by the extended alloy catalyst droplet and crystallize out after the concentration of extended nanowire atoms reaches saturation, realizing the continuous upward growth of extended nanowires. During the growth process, the extended metal atoms in the extended alloy catalyst droplet are embedded in the lattice of the extended nanowires until the concentration of extended nanowire atoms in the extended alloy catalyst droplet becomes too low to precipitate, thus ending the growth. Finally, the in-situ doped upright extended nanowires are extended on the original upright nanowires.
[0071] The nanowire extension method of this invention first forms a dielectric layer flush with the surface of the upright nanowire layer using a CMP process. Then, based on different etching selectivity ratios between the dielectric layer and the upright nanowires, the upright nanowires are etched to form blind holes above them. These blind holes establish a basis for the dielectric layer and the upper surface of the upright nanowire layer to have different horizontal heights. This results in the subsequently formed extension metal catalyst layer also having an uneven surface, allowing for easy removal of the extension metal catalyst layer on the dielectric layer surface while retaining the extension metal catalyst layer on the upright nanowire layer, achieving precise alignment between the extension metal catalyst layer and the upright nanowire layer. Finally, based on the precisely aligned extension metal catalyst layer, in-situ doping of the extension nanowires on the upright nanowires is achieved, enabling upright extension. This extension method can achieve more than two growths of semiconductor nanowires after semiconductor processing, providing a basis for constructing homojunctions or heterojunctions. Furthermore, this extension method avoids secondary photolithography, is simple in process, and easy to implement; the extension reaction time for the nanowires is short, the cost is low, and the raw materials are environmentally friendly.
[0072] The growth direction of the extended nanowires in this invention is consistent with the vertical direction of the upright nanowires. Therefore, the materials of the extended nanowires and the upright nanowires need to have the same crystal plane in their extension direction. Based on this, when the materials of the extended nanowires and the upright nanowires are the same, a homojunction can be constructed; when the materials are different, a heterojunction can be constructed. For example, when the materials of the extended nanowires and the upright nanowires are the same, both are germanium. Generally, the growth direction of germanium nanowires is (111). Therefore, when a germanium (111) substrate is used, the extended nanowires and the upright nanowires can be grown perpendicularly on the germanium (111) substrate, thus constructing a homojunction of germanium material.
[0073] As an example, both the extended nanowire and the upright nanowire can be doped nanowires. The doping atoms enable the nanowire to have a corresponding conductivity type, such as P-type or N-type conductivity. The conductivity types of the two can be the same or different. When the conductivity types of the two nanowires are different but the materials are the same, a homojunction is formed; when the conductivity types of the two nanowires are different and the materials are also different, a heterojunction is formed; when the conductivity types of the two nanowires are the same and the materials are the same, a homogeneous extended nanowire is formed; when the conductivity types of the two nanowires are the same but the materials are different, a heterogeneous extended nanowire is formed. Taking the material of both the extended nanowire and the upright nanowire as germanium as an example, the doping atoms can be selected from one of indium, tin, gallium, bismuth, and gold, or their alloys. Indium, tin, and gallium can achieve P-type conductivity, and bismuth can achieve N-type conductivity. The specific doping atom is selected according to actual needs. In this invention, the doping of the extended nanowire is achieved in situ by embedding the extended metal atoms in the extended metal catalyst layer into the lattice of the extended nanowire during the extended nanowire extension process.
[0074] As an example, the dielectric layer can be a single-layer structure or a double-layer stacked structure.
[0075] When the medium layer is a single-layer structure, the process of forming the extended metal catalyst layer is as follows:
[0076] like Figure 1 and Figure 2 As shown, a substrate 10 is first provided, on which an upright nanowire layer 14 of semiconductor material is formed; wherein the upright nanowire layer 14 includes a plurality of upright nanowires 140.
[0077] like Figure 3 As shown, a dielectric layer 20 is then formed on the substrate 10, the dielectric layer 20 covering the upright nanowire layer 14 and having a thickness that at least covers the upper surface of the upright nanowire layer 14; the dielectric layer 20 can be deposited using ALD or CVD processes, but is not limited to these, and other suitable methods can be selected depending on the specific material of the dielectric layer 20;
[0078] like Figure 4 As shown, the dielectric layer 20 is ground using CMP process until the upper surface of the upright nanowires 140 is exposed. It should be noted that when the upper surface of the upright nanowires 140 has a metal catalyst, the metal catalyst also needs to be ground and removed during the CMP process.
[0079] like Figure 5 As shown, based on the different etching selectivity ratios between the dielectric layer 20 and the upright nanowires 140, the upright nanowires 140 are etched to form a plurality of blind holes 23 of a predetermined depth in the dielectric layer 20. The different etching selectivity ratios between the dielectric layer 20 and the upright nanowires 140 are generally determined by the selected etching method, such as dry etching or wet etching, and specifically by the material of the dielectric layer 20. For example, when the material of the upright nanowires 140 is germanium, and wet etching with hydrogen peroxide is selected, the material of the dielectric layer 20 can be selected as alumina or silicon dioxide to achieve the required etching selectivity ratio.
[0080] like Figure 6 As shown, a continuous metal catalyst layer 24 is formed on the upper surface of the dielectric layer 20 and the upright nanowire layer 14. The continuous metal catalyst layer 24 can be formed by a solvothermal method, firstly by preparing a colloidal solution of metal nanoparticle catalyst, then by spin-coating or drop-coating the colloidal solution of metal nanoparticle catalyst onto the entire surface of the structure, and then heating to obtain the continuous metal catalyst layer 24. Alternatively, the continuous metal catalyst layer 24 can be formed by a thin film deposition process. The specific steps of these two methods for forming the continuous metal catalyst layer 24 can be found in the subsequent process of forming the metal catalyst layer 11 on the substrate 10. In this invention, a thin film deposition process is preferred to form the continuous metal catalyst layer 24. For example, a suitable thin film deposition process can be selected, such as molecular beam epitaxy, electron beam deposition, sputtering, or evaporation. Thin film deposition can form a relatively uniform film thickness for uneven surfaces, and the size of the subsequently formed continuous alloy catalyst particle layer can be precisely controlled.
[0081] like Figure 7 As shown, the extended metal catalyst layer 24 on the surface of the medium layer 20 is removed by CMP grinding, while the extended metal catalyst layer 24 on the vertical nanowire layer 14 is retained; wherein the upper surface of the extended metal catalyst layer 24 on the surface of the vertical nanowire layer 14 is not higher than the upper surface of the remaining medium layer 20, that is, the upper surface of the remaining extended metal catalyst layer 24 after CMP grinding cannot be higher than the upper surface of the remaining medium layer 20;
[0082] like Figure 7As shown, the extended metal catalyst layer 24 is annealed using a rapid annealing process to form an extended alloy catalyst particle layer 25 between the extended metal catalyst layer 24 and the upright nanowires 140. The rapid annealing process in this step is preferably a laser annealing process or an RTP annealing process. Furthermore, when the rapid annealing process is selected as a laser annealing process, the laser is preferably a pulsed laser.
[0083] When the medium layer is a double-layer stacked structure, the process of forming the continuous metal alloy catalyst particles is as follows:
[0084] like Figure 1 and Figure 2 As shown, a substrate 10 is first provided, on which an upright nanowire layer 14 of semiconductor material is formed; wherein the upright nanowire layer 14 includes a plurality of upright nanowires 140.
[0085] like Figure 9 As shown, a first dielectric layer 21 and a second dielectric layer 22 are then sequentially formed on the substrate 10, wherein the upper surface of the first dielectric layer 21 is lower than the upper surface of the upright nanowire layer 14, and the thickness of the second dielectric layer 22 at least covers the upper surface of the upright nanowire layer 14; the first dielectric layer 21 and the second dielectric layer 22 can be deposited using ALD or CVD processes, but are not limited to these, and other suitable methods can be selected depending on the specific materials of the first dielectric layer 21 and the second dielectric layer 22;
[0086] like Figure 10 As shown, the second dielectric layer 22 is ground using CMP process until the upper surface of the upright nanowires 140 is exposed. It should be noted that when the upper surface of the upright nanowires 140 has a metal catalyst, the metal catalyst also needs to be ground and removed during the CMP process.
[0087] like Figure 11As shown, based on the different etching selectivity ratios of the first dielectric layer 21 and the second dielectric layer 22 with the vertical nanowire 140, the vertical nanowire 140 is etched to form a plurality of blind holes 23 of a predetermined depth in the first dielectric layer 21 and the second dielectric layer 22. The different etching selectivity ratios of the first dielectric layer 21 and the second dielectric layer 22 with the vertical nanowire 140 are generally determined by the selected etching method, such as dry etching or wet etching. Specifically, the materials of the first dielectric layer 21 and the second dielectric layer 22 are selected. For example, when the material of the vertical nanowire 140 is germanium and hydrogen peroxide wet etching is selected, the material of the first dielectric layer 21 can be selected as an oxide or nitride, and the material of the second dielectric layer 22 can be selected as an oxide or nitride or photoresist different from the material of the first dielectric layer 21, so as to achieve the required etching selectivity ratio.
[0088] like Figure 12 As shown, the extended metal catalyst layer 24 is formed on the upper surface of the second dielectric layer 22 and the upright nanowire layer 14. The extended metal catalyst layer 24 can be formed by a solvothermal method, firstly by preparing a colloidal solution of metal nanoparticle catalyst, then by spin-coating or drop-coating the colloidal solution of metal nanoparticle catalyst onto the entire surface of the structure, and then heating to obtain the metal catalyst layer 24. Alternatively, the extended metal catalyst layer 24 can be formed by a thin film deposition process. The specific steps of these two methods for forming the extended metal catalyst layer 24 can be found in the subsequent process of forming the metal catalyst layer 11 on the substrate 10. In this invention, the extended metal catalyst layer 24 is preferably formed by a thin film deposition process. For example, a suitable thin film deposition process can be selected, such as molecular beam epitaxy, electron beam deposition, sputtering, or evaporation. Thin film deposition can form a relatively uniform film thickness for uneven surfaces, and the size of the subsequently formed extended alloy catalyst particle layer can be precisely controlled.
[0089] like Figure 13 As shown, the extended metal catalyst layer 24 on the surface of the second dielectric layer 22 is removed by removing the second dielectric layer 22; as a preferred example, when the material of the second dielectric layer 22 is selected as photoresist, the second dielectric layer 22 can be simply removed by conventional methods such as ashing.
[0090] like Figure 13 As shown, the extended metal catalyst layer 24 is annealed using a rapid annealing process to form an extended alloy catalyst particle layer 25 between the extended metal catalyst layer 24 and the upright nanowires 140. The rapid annealing process in this step is preferably a laser annealing process or an RTP annealing process. Furthermore, when the rapid annealing process is selected as a laser annealing process, the laser is preferably a pulsed laser.
[0091] As an example, in step S9, it is preferable to use continuous laser irradiation of the extension solution to ensure that the laser energy increases the growth rate of the extension nanowires.
[0092] As an example, when the extended nanowire is a germanium nanowire, the extended solution in step S9 is formed by dissolving GeI2 inorganic salt in a solution formed by trioctylphosphine and / or oleylamine.
[0093] like Figure 5 and Figure 11 As shown, as an example, the depth of the blind hole 23 formed in step S4 is generally selected to be 15nm to 80nm. Further, as... Figure 7 and Figure 13 As shown, in step S6, the height difference between the upper surface of the extended alloy catalyst particle layer 25 on the surface of the upright nanowire layer 14 and the upper surface of the remaining medium layer is 5nm to 10nm, so that the extended alloy catalyst droplets formed by the subsequent melting of the extended alloy catalyst particle layer 25 are confined in the depression formed by the height difference, which can further improve the collimation rate of the extended nanowires relative to the upright nanowires when the extended nanowires are extended.
[0094] To more clearly demonstrate the technical solution and effects provided by this invention, the nanowire extension method of this invention will be described in detail below with reference to a specific embodiment and accompanying drawings.
[0095] Example 1
[0096] This embodiment includes two steps: the first step is to form an upright nanowire layer of semiconductor material on a substrate, and the second step is to continue growing a continuous nanowire layer on the upright nanowire layer formed in the first step.
[0097] Part One: As Figures 15 to 18 As shown, the process of forming a vertical nanowire layer 14 of semiconductor material on substrate 10 includes the following steps:
[0098] Step A, as Figure 15 As shown, a germanium material substrate of appropriate size is taken and cleaned with hexane, acetone and water respectively. Then, the intrinsic oxide layer on the substrate surface is removed with hydrofluoric acid or hydrochloric acid, and then a metal catalyst layer 11 is formed on the surface of the substrate 10.
[0099] In this embodiment, two methods are used to achieve the process of forming a metal catalyst layer 11 on the surface of the substrate 10.
[0100] Method 1: In a reaction flask, using 0.4g–0.8g of bismuth neodecanoate as the raw material, add 4mL–4.3mL of 1-octadecene, and purge with argon or nitrogen inert gas at 115℃–130℃ to remove water and oxygen for 60min–120min. Then, transfer the reaction flask to glove box 17, add 0.1mL–0.3mL of dodecanethiol, and stir at 40℃–80℃ for 8min–12min, forming a yellow liquid in the reaction flask. Next, add 0.5mL–1.5mL of trioctylphosphine to the yellow liquid obtained in the reaction flask, and carry out a reduction reaction at 60℃–70℃ for 20min–40min. Then, let it stand for 1.5h–2.5h to obtain bismuth metal nanoparticles. The bismuth metal nanoparticle catalyst colloidal solution is then diluted to 1.5 to 2.5 times its original volume for later use. 0.8 mL to 1.2 mL of the diluted bismuth metal nanoparticle catalyst colloidal solution is taken and centrifuged to obtain catalyst particles of the desired size, resulting in a brownish-yellow supernatant. This supernatant is the bismuth metal nanoparticle catalyst colloidal solution of the desired concentration. Finally, the substrate 10 is physically fixed to the bottom of the reaction vessel in the glove box 17. The bismuth metal nanoparticle catalyst colloidal solution of the desired concentration is then spin-coated or drop-coated onto the surface of the substrate 10 to form a bismuth metal nanoparticle catalyst colloidal liquid film. The substrate 10 with the bismuth metal nanoparticle catalyst colloidal liquid film is then heated, thereby forming the metal catalyst layer 11 on the surface of the substrate 10.
[0101] The second method involves directly forming a bismuth metal catalyst layer 11 on the surface of the substrate 10 using molecular beam epitaxy; the thickness of the metal catalyst layer can be selected, for example, from 2 nm to 10 nm.
[0102] Step B, as follows Figure 16 As shown, the metal catalyst layer 11 is annealed using a pulsed laser annealing process or an RTP annealing process to form an alloy catalyst particle layer 12 between the metal catalyst layer 11 and the substrate 10, that is, to form an alloy catalyst particle layer 12 of germanium-bismuth material. Since there is no solvent during annealing, there is no solvent interference, and the alloy formation rate is very fast, which will not cause the fusion and slippage of low-melting-point catalysts on the substrate, and the alloy catalyst particle layer 12 can be formed in situ.
[0103] Step C: Laser path calibration for irradiating the precursor solution: Turn on the laser guide light, check the collimation of the optical path, and after confirming that there are no objects obstructing the optical path, move the stage to transmit the laser spot to the preset position, and then turn on the laser.
[0104] Step D, Preparation of the precursor solution: Weigh 0.1g to 1.0g of GeI2 inorganic salt in a glove box and place it in the transition chamber for later use (GeI2 needs to be stored in an inert gas environment and protected from light after opening); Take out the reaction flask in an oven at 110℃ to 130℃ and quickly draw a certain volume, about 18mL to 22mL, of a single-component solution of trioctylphosphine or oleylamine, or a mixed component solution of trioctylphosphine and oleylamine, and place it in the reaction flask. Then, purge the solution with argon gas at 110℃ to 130℃ for 1.2h to 1.8h. After the solution cools to room temperature, transfer the weighed GeI2 inorganic salt to the cooled single-component solution of trioctylphosphine or oleylamine, or a mixed component solution of trioctylphosphine and oleylamine. Seal the flask and sonicate it in the dark for 15min to 20min to completely dissolve the yellow powder of GeI2 inorganic salt and obtain a clear, light yellow precursor solution for later use. Generally, precursor solutions should be prepared fresh before use.
[0105] Step E, as Figure 17 As shown, laser-induced growth and in-situ doping of upright nanowires 140: The substrate 10 containing the metal alloy catalyst layer 12 formed in step B is placed in a glove box 17, and the precursor solution obtained in step D is placed in the glove box 17. The precursor solution is irradiated with a continuous laser 16 with a wavelength of approximately 1064 nm, a power of approximately 25 W to 40 W, and a spot size of approximately 3 mm to 7 mm. Figure 18 As shown, with the irradiation of the continuous laser 16, the alloy catalyst particle layer 12 melts into alloy catalyst droplets 13, and the reduction reaction begins to accelerate, with the fastest reduction reaction rate near the surface of the substrate 10; as Figure 19 As shown, under the action of the bismuth catalyst, the reduction reaction on the alloy catalyst droplet 13 is the fastest. The germanium atoms formed enter the alloy catalyst droplet 13 and form catalyst droplets 18 that have absorbed precursor atoms. The germanium atoms are saturated and precipitated in the droplets to form... Figure 20 The upright nanowire layer 14 of germanium material in the catalyst droplet; as the reduction reaction continues, the growth ends when the concentration of germanium atoms in the alloy catalyst droplet becomes too low to precipitate, resulting in the desired product. Figure 21 The upright nanowire layer 14 shown is for ease of understanding. Figure 21 The diagram only shows one upright nanowire in the upright nanowire layer 14. During growth, bismuth catalyst atoms are gradually embedded into the lattice of the upright nanowire 140, achieving in-situ doping. The final upright nanowire 140 has a diameter of approximately 20 nm to 500 nm and a length of 0.3 μm to 8 μm.
[0106] It should be noted that, depending on the actual needs of the reaction, there is no specific order of steps A to E above. According to the reaction logic, some steps need to be performed sequentially, while others can be performed separately. For example, steps A and B have a logical order, but there is no logical order between them and step C. Steps A, B, and C can be performed simultaneously or sequentially. Similarly, there is no logical order between steps A, B, and D. They can be performed simultaneously or sequentially.
[0107] Part Two: Based on the upright nanowire layer 14 formed in Part One above, the process of growing a continuous nanowire layer 26 on the upright nanowire layer 14 is carried out. In this process, the medium layer is prepared by using two different structures to realize the preparation of the continuous metal alloy catalyst layer, specifically a single-layer structure and a double-layer stacked structure.
[0108] When the medium layer is a single-layer structure, the process of forming the extended alloy catalyst particle layer is as follows:
[0109] like Figure 1 and Figure 2 As shown, a substrate 10 is first provided, on which an upright nanowire layer 14 of semiconductor material is formed; wherein the upright nanowire layer 14 includes a plurality of upright nanowires 140.
[0110] like Figure 3 As shown, an alumina or silicon dioxide dielectric layer 20 is then formed on the substrate 10 using an ALD or CVD process. The dielectric layer 20 covers the upright nanowire layer 14 and its thickness at least covers the upper surface of the upright nanowire layer 14.
[0111] like Figure 4 As shown, the dielectric layer 20 is ground using CMP process until the upper surface of the upright nanowires 140 is exposed, and the metal catalyst ions on the upper surface of the upright nanowires 140 are removed.
[0112] like Figure 5 As shown, based on the different etching selectivity ratios of the dielectric layer 20 and the upright nanowire 140, the upright nanowire 140 is etched by hydrogen peroxide wet etching to form a plurality of blind holes 23 of a predetermined depth in the dielectric layer 20.
[0113] like Figure 6As shown, a bismuth-based extended metal catalyst layer 24 is formed on the upper surface of the dielectric layer 20 and the upright nanowire layer 14 using molecular beam epitaxy or sputtering. The thickness of the extended metal catalyst layer 24 is selected to be 2 nm to 10 nm. This step is the same as the bismuth-based metal catalyst layer 11 formed by the second method when forming the metal catalyst layer 11 on the surface of the substrate 10 in the first part. Therefore, the doping type of the subsequently formed extended nanowire layer is the same as that of the upright nanowire layer, which is bismuth-doped germanium nanowires. Of course, if the doping type of the subsequently formed extended nanowire layer is opposite to that of the upright nanowire layer, the material of the extended metal catalyst layer 24 in this step can be selected as tin, gallium, or indium.
[0114] like Figure 7 As shown, the extended metal catalyst layer 24 on the surface of the dielectric layer 20 is removed by CMP grinding, while the extended metal catalyst layer 24 on the upright nanowire layer 14 is retained.
[0115] like Figure 7 As shown, the extended metal catalyst layer 24 is annealed using an RTP rapid annealing process to form extended alloy catalyst particles 25 between the extended metal catalyst layer 24 and the upright nanowires 140.
[0116] When the medium layer is a double-layer stacked structure, the process of forming the extended metal alloy catalyst layer is as follows:
[0117] like Figure 1 and Figure 2 As shown, a substrate 10 is first provided, on which an upright nanowire layer 14 of semiconductor material is formed; wherein the upright nanowire layer 14 includes a plurality of upright nanowires 140.
[0118] like Figure 9 As shown, an alumina or silicon dioxide material first dielectric layer 21 and a photoresist material second dielectric layer 22 are sequentially formed on the substrate 10 using an ALD or CVD process. The upper surface of the first dielectric layer 21 is lower than the upper surface of the upright nanowire layer 14, and the thickness of the second dielectric layer 22 at least covers the upper surface of the upright nanowire layer 14.
[0119] like Figure 10 As shown, the second dielectric layer 22 is ground using CMP process until the upper surface of the upright nanowires 140 is exposed, and the metal catalyst ions on the upper surface of the upright nanowires 140 are removed.
[0120] like Figure 11As shown, based on the different etching selectivity ratios of the first dielectric layer 21 and the second dielectric layer 22 with the upright nanowire 140, the upright nanowire 140 is etched to form a plurality of blind holes 23 of a predetermined depth in the first dielectric layer 21 and the second dielectric layer 22.
[0121] like Figure 12 As shown, the extended metal catalyst layer 24 of bismuth material is formed on the upper surface of the second dielectric layer 22 and the vertical nanowire layer 14 using molecular beam epitaxy or sputtering.
[0122] like Figure 13 As shown, the extended metal catalyst layer 24 on the surface of the second medium layer 22 is removed by removing the second medium layer 22;
[0123] like Figure 13 As shown, the extended metal catalyst layer 24 is annealed using an RTP rapid annealing process to form extended alloy catalyst particles 25 between the extended metal catalyst layer 24 and the upright nanowires 140.
[0124] After forming the extended alloy catalyst particle layer 25 using the above two structures of dielectric layers, the subsequent extended nanowire layer 26 is prepared. In this embodiment, the extended nanowires 260 and the upright nanowires 140 in the extended nanowire layer 26 are made of the same material, germanium, and use the same precursor solution. That is, the preparation of the extended solution can be found in step D of the first part of this embodiment. Figure 8 and Figure 14 As shown, the entire substrate with the extended alloy catalyst particle layer 25 is finally placed in the extension solution, and the extension solution is irradiated with a continuous laser with a wavelength of approximately 1064 nm, a power of approximately 25 W to 40 W, and a spot size of approximately 3 mm to 7 mm. The extension process is the same as the growth process of the upright nanowires. For details, please refer to [link to documentation]. Figures 18 to 21 Finally, the continuous nanowire 260 is achieved on the vertical nanowire 140 in the vertical nanowire layer 14, and bismuth atoms are embedded in the lattice of the continuous nanowire 260 during the continuous nanowire 260 process to achieve in-situ doping.
[0125] In summary, this invention provides a method for nanowire extension. First, a dielectric layer flush with the surface of the upright nanowire layer is formed using a CMP process. Then, based on different etching selectivity ratios between the dielectric layer and the upright nanowires, the upright nanowires are etched to form blind holes above them. These blind holes establish a basis for the dielectric layer and the upper surface of the upright nanowire layer to have different horizontal heights. This results in the subsequently formed extension metal catalyst layer also having an uneven surface, allowing for easy removal of the extension metal catalyst layer on the dielectric layer surface while retaining the extension metal catalyst layer on the upright nanowire layer, achieving precise alignment between the extension metal catalyst layer and the upright nanowire layer. Finally, based on the precisely aligned extension metal catalyst layer, in-situ doping of the extension nanowires on the upright nanowires is achieved, enabling upright extension. This extension method can achieve more than two growths of semiconductor nanowires after semiconductor processing, providing a basis for constructing homojunctions or heterojunctions. Furthermore, this extension method avoids secondary photolithography, is simple to implement, and has a short reaction time, low cost, and environmentally friendly raw materials. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0126] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for extending nanowires, characterized in that, The method for extending the length includes the following steps: S1. A substrate is provided, on which a layer of upright nanowires of semiconductor material is formed; wherein the upright nanowire layer comprises a plurality of upright nanowires. S2. A dielectric layer is formed on the substrate, the dielectric layer covering the upright nanowire layer and having a thickness that at least covers the upper surface of the upright nanowire layer; S3. Grind the dielectric layer using CMP process until the upper surface of the upright nanowires is exposed; S4. Based on the different etching selectivity ratios of the dielectric layer and the upright nanowire, the upright nanowire is etched to form a plurality of blind holes of a predetermined depth in the dielectric layer. S5. A continuous metal catalyst layer is formed on the upper surface of the dielectric layer and the upright nanowire layer obtained in step S4. S6. Remove the extended metal catalyst layer on the surface of the dielectric layer, and retain the extended metal catalyst layer on the upright nanowire layer; The upper surface of the extended metal catalyst layer on the surface of the upright nanowire layer is not higher than the upper surface of the remaining dielectric layer; S7. The extended metal catalyst layer is annealed using a rapid annealing process to form an extended alloy catalyst particle layer between the extended metal catalyst layer and the upright nanowires. S8. The substrate with the extended alloy catalyst particle layer obtained in step S7 is placed in an extended solution, wherein the extended solution includes a semiconductor element precursor for forming extended nanowires. S9. The substrate in the extended solution is vertically irradiated with a laser. The thermal accumulation effect of laser heating liquefies the extended alloy catalyst particle layer into extended alloy catalyst droplets. Simultaneously, the photothermal effect of the liquefied extended alloy catalyst droplets under laser irradiation accelerates the redox reaction of the precursor in the extended solution. The atoms generated by the catalytic redox reaction dissolve into the extended alloy catalyst droplets. When the atoms reach a saturation concentration in the extended alloy catalyst droplets, they crystallize and grow epitaxially, realizing the vertical extension of extended nanowires on the corresponding upright nanowires. During the vertical extension of the extended nanowires, the extended metal atoms in the extended metal catalyst layer are embedded into the lattice of the extended nanowires to achieve in-situ doping. The growth direction of the extended nanowires is consistent with the upright direction of the upright nanowires.
2. The nanowire extension method according to claim 1, characterized in that: The medium layer is a single-layer structure; in step S6, the extended metal catalyst layer on the surface of the medium layer is removed by CMP process.
3. The nanowire extension method according to claim 1, characterized in that: The dielectric layer is formed by stacking a first dielectric layer located at the bottom and a second dielectric layer located at the top, both of which are made of different materials. In step S2, the upper surface of the first dielectric layer is lower than the upper surface of the upright nanowire layer, and the thickness of the second dielectric layer at least covers the upper surface of the upright nanowire layer. In step S3, the second dielectric layer is ground using CMP process until the upper surface of the upright nanowires is exposed; In step S4, the upper surface of the vertical nanowire corresponding to the blind hole is lower than the upper surface of the first dielectric layer; in step S6, the extended metal catalyst layer on the surface of the dielectric layer is removed by removing the second dielectric layer.
4. The nanowire extension method according to claim 3, characterized in that: The material of the second dielectric layer is photoresist.
5. The method for extending nanowires according to claim 1, characterized in that: The material of the extended nanowire is the same as that of the upright nanowire.
6. The method for extending nanowires according to claim 5, characterized in that: The materials of the extended nanowires and the upright nanowires are germanium.
7. The method for extending nanowires according to claim 6, characterized in that: The doping atoms of the extended nanowires are one of indium, tin, gallium, bismuth and gold or an alloy thereof; The doping atoms of the upright nanowires are one of indium, tin, gallium, bismuth and gold or an alloy thereof.
8. The method for extending nanowires according to claim 6, characterized in that: The extended solution mentioned in step S9 is formed by dissolving GeI2 inorganic salt in a solution formed by trioctylphosphine and / or oleylamine.
9. The method for extending nanowires according to claim 6, characterized in that: In step S4, the upright nanowires are etched using a wet etching process.
10. The method for extending nanowires according to claim 9, characterized in that: The etching solution used in the wet etching process in step S4 includes hydrogen peroxide.
11. The method for extending nanowires according to claim 1, characterized in that: In step S5, the extended metal catalyst layer is formed directly on the upper surface of the dielectric layer and the upright nanowire layer using a thin film deposition process.
12. The method for extending nanowires according to claim 11, characterized in that: The thin film deposition process is molecular beam epitaxy, electron beam deposition, sputtering, or vapor deposition.
13. The method for extending nanowires according to claim 1, characterized in that: The rapid annealing process in step S7 is either laser annealing or RTP annealing; in step S9, the extended solution is irradiated with a continuous laser.
14. The method for extending nanowires according to claim 1, characterized in that: The depth of the blind hole formed in step S4 is 15 nm to 80 nm; the height difference between the upper surface of the extended metal alloy catalyst layer and the upper surface of the remaining medium layer on the surface of the upright nanowire layer in step S6 is 5 nm to 10 nm.