A multi-chip LVDS ADC synchronization method and system for a hemispherical resonator gyro control circuit
Patent Information
- Application Number
- CN202610973311.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-01
- Publication Date
- 2026-10-09
AI Technical Summary
[0007]本发明的目的在于提供一种用于半球谐振陀螺控制电路的多片LVDS ADC同步方法及系统，用于解决现有技术尚无成熟、通用的方法能够有效解决多片串行LVDS ADC在半球谐振陀螺控制电路中的时钟同步与数据对齐问题
本方案可灵活选用多片多通道ADC及DAC，在一块电路板上即可集成3至6轴半球谐振陀螺的控制功能。实测使用该同步方法后，多片ADC之间的相位偏差由16ns降至110ps以下，数据采集严格同步。该方法有效解决了多片串行LVDS ADC时钟同步与数据对齐问题，满足了半球谐振陀螺控制对高精度采样的需求。同时，该方案减少了分立元件和复杂布线，降低了功耗，有利于实现半球谐振陀螺控制电路的小型化与集成化设计。
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Figure CN122881653A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of hemispherical resonant gyroscope technology, specifically to a method and system for synchronizing multiple LVDS ADCs in a hemispherical resonant gyroscope control circuit. Background Technology
[0002] A hemispherical resonant gyroscope is a solid-state wave gyroscope that utilizes the Coriolis effect to sense angular velocity. It mainly consists of three parts: an excitation shield, a hemispherical resonator, and a base. Compared to traditional mechanical gyroscopes, hemispherical resonant gyroscopes offer advantages such as high precision, good stability, strong shock resistance, and long lifespan, making them promising for widespread application in inertial navigation systems.
[0003] The control circuit of a hemispherical resonator gyroscope is a key component for realizing the excitation and detection of the vibration of the hemispherical resonator. It is usually composed of an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a system-on-a-chip (SOC) or a field-programmable gate array (FPGA), and their peripheral circuits. Among them, the ADC is used to detect the displacement signal of the resonator, and the DAC is used to output the excitation signal to drive the motion of the resonator.
[0004] With the increasing demands for miniaturization, integration, and low power consumption in inertial navigation systems, hemispherical resonator gyroscope control circuits need to integrate multiple ADCs and DACs on a single circuit board to achieve synchronous control of three-axis to six-axis hemispherical resonator gyroscopes. Therefore, synchronous acquisition among multiple ADCs and synchronous driving among multiple DACs have become critical technical problems that urgently need to be solved.
[0005] In existing technologies, commonly used ADC interface types include parallel CMOS, parallel LVDS, and serial LVDS. Among them, serial LVDS ADCs have gradually become the preferred choice for highly integrated control circuits due to their advantages such as fewer pins, simpler wiring, and stronger anti-interference capabilities. However, serial LVDS ADCs output a dedicated clock (DCO) and a frame synchronization signal (FCO) during operation, requiring the FPGA to deserialize the serial data. Because the PLL divider has a random phase after reset, the phase relationship between the deserialization clock and the system master clock between different ADC chips is uncertain, resulting in phase inconsistencies in the data acquired by multiple ADCs. This severely affects the control accuracy and system stability of the hemispherical resonator gyroscope.
[0006] Currently, there is no mature and universally applicable method to effectively solve the clock synchronization and data alignment problem of multiple serial LVDS ADCs in hemispherical resonator gyroscope control circuits. Therefore, this paper proposes a reliable and efficient method and system for synchronizing multiple LVDS ADCs, which is of great significance for realizing the low-power, miniaturized, and integrated design of hemispherical resonator gyroscope control circuits. Summary of the Invention
[0007] The purpose of this invention is to provide a method and system for synchronizing multiple LVDS ADCs in a hemispherical resonant gyroscope control circuit, which solves the problem that there is no mature and universal method in the prior art that can effectively solve the clock synchronization and data alignment problem of multiple serial LVDS ADCs in a hemispherical resonant gyroscope control circuit.
[0008] To achieve the above objectives, the present invention provides the following technical solution:
[0009] A method for synchronizing multiple LVDS ADCs in a hemispherical resonant gyroscope control circuit includes the following steps: Step 1: Specify the expected number of shifts (RequiredSlipCnt); Step 2: After the FPGA system is reset or a reset signal is sent to the PS terminal of the SOC, reset the ADC decoding module, PLL module and ISERDESE2 module; Step 3: Clear the shift counter SlipCount to zero; Step 4: After reset and release, the PLL module is locked in a random phase; Step 5: The ADC decoding module detects the deserialized frame synchronization signal FCO[7:0]. If it is not 8'b11110000, it sends a BIT_SLIP shift pulse to the ISERDESE2 module and increments SlipCount by 1. This step is repeated until FCO[7:0] is aligned. Step 6: After alignment, determine whether SlipCount is equal to RequiredSlipCnt except for the least significant bit. If not, re-trigger the PLL module and ISERDESE2 module to reset, and repeat steps 3 to 6 until SlipCount meets the requirements, thereby determining the phase relationship between the low-frequency clock CLK_DIV_IN and the main clock CLK+ / CLK-, and realizing synchronous acquisition of multiple LVDS ADCs.
[0010] Furthermore, the expected number of shifts, RequiredSlipCnt, ranges from 0 to 2.
[0011] Furthermore, the PLL module is a PLL, MMCM, or BUFR module inside the FPGA, used to divide the LVDS clock DCO+ / DCO- output by the ADC to generate a high-frequency clock CLK_IN with the same frequency and phase, and a low-frequency clock CLK_DIV_IN divided by 4.
[0012] Furthermore, the ISERDESE2 module is used to serially deserialize LVDS data DA[1:0]+ / DA[1:0]-, DB[1:0]+ / DB[1:0]-, DC[1:0]+ / DC[1:0]- and frame synchronization signals FCO+ / FCO-, and output parallel data.
[0013] A multi-chip LVDS ADC synchronization system for a hemispherical resonant gyroscope control circuit includes:
[0014] Multiple serial LVDS ADCs are used to acquire the detection signals of the hemispherical resonant gyroscope;
[0015] An FPGA or SOC is used to provide the master clock CLK+ / CLK- to each ADC and to receive the LVDS clock DCO+ / DCO-, LVDS data and LVDS frame synchronization signal output by each ADC.
[0016] The signal conditioning circuit is connected between the hemispherical resonant gyroscope and the ADC;
[0017] The driver amplifier circuit is connected between the DAC and the hemispherical resonant gyroscope;
[0018] Multiple DACs are used to output excitation signals;
[0019] The FPGA or SOC includes a PLL module, an ISERDESE2 module, and an ADC decoding module, wherein the ADC decoding module performs the synchronization method as described in claim 1.
[0020] Furthermore, the ADC is a 4-channel serial LVDS type 16-bit ADC, and the DAC is a 2-channel parallel LVDS type 16-bit DAC.
[0021] Furthermore, the master clock inside the FPGA or SOC is simultaneously output to all ADCs and DACs to ensure that the clocks originate from the same source.
[0022] Furthermore, the ADC decoding module outputs parallel data clocked by the master clock CLK to the hemispherical resonator gyroscope calculation module for closed-loop control calculation.
[0023] Furthermore, the synchronization method is applied to the control circuit of 3-axis to 6-axis hemispherical resonant gyroscopes to achieve integrated control of multi-axis gyroscopes.
[0024] Furthermore, the system achieves a phase deviation of less than 110 ps between multiple ADCs, and the sampled data is strictly synchronized.
[0025] Compared with the prior art, the beneficial effects of the present invention are: This solution allows for the flexible selection of multiple multi-channel ADCs and DACs, integrating the control functions of 3 to 6-axis hemispherical resonator gyroscopes onto a single circuit board. Actual measurements using this synchronization method reduced the phase deviation between multiple ADCs from 16ns to below 110ps, ensuring strict data synchronization. This method effectively solves the clock synchronization and data alignment problems of multiple serial LVDS ADCs, meeting the high-precision sampling requirements of hemispherical resonator gyroscope control. Simultaneously, this solution reduces discrete components and complex wiring, lowers power consumption, and facilitates the miniaturization and integration of the hemispherical resonator gyroscope control circuit. Attached Figure Description
[0026] Figure 1 This is a circuit block diagram of a multi-chip LVDS ADC synchronization system for a hemispherical resonant gyroscope control circuit according to the present invention.
[0027] Figure 2 This is an HDL block diagram of a multi-chip LVDS ADC synchronization system for a hemispherical resonant gyroscope control circuit according to the present invention.
[0028] Figure 3 This is a timing diagram of the ADC decoding section of the present invention;
[0029] Figure 4 This is a flowchart of a method for synchronizing multiple LVDS ADCs in a hemispherical resonant gyroscope control circuit according to the present invention. Detailed Implementation
[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0031] The following detailed description, in conjunction with the accompanying drawings and embodiments, provides a method and system for synchronizing multiple LVDSADCs in a hemispherical resonant gyroscope control circuit according to the present invention. It should be noted that the following embodiments are for illustrative purposes only and do not constitute a limitation on the scope of protection of the present invention.
[0032] I. Hardware Components of a Six-Axis Hemispherical Resonant Gyroscope Control System
[0033] like Figure 1The diagram shown is a circuit block diagram of one embodiment of the present invention. This circuit is used to control a six-axis hemispherical resonant gyroscope. The master clock CLK generated inside the FPGA or SOC is differentially driven and simultaneously output to two three-channel serial LVDS 16-bit ADCs and three two-channel parallel LVDS 16-bit DACs to ensure that the sampling clocks of all ADCs and DACs are from the same source as the driving clocks.
[0034] The detection signals from the six-axis hemispherical resonator gyroscope are processed by signal conditioning circuits (including filtering and amplification) before being input to two ADCs. Each ADC uses its first three channels, corresponding to the detection signals from the three-axis gyroscopes. The ADCs sample and convert the analog signals using the master clock CLK+ / CLK- as a reference. The converted data is then output to the FPGA or SOC via a serial LVDS interface.
[0035] The FPGA or SOC internally decodes, processes, and encodes the received serial LVDS signal to generate corresponding drive data, which is then output to three DACs via the LVDS interface. The DACs convert the digital signal into analog excitation signal, which is then amplified by the drive circuit and output to the six-axis hemispherical resonator gyroscope to form a closed-loop control.
[0036] II. FPGA Internal HDL Implementation Method
[0037] like Figure 2 The diagram shown is an HDL principle block diagram of one embodiment of the present invention, with one three-channel ADC as an example for illustration.
[0038] The ADC receives the master clock CLK+ / CLK- driven differentially from the FPGA or SOC, uses this clock as a reference to sample analog signals, and after analog-to-digital conversion, outputs the following signals through the serial LVDS interface:
[0039] The LVDS clock DCO+ / DCO- has a frequency that is 4 times that of the master clock CLK+ / CLK-.
[0040] LVDS data DA[1:0]+ / DA[1:0]-, DB[1:0]+ / DB[1:0]-, DC[1:0]+ / DC[1:0]-;
[0041] LVDS frame synchronization signals FCO+ / FCO-
[0042] After the above signals are input to the FPGA, DCO+ / DCO- first enters the PLL module (MMCM or BUFR modules can also be used, hereinafter collectively referred to as PLL). The PLL module outputs two clock signals:
[0043] CLK_IN: A high-frequency clock that is in phase and frequency with DCO+ / DCO-;
[0044] CLK_DIV_IN: The low-frequency clock after dividing DCO+ / DCO- by 4.
[0045] CLK_IN and CLK_DIV_IN are simultaneously input to the ISERDESE2 module to perform serial deserialization on DA[1:0]+ / DA[1:0]-, DB[1:0]+ / DB[1:0]-, DC[1:0]+ / DC[1:0]- and FCO+ / FCO-, and output parallel data DA[15:0], DB[15:0], DC[15:0] and FCO[7:0] with CLK_DIV_IN as the clock.
[0046] The ADC decoding module sends a BIT_SLIP shift pulse to the ISERDESE2 module based on the state of FCO[7:0]. At the same time, based on the comparison result between the shift count SlipCount and the expected shift count RequiredSlipCnt, the ADC decoding module sends reset signals PLL_RESET and IO_RESET to the PLL module and the ISERDESE2 module.
[0047] Once the ADC decoding module detects that the parallel data is aligned and the clock is synchronized, it outputs synchronized parallel data DA'[15:0], DB'[15:0], DC'[15:0], and FCO'[7:0], clocked with the master clock CLK, to the hemispherical resonator gyroscope calculation module. This calculation module can be implemented using existing technologies, such as PID control and frequency demodulation.
[0048] III. Explanation of Timing Relationships
[0049] like Figure 3 The diagram shown is a timing diagram of the ADC decoding part of this invention, with the data DA of one channel as an example for illustration.
[0050] CLK: Internal master clock of FPGA or SOC;
[0051] DCO: Serial LVDS clock output by the ADC, with a frequency 4 times that of the master clock and a phase delay of 90° compared to the data.
[0052] DA[0] and DA[1]: The first channel data output by the ADC serial LVDS interface, with data bits numbered D15~D0 in sequence;
[0053] FCO: Frame synchronization signal. The first 4 bits of each frame of data are high level and the last 4 bits are low level.
[0054] CLK_IN: A high-frequency clock output from the PLL that is in phase and frequency with the DCO;
[0055] CLK_DIV_IN: The low-frequency clock output by 4 from the PLL. The dashed line in the figure represents all possible random phases after reset and release, and the thick solid line represents the expected definite phase after synchronization.
[0056] DA[15:0]: Parallel data after deserialization, clocked by CLK_DIV_IN;
[0057] DA'[15:0]: Parallel data output after synchronization, with CLK as the clock.
[0058] The method of this invention can lock the phase of CLK_DIV_IN from an uncertain state (dashed line) to an expected state (thick solid line), thereby ensuring that the parallel data after deserialization of multiple ADCs is strictly synchronized with the system master clock.
[0059] IV. Synchronization Method and Flow
[0060] like Figure 4 The diagram shows a flowchart of the multi-chip LVDS ADC synchronization method of the present invention, which specifically includes the following steps:
[0061] Step 1: Based on the system design requirements, specify an expected number of shifts RequiredSlipCnt, typically ranging from 0 to 2;
[0062] Step 2: After the FPGA system is powered on and reset or a reset signal is sent from the PS terminal of the SOC, reset the ADC decoding module, PLL module and ISERDESE2 module;
[0063] Step 3: Clear the shift counter SlipCount to zero;
[0064] Step 4: After reset and release, the PLL module locks into a random phase, corresponding to... Figure 3 The position of the dashed line in CLK_DIV_IN;
[0065] Step 5: The ADC decoding module detects the deserialized frame synchronization signal FCO[7:0]:
[0066] If FCO[7:0] is not equal to 8'b11110000, it means that the parallel data is not aligned;
[0067] At this time, a BIT_SLIP shift pulse is sent to the ISERDESE2 module, and SlipCount is incremented by 1;
[0068] Repeat step 5 until FCO[7:0] equals 8'b11110000, indicating that the data is aligned;
[0069] Step 6: After data alignment, determine whether SlipCount meets the requirement, that is, whether SlipCount is equal to RequiredSlipCnt except for the least significant bit:
[0070] If the conditions are met, synchronization is completed, and the CLK_DIV_IN phase is determined.
[0071] If the requirements are not met, the PLL module and ISERDESE2 module are reset, and the process returns to step 3 to re-align and count until SlipCount meets the requirements.
[0072] The above method was used to perform synchronization tests on two three-channel serial LVDS ADCs, driven by the same master clock. The experimental results show that the phase deviation between the two ADCs before synchronization was approximately 16 ns, and after synchronization, the phase deviation decreased to below 110 ps, meeting the requirements for high-precision hemispherical resonator gyroscope control.
[0073] Those skilled in the art should understand that this invention is not only applicable to six-axis hemispherical resonant gyroscope control systems, but can also be extended to multi-axis configurations such as three-axis, four-axis, and five-axis systems. The model, number of channels, and bit depth of the ADC and DAC can be flexibly selected according to actual needs. As long as the synchronization method and system architecture proposed in this invention are adopted, they all fall within the protection scope of this invention.
[0074] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A method for synchronizing multiple LVDS ADCs in a hemispherical resonant gyroscope control circuit, characterized in that, Includes the following steps: Step 1: Specify the expected number of shifts (RequiredSlipCnt); Step 2: After the FPGA system is reset or a reset signal is sent from the PS terminal of the SOC, reset the ADC decoding module, PLL module and ISERDESE2 module; Step 3: Clear the shift counter SlipCount to zero; Step 4: After reset and release, the PLL module is locked in a random phase; Step 5: The ADC decoding module detects the deserialized frame synchronization signal FCO[7:0]. If it is not 8'b11110000, it sends a BIT_SLIP shift pulse to the ISERDESE2 module and increments SlipCount by 1. This step is repeated until FCO[7:0] is aligned. Step 6: After alignment, determine whether SlipCount is equal to RequiredSlipCnt except for the least significant bit. If not, re-trigger the PLL module and ISERDESE2 module to reset, and repeat steps 3 to 6 until SlipCount meets the requirements, thereby determining the phase relationship between the low-frequency clock CLK_DIV_IN and the main clock CLK+ / CLK-, and realizing synchronous acquisition of multiple LVDS ADCs.
2. The method according to claim 1, characterized in that: The expected number of shifts, RequiredSlipCnt, ranges from 0 to 2.
3. The method according to claim 1, characterized in that: The PLL module is a PLL, MMCM, or BUFR module inside the FPGA, used to divide the LVDS clock DCO+ / DCO- output by the ADC to generate a high-frequency clock CLK_IN with the same frequency and phase, and a low-frequency clock CLK_DIV_IN divided by 4.
4. The method according to claim 1, characterized in that: The ISERDESE2 module is used to serially deserialize LVDS data DA[1:0]+ / DA[1:0]-, DB[1:0]+ / DB[1:0]-, DC[1:0]+ / DC[1:0]- and frame synchronization signals FCO+ / FCO-, and output parallel data.
5. A multi-chip LVDS ADC synchronization system for a hemispherical resonant gyroscope control circuit, characterized in that, include: Multiple serial LVDS ADCs are used to acquire the detection signals of the hemispherical resonant gyroscope; An FPGA or SOC is used to provide the master clock CLK+ / CLK- to each ADC and to receive the LVDS clock DCO+ / DCO-, LVDS data and LVDS frame synchronization signal output by each ADC; The signal conditioning circuit is connected between the hemispherical resonant gyroscope and the ADC; The driver amplifier circuit is connected between the DAC and the hemispherical resonant gyroscope; Multiple DACs are used to output excitation signals; The FPGA or SOC includes a PLL module, an ISERDESE2 module, and an ADC decoding module, wherein the ADC decoding module performs the synchronization method as described in claim 1.
6. The system according to claim 5, characterized in that: The ADC is a 4-channel serial LVDS 16-bit ADC, and the DAC is a 2-channel parallel LVDS 16-bit DAC.
7. The system according to claim 5, characterized in that: The master clock inside the FPGA or SOC is simultaneously output to all ADCs and DACs to ensure that the clocks originate from the same source.
8. The system according to claim 5, characterized in that: The ADC decoding module outputs parallel data with the master clock CLK as the clock to the hemispherical resonator gyroscope calculation module for closed-loop control calculation.
9. The method according to claim 1, characterized in that: The synchronization method is applied to the control circuit of 3-axis to 6-axis hemispherical resonant gyroscopes to achieve integrated control of multi-axis gyroscopes.
10. The system according to claim 5, characterized in that: The system achieves a phase deviation of less than 110 ps between multiple ADCs and ensures strict synchronization of sampling data.