An interleaved binning low noise infrared readout circuit structure

Abstract

The application discloses a kind of interlaced binning low-noise infrared readout circuit structure, belong to infrared detector readout circuit technical field, specifically using binning and non-binning mode alternate reading working mode, including multiplexed readout channel, each readout channel corresponds a column of pixels, including sequentially connected channel, CTIA, sample-and-hold circuit and ADC;The input end and the output end of CTIA in adjacent readout channel are connected in parallel by switch respectively, enter non-binning mode when two switches are disconnected, enter binning mode when conducting;In the holding stage after integration in binning mode, the corresponding CTIA is not reset, and the same output signal is finally output.The application realizes the binning readout of multiple rows of pixels without increasing additional circuit devices, and takes into account high resolution and low NETD performance.

Description

Technical Field

[0001] This invention belongs to the field of infrared detector readout circuit technology, specifically relating to a low-noise infrared readout circuit structure with interleaving binning. Background Technology

[0002] NETD (Noise Equivalent Temperature Difference), as a core evaluation indicator of infrared detector imaging quality, is essentially the ratio of detector temporal noise to responsivity, i.e., the noise-to-signal ratio. The lower the NETD value, the higher the imaging quality. Temporal noise is mainly composed of front-end pixel noise and readout circuit noise, while responsivity is determined by pixel resistance, bias voltage, and integration time.

[0003] Currently, the main technical means to reduce NETD include extending the integration time, increasing the pixel bias voltage, and reducing the pixel resistance. However, all of these approaches face significant technical limitations: the integration time is limited by the array size and frame rate requirements and cannot be increased indefinitely; while increasing the pixel bias voltage and reducing the pixel resistance can improve the response, they also bring side effects such as increased circuit power consumption, deterioration of spatial uniformity, and reduction of the detector's observation range. Therefore, the three existing mainstream optimization schemes are gradually approaching their performance limits.

[0004] Furthermore, patent CN114660671A discloses a pixel signal output method and a readout circuit for an infrared focal plane detector, while patent CN111988539A discloses an infrared detector merging structure and its merging method. Both aim to reduce NETD by enhancing the responsivity. To achieve the superposition of pixel signals from different rows, additional readout circuitry is required. This leads to a sharp increase in the number of circuitry components as the binning array size increases, severely encroaching on chip area and significantly increasing power consumption.

[0005] Pixel thermal noise and 1 / f noise are the main problems with detector noise, but with the improvement of thin film quality, the noise of the readout circuit has also become significant. Therefore, if it is possible to suppress pixel and readout circuit noise while maintaining the responsivity, it will be an effective way to overcome the performance bottleneck of NETD. Summary of the Invention

[0006] To address the technical problems existing in the prior art, this invention provides a low-noise infrared readout circuit structure with interleaved binning. It eliminates the reset mechanism between specific rows, allowing the cells in the next row to directly continue integrating based on the integration result of those cells, thereby physically achieving row-by-row charge accumulation and summation, i.e., completing the binning operation in the row direction. This invention effectively achieves binning readout of multiple rows of cells without adding any extra circuit components, fundamentally avoiding the area and power consumption bottlenecks caused by the surge in the number of components in traditional solutions.

[0007] The technical solution adopted in this invention is as follows:

[0008] A low-noise infrared readout circuit structure with interleaving binning includes multiple readout channels. Each readout channel includes a channel (detection bridge), a CTIA (capacitive feedback transimpedance amplifier), a sample-and-hold circuit, and an ADC (analog-to-digital converter) connected in sequence. Each readout channel corresponds to a column of pixels, and the channel is connected to different rows of pixels in the same column.

[0009] The low-noise infrared readout circuit structure with interleaved binning adopts an alternating readout mode of binning mode and non-binning mode.

[0010] The input terminals of CTIA in adjacent readout channels are connected via CTRL. A The switches are connected in parallel, and the output is connected via CTRL. B Switches in parallel; when CTRL A Switch and CTRL B When the switch is off, the corresponding cells connected to the adjacent readout channel enter non-binning mode; when CTRL... A Switch and CTRL B When the switch is turned on, the corresponding cells connected to the adjacent readout channels enter binning mode;

[0011] A binning unit is defined as an array consisting of several rows and columns of pixels. When a binning unit enters binning mode, it first integrates the pixels in different columns of the first row. During the hold phase after integration, the CTIA of the corresponding readout channel is not reset. Then, it switches to integrating the pixels in different columns of the second row until the integration of all pixels in the binning unit is completed. The ADC of the corresponding readout channel outputs the same output signal.

[0012] Furthermore, for detectors with several binning units, pixels in the same column share a single readout channel, and the CTIA of the corresponding readout channel is reset between binning units in adjacent rows.

[0013] Furthermore, when the binning unit enters the binning mode, the input terminals of the CTIA of several columns of pixels corresponding to the readout channels are connected in parallel in sequence, and the output terminals are connected in parallel in sequence. In the binning mode, the several rows of pixels are integrated in sequence, and the CTIA of each readout channel is not reset during the hold phase after the integration of each row.

[0014] Furthermore, the signal output terminal of the channel is connected to the Ctrl1B switch and the Ctrl1 switch respectively, and their control signals are inverted signals; the Ctrl1B switch is then connected to the CTRL switch. A Switch Ctrl1 is then connected to the reference voltage VREF.

[0015] Furthermore, each readout channel is connected to a blind cell. The channel includes a first transistor and a second transistor. The first transistor is connected to the corresponding pixel, and the second transistor is connected to the blind cell. During detection, the second transistor and the first transistor generate bias currents respectively. The difference between the two currents is the integral current, which is output through the signal output terminal of the channel.

[0016] Furthermore, the CTIA includes an operational amplifier, an RST (reset) switch, and an integrating capacitor C. int Binning capacitor C bin and Ctrl binning Switch; where capacitor C bin With Ctrl binning The series circuit of the switch with RST switch and integrating capacitor C int These components are connected in parallel, sharing a common connection between the inverting input and output of the operational amplifier; the non-inverting input of the operational amplifier is connected to the reference voltage VREF, and the inverting input is connected to CTRL. A The switch's output is connected to CTRL. B switch.

[0017] Furthermore, in binning mode, the Ctrl key controlling the corresponding readout channel... binning The switch is turned on to connect capacitor C. bin .

[0018] Furthermore, for each binning unit, during the integration process in binning mode, the Ctrl1 switch of the corresponding readout channel is turned off and the Ctrl1B switch is turned on, so that the integration current output by the channel flows equally into multiple CTIAs connected in parallel, and the output terminals of the corresponding multiple operational amplifiers output voltage values. During the hold phase after integration, the Ctrl1B switch of the corresponding readout channel is turned off and the Ctrl1 switch is turned on, so that the integration current output by the channel does not flow into the CTIA. In binning mode, the RST switch of each readout channel is always kept off, and the voltage value output by the next line of integration is superimposed on the voltage value of the previous line of integration. After the voltage values ​​of all lines of integration are superimposed, the output signal of the binning unit that has entered binning mode is output.

[0019] Furthermore, between the binning units of adjacent rows, the RST switch of the corresponding readout channel is briefly turned on to reset the output signal to the reference voltage VREF.

[0020] Furthermore, in non-binning mode, the Ctrl key controlling the corresponding readout channel... binning The switch remains off, the Ctrl1 switch remains off, the Ctrl1B switch remains on, the RST switch is off during integration and on during the hold phase after integration.

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0022] 1. This invention proposes a low-noise infrared readout circuit structure with interleaved binning. By connecting the input and output terminals of CTIA in adjacent readout channels in parallel, binning in the column direction is achieved. The holding phase after integration is completed is not reset, and the next row integration is performed on the integration result of the previous row, thereby achieving binning in the row direction and realizing multi-row and multi-column pixel binning readout.

[0023] 2. Importantly, compared to the non-binning mode, the output noise of this invention is significantly reduced in the binning mode, approaching half of the output noise in the non-binning mode, thereby significantly reducing NETD and improving image quality;

[0024] 3. This invention outputs low-noise and low-resolution image pairs and high-noise and high-resolution image pairs by alternating between binning and non-binning modes, thus achieving a readout method that balances high resolution and low NETD.

[0025] 4. Compared to the traditional method of reducing NETD by enhancing the response rate, this invention does not require additional readout circuit components. Different rows of pixels in the same column share the same readout channel. No matter how the binning array size (such as 2×2, 4×4 or even larger) expands, the number of core components of the readout circuit (CTIA, sample-and-hold circuit, ADC) remains unchanged. It does not need to increase linearly with the increase of the number of merged rows, completely avoiding the sharp expansion of chip area, improving the compactness and uniformity of circuit layout, and ensuring that the overall power consumption of the readout circuit does not increase significantly with the increase of binning size. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the low-noise infrared readout circuit structure with interleaved binning proposed in Example 1;

[0027] Figure 2 This is a timing diagram illustrating the alternating readout in binning mode and non-binning mode in Example 1;

[0028] Figure 3 This is a schematic diagram showing the connection between the low-noise infrared readout circuit structure with interleaved binning and the binning unit array in Example 2. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0030] Example 1.

[0031] This embodiment proposes a low-noise infrared readout circuit structure with interleaving binning for a 2×2 pixel array detector, operating in a rolling shutter readout mode. The specific structure is as follows: Figure 1 As shown, it includes two readout channels. The first readout channel includes channel1, CTIA1, sample-and-hold circuit 1 and ADC1 connected in sequence. The second readout channel includes channel2, CTIA2, sample-and-hold circuit 2 and ADC2 connected in sequence.

[0032] In a 2×2 pixel array detector, pixels 1 and 2 are two pixels in the first column, pixels 3 and 4 are two pixels in the second column, pixels 1 and 3 are two pixels in the first row, and pixels 2 and 4 are two pixels in the second row. This forms a 2×2 pixel array, which is considered a binning unit.

[0033] Row selection switches control channel 1 to connect to different rows of pixels in the first column, and channel 2 to connect to different rows of pixels in the second column. A single row selection signal controls the activation of the row selection switches corresponding to different columns of pixels in the same row, enabling simultaneous reading of pixels from different columns in the same row by two readout channels. The row selection signals Ctrl_row1 for the first row and Ctrl_row2 for the second row are generated using shift registers.

[0034] In addition, there are two blind cells that are always connected to the corresponding readout channels. The blind cells are alum oxide resistors that have been shielded from light and are thermally short-circuited to the substrate. Their positions are usually close to the first row of pixels.

[0035] The low-noise infrared readout circuit structure adopts an alternating readout mode of binning and non-binning modes.

[0036] The input terminals of CTIA1 and CTIA2 are connected via CTRL. A The switches are connected in parallel, and the outputs of CTIA1 and CTIA2 are connected via CTRL. B The switches are connected in parallel. When CTRL... A Switch and CTRL B When both switches are open, the corresponding pixels connected to the two readout channels enter non-binning mode; when CTRL... A Switch and CTRL B When both switches are turned on, the corresponding pixels connected to the two readout channels enter binning mode.

[0037] Channel 1 includes a first transistor M1 and a second transistor M2. The source of the first transistor M1 is connected to the signal output terminal of the channel, its drain is connected to one end of the corresponding dead pixel, the other end of the dead pixel is connected to a first bias voltage VSK, and its gate is connected to a second bias voltage VEB. The source of the second transistor M2 is connected to the corresponding pixel, its drain is connected to the signal output terminal of the channel, and its gate is connected to a third bias voltage VFID. The signal output terminal of the channel is connected to both the Ctrl1B switch and the Ctrl1 switch, with their control signals being inverted. The Ctrl1B switch is then connected to the CTRL switch. A Switch Ctrl1 is then connected to the reference voltage VREF.

[0038] The CTIA1 includes an operational amplifier (OP), an RST switch, and an integrating capacitor C. int Binning capacitor C bin and Ctrl binning Switch; where capacitor C bin With Ctrl binningThe series circuit of the switch with RST switch and integrating capacitor C int These components are connected in parallel, sharing a common connection between the inverting input and output of the operational amplifier; the non-inverting input of the operational amplifier is connected to the reference voltage VREF, and the inverting input is connected to CTRL. A Switch, output terminal V O Connect to CTRL B switch.

[0039] The structure of channel2 is exactly the same as that of channel1, and the structure of CTIA1 is exactly the same as that of CTIA2.

[0040] During readout, the blind cell and the pixel are biased by the first transistor M1 and the second transistor M2, respectively, generating corresponding bias currents I1 and I2. When the target temperature is the same as the ambient temperature, I1 = I2, and the integral current I output by channel1 is... signal =I1-I2=0; During infrared detection, since the blind element does not sense infrared radiation, while the pixel's resistance is affected by infrared radiation, when the target temperature changes, the infrared radiation power incident on the pixel changes, thus causing the pixel's resistance to change. At this time, I1≠I2, and the integral current I output from channel1 is... signal ≠0.

[0041] Because the readout process alternates between binning and non-binning modes, one frame is read out in non-binning mode first, followed by one frame read out in binning mode. The readout timing is as follows: Figure 2 As shown.

[0042] In non-binning mode, different column cells on the same row (e.g.) Figure 1 Pixels 1 and 3 in the same row are read out by readout circuits on different columns within the same row time. Pixels in different rows of the same column (such as...) Figure 1 Pixel 1 and Pixel 2 in the image are read out in time-division multiplexing by the same readout circuit at different line times.

[0043] Specifically, controlling CTRL A Switch and CTRL B The switch remains off, and the Ctrl key controls both readout channels. binning The switch remains off, Ctrl1 switch remains off, and Ctrl1B switch remains on. First, the row selection switch controls pixel 1 and pixel 3 to connect to their respective readout channels, and the RST switches of both readout channels are opened. After pixel 1 is quantized, the integrated current I output via channel 1... signal The input flows into CTIA1 for integration, and the output voltage V at the output terminal of the operational amplifier in CTIA1 is... O1The integral current I output from channel 2 after pixel 3 is quantized signal The input flows into CTIA2 for integration, and the output voltage V at the output terminal of the operational amplifier in CTIA2 is... O3 During the hold phase after integration, the RST switches of both readout channels are turned on, controlling the integration capacitor C. int A reset is performed; then, the row selection switch controls pixel 2 and pixel 4 to be connected to their respective readout channels, and the RST switches of the two readout channels are opened. After pixel 2 is quantized, the integrated current I output through channel 1 is... signal The input flows into CTIA1 for integration, and the output voltage V at the output terminal of the operational amplifier in CTIA1 is... O2 The integral current I output from channel 2 after pixel 4 is quantized signal The input flows into CTIA2 for integration, and the output voltage V at the output terminal of the operational amplifier in CTIA2 is... O4 Therefore, four independent output voltage values ​​V are obtained. O1 ~V O4 After being quantized by the ADC in the corresponding readout circuit, the final digital output is obtained and transmitted to the outside of the chip.

[0044] Taking pixel 1 as an example, since the signal current of pixel 1 only flows into CTIA1, therefore V O1 The output expression is as follows:

[0045]

[0046] In the formula, Reference voltage; This is the integral current corresponding to pixel 1; The integration time; It is an integrating capacitor.

[0047] Output noise corresponding to pixel 1 Represented as:

[0048]

[0049] In the formula, For the integral current The noise mainly includes thermal noise, fn noise and thermal conduction noise of pixel 1, as well as noise of channel 1; This refers to the output noise of the operational amplifier in CTIA1. The noise equivalent bandwidth of CTIA is mainly determined by the integration time. Decide.

[0050] In binning mode, control CTRL. A Switch and CTRLB The switch remains on, and the RST switch controlling the two read channels remains off at all times. Ctrl binning The switch is turned on to connect capacitor C. bin .

[0051] First, the row selection switches control pixel 1 and pixel 3 to connect to their respective readout channels. The Ctrl1 switch of both readout channels is then turned off, and the Ctrl1B switch is turned on. After pixel 1 is quantized, the integrated current I output via channel 1... signal The current is evenly distributed into CTIA1 and CTIA2 for integration. After pixel 3 is quantized, the integrated current I is output through channel 2. signal The inputs are evenly distributed into CTIA1 and CTIA2 for the first integration, achieving pixel binning in the column direction of the first row. At this point, the outputs of the operational amplifiers in CTIA1 and CTIA2 output the same voltage value. :

[0052]

[0053] In the formula, and These are the integral currents corresponding to pixel 1 and pixel 3, respectively; For binning capacitors.

[0054] During the hold phase after integration, the Ctrl1B switch of both readout channels is deactivated and the Ctrl1 switch is activated, preventing the integration current from flowing into the CTIA. Since the RST switch remains deactivated, the integration capacitor C is not activated during this phase. int A reset is performed, thereby maintaining the voltage value at the output terminals of the operational amplifiers in CTIA1 and CTIA2. .

[0055] Then, by controlling the row selection switch, pixels 2 and 4 are connected to their respective readout channels, and the Ctrl1 switch of the two readout channels is turned off and the Ctrl1B switch is turned on. After pixel 2 is quantized, the integral current I output through channel 1 is... signal The current is evenly distributed into CTIA1 and CTIA2 for integration. After pixel 4 is quantized, the integrated current I is output through channel 2. signal The voltage is evenly distributed into CTIA1 and CTIA2 for a second integration, achieving pixel binning in the column direction of the second row. Since the RST switch remains open during binning mode, the voltage value output from the next row's integration process is superimposed on the voltage value from the previous row's integration process. At this point, the operational amplifiers in CTIA1 and CTIA2 output the same voltage value. :

[0056]

[0057] In the formula, and These are the integral currents corresponding to pixel 2 and pixel 4, respectively; This represents the average value of the integral current corresponding to pixel 1, pixel 2, pixel 3, and pixel 4.

[0058] The voltage values ​​output by CTIA1 and CTIA2 After quantization by the ADC in the corresponding readout circuit, the summation yields the total digital output in binning mode, which is then transmitted to the outside of the chip.

[0059] Furthermore, the output noise in binning mode Represented as:

[0060]

[0061] In the formula, , and These are the integral currents. Integral current and integral current noise; This refers to reset noise introduced by the Ctrl1B and Ctrl1 switches.

[0062] Due to reset noise Significantly lower than the noise of the analog front-end circuit (referring to the noise including pixels, channels, CTIA, and sample-and-hold circuitry), ignoring reset noise. Output noise of the integrating operational amplifier Under the influence of binning mode, the output noise This can be approximated as the output noise in non-binning mode. .

[0063] Regarding response rate, V in non-binning mode O1 For integral current The response rate In binning mode For integral current The response rate Therefore, the response rate in binning mode can be approximated as the response rate in non-binning mode. .

[0064] Therefore, NETD in binning mode can be approximated as 1 / 2 of NETD in non-binning mode.

[0065] At an ambient temperature of 25℃ and a target temperature, the integrating capacitor C is set. int =binning capacitor C bin =8pF, integration time The output noise was simulated in both non-binning and binning modes for a duration of 32 μs. For a 2×2 pixel array, the simulated output noise for the non-binning mode was 625.5 μV, while that for the binning mode was only 389.5 μV. This demonstrates that the binning mode proposed in this embodiment significantly reduces output noise, thereby reducing NETD and contributing to improved image quality.

[0066] Since the output image resolution of a 2×2 pixel array will decrease in binning mode, this embodiment adopts an alternating readout mode of binning mode and non-binning mode to compensate for this defect. This compensates for the resolution loss in binning mode and reduces the high output noise in non-binning mode, thus achieving a readout mode that balances high resolution and low NETD.

[0067] Example 2.

[0068] Using the 2×2 pixel array described in Example 1 as a binning unit, this example proposes a low-noise infrared readout circuit structure with interleaved binning for a 2×2 binning unit array detector (i.e., a 4×4 pixel array detector), operating in a rolling shutter readout mode. The specific structure is as follows: Figure 3 As shown, it includes four readout channels. The first readout channel includes channel1, CTIA1, sample-and-hold circuit 1, and ADC1 connected in sequence. The second readout channel includes channel2, CTIA2, sample-and-hold circuit 2, and ADC2 connected in sequence. The third readout channel includes channel3, CTIA3, sample-and-hold circuit 3, and ADC3 connected in sequence. The fourth readout channel includes channel4, CTIA4, sample-and-hold circuit 4, and ADC4 connected in sequence.

[0069] Each readout channel corresponds to a column of pixels. Channels 1 to 4 are connected to different rows of pixels in the corresponding column and are selected by row selection switches.

[0070] In addition, there are two blind cells that are always connected to the corresponding readout channels. The blind cells are alum oxide resistors that have been shielded from light and are thermally short-circuited to the substrate. Their positions are usually close to the first row of pixels.

[0071] The low-noise infrared readout circuit structure adopts an alternating readout mode of binning and non-binning modes.

[0072] The input terminals of CTIA1 and CTIA2 are connected via CTRL. A The switches are connected in parallel, and the input terminals of CTIA3 and CTIA4 are connected via CTRL. A The switches are connected in parallel, and the outputs of CTIA1 and CTIA2 are connected via CTRL. B The switches are connected in parallel, and the outputs of CTIA3 and CTIA4 are connected via CTRL. B The switches are connected in parallel.

[0073] In each binning unit, when the CTRL of the corresponding two read channels... A Switch and CTRL B When the switches are simultaneously open, the corresponding pixels connected to the two readout channels enter non-binning mode; when the CTRL keys of the corresponding two readout channels are pressed... A Switch and CTRL B When both switches are turned on, the corresponding pixels connected to the two readout channels enter binning mode.

[0074] The circuit structures of channels 1 to 4 in this embodiment are the same as those of channel 1 in embodiment 1, and the circuit structures of CTIA1 to CTIA4 in this embodiment are the same as those of CTIA1 in embodiment 1. Furthermore, the readout timing of alternating between binning mode and non-binning mode in each binning unit is also the same as in embodiment 1.

[0075] In non-binning mode, different column cells on the same row (e.g.) Figure 3 Pixels 1, 3, 5, and 7 in the same row are read out by readout circuits on different columns within the same row time. Pixels in different rows of the same column (e.g., ...) Figure 1 Pixels 1, 2, 9, and 13 in the image are read out in a time-division multiplexing manner by the same readout circuit at different line times. The control method of each component in each readout circuit is the same as in Example 1, thereby obtaining 16 independent output voltage values ​​V. O1 ~V O16 After being quantized by the ADC in the corresponding readout circuit, the final digital output is obtained and transmitted to the outside of the chip.

[0076] In binning mode, control the CTRL key between the first read channel and the second read channel. A Switch and CTRL BThe switch remains on, and the CTRL key between the third and fourth read channels... A Switch and CTRL B The switch remains on, and the Ctrl key controls each readout channel. binning The switch is turned on to connect capacitor C. bin .

[0077] First, control the two binning units in the first row to enter binning mode. Each binning unit works according to the control method of each component in each readout circuit of Example 1, and keeps the RST switch of each readout channel always open.

[0078] After completing the binning mode operation of the first row binning unit, the RST switch of each readout channel is briefly turned on to reset the output signal to the reference voltage VREF.

[0079] Then, the two binning units in the second row are controlled to enter binning mode respectively. Each binning unit works according to the control method of each component in each readout circuit of Embodiment 1, and keeps the RST switch of each readout channel always open.

[0080] Finally, the four binning units output their respective total voltage values, each total voltage value consisting of two identical voltage values. The sum is obtained.

[0081] The low-noise infrared readout circuit structure with interleaved binning described in this embodiment can be extended to binning unit array detectors of any size. Since different rows of pixels in the same column share the same readout channel, the number of core components (CTIA, sample-and-hold circuit, ADC) of the readout circuit remains unchanged regardless of how the size of the binning unit array detector (such as 2×2, 4×4 or even larger) increases. It does not need to increase linearly with the increase of the number of merged rows, thus completely avoiding the sharp expansion of chip area, improving the compactness and uniformity of circuit layout, and ensuring that the overall power consumption of the readout circuit does not increase significantly with the increase of binning size.

[0082] It should be noted that this is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A low-noise infrared readout circuit structure with interleaving binning, comprising multiple readout channels, each readout channel comprising a channel, a CTIA, a sample-and-hold circuit and an ADC connected in sequence; each readout channel corresponds to a column of pixels, and the channel is connected to different rows of pixels in the same column; Its features are, The low-noise infrared readout circuit structure with interleaved binning adopts an alternating readout mode of binning mode and non-binning mode. The input terminals of CTIA in adjacent readout channels are connected via CTRL. A The switches are connected in parallel, and the output is connected via CTRL. B Switches in parallel; when CTRL A Switch and CTRL B When the switch is off, the corresponding cells connected to the adjacent readout channel enter non-binning mode; when CTRL... A Switch and CTRL B When the switch is turned on, the corresponding cells connected to the adjacent readout channels enter binning mode; A binning unit is defined as an array consisting of several rows and columns of pixels. When a binning unit enters binning mode, it first integrates the pixels in different columns of the first row. During the hold phase after integration, the CTIA of the corresponding readout channel is not reset. Then, it switches to integrating the pixels in different columns of the second row until the integration of all pixels in the binning unit is completed. The ADC of the corresponding readout channel outputs the same output signal.

2. The low-noise infrared readout circuit structure with interleaved binning according to claim 1, characterized in that, For detectors with several binning units, pixels in the same column share a single readout channel. Between binning units in adjacent rows, the CTIA of the corresponding readout channel is reset.

3. The low-noise infrared readout circuit structure with interleaved binning according to claim 2, characterized in that, The signal output terminals of the channel are connected to the Ctrl1B switch and the Ctrl1 switch respectively, and their control signals are inverted signals; the Ctrl1B switch is then connected to the Ctrl1 switch. A Switch Ctrl1 is then connected to the reference voltage VREF.

4. The low-noise infrared readout circuit structure with interleaving binning according to claim 3, characterized in that, Each readout channel is connected to a blind cell. The channel includes a first transistor and a second transistor. The first transistor is connected to the corresponding pixel, and the second transistor is connected to the blind cell. During detection, the second transistor and the first transistor generate bias currents respectively. The difference between the two currents is the integral current, which is output through the signal output terminal of the channel.

5. The low-noise infrared readout circuit structure with interleaving binning according to claim 4, characterized in that, The CTIA includes an operational amplifier, an RST switch, and an integrating capacitor C. int Binning capacitor C bin and Ctrl binning switch; Wherein, capacitor C bin With Ctrl binning The series circuit of the switch with RST switch and integrating capacitor C int These components are connected in parallel, sharing a common connection between the inverting input and output of the operational amplifier; the non-inverting input of the operational amplifier is connected to the reference voltage VREF, and the inverting input is connected to CTRL. A The switch's output is connected to CTRL. B switch.

6. The low-noise infrared readout circuit structure with interleaving binning according to claim 5, characterized in that, In binning mode, control the Ctrl key of the corresponding read channel. binning The switch is turned on to connect capacitor C. bin .

7. The low-noise infrared readout circuit structure with interleaved binning according to claim 6, characterized in that, For each binning unit, during the integration process in binning mode, the Ctrl1 switch of the corresponding readout channel is turned off and the Ctrl1B switch is turned on. The integrated current output by the channel flows equally into multiple CTIAs connected in parallel, and the output voltage value of the corresponding multiple operational amplifiers is output. During the hold phase after integration, the Ctrl1B switch of the corresponding readout channel is turned off and the Ctrl1 switch is turned on, so that the integration current output by the channel does not flow into the CTIA. In binning mode, the RST switches of each readout channel are always kept off. The voltage value output by the next line of integration is superimposed on the voltage value of the previous line of integration. After the voltage values ​​of all lines of integration are superimposed, the output signal of the binning unit that has entered binning mode is output.

8. The low-noise infrared readout circuit structure with interleaved binning according to claim 7, characterized in that, Between the binning cells of adjacent rows, the RST switch of the corresponding readout channel is briefly turned on to reset the output signal to the reference voltage VREF.

9. The low-noise infrared readout circuit structure with interleaving binning according to any one of claims 5 to 8, characterized in that, In non-binning mode, control the Ctrl key of the corresponding readout channel. binning The switch remains off, the Ctrl1 switch remains off, the Ctrl1B switch remains on, the RST switch is off during integration and on during the hold phase after integration.

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