Reference source circuit, electronic device, and control method

Abstract

Embodiments of the present disclosure provide a reference source circuit, comprising an output circuit, a monitoring circuit and a conditioning circuit. The output circuit comprises an output resistor, and the output circuit is configured to generate an output current and output a current reference in a current reference mode or make the output current flow through the output resistor to form a voltage reference in a voltage reference mode; the monitoring circuit is configured to generate a monitoring voltage based on the output current; and the conditioning circuit is configured to generate a feedback control signal according to the monitoring voltage and a compensation relationship corresponding to a current output mode, and feed back the feedback control signal to the output circuit to adjust the output current. The reference source circuit can realize reconfigurable output of the current reference and the voltage reference in the same circuit structure, and improve the accuracy of the reference source circuit, reduce the process dependency and support digital adjustment of the output value.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of circuits, specifically to a reference source circuit, electronic device, and control method. Background Technology

[0002] Reference source circuits are widely used in analog-to-digital converters, digital-to-analog converters, sensor interfaces, power management chips, and various analog / mixed-signal systems to provide stable voltage or current references. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a reference source circuit, including an output circuit, a monitoring circuit, and a conditioning circuit; wherein the output circuit is coupled to the monitoring circuit, and the conditioning circuit is connected between the monitoring circuit and the output circuit; the output circuit includes an output resistor; the output circuit is configured to generate an output current and output a current reference in a current reference mode, or allow the output current to flow through the output resistor to form a voltage reference in a voltage reference mode; the monitoring circuit is configured to generate a monitoring voltage based on the output current; the conditioning circuit is configured to generate a feedback control signal according to the monitoring voltage and a compensation relationship corresponding to the current output mode, and feed the feedback control signal back to the output circuit to adjust the output current; wherein the compensation relationship includes a first compensation relationship corresponding to the current reference mode and a second compensation relationship corresponding to the voltage reference mode; in the current reference mode, the conditioning circuit is configured to adjust the output current according to the first compensation relationship; in the voltage reference mode, the conditioning circuit is configured to adjust the output current according to the second compensation relationship.

[0004] For example, in at least one embodiment of this disclosure, the monitoring voltage includes a first monitoring voltage, a second monitoring voltage, and a sensing resistor voltage corresponding to the output current; the conditioning circuit includes a first conditioning sub-circuit, a second conditioning sub-circuit, and a third conditioning sub-circuit; the first conditioning sub-circuit is coupled to the monitoring circuit and configured to quantize the first monitoring voltage, the second monitoring voltage, and the sensing resistor voltage to obtain a first digital monitoring quantity and a second digital monitoring quantity characterizing the temperature and output current state; the second conditioning sub-circuit is coupled to the first conditioning sub-circuit and the third conditioning sub-circuit respectively and configured to compensate at least one of the first digital monitoring quantity and the second digital monitoring quantity to generate an error signal; and the third conditioning sub-circuit is connected between the second conditioning sub-circuit and the output circuit and configured to generate the feedback control signal based on the error signal to adjust the output current through the feedback control signal.

[0005] For example, in at least one embodiment of this disclosure, the first conditioning sub-circuit includes an analog-to-digital conversion module, which is coupled to the monitoring circuit and the second conditioning sub-circuit respectively, and is configured to generate a first digital monitoring quantity and a second digital monitoring quantity based on the first monitoring voltage, the second monitoring voltage and the sensing resistor voltage, wherein the first digital monitoring quantity represents the ratio between the first monitoring voltage and the sensing resistor voltage, and the second digital monitoring quantity represents the ratio between the second monitoring voltage and the sensing resistor voltage.

[0006] For example, in at least one embodiment of this disclosure, the analog-to-digital conversion module includes a current-to-analog-to-digital converter (DAC), which includes a continuous-time integrator and a quantizer. The continuous-time integrator includes an operational amplifier and an integrating capacitor. The continuous-time integrator is coupled to the monitoring circuit and the quantizer, respectively, and is configured to generate a detection current based on the relationship between the first monitoring voltage or the second monitoring voltage and the sensing resistor voltage. The quantizer is coupled to the continuous-time integrator and is configured to generate a bit current signal based on the output of the continuous-time integrator. The bit current signal is used to control a feedback current corresponding to the output current. The continuous-time integrator is further configured to integrate the difference between the detection current and the feedback current, causing the current-to-analog-to-digital converter to generate the first digital monitoring quantity or the second digital monitoring quantity.

[0007] For example, in at least one embodiment of this disclosure, the conditioning circuit further includes a reset switch coupled to the integrating capacitor and configured to release residual charge on the integrating capacitor during switching between monitoring the first monitoring voltage and monitoring the second monitoring voltage.

[0008] For example, in at least one embodiment of this disclosure, the second conditioning sub-circuit includes a digital polynomial processing unit and an error generation unit; the digital polynomial processing unit is coupled to the first conditioning sub-circuit and configured to perform a compensation operation on at least one of the first digital monitoring quantity and the second digital monitoring quantity according to the polynomial coefficients corresponding to the current output mode to obtain a compensated monitoring quantity; and the error generation unit is coupled to the digital polynomial processing unit and the first conditioning sub-circuit respectively and configured to generate the error signal according to the difference between the compensated monitoring quantity and at least one of the first digital monitoring quantity and the second digital monitoring quantity.

[0009] For example, in at least one embodiment of this disclosure, the digital polynomial processing unit includes a batch calibration unit and a single-chip calibration unit arranged in parallel; the batch calibration unit is configured to perform batch calibration operations on at least one of the first digital monitoring quantity and the second digital monitoring quantity according to the batch calibration polynomial coefficients to generate a batch calibration quantity; and the single-chip calibration unit is configured to perform single-chip calibration operations on at least one of the first digital monitoring quantity and the second digital monitoring quantity according to the single-chip calibration polynomial coefficients to generate a single-chip calibration quantity; the digital polynomial processing unit is configured to generate the compensated monitoring quantity according to the batch calibration quantity and the single-chip calibration quantity.

[0010] For example, in at least one embodiment of this disclosure, the digital polynomial processing unit stores multiple sets of polynomial coefficients corresponding to different output modes; wherein, at least one set of polynomial coefficients is used to characterize the first compensation relationship to determine the target temperature characteristics of the output current in the current reference mode; and at least another set of polynomial coefficients is used to characterize the second compensation relationship to determine the target temperature characteristics of the output current in the voltage reference mode, so that the temperature change of the output current compensates for the temperature change of the output resistance.

[0011] For example, in at least one embodiment of this disclosure, the digital polynomial processing unit is configured to determine the polynomial coefficients based on digital configuration information, the digital configuration information including coefficient group selection information and / or coefficient adjustment information, so that the reference source circuit outputs different current reference values ​​or different voltage reference values.

[0012] For example, in at least one embodiment of this disclosure, the coefficient group selection information is configured to select a set of polynomial coefficients from multiple sets of preset polynomial coefficients, with different sets of polynomial coefficients corresponding to different current reference values ​​or different voltage reference values; the coefficient adjustment information is configured to adjust the polynomial coefficients or adjust the digital monitoring quantity input to the digital polynomial processing unit to continuously adjust the current reference value or the voltage reference value.

[0013] For example, in at least one embodiment of this disclosure, the third conditioning sub-circuit includes a digital integrator and a digital-to-analog converter module; the digital integrator is connected between the second conditioning sub-circuit and the digital-to-analog converter module and is configured to accumulate the error signal to generate a digital feedback quantity; and the digital-to-analog converter module is connected between the digital integrator and the output circuit and is configured to convert the digital feedback quantity into a feedback control signal and apply the feedback control signal to the output circuit to adjust the output current.

[0014] For example, in at least one embodiment of this disclosure, the digital-to-analog conversion module includes a modulator and a current-to-digital-to-analog conversion circuit; the modulator is configured to convert the digital feedback quantity into a single-bit stream; the current-to-digital-to-analog conversion circuit includes a bias generation circuit and a filter circuit coupled in sequence; wherein the bias generation circuit is configured to generate a bias signal based on the single-bit stream; the filter circuit is configured to filter the bias signal and generate the feedback control signal based on the filtered bias signal.

[0015] For example, in at least one embodiment of this disclosure, the monitoring circuit includes a current replication branch, a sensing resistor, and a transistor detection branch; the current replication branch is coupled to the sensing resistor and the transistor detection branch respectively, and is configured to provide a replication current to the sensing resistor and the transistor detection branch based on the output current; the sensing resistor is configured to perform current conversion on the first monitoring voltage or the second monitoring voltage to form a detection current; and the transistor detection branch is configured to generate the first monitoring voltage and the second monitoring voltage under different current density conditions.

[0016] For example, in at least one embodiment of this disclosure, the transistor detection branch includes a single bipolar transistor configured to receive a first bias current and a second bias current in a time-division multiplexing manner to generate a first monitoring voltage and a second monitoring voltage, respectively, wherein the first bias current and the second bias current have a preset ratio; wherein the first monitoring voltage is the voltage between the base and emitter of the bipolar transistor under the first bias current condition, and the second monitoring voltage is the voltage between the base and emitter of the bipolar transistor under the second bias current condition; the conditioning circuit is configured to switch between a first monitoring mode and a second monitoring mode in a time-multiplexed manner, wherein the first monitoring mode corresponds to the monitoring of the first monitoring voltage, and the second monitoring mode corresponds to the monitoring of the second monitoring voltage.

[0017] For example, in at least one embodiment of this disclosure, the monitoring circuit further includes a feedback switch and a virtual transistor branch, the virtual transistor branch being coupled to the switching node where the feedback switch is located and configured to receive unmonitored current during current switching or when the feedback switch is open, in order to stabilize the potential of the switching node.

[0018] For example, in at least one embodiment of this disclosure, the current replication branch includes a current source array, a plurality of current-directing switches, and a matching control unit; the current source array includes a plurality of unit current sources; the plurality of current-directing switches are coupled to the plurality of unit current sources, the transistor detection branch, the sensing resistor, and the output circuit; and the matching control unit is coupled to the plurality of current-directing switches and configured to control the conduction state of the current-directing switches according to a preset rotation sequence, such that the plurality of unit current sources are connected to at least two of the transistor detection branch, the sensing resistor, and the output circuit in different time slots.

[0019] For example, in at least one embodiment of this disclosure, the output circuit further includes a current source, a mode selection switch, a first output terminal, and a second output terminal, wherein the output resistor is coupled to the second output terminal; the current source is configured to generate the output current according to the feedback control signal; and the mode selection switch is coupled to the current source, the first output terminal, and the second output terminal respectively, and is configured to select providing the output current to the first output terminal to output the current reference, or select providing the output current to the output resistor to form the voltage reference at the second output terminal.

[0020] For example, in at least one embodiment of this disclosure, the current source includes a PMOS transistor, a first terminal of the PMOS transistor is coupled to a power supply, a second terminal of the PMOS transistor is coupled to the mode selection switch, and a feedback control signal is applied to the third terminal of the PMOS transistor to change the output current by adjusting the voltage of the third terminal of the PMOS transistor.

[0021] At least one embodiment of this disclosure also provides an electronic device including a reference source circuit as described in any of the above embodiments.

[0022] At least one embodiment of this disclosure also provides a control method for a reference source circuit as described in any of the above embodiments, wherein the method includes: generating an output current using the output circuit, and controlling the output circuit to output a current reference in a current reference mode or to allow the output current to flow through the output resistor to form a voltage reference in a voltage reference mode, according to a current output mode; generating a monitoring voltage using the monitoring circuit based on the output current; and generating a feedback control signal using the conditioning circuit based on the monitoring voltage and a compensation relationship corresponding to the current output mode, and feeding the feedback control signal back to the output circuit to adjust the output current. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure, and are not intended to limit this disclosure.

[0024] Figure 1 A schematic block diagram of a reference source circuit provided for at least one embodiment of this disclosure; Figure 2 A schematic diagram of a reference source circuit provided for at least one embodiment of this disclosure; Figure 3 A schematic block diagram of an analog-to-digital conversion module provided in at least one embodiment of this disclosure; Figure 4 A schematic diagram illustrating the relationship between the first and second digital monitoring quantities and temperature and output current, provided for at least one embodiment of this disclosure; Figure 5 A schematic diagram illustrating a digital polynomial processing method provided in at least one embodiment of this disclosure; Figure 6 A schematic diagram illustrating another digital polynomial processing method provided in at least one embodiment of this disclosure; Figure 7 A schematic diagram illustrating the variation of output current with temperature in current reference mode and voltage reference mode, provided for at least one embodiment of this disclosure; Figure 8 A schematic diagram of a digital-to-analog conversion module provided in at least one embodiment of this disclosure; Figure 9 A schematic diagram of a monitoring circuit and a first conditioning sub-circuit provided for at least one embodiment of this disclosure; Figure 10 A timing diagram illustrating the switching between a first monitoring mode and a second monitoring mode provided for at least one embodiment of this disclosure; Figure 11 A schematic block diagram illustrating a control method provided in at least one embodiment of this disclosure; Figure 12 A schematic diagram of an electronic device provided for at least one embodiment of this disclosure; and Figure 13 This is a schematic diagram of another electronic device provided for at least one embodiment of the present disclosure. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0026] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0027] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0028] Precision voltage and current reference source circuits are the foundation of high-precision analog and mixed-signal integrated circuits, and are widely used in high-precision analog-to-digital converters (ADCs), sensor readout circuits, measuring instruments, and other fields. In these applications, the system accuracy is often limited by the stability of the reference source under variations in process, voltage, and temperature (PVT).

[0029] Currently, the core of improving the accuracy of reference sources lies in compensating for the temperature coefficient (TC) of the output. For example, temperature compensation techniques mainly include the following categories: First, traditional first-order compensation schemes combine negative temperature coefficient (CTAT) voltage terms, for example (in bipolar transistors). And the positive temperature coefficient (PTAT) voltage term, for example... This allows for first-order TC compensation. However, the residual higher-order TC curvature makes it difficult to exceed the accuracy limit of 10 ppm / °C.

[0030] Second, the on-chip temperature control scheme uses an on-chip heating loop to maintain the chip temperature within a nearly constant range, theoretically achieving an extremely low temperature drift of about 0.1 ppm / °C. However, this comes at the cost of extremely high power consumption at low temperatures (about 1 W), long startup time, and the need for a power supply voltage higher than 6 V (based on a Zener reference source), while also limiting the applicable temperature range.

[0031] Third, purely simulate high-order compensation schemes, such as by introducing additional... Methods include branching, utilizing the complementary second-order TC curvatures of MOS and bipolar junction transistors (BJTs), or introducing higher-order PTAT currents. However, these methods typically only compensate up to the second order, and higher-order residual TC curvatures will still limit the accuracy to ±0.05% or higher.

[0032] Fourth, the segmented compensation scheme uses segmented detectors or segmented linear DACs for compensation, but it has problems such as discontinuity and hysteresis during switching, and its accuracy is still limited by the curvature of higher-order TC.

[0033] Fifth, the digital domain post-processing scheme eliminates the higher-order TC curvature of the bandgap reference source in the digital domain using a temperature sensor. However, the compensated output only exists in the digital domain and lacks direct analog driving capability, making it unsuitable for circuits that require actual analog voltage output, such as low dropout regulators (LDOs).

[0034] In summary, current technology still faces the following prominent problems: First, there is the bottleneck of accuracy. Pure analog compensation schemes can only compensate up to the second order at most. The residual error of higher orders limits the accuracy to ±0.05% or more, making it increasingly difficult to meet the ever-increasing demand for high accuracy.

[0035] Secondly, it has high power consumption and area costs. Although on-chip temperature control schemes can achieve extremely low temperature drift, the power consumption at low temperatures is close to 1 W, and a power supply voltage higher than 6 V is required. This not only makes it incompatible with standard deep submicron CMOS processes, but also limits the temperature operating range.

[0036] Third, they lack direct analog output capability. Most existing digital-aided solutions only achieve high precision in the digital domain and cannot directly provide high-precision analog output, thus limiting their application in practical analog circuits.

[0037] Fourth, there is a lack of flexibility. Current high-precision reference sources are often designed for specific processes. Once ported to other processes, inaccuracies in the device model may lead to significant deviations from expected performance. Furthermore, analog tuning faces trade-offs between tuning range, resolution, and the accuracy of switching leakage across the entire temperature range.

[0038] Fifth, they have limited functionality. Most reference source circuits can only output voltage or current independently, do not support mode reconfiguration, and cannot flexibly adjust the output value.

[0039] This disclosure provides a reference source circuit. The reference source circuit includes an output circuit, a monitoring circuit, and a conditioning circuit. The output circuit is coupled to the monitoring circuit, and the conditioning circuit is connected between the monitoring circuit and the output circuit. The output circuit includes an output resistor and is configured to generate an output current and output a current reference in a current reference mode, or to allow the output current to flow through the output resistor to form a voltage reference in a voltage reference mode. The monitoring circuit is configured to generate a monitoring voltage based on the output current. The conditioning circuit is configured to generate a feedback control signal according to the monitoring voltage and a compensation relationship corresponding to the current output mode, and feed the feedback control signal back to the output circuit to adjust the output current. The compensation relationship includes a first compensation relationship corresponding to the current reference mode and a second compensation relationship corresponding to the voltage reference mode. In the current reference mode, the conditioning circuit is configured to adjust the output current according to the first compensation relationship; in the voltage reference mode, the conditioning circuit is configured to adjust the output current according to the second compensation relationship.

[0040] The reference source circuit provided in at least one embodiment of this disclosure, through an output circuit, a monitoring circuit, and a conditioning circuit forming a closed-loop regulation structure, can achieve reconfigurable outputs of current and voltage references within the same circuit structure, thereby reducing circuit area and design complexity. In at least one embodiment of this disclosure, by performing digital compensation based on the monitored voltage and configuring corresponding compensation relationships according to different output modes, the drift of the output reference caused by temperature changes can be reduced, improving the temperature stability of the reference output. Furthermore, in at least one embodiment of this disclosure, by configuring digital polynomial coefficients and feedback control, the adjustment accuracy and configuration flexibility of the output value can be improved. Further, in at least one embodiment of this disclosure, by using time-division monitoring, dynamic matching, and virtual branch designs, the impact of device mismatch, current source mismatch, and switching transient errors on the reference output can be reduced, thereby improving the output accuracy, stability, and consistency of the reference source circuit.

[0041] Figure 1 A schematic block diagram of a reference source circuit provided for at least one embodiment of this disclosure.

[0042] like Figure 1As shown, the reference source circuit 100 includes an output circuit 110, a monitoring circuit 120, and a conditioning circuit 130. The output circuit 110 is coupled to the monitoring circuit 120, and the conditioning circuit 130 is connected between the monitoring circuit 120 and the output circuit 110.

[0043] For example, the output circuit 110 may include an output resistor, and the output circuit 110 may be configured to generate an output current and output a current reference in current reference mode, or to allow the output current to flow through the output resistor to form a voltage reference in voltage reference mode.

[0044] For example, the monitoring circuit 120 can be configured to generate a monitoring voltage based on the output current.

[0045] For example, the conditioning circuit 130 can be configured to generate a feedback control signal based on the monitored voltage and the compensation relationship corresponding to the current output mode, and feed the feedback control signal back to the output circuit 110 to regulate the output current.

[0046] For example, the compensation relationship may include a first compensation relationship corresponding to the current reference mode and a second compensation relationship corresponding to the voltage reference mode.

[0047] For example, in current reference mode, the conditioning circuit 130 can adjust the output current according to a first compensation relationship. For example, adjusting the output current according to the first compensation relationship can make the output current have the target temperature characteristics required by the current reference, such as making the output current independent of temperature.

[0048] For example, in voltage reference mode, the conditioning circuit 130 can adjust the output current according to a second compensation relationship. For example, adjusting the output current according to the second compensation relationship can compensate for temperature changes in the output resistance by changes in the temperature of the output current, thereby resulting in a lower temperature drift in the voltage reference formed by the output current and the output resistance. For example, the first and second compensation relationships can be compensation relationships determined by digital polynomials in current reference mode and voltage reference mode, respectively.

[0049] The reference source circuit provided in at least one embodiment of this disclosure monitors the output current through a monitoring circuit and performs closed-loop regulation of the output current through a conditioning circuit based on a compensation relationship corresponding to the current output mode. This allows the same circuit to be reconfigured as a current reference or a voltage reference, saving circuit area and improving application flexibility.

[0050] Figure 2 This is a schematic diagram of a reference source circuit provided for at least one embodiment of the present disclosure.

[0051] like Figure 2As shown, the reference source circuit may include an output circuit 110, a monitoring circuit 120, and a conditioning circuit 130.

[0052] like Figure 2 As shown, the output circuit 110 may include an output resistor. The output circuit 110 may also include a current source, a mode selection switch 111, a first output terminal 112, and a second output terminal 113. For example, an output resistor. It can be coupled to the second output terminal 113. For example, a current source can be configured to generate an output current based on a feedback control signal. For example, mode selection switch 111 can be coupled to a current source, a first output terminal 112, and a second output terminal 113, respectively, and configured to select the output current. Provided to the first output terminal 112 as an output current reference Alternatively, you can choose to reduce the output current. Provide to output resistor To form a voltage reference at the second output terminal 113. For example, in current reference mode, the current reference... The current value of t can be equal to the output current. The current value; in voltage reference mode, = · .

[0053] For example, the mode selection switch can toggle based on the current output mode. The current output mode can be determined by digital configuration information, which can be provided by user input, system control logic, or a preset configuration, and is used to indicate whether the reference source circuit operates in current reference mode or voltage reference mode. When the digital configuration information indicates current reference mode, the mode selection switch selects to output current... Provided to the first output terminal as an output current reference When the digital configuration information indicates voltage reference mode, the mode selection switch selects to output current. Provide to output resistor Make the output current Flow through the output resistor To form a voltage reference at the second output terminal. For example, digital configuration information can also be used to determine the compensation relationships or polynomial coefficients in the conditioning circuit, so that the selection of the output path corresponds to the closed-loop compensation target.

[0054] like Figure 2 As shown, the current source may include a PMOS transistor. The first terminal of the PMOS transistor is coupled to the power supply, the second terminal is coupled to the mode selection switch, and a feedback control signal is applied to the third terminal of the PMOS transistor to change the output current by adjusting the voltage at the third terminal. PMOS transistors are P-channel metal-oxide-semiconductor field-effect transistors (PMOS).

[0055] For example, the source of a PMOS transistor is coupled to a power supply, and the drain is coupled to a mode selection switch. A feedback control signal is applied to the gate of the PMOS transistor to adjust the gate-source voltage of the PMOS transistor. Change output current 。 For example, a PMOS transistor can be configured to generate an output current based on a feedback control signal. In some embodiments, the first electrode can be the source, the second electrode can be the drain, and the third electrode can be the gate; in other embodiments, the first electrode can be one of the source and drain, the second electrode can be the other of the source and drain, and the third electrode is the gate. The above connection relationship is only an example, and the embodiments disclosed herein are not limiting.

[0056] For example, the monitoring voltage may include a first monitoring voltage, a second monitoring voltage, and a sensing resistor voltage corresponding to the output current. For instance, the sensing resistor voltage is used to indicate that the resistance value of the sensing resistor is equal to or equal to the output current. The voltage is the product of the current and the voltage across the sensor resistor. Not limited to sensing resistors The physical voltage actually generated or applied at both ends.

[0057] For example, such as Figure 2 As shown, the monitoring circuit 120 may include a current replication branch 121, a transistor detection branch 123, and a sensing resistor 122. For example, the current replication branch 121 may be coupled to the sensing resistor 122 and the transistor detection branch 123, respectively, and configured to be based on the output current. A replica current is provided to the sensing resistor 122 and the transistor detection branch 123. For example, the transistor detection branch 123 can be configured to generate a first monitoring voltage under different current density conditions. Second monitoring voltage For example, when the replication current is supplied to the transistor detection branch, a first bias current or a second bias current under different current density conditions can be formed.

[0058] For example, such as Figure 2As shown, the transistor detection branch 123 may include bipolar transistor Q1 and bipolar transistor Q2. For example, bipolar transistors Q1 and Q2 can generate a first monitoring voltage under different current density conditions. Second monitoring voltage For example, bipolar transistors Q1 and Q2 can have different emitter area ratios (e.g., 1:N) to generate a first monitoring voltage under different current density conditions. Second monitoring voltage In addition, sensing resistance It can be configured to monitor the first voltage. Or the second monitoring voltage This is converted into a corresponding detection current. For example, the voltage across the sensing resistor. It can be used to represent output current. Or equal to the current value Either of the replicating currents and the sensing resistance The product of the resistance values.

[0059] like Figure 2 As shown, the conditioning circuit 130 may include a first conditioning sub-circuit 131, a second conditioning sub-circuit 132, and a third conditioning sub-circuit 133. For example, the first conditioning sub-circuit 131 is coupled to the monitoring circuit 120. Figure 2 (not shown in the image), and can be configured to monitor a first voltage. Second monitoring voltage and sensing resistance voltage Quantization is performed to obtain the first digital monitoring quantity characterizing the temperature and output current status. Second digital monitoring quantity .

[0060] For example, the second conditioning sub-circuit 132 can be coupled to the first conditioning sub-circuit 131 and the third conditioning sub-circuit, respectively, and configured to monitor the first digital quantity. Second digital monitoring quantity At least one of them is compensated to generate an error signal. For example, the second conditioning circuit 132 can regulate the first digital monitoring value. After compensation by the digital polynomial p(·), p(μ1) is obtained, which is compared with the second digital monitoring quantity. Subtraction to generate an error signal .

[0061] For example, the third conditioning sub-circuit 133 can be connected between the second conditioning sub-circuit 132 and the output circuit 110, and is configured to adjust according to the error signal. Generate a feedback control signal to regulate the output current. .

[0062] For example, the error signal μE(T) can be accumulated in the digital integrator of the third conditioning circuit 133, and after upsampling and digital-to-analog conversion, converted into an analog feedback control signal. The feedback control signal can be used to adjust the gate-source voltage of the PMOS transistor. To adjust the output current This forms a closed-loop control. The digital integrator provides a near-infinite loop gain to drive the error signal. The average value tends to zero, causing the system to enter a "current-locked state" determined by the compensation relationship (i.e., the characteristics of the digital polynomial p(·)).

[0063] For example, such as Figure 2 As shown, the first conditioning sub-circuit 131 may include analog-to-digital conversion modules, such as analog-to-digital converter 1 (ADC1) and analog-to-digital converter 2 (ADC2). For example, in some embodiments, ADC1 and ADC2 may be two independent analog-to-digital converters. In other embodiments, ADC1 and ADC2 may also represent two conversion paths or two time-multiplexed conversion modes of the same analog-to-digital converter.

[0064] For example, the analog-to-digital conversion module can be coupled to the monitoring circuit 120 and the second conditioning sub-circuit 132 respectively, and configured to adjust according to the first monitoring voltage. Second monitoring voltage and sensing resistance voltage Generate the first digital monitoring quantity μ1(T) and the second digital monitoring quantity μ2(T).

[0065] For example, the first digital monitoring quantity μ1(T) can characterize the first monitoring voltage. With sensing resistance voltage The ratio between them. Specifically, it can be calculated using the following formula:

[0066] in, As the primary digital monitoring quantity, The voltage across the sensing resistor. For sensing resistance, The voltage across the sensing resistor. The value of the output current. This is the first monitoring voltage.

[0067] For example, the second digital monitoring quantity μ2(T) can characterize the second monitoring voltage. With sensing resistance voltage The ratio between them. Specifically, it can be calculated using the following formula:

[0068] in, This is the second digital monitoring quantity. The voltage across the sensing resistor. For sensing resistance, The voltage across the sensing resistor. The value of the output current. This is the second monitoring voltage.

[0069] Figure 3 This is a schematic block diagram of an analog-to-digital conversion module provided in at least one embodiment of the present disclosure.

[0070] For example, analog-to-digital conversion module 1311 may include a current-to-analog-to-digital converter, which includes a continuous-time integrator 1313 and a quantizer 1312.

[0071] For example, such as Figure 3 As shown, the continuous-time integrator 1313 may include an operational amplifier 1314 and an integrating capacitor 1315. For example, the continuous-time integrator 1313 may be coupled to a monitoring circuit and a quantizer 1312, respectively, and configured to form a detection current based on the relationship between a first or second monitoring voltage and the sensing resistor voltage. For example, the continuous-time integrator may force the sensing resistor to... The voltage across the two ends is clamped to the base-emitter voltage of the transistor detection branch. This causes the current to flow through the sensing resistor. The current (i.e.) / This generates a detection current. For example, The first monitoring voltage Or the second monitoring voltage .

[0072] For example, such as Figure 3 As shown, quantizer 1312 can be coupled to continuous-time integrator 1313 and configured to generate a bitstream signal based on the output of continuous-time integrator 1313. For example, quantizer 1312 can operate at a sampling frequency F. S (e.g. F) SThe output of the continuous-time integrator 1313 (500kHz) is quantized to generate a bit current signal. For example, the bit current signal can be used to control a feedback current corresponding to the output current. For example, the feedback current can be formed by a replica current provided by a current replication branch, controlled by the bit current signal. For example, when the bit current signal is active, the replica current is connected to the feedback branch of the continuous-time integrator; when the bit current signal is inactive, the replica current is not connected to the feedback branch. For example, the current values ​​of the feedback current and the replica current can be equal to the output current. The current value.

[0073] For example, the continuous-time integrator 1313 can also be configured to integrate the difference between the detected current and the feedback current, causing the current analog-to-digital converter to generate a first digital monitored quantity or a second digital monitored quantity. Specifically, taking advantage of the oversampling and noise shaping characteristics of the continuous-time Delta-Sigma modulator (CT-ΔΣM), the detected current (i.e., / It will maintain charge balance with the feedback current controlled by the potential current signal.

[0074] For example, when the loop reaches a steady state, the average value of the bit stream signal over time can be expressed by the following formula:

[0075] Where μ is the equivalent digital output of the analog-to-digital converter module. When the current-to-analog-to-digital converter is working in the first monitoring mode, μ is the first digital monitoring quantity μ1; when the current-to-analog-to-digital converter is working in the second monitoring mode, μ is the second digital monitoring quantity μ2. The base-emitter voltage of the bipolar transistor under the current monitoring mode varies with temperature T. This is the output current value.

[0076] like Figure 3 As shown, when generating the first digital monitoring quantity μ1, the current injected into the transistor detection branch can be N· Where N>1, The current value is the output current; when generating the second digital monitoring value μ2, the current injected into the transistor detection branch can be... .

[0077] The analog-to-digital converter module provided in at least one embodiment of this disclosure has at least the following advantages: (1) Natural current-domain division operation: The above process completes the division operation and signal digitization simultaneously in the current domain, without the need for an additional voltage-to-current conversion stage, thereby reducing circuit overhead and non-ideal effects; (2) Architectural compatibility: Since the goal of the entire closed-loop system is to control the output current, the current-to-analog-to-digital converter can directly complete the sampling and quantization of the signal in the current domain, avoiding the additional VI conversion circuit required by the voltage-to-analog-to-digital converter, and reducing the introduction of non-ideal effects; (3) Naturally embedded ratio quantization: The output of the analog-to-digital converter module is directly... and The ratio of the system loop's required temperature and current information is naturally contained within this ratio, and can be used by the second conditioning circuit without any subsequent additional calculations.

[0078] For example, in at least one embodiment, the conditioning circuit 130 may further include a reset switch, which may be coupled to the integrating capacitor and configured to release residual charge on the integrating capacitor during switching between monitoring of a first monitoring voltage and monitoring of a second monitoring voltage. For example, as described below... Figure 9 and Figure 10 In the first monitoring mode (corresponding to the first monitoring voltage) (monitoring) and second monitoring mode (corresponding to the second monitoring voltage) During the transition between monitoring modes, to prevent the historical state left over from the previous mode from interfering with the next quantization, the circuit quickly clears the residual charge on the integrating capacitors (e.g., the first-stage integrating capacitor CINT1, and the second-stage integrating capacitor in the case of a second-stage integrator including a switched capacitor) in the continuous-time integrator via a dedicated reset switch (e.g., controlled by the reset signal RST). This operation cuts off the signal coupling path between the two monitoring modes, ensuring independence and conversion accuracy between different sampling periods. For example, the reset switch can be controlled by the reset signal RST. The reset signal RST can be generated by the timing control logic in the conditioning circuit according to the switching timing of the first and second monitoring modes. When the current-to-analog converter switches from the first monitoring mode to the second monitoring mode, or from the second monitoring mode to the first monitoring mode, the reset signal RST controls the reset switch to close to release the residual charge on the integrating capacitor; during normal quantization in the first or second monitoring mode, the reset signal RST controls the reset switch to open to allow the continuous-time integrator to perform integration.

[0079] Figure 4 This diagram illustrates the relationship between the first and second digital monitoring quantities and temperature and output current, provided for at least one embodiment of this disclosure.

[0080] like Figure 4As shown, within the temperature range T from -40℃ to 125℃, both the first digital monitoring quantity μ1 and the second digital monitoring quantity μ2 exhibit their respective trends with temperature T. For smaller output currents... (μ1, small) μ2, small and larger output current (μ1, large) μ2, large The positions of the curves for μ1 and μ2 undergo a systematic shift. In other words, the output current... The information is contained in the absolute values ​​of μ1 and μ2, while the ratio (or difference) between μ1 and μ2 primarily contains information about temperature T. Therefore, the second conditioning sub-circuit can be described later... Figure 5 The digital polynomial processes μ1 and μ2 to separate temperature and current information and generate an error signal.

[0081] Figure 5 This is a schematic diagram of a digital polynomial processing method provided in at least one embodiment of the present disclosure.

[0082] For example, such as Figure 5 As shown, the second conditioning sub-circuit may include a digital polynomial processing unit 1321 and an error generation unit 1322.

[0083] For example, the digital polynomial processing unit 1321 is coupled to the first conditioning sub-circuit 131 and configured to perform a compensation operation on at least one of the first digital monitoring quantity μ1 and the second digital monitoring quantity μ2 according to the polynomial coefficients corresponding to the current output mode to obtain a compensated monitoring quantity. For example, the digital polynomial processing unit can perform a compensation operation on the first digital monitoring quantity μ1 to obtain the compensated monitoring quantity p(μ1).

[0084] For example, the error generation unit 1322 is coupled to the digital polynomial processing unit 1321 and the first conditioning sub-circuit, respectively, and is configured to generate an error signal based on the difference between the compensated monitoring quantity and at least one of the first digital monitoring quantity and the second digital monitoring quantity. For example, the error generation unit 1322 can generate an error signal based on the difference between the compensated monitoring quantity p(μ1) and the second digital monitoring quantity μ2, i.e., μE = p(μ1) - μ2.

[0085] For example, such as Figure 5As shown, before the second conditioning sub-circuit 132 processes the first digital monitoring quantity μ1 and the second digital monitoring quantity μ2, the first conditioning sub-circuit 131 may further include a digital filtering and decimation unit. For example, the digital filtering and decimation unit can use a second-order sinc (sinc²) filter to decimate (downsample) the bit current signals BS1 and BS2 output by the current-to-analog converter, respectively, to obtain high-precision digital values ​​(e.g., 22 bits, approximately 60Hz) of the first digital monitoring quantity μ1 and the second digital monitoring quantity μ2, and can hold the obtained digital values ​​through a hold unit. For example, BS1 and BS2 correspond to the bit current signals in the first monitoring mode and the second monitoring mode, respectively.

[0086] For example, in at least one embodiment, the digital polynomial processing unit may include a batch calibration unit 1321a and a single-chip calibration unit 1321b arranged in parallel.

[0087] For example, batch calibration unit 1321a can be configured to perform batch calibration operations on at least one of a first digital monitoring quantity and a second digital monitoring quantity based on batch calibration polynomial coefficients to generate a batch calibration quantity. For example, batch calibration unit 1321a can implement batch calibration polynomial P. B (·), batch calibration polynomial P B (·) For example, a fourth-order polynomial is used to eliminate systematic nonlinearity and high-order curvature error of chips in the same batch. The batch calibration polynomial coefficients are obtained by fitting statistical data of the chips in the batch and are shared by all chips in the same batch.

[0088] For example, the single-chip calibration unit 1321b can be configured to perform a single-chip calibration operation on at least one of a first digital monitoring quantity and a second digital monitoring quantity based on the coefficients of a single-chip calibration polynomial to generate a single-chip calibration quantity. For example, the single-chip calibration unit 1321b can implement the single-chip calibration polynomial P. I (·), Single-chip calibration polynomial P I (·) For example, a linear polynomial is used to eliminate linear offset and gain error introduced by random mismatch of local devices in each chip; if a point calibration is used, it is only used to eliminate misalignment error.

[0089] For example, the digital polynomial processing unit can be configured to generate a compensated monitoring value based on the batch calibration value and the single-chip calibration value. For example, the digital polynomial processing unit can superimpose the batch calibration value and the single-chip calibration value to generate the compensated monitoring value. For example, the batch calibration value and the single-chip calibration value can each represent a correction amount relative to the digital monitoring value to be compensated.

[0090] The digital polynomial processing unit provided in at least one embodiment of this disclosure adopts a separate calibration strategy, which significantly reduces the independent calibration cost of each chip in the mass production stage while ensuring high compensation accuracy.

[0091] It should be noted that the batch calibration polynomial and the single-chip calibration polynomial can also be combined in the actual circuit to save digital circuit overhead. That is, the above calibration strategy can also be achieved by directly modifying the coefficients of the overall polynomial. The embodiments disclosed herein do not limit this.

[0092] For example, the coefficients of the polynomial p(·) can be obtained in the following way: during the simulation phase, the ideal output current is used. The data is fed into a current-to-analog-to-digital converter, and polynomial coefficients are obtained by fitting the outputs of the first digital monitoring quantity μ1 and the second digital monitoring quantity μ2. During the actual measurement phase, an external auxiliary loop is used to drive the loop to the target value, and the corresponding μ1 and μ2 values ​​are recorded before fitting. For example, the external auxiliary loop is a closed-loop automatic calibration architecture based on Successive Approximation Register (SAR) logic.

[0093] In addition, for example, such as Figure 5 As shown, the second conditioning sub-circuit 132 can also perform linearization processing based on the first digital monitoring quantity μ1 and the second digital monitoring quantity μ2, and output a digital temperature value through the temperature polynomial PT(·), thereby adding a temperature sensing output function in addition to the reference source function. The embodiments of this disclosure do not limit this.

[0094] For example, linearization can be expressed by the following formula:

[0095] Where α is the linearization coefficient. This represents the difference between the first and second monitoring voltages under two different current density conditions. The linearized digital temperature quantity μlin can be further processed by a temperature polynomial to generate a digital temperature value.

[0096] Figure 6 This is a schematic diagram of another digital polynomial processing method provided in at least one embodiment of the present disclosure.

[0097] For example, in at least one embodiment, the digital polynomial processing unit can be configured to determine polynomial coefficients based on digital configuration information, including coefficient group selection information and / or coefficient adjustment information, so that the reference source circuit outputs different current reference values ​​or different voltage reference values.

[0098] For example, the coefficient group selection information can be configured to select one set of polynomial coefficients from multiple preset sets of polynomial coefficients, with different sets of polynomial coefficients corresponding to different current reference values ​​or different voltage reference values. For instance, multiple sets of polynomial coefficients can be stored in the digital domain, directly corresponding to different output values ​​(e.g., voltage reference values ​​of 0.8V, 0.9V, and 1V, or current reference values ​​of 9μA, 10μA, and 11μA), achieving discrete multi-mode switching, which is sufficient to meet the needs of some scenarios requiring different output levels. It should be noted that the specific values ​​of the voltage and current reference values ​​mentioned above are merely examples, and other specific values ​​are also possible; the embodiments disclosed herein do not limit this.

[0099] like Figure 6 As shown, the coefficient adjustment information can be configured to adjust the polynomial coefficients or the digital monitoring quantity input to the digital polynomial processing unit to continuously regulate the current reference value or voltage reference value. For example, digital configuration information D can be received through a digital input interface. IN And according to the digital configuration information D IN By directly controlling the polynomial coefficients, a continuously adjustable high-resolution reference output is achieved, essentially realizing a high-precision programmable reference source with digital-to-analog conversion characteristics.

[0100] For example, such as Figure 6 As shown, in this method, the first monitoring voltage is predicted and corrected. Second monitoring voltage With output current The changing relationship is used to correct the values ​​of the first digital monitoring quantity μ1 and the second digital monitoring quantity μ2 using coefficient units (e.g., coefficients k1, k2 and adjustment polynomial pD(·)) (e.g., to obtain corrected μ1′ and μ2′), so that the output value can be continuously adjusted while the main body of the polynomial remains unchanged.

[0101] Figure 7 This is a schematic diagram illustrating the variation of output current with temperature in current reference mode and voltage reference mode, provided for at least one embodiment of this disclosure.

[0102] For example, such as Figure 7 As shown, the digital polynomial processing unit stores multiple sets of polynomial coefficients corresponding to different output modes. For example, at least one set of polynomial coefficients is used to characterize a first compensation relationship to determine the target temperature characteristics of the output current in the current reference mode; at least another set of polynomial coefficients is used to characterize a second compensation relationship to determine the target temperature characteristics of the output current in the voltage reference mode, so that the temperature change of the output current compensates for the temperature change of the output resistance.

[0103] In current-reference mode, the polynomial p(·) is designed to make the output current It is independent of temperature. Specifically, it can be expressed by the following formula:

[0104] Among them, output current Directly output as a current reference .

[0105] For example, in voltage reference mode, the output current The temperature coefficient is designed to exactly offset the output resistance. The temperature coefficient makes = · It is independent of temperature. Specifically, it can be expressed by the following formula:

[0106] like Figure 7 As shown, in current reference mode, the output current... The output current remains essentially constant across the entire temperature range; however, in voltage reference mode, the output current... It varies with temperature (e.g., decreases as temperature increases) to compensate for output resistance. The output changes with temperature. Then, the first or second output terminal can be selected via a mode selection switch to achieve the output of a voltage reference or a current reference.

[0107] The reference source circuit provided in at least one embodiment of this disclosure generates currents with different temperature coefficients by configuring different digital polynomial coefficients p(·), thereby realizing both current reference and voltage reference modes on the same circuit.

[0108] Figure 8 This is a schematic diagram of a digital-to-analog conversion module provided in at least one embodiment of the present disclosure.

[0109] For example, such as Figure 5 and Figure 8 As shown, the third conditioning sub-circuit 133 may include a digital integrator 1331 and a digital-to-analog converter module 1332. Figure 5 The diagram illustrates how the error signal μE is processed by a digital integrator, an upsampling unit, and a 1-bit Delta-Sigma modulator (1-bit DSM) to generate a single-bit bit stream. Digital feedback implementation; Figure 8 A single-bit stream is shown. After being supplied to the bias generation circuit 13321, the signal is converted from a digital-to-analog converter to a feedback control signal generated by the filter circuit 13322. For example, Figure 8 In It can be understood as Figure 5The output of the 1-bit DSM.

[0110] For example, such as Figure 5 As shown, the digital integrator 1331 is connected between the second conditioning sub-circuit 132 and the digital-to-analog converter module 1332, and is configured to accumulate the error signal to generate a digital feedback quantity. For example, the error signal μE after digital polynomial processing enters the digital integrator for accumulation. The digital integrator 1331 can provide an approximately infinite loop DC gain, ensuring that the average value of the error signal μE is driven to zero, thereby causing the system to enter a current-locked state determined by the characteristics of the digital polynomial.

[0111] For example, such as Figure 5 As shown, the digital integrator 1331 may include an accumulator Σ and is configured to accumulate the error signal μE to generate a digital feedback quantity. For example, as Figure 5 As shown, the digital feedback quantity can be upsampled by the upsampling unit and then provided to the modulator 13323. The modulator 13323 can be, for example, a single-bit ΔΣ modulator (1-bit DSM) and is configured to convert the upsampled digital feedback quantity into a single-bit bit stream. .

[0112] For example, the digital-to-analog converter module 1332 is connected between the digital integrator and the output circuit and is configured to convert the digital feedback quantity into a feedback control signal and apply the feedback control signal to the output circuit to regulate the output current.

[0113] For example, such as Figure 8 As shown, the digital-to-analog conversion module 1332 may include a modulator 13323, a bias generation circuit 13321, and a filter circuit 13322.

[0114] For example, modulator 13323 is configured to convert digital feedback into a single-bit stream. For example, after accumulation and upsampling by a digital integrator, a high-bit-width, low-rate digital signal (e.g., 22-bit, approximately 60Hz) can be converted into a high-speed single-bit stream using a fully digital first-order ΔΣ modulator. (e.g., 1 bit, 4MHz). This single-bit stream. It is fed into the current analog-to-digital converter circuit for digital-to-analog conversion. This is the operating clock or update clock for the current analog-to-digital-to-analog converter circuit, a single-bit stream. It is possible Under the control of the trigger, the bias is provided to the bias generation circuit 13321 after synchronization.

[0115] For example, the bias generation circuit 13321 and the filter circuit 13322 are coupled in sequence.

[0116] For example, the bias generation circuit 13321 is configured to generate a bias signal based on a single-bit stream. For example, as Figure 8 As shown, the reference voltage of the bias generation circuit 13321 can be generated by a dedicated CTAT bias circuit (e.g., generating voltage). and To achieve a balance between noise and power supply sensitivity; subject to single-bit stream (For example, controlled by a trigger with frequency FDAC=4MHz synchronization), the bias generation circuit can... and A choice is made between current-reference mode and voltage-reference mode to generate the bias signal. In both current-reference and voltage-reference modes, the CTAT bias current generated by the bias generation circuit can... and The output current is adjusted to the target value corresponding to the current output mode by taking a value between these ranges. For example, in voltage reference mode, due to the output current... The temperature coefficient needs to compensate for the output resistance. The temperature coefficient of CTAT bias current can be In current reference mode, the CTAT bias current can be... .

[0117] For example, filter circuit 13322 is configured to filter the bias signal. For example, the filter circuit can be a third-order RC filter (e.g., including resistors RF1, RF2, RF3 and capacitors CF1, CF2, CF3) to filter out quantization noise and broadband noise.

[0118] For example, the filter circuit 13322 is also configured to generate a feedback control signal based on the filtered bias signal. For example, the filter circuit 13322 can generate a signal for adjusting the gate-source voltage of the PMOS transistor based on the filtered bias signal. The feedback control signal is applied to the PMOS transistor M0 in the output circuit to regulate the output current. The current replication branch can generate a corresponding replication current based on the regulated output current, and then provide the replication current to the monitoring circuit.

[0119] The digital-to-analog conversion module provided in at least one embodiment of this disclosure ensures the monotonicity of the digital-to-analog conversion by employing single-bit ΔΣ digital-to-analog conversion. Utilizing high-resolution polynomial coefficients in the digital domain, the system can achieve sub-ppm level ultra-high resolution tuning.

[0120] For example, the loop bandwidth can be designed to be approximately 10 Hz to achieve a balance between front-end / analog-to-digital converter noise (which is low-pass filtered) and digital-to-analog converter module / current source noise (which is high-pass filtered). The embodiments of this disclosure do not limit the specific design value of the loop bandwidth.

[0121] Figure 9 A schematic diagram of a monitoring circuit and a first conditioning sub-circuit provided for at least one embodiment of this disclosure.

[0122] For example, such as Figure 9 As shown, the monitoring circuit 120 may include a current replication branch 121, a sensing resistor 122, and a transistor detection branch 123. For example, the current replication branch 121 is coupled to the sensing resistor 122 and the transistor detection branch 123, respectively, and is configured to provide a replicated current to the sensing resistor 122 and the transistor detection branch 123 based on the output current; the sensing resistor 122 is configured to respond to a first monitoring voltage. Or the second monitoring voltage A current conversion is performed to form a detection current; the transistor detection branch 123 can be configured to generate a first monitoring voltage under different current density conditions. Second monitoring voltage For example, sensing resistors Used to measure the base-emitter voltage in the current monitoring mode under the negative feedback of the continuous-time integrator. Converted to detection current, the value of the detection current is equal to / For example, the replication current provided to the transistor detection branch 123 can form a first bias current or a second bias current.

[0123] For example, in at least one embodiment, the transistor detection branch may include a single bipolar transistor (BPT) QCORE, configured to receive a first bias current and a second bias current in a time-division multiplexing manner to generate a first monitoring voltage and a second monitoring voltage, respectively, wherein the first bias current and the second bias current have a preset ratio. For example, the first bias current and the second bias current may be formed by a replication current. For example, the first monitoring voltage is the voltage between the base and emitter of the BPT QCORE under the first bias current condition, and the second monitoring voltage is the voltage between the base and emitter of the BPT QCORE under the second bias current condition. For example, the conditioning circuit is configured to switch between a first monitoring mode and a second monitoring mode in a time-multiplexed manner, the first monitoring mode corresponding to the monitoring of the first monitoring voltage and the second monitoring mode corresponding to the monitoring of the second monitoring voltage.

[0124] For example, the first bias current can be N× (For example, N=5, i.e., 5×) The second bias current can be 1× That is, the preset ratio is N:1. For example, the first monitoring voltage For the bipolar transistor QCORE, at the first bias current (large current N×) The voltage between the base and emitter under the given conditions, the second monitoring voltage. For the bipolar transistor QCORE, at the second bias current (small current 1×) The voltage between the base and emitter under the condition of ( ). That is, the voltage between the base and emitter under the condition of ( ). Figure 2 Unlike the previous method which used two bipolar transistors Q1 and Q2, this embodiment uses only one bipolar transistor QCORE. By dynamically switching the mirror ratio (N) of the replication current injected into QCORE, the first monitoring voltage is alternately generated on the same bipolar transistor in a time-sharing manner. Second monitoring voltage It should be noted that the specific value of N can be adjusted according to the device characteristics of the bipolar transistor, the target detection accuracy, and the circuit design requirements, and this embodiment does not impose any limitations on this. For example, the conditioning circuit 130 is configured to switch between a first monitoring mode and a second monitoring mode in a time-multiplexed manner, the first monitoring mode corresponding to a first monitoring voltage. The monitoring mode corresponds to the second monitoring voltage. Monitoring.

[0125] Figure 10 A schematic diagram illustrating the switching timing of a first monitoring mode and a second monitoring mode provided for at least one embodiment of this disclosure.

[0126] For example, such as Figure 10 As shown, the current-to-analog-to-digital converter (DAC) switches between a first monitoring mode and a second monitoring mode via a μ1 / μ2 selection signal, switching in a time-interleaved manner between the conversion mode generating the first digital monitoring quantity μ1 (output bit stream BS1) and the conversion mode generating the second digital monitoring quantity μ2 (output bit stream BS2). For example, at each mode switch, a reset signal closes the aforementioned reset switch to release residual charge on the integrating capacitor. For example, the switching between the first and second monitoring modes can be controlled by the μ1 / μ2 selection signal. The μ1 / μ2 selection signal can be generated by timing control logic in the conditioning circuit and used to control the switching of the monitoring circuit and the first conditioning sub-circuit between the first and second monitoring modes. When the μ1 / μ2 selection signal indicates the first monitoring mode, the transistor detection branch receives a first bias current and generates a first monitoring voltage; when the μ1 / μ2 selection signal indicates the second monitoring mode, the transistor detection branch receives a second bias current and generates a second monitoring voltage.

[0127] The single-device time-division extraction design provided in at least one embodiment of this disclosure has the following advantages: (1) It fundamentally eliminates bipolar transistor mismatch: due to the first monitoring voltage Second monitoring voltage All of them come from the same bipolar transistor, which fundamentally eliminates the process mismatch error between the two bipolar transistors (such as the mismatch of saturation current), thereby achieving higher measurement accuracy; (2) Time interleaving multiplexing: the analog-to-digital conversion module of the later stage can seamlessly switch between the two conversion modes of μ1 and μ2 in a time interleaving manner. By reusing the same set of core analog circuits (including bipolar transistors, analog-to-digital converters, etc.), the silicon area of ​​the chip is greatly saved, and the analog accuracy that the system can achieve is further improved.

[0128] For example, such as Figure 9 As shown, in at least one embodiment, the monitoring circuit 120 may further include a feedback switch 126 and a virtual transistor branch 125. The virtual transistor branch 125 is coupled to the switching node where the feedback switch 126 is located and is configured to receive current not being monitored during current switching or when the feedback switch is open, in order to stabilize the potential of the switching node. For example, the virtual transistor branch 125 may receive a replicated current not connected to the continuous-time integrator, or a replicated current not used as a first bias current or a second bias current in the current monitoring mode, in order to stabilize the potential of the corresponding switching node. For example, the feedback switch 126 may be a current-directed switch controlled by a bit current signal BS. The bit current signal BS may be a bit current signal BS1 output by a current-to-analog-to-digital converter in the first monitoring mode, or a bit current signal BS2 output by a current-to-analog-to-digital converter in the second monitoring mode. For example, when the bit current signal BS is active, the feedback switch 126 connects the replicated current to the feedback branch of the continuous-time integrator, so that the replicated current forms a feedback current and participates in the feedback balance of the continuous-time integrator; when the bit current signal BS is inactive, the feedback switch 126 directs the replicated current that is not monitored to the virtual transistor branch.

[0129] For example, such as Figure 9 As shown, the virtual transistor branch can include virtual bipolar transistors QD0, QD1 and QD2.

[0130] For example, in the first monitoring mode, 5× The total current is fully injected into the QCORE as the first bias current, so that the QCORE generates the first monitoring voltage. However, during the period when the feedback switch controlled by the current signal is off (i.e., when BS=0), in order to avoid bias point drift and recovery delay caused by directly shutting off the current source, the replicated current not utilized by the continuous-time integrator is directed to the virtual bipolar transistor QD0 for discharge. This current-directing mechanism ensures that the main current source always remains on, greatly suppressing switching transient interference caused by current surges.

[0131] For example, in the second monitoring mode, only 1× is retained. The current is injected into the QCORE as a second bias current to cause the QCORE to generate a second monitoring voltage. To avoid shutting off unused current sources, 4×1× The current is bypassed to the virtual bipolar transistor QD1; and, during the bit current signal BS=0 in this mode, the unused replicated current is directed as a discharge current to a virtual bipolar transistor array with a total emitter area five times that of the unit area, such as a combination of QD0 and QD2. The unit area can refer to the emitter area of ​​a single bipolar transistor. The reason for using a virtual device with five times the area is to match the reduced current density of QCORE during the conduction phase (BS=1), which is reduced by a factor of five. It should be noted that the above current ratio, virtual transistor area ratio, and specific current allocation method are merely exemplary designs, and the embodiments disclosed herein do not limit the specific values.

[0132] The monitoring circuit provided in at least one embodiment of this disclosure, under given device parameters and temperature conditions, ensures that the voltage of the bipolar transistor is primarily determined by the current density. This area matching ensures that the potential difference across the switching node controlled by the potential current signal BS does not change due to switching of monitoring modes, regardless of the state of the feedback switch (on or off). The stability of the switching node voltage greatly suppresses charge injection errors related to parasitic capacitance charging and discharging, guaranteeing high-precision signal extraction from the hardware level.

[0133] For example, such as Figure 9 As shown, in at least one embodiment, the current replication branch may include a current source array ( Figure 9 (Not shown in the diagram) Multiple current-directed switches 124 and a matching control unit 1211. For example, the current source array includes multiple unit current sources that can be configured to generate multiple unit currents based on feedback control signals. For example, the current value of the unit current generated by each unit current source can be equal to the output current. The current value. For example, multiple current-directed switches 124 can be coupled to multiple unit current sources, a transistor detection branch 123, a sensing resistor 122, and an output circuit; a matching control unit 1211 is coupled to the multiple current-directed switches 124 and configured to control the conduction state of the multiple current-directed switches according to a preset rotation sequence, so that the multiple unit current sources are connected to at least two of the transistor detection branch, the sensing resistor, and the output circuit in different time slots. For example, the multiple current-directed switches can be controlled by a dynamic element matching control signal generated by the matching control unit. The matching control unit can generate a dynamic element matching control signal according to a preset rotation sequence to control the conduction state of the multiple current-directed switches in different time slots, so that the current generated by the multiple unit current sources is rotated to at least two of the transistor detection branch, the sensing resistor, and the output circuit. Through the above rotation control, the static mismatch between the multiple unit current sources can be time-averaged, thereby reducing the impact of current source mismatch on monitoring results and output reference.

[0134] It should be noted that the current source array can be a shared current source / current mirror array for both the output circuit and the monitoring circuit. For example, the current replication branch may include sections for providing replicated current to the sensing resistor, transistor detection branch, and feedback branch of the continuous-time integrator, while the current source of the output circuit may include sections for providing output current to the output terminal. For example, in different time slots, when a unit current is directed to the output circuit, this unit current can form the output current. When a unit current is directed to the monitoring circuit, this unit current can form a relationship with the output current. The corresponding replication current. For example, when the replication current is directed to the transistor detection branch 123, it can form a first bias current or a second bias current. For example, when the replication current is directed to the feedback branch of the continuous-time integrator via the feedback switch 126, it can form a feedback current.

[0135] For example, such as Figure 9 As shown, in order to improve the sensitivity of temperature sensing (and...) A trade-off can be struck between the amplitude-dependent bias and the overall circuit area / power complexity. A 5:1 ratio between the first and second bias currents (i.e., N=5) can be chosen. Therefore, the system can achieve a 5×... The current is injected into a single bipolar transistor QCORE in the transistor detection branch 123; at the same time, the current with a size of 1× and 2× The current is directed to the sensing resistors respectively. The branch and output circuit, for example Figure 9The "to IOUT / VOUT" in the text refers to the current source array, which may include eight unit current sources (5+1+2=8 units). To eliminate static device mismatch among these eight unit current sources, the matching control unit can introduce dynamic element matching (DEM) technology. For example, its clock rotation frequency can be set to FDEM=FS / 64 (e.g., FDEM=7.8125kHz, FS=500kHz). Through dynamic averaging in the time domain, the mismatch error of the current mirror is effectively pushed to a high frequency and then filtered out by a low-pass filter. It should be noted that the above current ratio, number of current sources, and dynamic element matching frequency are only exemplary designs, and the embodiments disclosed herein do not limit the specific values.

[0136] For specific device selection and layout, the present disclosure may use the following examples, but the present disclosure does not limit them.

[0137] For example, in the selection of bipolar transistors, all unit bipolar transistors can be vertical PNP transistors adapted to standard CMOS processes, with the emitter area of ​​each unit bipolar transistor set to, for example, 10μm × 10μm. Similarly, in the selection of resistors, to enhance the chip's anti-aging stability during long-term operation and under harsh environments, both the output resistor (value, for example, approximately 90kΩ) and the sensing resistor (value, for example, approximately 225kΩ) can employ N-diffusion resistor structures, which offer greater physical stability than traditional polysilicon. For example, for current source bias structures, considering the requirements for high output impedance and low-frequency noise characteristics, the transistor bias design of the current source array can introduce dual robustness techniques. On the one hand, a cascode structure is used to significantly increase the output impedance and ensure the current constantness over a wide voltage range. On the other hand, a source degeneration resistor RDEG (e.g., RDEG≈26kΩ) is introduced at the source end of the current source to effectively reduce the transconductance of the bias transistor through a negative feedback mechanism, thereby significantly suppressing its contribution to the low-frequency 1 / f noise and thermal noise of the overall output.

[0138] In addition, such as Figure 9 As shown, the continuous-time integrator in the first conditioning circuit 131 may also employ chopping technology (e.g., chopping frequency FCHOP = 62.5kHz) and may include a switched-capacitor second-stage integrator (SC2nd Stage) to further suppress operational amplifier offset and low-frequency noise, which is not limited in the embodiments of this disclosure.

[0139] It should also be noted that, for clarity and brevity, the embodiments of this disclosure do not show all the constituent units of the above-described reference source circuit. To achieve the necessary functions of the above-described reference source circuit, those skilled in the art can provide and configure other constituent units (not shown) according to specific needs, and the embodiments of this disclosure do not impose any limitations on this.

[0140] Figure 11 This is a schematic block diagram illustrating a control method provided in at least one embodiment of the present disclosure.

[0141] At least one embodiment of this disclosure also provides a control method that can be used in the reference source circuit 100 described in any of the above embodiments. Figure 11 As shown, the control method includes steps S110-S130.

[0142] Step S110: Use the output circuit to generate an output current, and according to the current output mode, control the output circuit to output a current reference in current reference mode, or make the output current flow through the output resistor to form a voltage reference in voltage reference mode.

[0143] Step S120: Use the monitoring circuit to generate a monitoring voltage based on the output current.

[0144] Step S130: The conditioning circuit generates a feedback control signal based on the monitored voltage and the compensation relationship corresponding to the current output mode, and feeds the feedback control signal back to the output circuit to adjust the output current.

[0145] For example, in step S130, in current reference mode, the conditioning circuit adjusts the output current according to the first compensation relationship so that the output current is basically independent of temperature; in voltage reference mode, the conditioning circuit adjusts the output current according to the second compensation relationship so that the temperature change of the output current compensates for the temperature change of the output resistance.

[0146] The specific implementation of this control method can be referred to the corresponding description of the reference source circuit 100 above. The repeated parts will not be repeated. It can achieve the same or similar technical effects as the reference source circuit 100.

[0147] Figure 12 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure. Figure 12 As shown, the electronic device 300 also provides an electronic device 300 including the reference source circuit 100 described in any of the above embodiments.

[0148] For example, electronic device 300 can be any device or apparatus that requires a voltage reference and / or current reference, such as an analog-to-digital converter chip, a digital-to-analog converter chip, a sensor chip, a power management chip, a clock circuit, or a measuring instrument. The embodiments of this disclosure do not limit this.

[0149] Since the electronic device 300 includes the reference source circuit 100 described in any of the above embodiments, the electronic device 300 can also reconfigure a high-precision current reference and voltage reference on the same circuit. The specific implementation method and technical effect can be referred to the corresponding description of the reference source circuit 100 above, and will not be repeated here.

[0150] Figure 13 This is a schematic diagram of another electronic device provided for at least one embodiment of the present disclosure.

[0151] like Figure 13 As shown, in some examples, electronic device 300 includes a processing unit (e.g., central processing unit, graphics processor, etc.) 301, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 302 or a program loaded from storage device 308 into random access memory (RAM) 303. The RAM 303 also stores various programs and data required for the operation of the computer system. The processing unit 301, ROM 302, and RAM 303 are interconnected via bus 304. An input / output (I / O) interface 305 is also connected to bus 304. For example, the input / output (I / O) interface 305 may include, for example, a USB interface or a network interface.

[0152] For example, the following components can be connected to I / O interface 305: input devices 306 including, for example, touch screens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 307 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 308 including, for example, magnetic tapes, hard disks, etc.; and communication devices 309, such as network interface cards like LAN cards and modems, etc. Communication device 309 allows electronic device 300 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 310 is also connected to I / O interface 305 as needed. Removable media 311, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on drive 310 as needed so that computer programs read from them can be installed into storage device 308 as needed.

[0153] For example, the processing device 301, input / output interface 305, and communication device 309 in electronic device 300 may include reference source circuit 100.

[0154] Although Figure 13 An electronic device 300 including various devices is shown; however, it should be understood that implementation or inclusion of all shown devices is not required. More or fewer devices may be implemented or included alternatively.

[0155] For example, the electronic device 300 may further include a peripheral interface (not shown in the figure). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 309 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0156] For example, the electronic device 300 may include any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, server, etc., or any combination of hardware. The embodiments disclosed herein do not limit this.

[0157] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to the embodiments of the present disclosure, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present disclosure are within the scope of protection claimed by the present disclosure.

[0158] The following points should be noted regarding this disclosure: (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0159] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0160] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0161] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A reference source circuit, comprising an output circuit, a monitoring circuit, and a conditioning circuit; wherein, The output circuit is coupled to the monitoring circuit, and the conditioning circuit is connected between the monitoring circuit and the output circuit. The output circuit includes an output resistor and is configured to generate an output current and output a current reference in current reference mode, or to allow the output current to flow through the output resistor to form a voltage reference in voltage reference mode. The monitoring circuit is configured to generate a monitoring voltage based on the output current; The conditioning circuit is configured to generate a feedback control signal based on the monitored voltage and the compensation relationship corresponding to the current output mode, and to feed the feedback control signal back to the output circuit to adjust the output current. The compensation relationship includes a first compensation relationship corresponding to the current reference mode and a second compensation relationship corresponding to the voltage reference mode. In the current reference mode, the conditioning circuit is configured to adjust the output current according to the first compensation relationship; In the voltage reference mode, the conditioning circuit is configured to adjust the output current according to the second compensation relationship.

2. The reference source circuit according to claim 1, wherein, The monitoring voltage includes a first monitoring voltage, a second monitoring voltage, and a sensing resistor voltage corresponding to the output current; the conditioning circuit includes a first conditioning sub-circuit, a second conditioning sub-circuit, and a third conditioning circuit; The first conditioning sub-circuit is coupled to the monitoring circuit and is configured to quantize the first monitoring voltage, the second monitoring voltage, and the sensing resistor voltage to obtain a first digital monitoring quantity and a second digital monitoring quantity characterizing the temperature and output current state. The second conditioning sub-circuit is coupled to the first conditioning sub-circuit and the third conditioning sub-circuit respectively, and is configured to perform compensation processing on at least one of the first digital monitoring quantity and the second digital monitoring quantity to generate an error signal; as well as The third conditioning sub-circuit is connected between the second conditioning sub-circuit and the output circuit, and is configured to generate the feedback control signal based on the error signal, so as to adjust the output current through the feedback control signal.

3. The reference source circuit according to claim 2, wherein, The first conditioning sub-circuit includes an analog-to-digital converter module. The analog-to-digital conversion module is coupled to the monitoring circuit and the second conditioning sub-circuit, respectively, and is configured to generate a first digital monitoring quantity and a second digital monitoring quantity based on the first monitoring voltage, the second monitoring voltage, and the sensing resistor voltage, wherein the first digital monitoring quantity represents the ratio between the first monitoring voltage and the sensing resistor voltage, and the second digital monitoring quantity represents the ratio between the second monitoring voltage and the sensing resistor voltage.

4. The reference source circuit according to claim 3, wherein, The analog-to-digital conversion module includes a current-to-analog-to-digital converter, which includes a continuous-time integrator and a quantizer. The continuous-time integrator includes an operational amplifier and an integrating capacitor. The continuous-time integrator is coupled to the monitoring circuit and the quantizer, respectively, and is configured to form a detection current based on the relationship between the first monitoring voltage or the second monitoring voltage and the voltage of the sensing resistor. The quantizer is coupled to the continuous-time integrator and configured to generate a bit stream signal based on the output of the continuous-time integrator, wherein the bit stream signal is used to control a feedback current corresponding to the output current. The continuous-time integrator is further configured to integrate the difference between the detected current and the feedback current, so that the current analog-to-digital converter generates the first digital monitoring quantity or the second digital monitoring quantity.

5. The reference source circuit according to claim 4, wherein, The conditioning circuit further includes a reset switch coupled to the integrating capacitor and configured to release residual charge on the integrating capacitor during switching between monitoring the first monitoring voltage and monitoring the second monitoring voltage.

6. The reference source circuit according to claim 2, wherein, The second conditioning sub-circuit includes a digital polynomial processing unit and an error generation unit; The digital polynomial processing unit is coupled to the first conditioning sub-circuit and configured to perform a compensation operation on at least one of the first digital monitoring quantity and the second digital monitoring quantity according to the polynomial coefficients corresponding to the current output mode, so as to obtain a compensated monitoring quantity; and The error generation unit is coupled to the digital polynomial processing unit and the first conditioning sub-circuit, respectively, and is configured to generate the error signal based on the difference between the compensated monitoring quantity and at least one of the first digital monitoring quantity and the second digital monitoring quantity.

7. The reference source circuit according to claim 6, wherein, The digital polynomial processing unit includes a batch calibration unit and a single-chip calibration unit arranged in parallel. The batch calibration unit is configured to perform batch calibration operations on at least one of the first digital monitoring quantity and the second digital monitoring quantity according to the batch calibration polynomial coefficients to generate a batch calibration quantity; and The single-chip calibration unit is configured to perform a single-chip calibration operation on at least one of the first digital monitoring quantity and the second digital monitoring quantity according to the single-chip calibration polynomial coefficients to generate a single-chip calibration quantity. The digital polynomial processing unit is configured to generate the compensated monitoring quantity based on the batch calibration quantity and the single-chip calibration quantity.

8. The reference source circuit according to claim 6, wherein, The digital polynomial processing unit stores multiple sets of polynomial coefficients corresponding to different output modes. Wherein, at least one set of polynomial coefficients is used to characterize the first compensation relationship in order to determine the target temperature characteristics of the output current in the current reference mode; At least another set of polynomial coefficients is used to characterize the second compensation relationship to determine the target temperature characteristics of the output current under the voltage reference mode, so that the temperature change of the output current compensates for the temperature change of the output resistance.

9. The reference source circuit according to claim 6, wherein, The digital polynomial processing unit is configured to determine the polynomial coefficients based on digital configuration information, which includes coefficient group selection information and / or coefficient adjustment information, so that the reference source circuit outputs different current reference values ​​or different voltage reference values.

10. The reference source circuit according to claim 9, wherein, The coefficient group selection information is configured to select a set of polynomial coefficients from multiple preset polynomial coefficients, with different sets of polynomial coefficients corresponding to different current reference values ​​or different voltage reference values. The coefficient adjustment information is configured to adjust the polynomial coefficients or adjust the digital monitoring quantity input to the digital polynomial processing unit to continuously adjust the current reference value or the voltage reference value.

11. The reference source circuit according to claim 2, wherein, The third conditioning sub-circuit includes a digital integrator and a digital-to-analog converter module; The digital integrator is connected between the second conditioning sub-circuit and the digital-to-analog converter module, and is configured to accumulate the error signal to generate a digital feedback quantity; as well as The digital-to-analog converter module is connected between the digital integrator and the output circuit, and is configured to convert the digital feedback quantity into a feedback control signal, and apply the feedback control signal to the output circuit to adjust the output current.

12. The reference source circuit according to claim 11, wherein, The digital-to-analog conversion module includes a modulator and a current-to-digital-to-analog conversion circuit; The modulator is configured to convert the digital feedback quantity into a single-bit stream; The current analog-to-digital-to-analog converter circuit includes a bias generation circuit and a filter circuit coupled in sequence; wherein, The bias generation circuit is configured to generate a bias signal based on the single-bit stream. The filtering circuit is configured to filter the bias signal and generate the feedback control signal based on the filtered bias signal.

13. The reference source circuit according to claim 2, wherein, The monitoring circuit includes a current replication branch, a sensing resistor, and a transistor detection branch. The current replication branch is coupled to the sensing resistor and the transistor detection branch respectively, and is configured to provide a replication current to the sensing resistor and the transistor detection branch based on the output current; The sensing resistor is configured to perform current conversion on either the first monitoring voltage or the second monitoring voltage to form a detection current; as well as The transistor detection branch is configured to generate the first monitoring voltage and the second monitoring voltage under different current density conditions.

14. The reference source circuit according to claim 13, wherein, The transistor detection branch includes a single bipolar transistor, which is configured to receive a first bias current and a second bias current in a time-division manner to generate a first monitoring voltage and a second monitoring voltage, respectively, wherein the first bias current and the second bias current have a preset ratio. Wherein, the first monitoring voltage is the voltage between the base and emitter of the bipolar transistor under the first bias current condition, and the second monitoring voltage is the voltage between the base and emitter of the bipolar transistor under the second bias current condition; The conditioning circuit is configured to switch between a first monitoring mode and a second monitoring mode in a time-multiplexed manner, wherein the first monitoring mode corresponds to the monitoring of the first monitoring voltage and the second monitoring mode corresponds to the monitoring of the second monitoring voltage.

15. The reference source circuit according to claim 13, wherein, The monitoring circuit also includes a feedback switch and a virtual transistor branch, the virtual transistor branch being coupled to the switching node where the feedback switch is located and configured to receive current not being monitored during current switching or when the feedback switch is open, in order to stabilize the potential of the switching node.

16. The reference source circuit according to claim 13, wherein, The current replication branch includes a current source array, multiple current-directing switches, and a matching control unit; The current source array includes multiple unit current sources; The plurality of current-guided switches are coupled to the plurality of unit current sources, the transistor detection branch, the sensing resistor and the output circuit; as well as The matching control unit is coupled to the plurality of current-directing switches and is configured to control the conduction state of the current-directing switches according to a preset rotation sequence, so that the plurality of unit current sources are connected to at least two of the transistor detection branch, the sensing resistor and the output circuit in different time slots.

17. The reference source circuit according to claim 1, wherein, The output circuit further includes a current source, a mode selection switch, a first output terminal and a second output terminal, wherein the output resistor is coupled to the second output terminal; The current source is configured to generate the output current according to the feedback control signal; and The mode selection switch is coupled to the current source, the first output terminal and the second output terminal respectively, and is configured to select to provide the output current to the first output terminal to output the current reference, or to select to provide the output current to the output resistor to form the voltage reference at the second output terminal.

18. The reference source circuit according to claim 17, wherein, The current source includes a PMOS transistor, the first terminal of which is coupled to a power supply, the second terminal of which is coupled to the mode selection switch, and the feedback control signal is applied to the third terminal of the PMOS transistor to change the output current by adjusting the voltage of the third terminal of the PMOS transistor.

19. An electronic device comprising a reference source circuit as described in any one of claims 1-18.

20. A control method for a reference source circuit as described in any one of claims 1-18, wherein, The method includes: The output circuit generates an output current, and according to the current output mode, the output circuit is controlled to output a current reference in current reference mode, or to make the output current flow through the output resistor to form a voltage reference in voltage reference mode. The monitoring circuit generates a monitoring voltage based on the output current; and The conditioning circuit generates a feedback control signal based on the monitored voltage and the compensation relationship corresponding to the current output mode, and feeds the feedback control signal back to the output circuit to adjust the output current.

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