A method and system for a matcher to detect input signal frequency

Abstract

The present application relates to a kind of matcher detection input signal frequency method, acquisition radio frequency input signal and it is converted into digital sampling signal;Pre-set positive threshold and negative threshold are opposite each other, and double threshold comparison is carried out to digital sampling signal, generate and fit the sine wave synchronous signal of radio frequency input signal same frequency;By monitoring whether the adjacent edge interval of fitting sine wave synchronous signal exceeds preset maximum period count threshold, pulse low level state and effective signal state are automatically distinguished;Enable period counter and time reference counter, in the preset time reference window in effective signal state, the number of rising edge is counted to calculate frequency, in the pulse low level state, the two counters are suspended;The frequency calculated is output to LC tuning network parameter calculation module in real time.The present application realizes the full digital processing of frequency detection, with strong anti-interference ability, dual-mode self-adaptive, low response delay characteristics, effectively reduce the power reflection loss of radio frequency system.

Description

Technical Field

[0001] This invention relates to the field of radio frequency matching devices, and more specifically, to a method and system for a matching device to detect the frequency of an input signal. Background Technology

[0002] Radio frequency (RF) matching devices are widely used in industrial RF systems such as semiconductor plasma etching and chemical vapor deposition. Their function is to adjust the impedance between the RF power supply and the plasma load in real time to maximize power transmission efficiency and reduce power reflection loss. The impedance adjustment strategy of the RF matching device relies on the accurate detection of the RF input signal frequency. The accuracy and real-time performance of frequency detection directly determine the response speed and matching effect of the matching device.

[0003] Chinese patent CN114914146A discloses a control method for an RF matching circuit. This method involves setting voltage and current probes at the input of the matching circuit to collect analog signals of RF voltage and current. These signals are then analyzed by an external signal processing circuit, and the frequency information is fed back to the matching circuit control system to drive impedance adjustment. The shortcomings of this solution are: its frequency detection relies on external analog sensors and signal processing circuits; temperature drift, gain error, and noise accumulation in the analog link can introduce frequency measurement errors; and when the RF power supply operates in pulse mode, the pulse silence period interferes with the frequency calculation results, leading to frequency measurement distortion.

[0004] Chinese patent CN104752139A discloses a radio frequency pulse system and its impedance matching method, involving an impedance adjustment strategy for pulsed radio frequency signals. This scheme focuses on the impedance switching timing in pulse mode, but its frequency detection part relies on external circuitry to sample the radio frequency signal using analog signals. It fails to automatically distinguish between high-level and low-level pulse states and to automatically mask and count during the low-level pulse period, making it difficult to fundamentally guarantee the accuracy of frequency detection results under pulsed radio frequency conditions.

[0005] In summary, the existing RF matching frequency detection schemes have the following common defects: frequency detection relies on analog circuits, which are susceptible to device drift and noise interference, resulting in insufficient frequency measurement stability; there is a lack of effective suppression mechanism for zero-crossing noise of RF signals, which easily leads to false triggering; and in pulse operating mode, it fails to achieve automatic identification and shielding of the low-level silent pulse, resulting in deviations in frequency calculation results. Summary of the Invention

[0006] To overcome the problems of the prior art, the present invention provides a method and system for a matcher to detect the frequency of an input signal.

[0007] The technical solution of this invention is as follows:

[0008] A method for detecting the frequency of an input signal using a matching circuit, executed by a digital control unit integrated within the radio frequency matching circuit, is characterized by comprising the following steps:

[0009] Step S1, Signal Acquisition and Digitization: The radio frequency input signal is acquired by a sensor set at the input end of the radio frequency matching unit, and the radio frequency input signal is converted into a digital sampling signal by the analog-to-digital conversion unit;

[0010] Step S2: Generation of dual-threshold fitting synchronization signal: Preset positive and negative thresholds that are opposites of each other, and the absolute value of both is not greater than the maximum amplitude of the digital sampling signal; when the digital sampling signal rises above the positive threshold, the level of the fitting synchronization signal is set high; when the digital sampling signal falls below the negative threshold, the level of the fitting synchronization signal is set low; repeat this cycle to generate a fitting sine wave synchronization signal with the same frequency as the RF input signal.

[0011] Step S3, Pulse State Judgment: A maximum period count threshold is preset, and the interval between adjacent edges of the fitted sine wave synchronization signal is monitored in real time; when the interval between adjacent edges exceeds the maximum period count threshold, the current state is determined to be a low-level pulse state; otherwise, it is determined to be a high-level pulse state or a non-pulse continuous sine wave state.

[0012] Step S4: Enable the period counter and time base counter; in the pulse high-level state or non-pulse continuous sine wave state, the period counter increments by 1 with each rising edge of the fitted sine wave synchronization signal, and the time base counter increments synchronously; when the time base counter reaches the clock counting threshold corresponding to the preset time base, the frequency is calculated based on the cumulative count value of the period counter, the actual cumulative count value of the time base counter, and the system clock frequency of the digital control unit, and both counters are reset to zero synchronously; in the pulse low-level state, both counters stop counting;

[0013] Step S5, Frequency Output: Output the frequency to the impedance adjustment control unit of the matching unit as the input for calculating the LC tuning network parameters, and drive the RF matching unit to update the impedance matching strategy in real time.

[0014] As a preferred embodiment of the present invention, in step S2, the positive threshold and the negative threshold are automatically adjusted based on the peak amplitude detection result of the digital sampling signal during the initialization phase, and are determined by the following formula:

[0015] V th+ =α× V peak V th- = -α× V peak , where V th+ As a positive threshold, V th- For a negative threshold, V peakThe peak amplitude of the digital sampling signal detected during the initialization phase is α, which is a preset scaling factor and satisfies 0 < α < 1.

[0016] As a preferred embodiment of the present invention, in step S3, the digital control unit is equipped with an edge counter. The edge counter is immediately reset and restarted each time a rising or falling edge of the fitted sine wave synchronization signal is detected. When its count value exceeds the maximum period count threshold, a pulse low-level flag is triggered. When the next edge arrives, the flag is reset, restoring the normal frequency measurement process. The maximum period count threshold is determined by the following formula: K = β × (ƒ clk / ƒ0); where K is the maximum period count threshold, ƒ clk ƒ0 is the clock frequency of the digital control unit, ƒ0 is the rated frequency of the detected radio frequency signal, and β is a safety margin factor greater than 1.

[0017] As a preferred embodiment of the present invention, the method further includes step S41, pulse duty cycle calculation; during the execution of step S4, the digital control unit is provided with a pulse high-level cumulative timer and a total cycle timer. The pulse high-level cumulative timer increments only when the pulse is high-level, while the total cycle timer increments continuously in both pulse high-level and pulse low-level states; when the total cycle timer reaches a preset pulse statistics window time, the pulse duty cycle is calculated using the following formula: D=(T H / T P ) ×100%; where D is the pulse duty cycle, T H T is the cumulative value of the pulse high-level accumulator timer within the pulse statistics window. P The total cycle timer cumulative value corresponding to the preset pulse statistical window time is used; the pulse duty cycle is output to the matching unit control unit as an auxiliary parameter for dynamic adjustment of the impedance matching strategy in pulse mode.

[0018] As a preferred technical solution of the present invention, in step S2, the digital control unit is provided with a dual threshold comparison unit, which is configured with a positive threshold and a negative threshold, respectively corresponding to the amplitude characteristics of different frequency components in the radio frequency system to be detected.

[0019] Furthermore, in step S4, each frequency component corresponds to an independent period counter and a time base counter, which synchronously complete the frequency measurement of each frequency component, thereby realizing the parallel detection and separation output of each frequency component of the multi-frequency superimposed radio frequency signal.

[0020] As a preferred embodiment of the present invention, the digital control unit is a field-programmable gate array integrated on the printed circuit board of the radio frequency matching unit body, the analog-to-digital conversion unit in step S1 is a high-speed analog-to-digital conversion chip directly connected to it, the sampling frequency is not less than 10 times the highest frequency of the detected radio frequency signal, and all logic operations, counter operations and frequency calculations in steps S2 to S5 are implemented in parallel in the internal logic resources of the field-programmable gate array.

[0021] As a preferred technical solution of the present invention, step S4a, frequency validity verification, is included before step S5; the mean and standard deviation of the frequency values ​​obtained from multiple consecutive time reference windows in step S4 are calculated; when the deviation of a certain calculation result from the mean exceeds the product of the preset anomaly judgment multiple and the standard deviation, the result is determined to be an anomaly and discarded, and the previous valid frequency value is used as the current output; when anomalies are generated in a preset number of consecutive time windows, a frequency detection anomaly alarm is triggered and the matcher control system is notified.

[0022] As a preferred technical solution of the present invention, in step S4, the preset time reference is adaptively adjusted according to the currently detected frequency range: when the radio frequency is lower than the preset low frequency boundary value, the time reference is increased to ensure that enough cycles are accumulated within the time window to improve the low frequency measurement accuracy; when the radio frequency is higher than the preset high frequency boundary value, the time reference is decreased to accelerate the frequency update rate of the high frequency signal; the value of each time reference satisfies the constraint that the minimum cumulative count value of the cycle counter in the corresponding frequency band is not lower than the preset minimum statistical cycle number.

[0023] The present invention also provides a system for a matched circuit to detect the frequency of an input signal, for implementing the above-described method for a matched circuit to detect the frequency of an input signal, the apparatus comprising:

[0024] The sensor unit, located at the input of the RF matching unit, is used to acquire RF input signals;

[0025] An analog-to-digital converter, connected to the sensor unit, is used to convert the radio frequency input signal into a digital sampling signal;

[0026] A dual threshold comparison unit, connected to the analog-to-digital conversion unit, pre-stores positive and negative thresholds that are opposites of each other. When the digital sampling signal rises above the positive threshold, it outputs a high level; when it falls below the negative threshold, it outputs a low level, generating a fitted sine wave synchronization signal with the same frequency as the radio frequency input signal.

[0027] The pulse state judgment unit is connected to the dual threshold comparison unit and is used to monitor the adjacent edge interval of the fitted sine wave synchronization signal. When the adjacent edge interval exceeds the preset maximum period count threshold, it is determined to be a pulse low level state; otherwise, it is determined to be a pulse high level state or a non-pulse continuous sine wave state.

[0028] A dual-counter frequency measurement unit, connected to the pulse state judgment unit, includes a period counter and a time base counter. In a pulse high-level state or a non-pulse continuous sine wave state, the period counter increments by 1 with each rising edge of the fitted sine wave synchronization signal, and the time base counter increments synchronously. When the time base counter reaches the clock counting threshold corresponding to the preset time base, the frequency is calculated based on the cumulative count value of the period counter, the actual cumulative count value of the time base counter, and the system clock frequency, and both counters are synchronously reset to zero. In a pulse low-level state, both counters pause counting.

[0029] The frequency output unit, connected to the dual-counter frequency measurement unit, is used to output the calculated frequency to the matching circuit impedance adjustment control unit as input for LC tuning network parameter calculation.

[0030] As a preferred embodiment of the present invention, it further includes:

[0031] The duty cycle calculation unit, connected to the pulse state judgment unit, includes a pulse high-level cumulative timer and a total cycle timer; the former increments only in the pulse high-level state, while the latter increments continuously in both the pulse high-level and pulse low-level states; when the total cycle timer reaches the preset pulse statistical window time, the pulse duty cycle is calculated based on the ratio of the cumulative values ​​of the two counters, and output to the matching unit control unit as an auxiliary parameter for dynamic adjustment of the impedance matching strategy in pulse mode.

[0032] According to the above-described solution, the beneficial effects of this invention are as follows:

[0033] This invention converts the radio frequency input signal into a digital sampling signal through an analog-to-digital conversion unit. Subsequent double threshold comparison, synchronization signal generation, counting frequency measurement, and frequency calculation are all completed within the digital control unit, realizing fully digital processing of frequency detection. Compared with existing schemes that rely on analog circuits for frequency detection, this invention eliminates the influence of analog device temperature drift, gain error, and noise accumulation on frequency measurement accuracy. The frequency measurement results are stable and repeatable, improving the frequency detection consistency of the RF matching unit under different operating environments.

[0034] This invention presets positive and negative thresholds that are opposites to each other, forming a symmetrical hysteresis decision window for the digital sampling signal. The level of the fitted synchronization signal flips only when the signal amplitude crosses the positive threshold and then crosses the negative threshold in the opposite direction. This mechanism effectively suppresses multiple false triggers of the radio frequency signal near the zero crossing point caused by noise superposition, ensuring the uniqueness and accuracy of the edge of the fitted sine wave synchronization signal, thereby improving the anti-interference capability of frequency detection.

[0035] This invention automatically distinguishes between a low-level pulse state and a valid signal state by monitoring whether the interval between adjacent edges of the fitted sinusoidal synchronization signal exceeds a preset maximum period count threshold, and automatically pauses the period counter and time base counter during the low-level pulse period. This mechanism does not require an external pulse trigger signal or manual mode switching, enabling the invention to be applied to both continuous output and pulse output modes of the RF source. It eliminates the interference of the pulse silence period on the frequency calculation results and ensures that the measured frequency truly reflects the carrier frequency of the RF signal.

[0036] This invention employs a frequency measurement method that accumulates the number of rising edges within a fixed time reference window. The frequency calculation logic is simple, the operation delay is low, and the measured frequency can be output to the LC tuning network parameter calculation module in real time, directly driving the RF matching unit to update the impedance matching strategy. This shortens the system delay from frequency change to impedance response, helps reduce power reflection loss caused by frequency mismatch between the RF source and the load, and improves the overall transmission efficiency of the RF system. Attached Figure Description

[0037] Figure 1 This is a flowchart of the method of the present invention;

[0038] Figure 2 A flowchart illustrating the method for generating a synchronization signal using dual-threshold fitting.

[0039] Figure 3 The flowchart shows the process of pulse state determination and frequency measurement using dual counters.

[0040] Figure 4 This is a system structure diagram of the present invention. Detailed Implementation

[0041] To better understand the purpose, technical solution, and technical effects of this invention, the invention will be further explained and described below in conjunction with the accompanying drawings and embodiments. It should be noted that similar reference numerals and letters in the following drawings indicate similar items; therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. It is also stated that the embodiments described below are only for explaining this invention and are not intended to limit this invention.

[0042] like Figure 1 As shown, this embodiment provides a method for a matching unit to detect the frequency of an input signal, which is executed by a digital control unit integrated within the radio frequency matching unit, and specifically includes the following steps.

[0043] Step S1: Signal Acquisition and Digitization

[0044] The RF matching unit has a sensor at its input, which can be a current transformer or a capacitive voltage divider, used to couple and acquire the RF input signal without interrupting RF power transmission. The acquired RF input signal is an analog quantity. The analog signal is input to an analog-to-digital converter (ADC) directly connected to the digital control unit (DCU). After sampling and quantization by the ADC, a digital sampled signal is output. The amplitude range of the digital sampled signal corresponds to the quantization bit depth of the ADC, and can fully reflect the amplitude variation characteristics of the RF input signal.

[0045] like Figure 2 As shown, step S2: Generation of dual-threshold fitting synchronization signal:

[0046] A positive threshold and a negative threshold are preset within the digital control unit. The two thresholds are opposites of each other, and their absolute values ​​are not greater than the maximum amplitude of the digital sampled signal. The positive threshold is set within a reasonable range of the amplitude of the positive half-cycle of the digital sampled signal, while the negative threshold is symmetrically distributed on both sides of the zero value, together forming a hysteresis decision window symmetrical about the zero value.

[0047] The digital control unit performs real-time, frame-by-frame judgment on the digital sampled signal: when the current value of the digital sampled signal rises from low to high and exceeds a positive threshold, the logic level of the fitted synchronization signal is set to high; when the current value of the digital sampled signal falls from high to low and falls below a negative threshold, the logic level of the fitted synchronization signal is set to low; if the current value of the digital sampled signal is between the positive and negative thresholds, the fitted synchronization signal maintains its current level. This process is repeated cyclically to output a fitted sine wave synchronization signal that is synchronized with the RF input signal.

[0048] The technical significance of this dual-threshold hysteresis structure is that the small fluctuations of the radio frequency signal near the zero crossing point caused by noise superposition are usually insufficient to cross the positive and negative thresholds at the same time. Therefore, they will not trigger the level flip of the fitted synchronization signal, thereby effectively avoiding edge error generation caused by noise interference and ensuring that the fitted sine wave synchronization signal generates only one rising edge and one falling edge in each radio frequency cycle.

[0049] like Figure 3 As shown, step S3: Pulse state determination:

[0050] An edge counter is installed inside the digital control unit. This edge counter continuously counts based on the system clock of the digital control unit and is immediately reset to zero and restarted each time a rising or falling edge of the fitted sine wave synchronization signal is detected. Simultaneously, a maximum cycle count threshold is preset. This maximum cycle count threshold is estimated based on the rated frequency of the detected RF signal and the system clock frequency, and its value is slightly greater than the clock count corresponding to one complete cycle of the RF signal.

[0051] When the current count value of the edge counter exceeds the maximum cycle count threshold, it indicates that no new edge has been detected within a complete RF cycle. The current RF signal is then determined to be in a pulse low-level silent state, triggering the pulse low-level flag. When the edge counter detects a new edge, the pulse low-level flag is reset, and the system resumes normal frequency measurement. If the edge interval never exceeds the maximum cycle count threshold, the current state is determined to be either a pulse high-level state or a non-pulse continuous sine wave state, and the system continues to perform frequency measurement and counting.

[0052] This step enables automatic identification of the radio frequency source's operating mode without the need for external trigger signals, allowing the invention to seamlessly adapt to both continuous radio frequency and pulsed radio frequency operating scenarios.

[0053] Step S4: Frequency measurement using dual counters:

[0054] Two independent counters are enabled within the digital control unit: a period counter and a time base counter. The time base counter is continuously incremented by the system clock and cyclically counts based on a preset clock count threshold corresponding to the time base. The period counter is specifically used to count the number of rising edges of the fitted sine wave synchronization signal, i.e., the number of cycles of the RF input signal.

[0055] In the pulse high-level state or the non-pulse continuous sine wave state, the period counter increments by 1 with each rising edge of the fitted sine wave synchronization signal, and the time base counter increments synchronously. When the count value of the time base counter reaches the clock count threshold corresponding to the preset time base, the cumulative count value N0 of the period counter and the actual cumulative count value N1 of the time base counter are read simultaneously, and the frequency of the RF input signal is calculated according to the following formula: ƒ = N0 × ƒ clk / N1; where ƒ is the calculated frequency, N0 is the cumulative count value of the period counter within the current time base, and ƒ clk N1 is the system clock frequency of the digital control unit, and N2 is the actual cumulative count value of the time base counter. After the calculation is completed, both counters are synchronously cleared to zero and enter the next counting cycle, realizing continuous real-time frequency measurement.

[0056] When the pulse is low, both counters pause counting, maintaining their current values ​​until the pulse low-level flag is reset and the counting resumes. This mechanism ensures that the rising edge statistics and time reference data used for frequency calculation are derived only from the effective time periods when the radio frequency signal actually exists, eliminating interference from the pulse silence period on the frequency measurement results.

[0057] Taking specific parameters as an example: if the system clock frequency ƒ clkThe preset time base is 100 MHz, corresponding to 1 ms, meaning the clock count threshold of the time base counter is set to 100,000. When the RF input signal frequency is 13.56 MHz, in non-pulse continuous sine wave mode, the calculation is triggered when the time base counter accumulates to 100,000. At this time, the accumulated value N0 of the period counter is approximately 13560, and the actual accumulated count value N1 of the time base counter is 100,000. The frequency is calculated from this. In pulse mode, because the two counters pause counting when the pulse is low and resume counting after the pulse is high, the actual accumulated count value of the time base counter when it reaches the threshold may deviate slightly from the threshold due to the randomness of the pulse high-low level switching time. For example, if the time base counter actually accumulates to 99987 within a certain effective counting period and triggers the calculation, and the accumulated value N0 of the period counter is 13558, then the calculated frequency... This result accurately reflects the actual carrier frequency within the effective counting period, eliminating the frequency measurement error caused by the quantization truncation between the preset constant and the actual effective timing.

[0058] Step S5: Frequency Output and Application

[0059] In step S4, after each frequency calculation, the obtained frequency value is transmitted in real time to the LC tuning network parameter calculation module as the core input variable for tuning the adjustable inductor and capacitor parameters of the matching network. Based on the current frequency value, the LC tuning network parameter calculation module calculates the required inductance and capacitance according to the impedance matching algorithm, and drives the corresponding stepper motor or relay to adjust the LC tuning network. This ensures that the input impedance of the RF matching circuit is matched with the standard output impedance of the RF power supply (usually 50Ω) in real time, reducing power reflection loss and improving RF power transmission efficiency.

[0060] Since the frequency calculation is completed inside the digital control unit and then directly transmitted to the LC tuning network parameter calculation module via the internal parallel bus, without the need for an external communication interface, the total delay from the occurrence of frequency change to the output of impedance adjustment command does not exceed one time reference window (typically 1 ms), which meets the requirements of industrial RF systems for the response speed of the matching unit.

[0061] In a preferred embodiment, considering that the output power ranges of different RF power supplies vary in practical engineering applications, the amplitude range of the digital sampling signal also differs. If the positive and negative thresholds are fixed preset values, when the actual signal amplitude deviates significantly from the preset values, problems may arise such as the threshold being too high, causing the synchronization signal to fail to flip normally, or the threshold being too low, resulting in insufficient noise suppression. To solve the above problems, this preferred embodiment adopts an adaptive tuning method. Specifically, during the power-on initialization phase of the RF matching unit, the digital control unit continuously monitors the amplitude of the digital sampling signal for several sampling cycles and records the maximum detected amplitude as the peak amplitude. After initialization, the positive and negative thresholds are automatically calculated using the following formula: V th+ =α× V peak V th- = -α× V peak , where V th+ As a positive threshold, V th- For a negative threshold, V peak The peak amplitude of the digital sampling signal detected during the initialization phase is α, which is a preset scaling factor and satisfies 0 < α < 1.

[0062] The typical range of the proportionality coefficient α is 0.3 to 0.7. When α is smaller, the threshold window is narrower, resulting in a more sensitive response to low-amplitude signals, but noise suppression capability is relatively reduced. When α is larger, the threshold window is wider, resulting in better noise suppression, but requiring higher tolerance for signal amplitude fluctuations. In practical applications, an appropriate α value can be selected based on the signal-to-noise ratio characteristics of the RF system, balancing response sensitivity and anti-interference capability. Through adaptive tuning, the positive and negative thresholds always maintain a reasonable proportional relationship with the actual signal amplitude, effectively adapting to application scenarios with different RF power supply power levels.

[0063] In a preferred embodiment, the digital control unit includes an edge counter that continuously increments driven by the system clock. Each time a rising or falling edge of the fitted sine wave synchronization signal is detected, the edge counter is immediately reset to zero and starts counting again from zero. The maximum period count threshold K is determined by the following formula: K = β × (ƒ clk / ƒ0); where K is the maximum period count threshold, ƒ clk ƒ represents the clock frequency of the digital control unit, ƒ0 represents the rated frequency of the detected radio frequency signal, and β represents a safety margin factor greater than 1. clk / ƒ0 represents the number of system clock counts within one complete cycle of the RF signal. Taking a 13.56 MHz RF signal and a 100 MHz system clock as an example, ƒ clk / ƒ0≈7.4, meaning that each half-cycle of the RF signal (rising edge to falling edge, or falling edge to rising edge) corresponds to approximately 3 to 4 clock counts. The typical value of the safety margin factor β is 1.5 to 3.0, which is used to accommodate normal fluctuations in the RF signal frequency near the rated value and avoid misinterpreting slight frequency deviations as pulse low-level states.

[0064] When the current value of the edge counter exceeds K, the trigger pulse low-level flag is set, and the system determines that it has entered the pulse low-level silence phase. When the next edge arrives, the pulse low-level flag is immediately reset, the edge counter is cleared to zero and starts counting again, and the system resumes normal frequency measurement. This mechanism can accurately distinguish between the pulse silence phase and the normal RF signal transmission phase, ensuring the validity of the frequency measurement data.

[0065] In a preferred embodiment, step S41 is added during the execution of step S4 to simultaneously complete the pulse duty cycle calculation.

[0066] While performing frequency measurement using dual counters, the digital control unit also sets up two additional timers: a pulse high-level accumulator timer and a total cycle timer. The pulse high-level accumulator timer increments with the system clock only when the pulse low-level flag is not set, i.e., when it is in a pulse high-level state or a non-pulse continuous sine wave state; the total cycle timer continuously increments with the system clock regardless of its current state, and is unaffected by the pulse state.

[0067] When the total cycle timer reaches the preset pulse statistics window time, the pulse duty cycle is calculated using the following formula: D=(T H / T P ) ×100%; where D is the pulse duty cycle, T H T is the cumulative value of the pulse high-level accumulator timer within the pulse statistics window. P This is the cumulative value of the total cycle timer corresponding to the preset pulse statistical window time. After calculation, both timers are synchronously reset to zero, and the next statistical window begins. The obtained pulse duty cycle D is output to the matching unit control unit as an auxiliary parameter for dynamic adjustment of the impedance matching strategy in pulse mode. For example, in a pulse RF system, the matching unit control unit can predict the arrival time of the pulse high level based on the duty cycle information, complete the impedance pre-adjustment in advance, further shorten the impedance mismatch time at the pulse high level establishment time, and improve the overall matching response speed.

[0068] In a preferred embodiment, step S4a is added between steps S4 and S5 to verify the validity of the frequency calculation results, thereby further improving the reliability of the frequency output. During the continuous operation of step S4, after each time reference window frequency calculation is completed, the obtained frequency value is stored in a first-in-first-out buffer. When the buffer accumulates frequency values ​​from multiple consecutive time reference windows, the arithmetic mean and standard deviation of all frequency values ​​in the buffer are calculated.

[0069] When the deviation of the newly calculated frequency value from the mean exceeds the product of the preset anomaly judgment multiple and the standard deviation, the calculation result is judged as an anomaly and discarded. The most recent valid frequency value in the buffer is used as the current frequency output to prevent abnormal calculation results caused by transient interference from being transmitted to the impedance adjustment control unit. When anomalies are generated in the buffer for a consecutive preset number of time windows, it indicates that the system may have entered a frequency change or signal abnormality state, triggering a frequency detection anomaly alarm and notifying the matching unit control system. The control system then decides on the subsequent processing strategy, such as pausing impedance adjustment or switching to a safe mode.

[0070] In a preferred embodiment, considering that in some industrial RF systems, the RF power supply may simultaneously output a fundamental frequency and a harmonic signal (e.g., a 13.56 MHz fundamental frequency and a 27.12 MHz harmonic), or multiple RF power supplies may jointly drive the same plasma chamber, the RF input signal is a superposition of multiple frequency components. For such multi-frequency superposition scenarios, a single set of dual-threshold comparison units can only extract the synchronization signal of one frequency component, and cannot simultaneously complete the parallel detection of multiple frequency components.

[0071] Therefore, this preferred embodiment configures a dual-threshold comparison unit inside the digital control unit. The dual-threshold comparison unit presets positive and negative thresholds for the amplitude characteristics of different frequency components. The dual-threshold comparison unit independently performs real-time judgment on the digitally sampled signal and generates a fitting synchronization signal for the corresponding frequency component. For example, for a superimposed signal of two frequency components, 13.56 MHz and 27.12 MHz, the first set of dual-threshold comparison units sets the threshold based on the amplitude characteristics of the 13.56 MHz component, and the second set sets the threshold based on the amplitude characteristics of the 27.12 MHz component. Each set independently outputs a fitted sine wave synchronization signal for the corresponding frequency component. Then, in step S4, each corresponding independent period counter and time base counter completes the frequency measurement of each frequency component, realizing parallel detection and separate output of each frequency component in the multi-frequency superimposed radio frequency signal.

[0072] Furthermore, the digital control unit is specifically implemented using a field-programmable gate array (FPGA) integrated on the printed circuit board of the RF matching unit. The analog-to-digital converter (ADC) unit in step S1 is a high-speed ADC chip directly connected to the FPGA. Its sampling frequency is no less than 10 times the highest frequency of the detected RF signal to satisfy the Nyquist sampling theorem and provide sufficient sampling margin, ensuring that the digital sampled signal can accurately reproduce the amplitude waveform characteristics of the RF input signal. All logic operations, counter operations, and frequency calculations in steps S2 to S5 are implemented in hardware parallelism within the internal logic resources of the FPGA. This includes the independent operation of each set of dual-threshold comparison units, the synchronous incrementing of independent counter sets corresponding to each frequency component, and the real-time transmission of frequency calculation results to the LC tuning network parameter calculation module, without the need for an external processor. This fully hardware parallel implementation allows the detection calculation of each frequency component to be completed synchronously within the same clock cycle, avoiding timing differences introduced by sequential processing of multiple frequency components and ensuring the time consistency of multi-frequency parallel detection results.

[0073] In a preferred embodiment, considering the limitations of fixed time references when applied over a wide frequency range: for low-frequency signals, only a small number of rising edge counts may accumulate within a fixed time reference, resulting in insufficient frequency resolution; for high-frequency signals, if the time reference is too long, the frequency update delay increases, and it cannot reflect frequency changes in a timely manner.

[0074] Therefore, this preferred embodiment adaptively adjusts the preset time base according to the currently detected frequency range: when the current frequency is lower than the preset low-frequency boundary value, the time base is increased to accumulate a sufficient number of cycles within the time window, improving low-frequency measurement resolution; when the current frequency is higher than the preset high-frequency boundary value, the time base is decreased to accelerate the frequency output update rate and improve the real-time performance of frequency measurement in high-frequency scenarios. The time base values ​​for each level meet the constraint condition: the minimum cumulative count value of the cycle counter within the corresponding frequency band is not lower than the preset minimum number of statistical cycles, ensuring that the statistical results of any level have sufficient reliability in a statistical sense. The time base adjustment is performed after each frequency calculation is completed. The time base is determined and switched to the corresponding level in real time based on the latest frequency value. The entire switching process is completed when the current counting cycle is reset to zero, without affecting the smoothness of continuous frequency measurement.

[0075] like Figure 4 As shown, the present invention also provides a system for detecting the frequency of an input signal by a matching unit, and a method for detecting the frequency of an input signal by a matching unit to implement the above-mentioned scheme. The device includes a sensor unit, an analog-to-digital conversion unit and a sensor unit, a dual threshold comparison unit, a pulse state judgment unit, a dual counter frequency measurement unit and a frequency output unit, all of which are integrated inside the RF matching unit body.

[0076] The sensor unit is located at the input of the RF matching unit, and can be a current transformer or a capacitive voltage divider. It acquires the RF input signal via electromagnetic coupling or capacitive coupling without interrupting the RF power transmission path. The analog-to-digital converter (ADC) is directly electrically connected to the sensor unit, receiving the RF analog signal output from the sensor unit, and outputting a digital sampled signal after sampling and quantization for use by the subsequent digital processing unit. The dual threshold comparison unit is connected to the ADC and internally stores positive and negative thresholds that are opposites of each other.

[0077] The dual-threshold comparison unit compares the amplitude of the digital sampled signal frame by frame: when the digital sampled signal rises above the positive threshold, it outputs a high level; when the digital sampled signal falls below the negative threshold, it outputs a low level; when the signal is between the two thresholds, the output level remains unchanged. This output logic forms a fitted sine wave synchronization signal with the same frequency as the RF input signal. The symmetrical distribution of the dual thresholds constitutes a hysteresis decision window, effectively suppressing multiple false flips caused by zero-crossing noise.

[0078] The pulse state judgment unit is connected to the dual threshold comparison unit to monitor the interval between adjacent edges of the fitted sine wave synchronization signal in real time. When the interval between adjacent edges exceeds the preset maximum period count threshold, it is determined that the current state is a pulse low level, and a pulse low level flag is output; otherwise, it is determined to be a pulse high level or a non-pulse continuous sine wave state, and a valid signal flag is output. This unit realizes the automatic determination of the RF source's operating mode and provides state control input for the subsequent dual counter frequency measurement unit.

[0079] The dual-counter frequency measurement unit is connected to the pulse state judgment unit and includes two independent counters: a period counter and a time base counter. Under valid signal conditions, the period counter increments by 1 with each rising edge of the fitted sine wave synchronization signal, while the time base counter increments synchronously with the system clock. When the time base counter reaches the clock counting threshold corresponding to the preset time base, both the accumulated count value of the period counter and the actual accumulated count value of the time base counter are read simultaneously. The current frequency is calculated by combining this with the system clock frequency, and both counters are then synchronously reset to zero to enter the next counting cycle. Under low pulse conditions, both counters pause counting until the state recovers, ensuring that frequency calculations are based only on periods when the radio frequency signal is validly present.

[0080] The frequency output unit is connected to the dual-counter frequency measurement unit, and transmits the frequency value obtained from each calculation to the impedance adjustment control unit of the matching unit in real time via the internal parallel bus. This serves as the input for calculating the LC tuning network parameters and drives the RF matching unit to update the impedance matching strategy in real time.

[0081] All of the above functional units are implemented in hardware logic within the field-programmable gate array (FPGA). The units operate in parallel and together form a complete closed-loop digital detection system from signal acquisition to frequency output.

[0082] In a preferred embodiment, a duty cycle calculation unit is added to the device to support synchronous detection of the duty cycle under pulsed RF conditions. Specifically, the duty cycle calculation unit is connected to the pulse state judgment unit and contains two independent timers: a pulse high-level cumulative timer and a total cycle timer. The pulse high-level cumulative timer increments with the system clock only when the pulse state judgment unit outputs a valid signal flag; the total cycle timer continuously increments with the system clock regardless of its current state. When the total cycle timer reaches a preset pulse statistical window time, the pulse duty cycle is calculated based on the ratio of the cumulative values ​​of the two counters, and the calculation result is output to the matching unit control unit as an auxiliary parameter for dynamic adjustment of the impedance matching strategy in pulse mode. Subsequently, both timers are synchronously cleared to enter the next statistical window. The duty cycle calculation unit and the dual-counter frequency measurement unit share the output signal of the pulse state judgment unit. They operate in parallel within the field-programmable gate array without interfering with each other, realizing synchronous real-time detection of frequency and duty cycle. This provides the matching unit control unit with a more complete RF signal characteristic description and supports a more refined pulse mode impedance matching strategy.

[0083] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0084] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for detecting the frequency of an input signal using a matched converter, characterized in that, Performed by a digital control unit integrated within the RF matching unit, the steps include: Step S1: Acquire the radio frequency input signal and convert the radio frequency input signal into a digital sampling signal; Step S2: Preset positive and negative thresholds that are opposites of each other. When the digital sampling signal rises above the positive threshold, the level of the fitting synchronization signal is set high; when the digital sampling signal falls below the negative threshold, the level of the fitting synchronization signal is set low. This process is repeated to generate a fitting sine wave synchronization signal with the same frequency as the RF input signal. Step S3: Preset the maximum period count threshold and monitor the adjacent edge interval of the fitted sine wave synchronization signal in real time; when the adjacent edge interval exceeds the maximum period count threshold, it is determined that the current state is a pulse low level; otherwise, it is determined to be a pulse high level state or a non-pulse continuous sine wave state. Step S4: Enable the period counter and time base counter; in the pulse high-level state or non-pulse continuous sine wave state, the period counter increments by 1 with each rising edge of the fitted sine wave synchronization signal, and the time base counter increments synchronously; when the time base counter reaches the clock counting threshold corresponding to the preset time base, the frequency is calculated based on the cumulative count value of the period counter, the actual cumulative count value of the time base counter, and the system clock frequency of the digital control unit, and both counters are reset to zero synchronously; in the pulse low-level state, both counters stop counting; Step S5: Output the frequency to the matching circuit impedance adjustment control unit.

2. The method for detecting the frequency of an input signal using a matched circuit according to claim 1, characterized in that, In step S2, the positive and negative thresholds are automatically adjusted based on the peak amplitude detection results of the digital sampling signal during the initialization phase, and are determined by the following formula: V th+ =α× V peak V th- = -α× V peak , where V th+ As a positive threshold, V th- For a negative threshold, V peak The peak amplitude of the digital sampling signal detected during the initialization phase is α, which is a preset scaling factor and satisfies 0 < α < 1.

3. The method for detecting the frequency of an input signal using a matched converter according to claim 1, characterized in that, In step S3, the digital control unit is equipped with an edge counter, which is immediately cleared and recounted each time the rising or falling edge of the fitted sine wave synchronization signal is detected. When the count value exceeds the maximum period count threshold, a low-level trigger flag is set; when the next edge arrives, the flag is reset, and the normal frequency measurement process resumes; the maximum period count threshold is determined by the following formula: K = β × (ƒ clk / ƒ0); Where K is the maximum period count threshold, ƒ clk ƒ0 is the clock frequency of the digital control unit, ƒ0 is the rated frequency of the detected radio frequency signal, and β is a safety margin factor greater than 1.

4. The method for detecting the frequency of an input signal using a matched converter according to claim 1, characterized in that, In step 4, the frequency is calculated using the following formula: ƒ = N0 × ƒ clk / N1; where ƒ is the calculated frequency, N0 is the cumulative count value of the period counter within the current time base, and ƒ clk N1 is the system clock frequency of the digital control unit, and N2 is the actual cumulative count value of the time base counter.

5. The method for detecting the frequency of an input signal using a matched circuit according to any one of claims 1 to 3, characterized in that, It also includes step S41, pulse duty cycle calculation; During step S4, the digital control unit is equipped with a pulse high-level cumulative timer and a total cycle timer. The pulse high-level cumulative timer increments only during the pulse high-level state, while the total cycle timer increments continuously during both the pulse high-level and pulse low-level states. When the total cycle timer reaches the preset pulse statistics window time, the pulse duty cycle is calculated using the following formula: D = (T H / T P ) ×100%; where D is the pulse duty cycle, T H T is the cumulative value of the pulse high-level accumulator timer within the pulse statistics window. P This is the total cycle timer cumulative value corresponding to the preset pulse statistics window time; The pulse duty cycle is output to the matching unit control unit as an auxiliary parameter for dynamic adjustment of the impedance matching strategy in pulse mode.

6. The method for detecting the frequency of an input signal using a matched converter according to claim 1, characterized in that, In step S2, the digital control unit is equipped with a dual threshold comparison unit, which is configured with a positive threshold and a negative threshold, respectively corresponding to the amplitude characteristics of different frequency components in the radio frequency system to be detected; in step S4, each frequency component corresponds to an independent period counter and a time reference counter, which synchronously complete the frequency measurement of each frequency component, thereby realizing the parallel detection and separation output of each frequency component of the multi-frequency superimposed radio frequency signal.

7. The method for detecting the frequency of an input signal using a matched circuit according to claim 1, characterized in that, Before step S5, there are also steps S4a and frequency validity verification; the mean and standard deviation of the frequency values ​​obtained from multiple consecutive time reference windows in step S4 are calculated; when the deviation of a certain calculation result from the mean exceeds the product of the preset anomaly judgment multiple and the standard deviation, the result is judged as an anomaly and discarded, and the previous valid frequency value is used as the current output; when anomalies are generated in a preset number of consecutive time windows, a frequency detection anomaly alarm is triggered and the matcher control system is notified.

8. The method for detecting the frequency of an input signal using a matched circuit according to claim 1, characterized in that, In step S4, the preset time reference is adaptively adjusted according to the currently detected frequency range: when the radio frequency is lower than the preset low frequency threshold, the time reference is increased; When the radio frequency is higher than the preset high-frequency threshold, the time base is reduced; the value of each time base satisfies the constraint that the minimum cumulative count value of the period counter in the corresponding frequency band is not lower than the preset minimum number of statistical cycles.

9. A system for detecting the frequency of an input signal using a matched converter, characterized in that, For implementing the method of a matched circuit for detecting the frequency of an input signal as described in any one of claims 1 to 8, the apparatus comprises: The sensor unit, located at the input of the RF matching unit, is used to acquire RF input signals; An analog-to-digital converter, connected to the sensor unit, is used to convert the radio frequency input signal into a digital sampling signal; A dual threshold comparison unit, connected to the analog-to-digital conversion unit, pre-stores positive and negative thresholds that are opposites of each other. When the digital sampling signal rises above the positive threshold, it outputs a high level; when it falls below the negative threshold, it outputs a low level, generating a fitted sine wave synchronization signal with the same frequency as the radio frequency input signal. The pulse state judgment unit is connected to the dual threshold comparison unit and is used to monitor the adjacent edge interval of the fitted sine wave synchronization signal. When the adjacent edge interval exceeds the preset maximum period count threshold, it is determined to be a pulse low level state; otherwise, it is determined to be a pulse high level state or a non-pulse continuous sine wave state. A dual-counter frequency measurement unit, connected to the pulse state judgment unit, includes a period counter and a time base counter. In a pulse high-level state or a non-pulse continuous sine wave state, the period counter increments by 1 with each rising edge of the fitted sine wave synchronization signal, and the time base counter increments synchronously. When the time base counter reaches the clock counting threshold corresponding to the preset time base, the frequency is calculated based on the cumulative count value of the period counter, the actual cumulative count value of the time base counter, and the system clock frequency, and both counters are synchronously reset to zero. In a pulse low-level state, both counters pause counting. The frequency output unit, connected to the dual-counter frequency measurement unit, is used to output the calculated frequency to the matching circuit impedance adjustment control unit as input for LC tuning network parameter calculation.

10. The system for detecting the frequency of an input signal using a matched converter according to claim 9, characterized in that, Also includes: The duty cycle calculation unit is connected to the pulse state judgment unit and includes a pulse high-level cumulative timer and a total cycle timer. The former increases only when the pulse is high, while the latter increases continuously in both high and low pulse states. When the total cycle timer reaches the preset pulse statistics window time, the pulse duty cycle is calculated based on the ratio of the cumulative values ​​of the two counters and output to the matching unit control unit as an auxiliary parameter for dynamic adjustment of the impedance matching strategy in pulse mode.

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