Duty cycle detection circuit and memory
Patent Information
- Application Number
- CN202510365843.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-25
- Publication Date
- 2026-10-09
AI Technical Summary
[0003]然而，相关技术中的时钟占空比检测电路，通常是使用不同器件分别对时钟高电平和低电平进行控制检测，极其容易因为器件参数漂移或失配等影响占空比检测结果的准确性
[0015]本申请一些实施例中提供的占空比检测电路包括信号处理模块、电荷泵、计数模块和控制模块。其中，信号处理模块被配置为接收待测时钟信号，并基于待测时钟信号输出第一时钟信号和待测时钟信号；其中，第一时钟信号为待测时钟信号的反相信号；电荷泵被配置为接收第一时钟信号，并在第一时钟信号的第一时间长度内输出第一电压信号，以及接收待测时钟信号，并在待测时钟信号的第二时间长度内输出第二电压信号；其中，第一时钟信号和第一时间长度和待测时钟信号的第二时间长度至少构成一个时钟信号周期；计数模块被配置为接收第一电压信号，并基于第一电压信号计数，输出第一计数值，以及接收第二电压信号，并基于第二电压信号计数，输出第二计数值；控制模块用于接收第一计数值和第二计数值，并基于第一计数值和第二计数值计算待测时钟信号的占空比。在对待测时钟信号进行占空比检测过程中，使用相同的器件(即电荷泵、计数模块和控制模块)对待测时钟信号以及与其反相的第一时钟信号进行占空比检测，可以避免使用不同电荷泵、计数模块和/或控制模块进行占空比检测时出现的器件漂移或失配现象，避免影响占空比检测结果，进而提高检测精度。
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Figure CN122882824A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to duty cycle detection circuits and memories. Background Technology
[0002] With the development of electronic technology, clocks are crucial for synchronizing the various modules within high-speed electronic devices and coordinating their actions. Therefore, clock signals can be monitored to correct errors. One method to determine if a clock signal error has occurred is by analyzing the clock duty cycle.
[0003] However, the clock duty cycle detection circuits in related technologies typically use different devices to control and detect the high and low levels of the clock separately, which is extremely easy to affect the accuracy of the duty cycle detection results due to device parameter drift or mismatch. Summary of the Invention
[0004] This application provides a duty cycle detection circuit and a memory. Based on the clock signal under test, a first clock signal inversely to it is obtained. Then, the same charge pump, counting module and control module are used to detect the duty cycle of the clock signal under test and the first clock signal. This can avoid the device drift or mismatch that occurs when using different charge pumps, counting modules and / or control modules for duty cycle detection, thus avoiding affecting the duty cycle detection results and improving detection accuracy.
[0005] To address the aforementioned technical problems, this application provides a duty cycle detection circuit, comprising a signal processing module, a charge pump, a counting module, and a control module. The signal processing module is configured to receive a clock signal to be tested and output a first clock signal and a clock signal to be tested based on the clock signal to be tested; wherein the first clock signal is the inverted signal of the clock signal to be tested; the charge pump is configured to receive the first clock signal and output a first voltage signal within a first time length of the first clock signal, and to receive the clock signal to be tested and output a second voltage signal within a second time length of the clock signal to be tested; wherein the first clock signal and the first time length and the second time length of the clock signal to be tested constitute at least one clock signal cycle; the counting module is configured to receive the first voltage signal and count based on the first voltage signal to output a first count value, and to receive the second voltage signal and count based on the second voltage signal to output a second count value; the control module is configured to receive the first count value and the second count value, and calculate the duty cycle of the clock signal to be tested based on the first count value and the second count value.
[0006] In some embodiments, the counting module includes a comparator, an AND gate, and a counter. The inverting input of the comparator is coupled to the output of a charge pump and receives a first voltage signal and a second voltage signal, respectively. The non-inverting input of the comparator is coupled to a reference voltage terminal. The comparator outputs a third voltage signal based on the first voltage signal and a fourth voltage signal based on the second voltage signal. The first input of the AND gate is coupled to the output of the comparator, and the second input of the AND gate receives an enable signal. The AND gate outputs a fifth voltage signal during the high levels of the third voltage signal and the enable signal, and outputs a sixth voltage signal during the high levels of the fourth voltage signal and the enable signal. The enable terminal of the counter is coupled to the output of the AND gate, receives the fifth voltage signal, counts based on the fifth voltage signal, and outputs a first count value; and receives the sixth voltage signal, counts based on the sixth voltage signal, and outputs a second count value.
[0007] In some embodiments, after receiving the first count value, the control module sends a reset signal to the counter and the charge pump; the counter and the charge pump perform a reset operation based on the reset signal.
[0008] In some embodiments, the charge pump includes a switching circuit and a charging / discharging circuit. The control terminal of the switching circuit is coupled to the output terminal of the signal processing module; the first terminal of the charging / discharging circuit is coupled to the switching circuit, and the second terminal of the charging / discharging circuit is grounded. The control terminal of the charging / discharging circuit receives a reset signal. The coupling point between the charging / discharging circuit and the switching circuit serves as the output terminal of the charge pump. The switching circuit charges the charging / discharging circuit during a low level of a first clock signal and outputs a first voltage signal during the charging cycle. The switching circuit also charges the charging / discharging circuit during a low level of a clock signal under test and outputs a second voltage signal during the charging cycle. Before the switching circuit receives the clock signal under test, the charging / discharging circuit has completed the discharging operation according to the reset signal.
[0009] In some embodiments, the switching circuit includes a current source and a first switching device. A first terminal of the first switching device is coupled to the output terminal of the current source, a second terminal of the first switching device is coupled to a charging / discharging circuit, and a control terminal of the first switching device is coupled to the output terminal of a signal processing module. The first switching device is turned on during a low level of a first clock signal, charging the charging / discharging circuit through the current source and outputting a first voltage signal during the charging cycle. The first switching device is turned on during a low level of the clock signal to be measured, charging the charging / discharging circuit through the current source and outputting a second voltage signal during the charging cycle. Before the first switching device receives the clock signal to be measured, the charging / discharging circuit has completed a discharge operation based on a reset signal.
[0010] In some embodiments, the charging and discharging circuit includes a capacitor and a second switching device. The first plate of the capacitor is coupled to the switching circuit, and the second plate of the capacitor is grounded. The first terminal of the second switching device is coupled to the first plate of the capacitor, and the second terminal of the second switching device is grounded. The control terminal of the second switching device is used to receive a reset signal. During the low level of the first clock signal, the switching circuit charges the capacitor and outputs a first voltage signal during the charging cycle, while the second switching device is in a cutoff state. During the low level of the clock signal to be measured, the switching circuit charges the capacitor and outputs a second voltage signal during the charging cycle, while the second switching device is in a cutoff state. Before the switching circuit receives the clock signal to be measured, the second switching device is turned on according to the reset signal to complete the discharging operation of the capacitor.
[0011] In some embodiments, the signal processing module includes a first processing unit and a second processing unit. The first processing unit receives a clock signal to be tested and outputs a first clock signal based on the clock signal to be tested; the second processing unit receives the clock signal to be tested and outputs the clock signal to be tested.
[0012] In some embodiments, the first processing unit includes an inverter and a third switching device. When the third switching device is turned on, the inverter inverts the clock signal to be tested and outputs a first clock signal.
[0013] In some embodiments, the control module obtains the duty cycle of the clock signal under test by dividing the second count value by the sum of the first count value and the second count value; wherein the first count value is inversely proportional to the high level time of the clock signal under test, and the second count value is inversely proportional to the low level time of the clock signal under test.
[0014] In order to solve the above-mentioned technical problems, this application provides another aspect of a memory, which includes the detection circuit described above.
[0015] The duty cycle detection circuit provided in some embodiments of this application includes a signal processing module, a charge pump, a counting module, and a control module. The signal processing module is configured to receive a clock signal to be tested and output a first clock signal and a clock signal to be tested based on the clock signal to be tested; wherein the first clock signal is an inverted signal of the clock signal to be tested; the charge pump is configured to receive the first clock signal and output a first voltage signal within a first time length of the first clock signal, and to receive the clock signal to be tested and output a second voltage signal within a second time length of the clock signal to be tested; wherein the first clock signal and the first time length and the second time length of the clock signal to be tested constitute at least one clock signal cycle; the counting module is configured to receive the first voltage signal, count based on the first voltage signal, and output a first count value, and to receive the second voltage signal, count based on the second voltage signal, and output a second count value; the control module is used to receive the first count value and the second count value, and calculate the duty cycle of the clock signal to be tested based on the first count value and the second count value. In the process of duty cycle detection of the clock signal under test, using the same devices (i.e., charge pump, counting module and control module) to perform duty cycle detection on the clock signal under test and the first clock signal that is opposite to it can avoid device drift or mismatch when using different charge pumps, counting modules and / or control modules for duty cycle detection, thus avoiding affecting the duty cycle detection results and improving detection accuracy. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:
[0017] Figure 1 This is a schematic diagram of the duty cycle detection circuit provided in some embodiments of this application;
[0018] Figure 2 This is a schematic diagram of the structure of the counting module provided in some embodiments of this application;
[0019] Figure 3 This is a schematic diagram of the charge pump provided in some embodiments of this application;
[0020] Figure 4 This is a schematic diagram of the switching circuit provided in some embodiments of this application;
[0021] Figure 5 This is a schematic diagram of the charging and discharging circuit provided in some embodiments of this application;
[0022] Figure 6This is a schematic diagram of the structure of the signal processing module provided in some embodiments of this application;
[0023] Figure 7 This is a schematic diagram of the structure of the signal processing module provided in some embodiments of this application;
[0024] Figure 8 This is a schematic diagram of the duty cycle detection circuit provided in some embodiments of this application;
[0025] Figure 9 yes Figure 8 The timing diagram of the duty cycle detection circuit shown is shown.
[0026] Figure 10 This is a schematic diagram of the memory structure provided in some embodiments of this application. Detailed Implementation
[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0028] See Figure 1 , Figure 1 This is a schematic diagram of the duty cycle detection circuit provided in some embodiments of this application. The duty cycle detection circuit 10 includes a signal processing module 101, a charge pump 102, a counting module 103, and a control module 104.
[0029] The signal processing module 101 is configured to receive the clock signal under test and output a first clock signal and the clock signal under test based on the clock signal under test. The first clock signal is the inverted signal of the clock signal under test. That is, the signal processing module 101 can output the first clock signal and the clock signal under test respectively as needed.
[0030] The charge pump 102 receives a first clock signal and outputs a first voltage signal within a first time length of the first clock signal.
[0031] The charge pump 102 receives the clock signal to be tested and outputs a second voltage signal within a second time length of the clock signal to be tested; wherein the first time length of the first clock signal and the second time length of the clock signal to be tested constitute at least one clock signal cycle.
[0032] The counting module 103 receives a first voltage signal, counts based on the first voltage signal, and outputs a first count value; it also receives a second voltage signal, counts based on the second voltage signal, and outputs a second count value.
[0033] In some embodiments, the first time length and the second time length can be determined based on the corresponding reference voltage value in the counting module 103. The first time length ends when the first voltage signal is greater than the reference voltage value. The second time length ends when the second voltage signal is greater than the reference voltage value.
[0034] In some embodiments, the first time length is related to the low level of the first clock signal. Since the first clock signal is the inverted signal of the clock signal under test, the first time length is related to the high level of the clock signal under test. The second time length is related to the low level of the clock signal under test. Based on this, the first count value is related to the high level of the clock signal under test, and the second count value is related to the low level of the clock signal under test.
[0035] In other embodiments, the first time length is related to the high level of the first clock signal. Since the first clock signal is the inverted signal of the clock signal under test, the first time length is related to the low level of the clock signal under test. The second time length is related to the high level of the clock signal under test. Based on this, the first count value is related to the low level of the clock signal under test, and the second count value is related to the high level of the clock signal under test.
[0036] The control module 104 receives the first count value and the second count value, and calculates the duty cycle of the clock signal under test based on the first count value and the second count value.
[0037] In some embodiments, the first count value is related to the high level of the clock signal under test, and the second count value is related to the low level of the clock signal under test. In one application scenario, the first count value is inversely proportional to the high level of the clock signal under test, and the second count value is inversely proportional to the low level of the clock signal under test. In another application scenario, the first count value is directly proportional to the high level of the clock signal under test, and the second count value is directly proportional to the low level of the clock signal under test.
[0038] In some embodiments, the first count value is related to a low level of the clock signal under test, and the second count value is related to a high level of the clock signal under test. In one application scenario, the first count value is inversely proportional to a low level of the clock signal under test, and the second count value is inversely proportional to a high level of the clock signal under test. In another application scenario, the first count value is directly proportional to a low level of the clock signal under test, and the second count value is directly proportional to a high level of the clock signal under test.
[0039] In some embodiments, the ratio between the first time length and the second time length can be determined according to the actual situation.
[0040] In some embodiments of this application, the duty cycle detection circuit 10 uses the same devices (i.e., charge pump 102, counting module 103, and control module 104) to detect the duty cycle of the clock signal under test and its inverse first clock signal. This avoids device drift or mismatch that occurs when different charge pumps 102, counting modules 103, and / or control modules 104 are used for duty cycle detection, thus avoiding affecting the duty cycle detection results and improving detection accuracy.
[0041] In some embodiments, such as Figure 2 As shown, Figure 2 This is a schematic diagram of the structure of a counting module provided in some embodiments of this application. The counting module 103 includes a comparator 1031, an AND gate 1032, and a counter 1033.
[0042] In this configuration, the inverting input of comparator 1031 is coupled to the output of charge pump 102, and receives a first voltage signal and a second voltage signal respectively. The non-inverting input of comparator 1031 is coupled to a reference voltage terminal. Comparator 1031 outputs a third voltage signal based on the first voltage signal and a fourth voltage signal based on the second voltage signal. In some embodiments, the second voltage signal is generated after the first voltage signal has finished.
[0043] The first input terminal of AND gate 1032 is coupled to the output terminal of comparator 1031, and the second input terminal of AND gate 1032 receives an enable signal; wherein, AND gate 1032 outputs a fifth voltage signal during the high level of the third voltage signal and the enable signal, and AND gate 1032 outputs a sixth voltage signal during the high level of the fourth voltage signal and the enable signal.
[0044] The enable terminal of counter 1033 is coupled to the output terminal of AND gate 1032. Counter 1033 receives a fifth voltage signal and counts based on the fifth voltage signal to output a first count value; and counter 1033 receives a sixth voltage signal and counts based on the sixth voltage signal to output a second count value.
[0045] For example, the inverting input of comparator 1031 ( Figure 2 (Used as a "-") for receiving the first voltage signal or the second voltage signal. Figure 2 In this text, "VC1" represents the first voltage signal and the second voltage signal, and the non-inverting input of comparator 1031 ( Figure 2 (Used as a "+") for receiving reference voltage signals. Figure 2 (represented by "VREF" in Chinese). Based on this, the two input terminals of comparator 1031 are used to receive a first voltage signal and a reference voltage signal, and compare the first voltage signal and the reference voltage signal to output a third voltage signal. Figure 2 In this context, "CNT_GT" represents the third voltage signal.
[0046] The two input terminals of comparator 1031 are used to receive a second voltage signal and a reference voltage signal, and compare the second voltage signal and the reference voltage signal to output a fourth voltage signal. Figure 2 In this context, "CNT_GT" represents the fourth voltage signal.
[0047] The first input of AND gate 1032 is used to receive a third voltage signal or a fourth voltage signal, and the second input of AND gate 1032 is used to receive an enable signal. Figure 2 (represented as "CNT_EN" in Chinese). Based on this, the two inputs of AND gate 1032 are used to receive the third voltage signal and the enable signal, and output the fifth voltage signal during the high level of the third voltage signal and the enable signal.
[0048] The two inputs of AND gate 1032 are used to receive a fourth voltage signal and an enable signal, and output a sixth voltage signal during the high level of the fourth voltage signal and the enable signal.
[0049] The enable terminal of counter 1033 (denoted as "EN" in the figure) is used to receive the fifth or sixth voltage signal. The pulse input terminal of counter 1033 ( Figure 2 (In Chinese, "CLK" is used to indicate the clock signal of the counter.) Figure 2 (represented by "CLK_CNT" in Chinese), the reset pin of counter 1033 is used to receive the reset signal. Figure 2 (RST is used as a symbol in the diagram). Based on this, the counter 1033 receives the fifth voltage signal and the enable signal, and when the enable signal is valid, it counts the fifth voltage signal and outputs the first count value to the control module 104.
[0050] Counter 1033 receives the sixth voltage signal and the enable signal, and counts the sixth voltage signal when the enable signal is valid, and outputs the second count value to the control module 104.
[0051] In some embodiments, when the first clock signal is detected, the enable signal received by AND gate 1032 is valid (i.e., high level), the first voltage signal is less than the reference voltage signal, the third voltage signal output by the output terminal of comparator 1031 is high level, after the third voltage signal and the enable signal are input to AND gate 1032, AND gate 1032 outputs high level, and the counter 1033 is started. The counter 1033 starts counting, and the count value increases continuously under the drive of the counter clock signal.
[0052] As the first voltage signal increases, when the first voltage signal exceeds the reference voltage signal, the third voltage signal output from the comparator 1031 becomes low. The third voltage signal and the enable signal are input to the AND gate 1032, which then outputs a low level, shutting down the counter 1033. The counter 1033 then outputs its first count value to the control module 104 for storage.
[0053] In some embodiments, when detecting the clock signal to be tested, the enable signal received by AND gate 1032 is valid (i.e., high level), the second voltage signal is less than the reference voltage signal, the fourth voltage signal output by the output terminal of comparator 1031 is high level, after the fourth voltage signal and the enable signal are input to AND gate 1032, AND gate 1032 outputs high level, starting counter 1033, counter 1033 starts counting, and the count value continuously increases under the drive of the counter clock signal.
[0054] As the second voltage signal increases, when the second voltage signal is greater than the reference voltage signal, the fourth voltage signal output by the comparator 1031 becomes low. After the fourth voltage signal and the enable signal are input to the AND gate 1032, the AND gate 1032 outputs a low level, shutting down the counter 1033. The counter 1033 then outputs the second count value at this time to the control module 104 for storage.
[0055] It is understandable that the count value in counter 1033 needs to be cleared before detecting the first clock signal or the clock signal to be tested.
[0056] It is worth noting that since the inverting input of comparator 1031 is used to receive the first voltage signal, the first count value is directly proportional to the time it takes for the first voltage signal to rise from 0 to the reference voltage signal. If the increase in the first voltage signal is determined by the high level of the first clock signal, then the larger the proportion of the high level period of the first clock signal in one clock signal cycle, the greater the rise amplitude and the faster the rise speed of the first voltage signal, that is, the shorter the time it takes for the first voltage signal to rise from 0 to the reference voltage signal. Based on this, the first count value is inversely proportional to the high level time of the first clock signal. Since the first clock signal is the inverted signal of the clock signal under test, the first count value is inversely proportional to the low level time of the clock signal under test.
[0057] If the increase in the first voltage signal is determined by the low level of the first clock signal, then the larger the proportion of the low level period of the first clock signal in one clock signal cycle, the greater the rise in the first voltage signal and the faster the rise speed, meaning the shorter the time for the first voltage signal to rise from 0 to the reference voltage signal. Based on this, the first count value is inversely proportional to the low level time of the first clock signal. Since the first clock signal is the inverted signal of the clock signal under test, the first count value is inversely proportional to the high level time of the clock signal under test.
[0058] Furthermore, since the inverting input of comparator 1031 is used to receive the second voltage signal, the second count value is directly proportional to the time it takes for the second voltage signal to rise from 0 to the reference voltage signal. If the increase in the second voltage signal is determined by the high level of the clock signal under test, then the larger the proportion of the high level period of the clock signal under test in one clock signal cycle, the greater the rise amplitude and the faster the rise speed of the second voltage signal, that is, the shorter the time it takes for the second voltage signal to rise from 0 to the reference voltage signal. Based on this, the second count value is inversely proportional to the high level time of the clock signal under test.
[0059] If the increase in the second voltage signal is determined by the low level of the clock signal under test, then the larger the proportion of the low level period of the clock signal under test in one clock signal cycle, the greater the rise amplitude and the faster the rise speed of the second voltage signal, that is, the shorter the time for the second voltage signal to rise from 0 to the reference voltage signal. Based on this, the second count value is inversely proportional to the low level time of the clock signal under test.
[0060] In summary, since the first clock signal is the inverted signal of the clock signal under test, if the increase of the first voltage signal is determined by the high level of the first clock signal and the increase of the second voltage signal is determined by the high level of the clock signal under test, then the first count value is inversely proportional to the low level time of the clock signal under test, and the second count value is inversely proportional to the high level time of the clock signal under test.
[0061] Since the first clock signal is the inverted signal of the clock signal under test, if the increase of the first voltage signal is determined by the low level of the first clock signal and the increase of the second voltage signal is determined by the low level of the clock signal under test, then the first count value is inversely proportional to the high level time of the clock signal under test and the second count value is inversely proportional to the low level time of the clock signal under test.
[0062] In some embodiments, after receiving the first count value, the control module 104 sends a reset signal to the counter 1033 and the charge pump 102; the counter 1033 and the charge pump 102 perform a reset operation based on the reset signal. The counter 1033 clears the count value based on the reset signal. The charge pump 102 performs a discharge operation based on the reset signal.
[0063] In some embodiments, after receiving the second count value, the control module 104 sends a reset signal to the counter 1033 and the charge pump 102; the counter 1033 and the charge pump 102 perform a reset operation based on the reset signal. The counter 1033 clears its count value based on the reset signal. The charge pump 102 performs a discharge operation based on the reset signal.
[0064] In some embodiments, the control module 104 sends a reset signal to both the counter 1033 and the charge pump 102 simultaneously, or the control module 104 sends a reset signal to the counter 1033, and the counter 1033 sends a reset signal to the charge pump 102 through the reset terminal.
[0065] It is understandable that after the counter 1033 finishes counting, if it wants to count other signals, it needs to use a reset signal to clear the count value to zero in order to avoid abnormal phenomena such as inaccurate counting or counting interruption.
[0066] In some embodiments, such as Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of a charge pump provided in some embodiments of this application. The charge pump 102 includes a switching circuit 1021 and a charging / discharging circuit 1022. The control terminal of the switching circuit 1021 is coupled to the output terminal of the signal processing module 101.
[0067] The first terminal of the charging and discharging circuit 1022 is coupled to the switching circuit 1021, the second terminal of the charging and discharging circuit 1022 is grounded, and the control terminal of the charging and discharging circuit 1022 receives a reset signal; wherein, the coupling point between the charging and discharging circuit 1022 and the switching circuit 1021 serves as the output terminal of the charge pump 102.
[0068] The switching circuit 1021 charges the charging and discharging circuit 1022 during the low level of the first clock signal and outputs the first voltage signal during the charging cycle; before the switching circuit 1021 receives the first clock signal, the charging and discharging circuit 1022 has completed the discharging operation according to the reset signal.
[0069] The first clock signal actually alternates between high and low levels. During the low level period of the first clock signal, the switching circuit 1021 charges the charging and discharging circuit 1022, meaning that the first voltage signal can be output with a gradually increasing output during the low level period. During the high level period, since the charging and discharging circuit 1022 has already been charged during the low level period, the output of the first voltage signal can be maintained by the charging and discharging circuit 1022 during the high level period. The voltage value of the first voltage signal will not increase during the high level period.
[0070] The switching circuit 1021 charges the charging and discharging circuit 1022 during the low level of the clock signal to be tested, and outputs a second voltage signal during the charging cycle; the charging and discharging circuit 1022 has completed the discharging operation according to the reset signal before the switching circuit 1021 receives the clock signal to be tested.
[0071] The clock signal under test actually alternates between high and low levels. During the low level period of the clock signal under test, the switching circuit 1021 charges the charging and discharging circuit 1022, which means that a gradually increasing second voltage signal can be output during the low level period. During the high level period, since the charging and discharging circuit 1022 has already been charged during the low level period, the output of the second voltage signal can be maintained by the charging and discharging circuit 1022 during the high level period. The voltage value of the second voltage signal will not increase during the high level period.
[0072] It is understood that before the control terminal of the switching circuit 1021 receives the clock signal to be tested or the first clock signal output by the signal processing module 101, the charging and discharging circuit 1022 receives the reset signal sent by the control module 104 or the counter 1033, and performs a reset operation based on the reset signal when the reset signal is valid, so as to set the initial state of the charging and discharging circuit 1022.
[0073] It is worth noting that before counting different signals, a discharge operation needs to be performed on the charging and discharging circuit 1022 to bring it to its initial state. This is to prevent the switching circuit 1021 and the charging and discharging circuit 1022 from affecting the magnitude of the output first voltage signal or second voltage signal, which in turn would affect subsequent counting operations.
[0074] In some embodiments, such as Figure 4 As shown, Figure 4 This is a schematic diagram of the structure of a switching circuit provided in some embodiments of this application. The switching circuit 1021 includes a current source 201 and a first switching device 202. The first terminal of the first switching device 202 is coupled to the output terminal of the current source 201, the second terminal of the first switching device 202 is coupled to the charging and discharging circuit 1022, and the control terminal of the first switching device 202 is coupled to the output terminal of the signal processing module 101.
[0075] The first switching device 202 is turned on during the low level of the first clock signal, and charges the charging and discharging circuit 1022 through the current source 201, and outputs the first voltage signal during the charging cycle; the charging and discharging circuit 1022 has completed the discharging operation according to the reset signal before the first switching device 202 receives the first clock signal.
[0076] The first clock signal actually alternates between high and low levels. During the low level period of the first clock signal, the first switching device 202 charges the charging and discharging circuit 1022 through the current source 201. That is, the switching circuit 1021 can output a gradually increasing first voltage signal to the aforementioned counting module 103 during the low level period. During the high level period, the first switching device 202 is turned off. Since the charging and discharging circuit 1022 has already been charged during the low level period, the output of the first voltage signal can be maintained by the charging and discharging circuit 1022 during the high level period. The voltage value of the first voltage signal will not increase during the high level period.
[0077] The first switching device 202 is turned on during the low level of the clock signal to be tested, and charges the charging and discharging circuit 1022 through the current source 201, and outputs the second voltage signal during the charging cycle; wherein, before the first switching device 202 receives the clock signal to be tested, the charging and discharging circuit 1022 has completed the discharging operation according to the reset signal.
[0078] The clock signal under test actually alternates between high and low levels. During the low level period of the clock signal under test, the first switching device 202 charges the charging and discharging circuit 1022 through the current source 201. That is, the switching circuit 1021 can output a gradually increasing second voltage signal to the counting module 103 during the low level period. During the high level period, the first switching device 202 is turned off. Since the charging and discharging circuit 1022 has already been charged during the low level period, the output of the second voltage signal can be maintained by the charging and discharging circuit 1022 during the high level period. The voltage value of the second voltage signal will not increase during the high level period.
[0079] In some embodiments, the first switching device 202 is a field-effect transistor. Specifically, the first switching device 202 is a PMOS (Positive channel Metal Oxide Semiconductor) transistor, with the source of the PMOS transistor coupled to the current source 201, the gate of the PMOS transistor coupled to the output terminal of the signal processing module 101, and the drain of the PMOS transistor coupled to the charging and discharging circuit 1022.
[0080] In some embodiments, such as Figure 5 As shown, Figure 5 This is a schematic diagram of the structure of a charging and discharging circuit provided in some embodiments of this application. The charging and discharging circuit 1022 includes a capacitor 203 and a second switching device 204.
[0081] In this circuit, the first plate of capacitor 203 is coupled to the switching circuit 1021, and the second plate of capacitor 203 is grounded. Capacitor 203 can be an electrolytic capacitor, a polarized capacitor, a non-polarized capacitor, or other types; no restrictions are imposed here.
[0082] The first terminal of the second switching device 204 is coupled to the first plate of the capacitor 203, the second terminal of the second switching device 204 is grounded, and the control terminal of the second switching device 204 is used to receive a reset signal. Figure 5 (Used as "RST" in Chinese).
[0083] In this circuit, the switching circuit 1021 charges the capacitor 203 during the low level of the first clock signal and outputs a first voltage signal during the charging cycle, while the second switching device 204 is in the off state. Before the switching circuit 1021 receives the first clock signal, the second switching device 204 is turned on according to a reset signal to complete the discharge operation of the capacitor 203.
[0084] The first clock signal actually alternates between high and low levels. During the low level period of the first clock signal, the switching circuit 1021 charges the capacitor 203, allowing it to output a gradually increasing first voltage signal during the low level period. During the high level period, the first switching device 202 is turned off. Since the capacitor 203 has already been charged during the low level period, it can maintain the output of the first voltage signal during the high level period. The voltage value of the first voltage signal will not increase during the high level period.
[0085] During the low-level period of the clock signal to be measured, the switching circuit 1021 charges the capacitor 203 and outputs a first voltage signal during the charging cycle, while the second switching device 204 is in the off state. Specifically, before the switching circuit 1021 receives the clock signal to be measured, the second switching device 204 is turned on according to a reset signal to complete the discharge operation of the capacitor 203.
[0086] The clock signal under test actually alternates between high and low levels. During the low level period of the clock signal under test, the switching circuit 1021 charges the capacitor 203, allowing it to output a gradually increasing second voltage signal during the low level period. During the high level period, the first switching device 202 is turned off. Since the capacitor 203 has already been charged during the low level period of the clock signal under test, it can maintain the output of the second voltage signal during the high level period. The voltage value of the second voltage signal does not increase during the high level period.
[0087] In some embodiments, the control terminal of the second switching device 204 serves as a reset signal input terminal for receiving a reset signal.
[0088] In some embodiments, the second switching device 204 is a field-effect transistor. Specifically, the second switching device 204 is an NMOS (N-Metal-Oxide-Semiconductor) transistor. The gate of the NMOS transistor is coupled to the reset terminal of the counter 1033, the source of the NMOS transistor is coupled to the lower plate of the capacitor 203, the drain of the NMOS transistor is coupled to the upper plate of the capacitor 203, the upper plate of the capacitor 203 is coupled to the drain of the NMOS transistor, and the lower plate of the capacitor 203 is grounded.
[0089] It is understandable that the second switching device 204, acting as a bleeder, can control the charging and discharging process of the capacitor 203.
[0090] It is understood that the signal processing module 101 is used to receive the clock signal under test, and output the clock signal under test and the first clock signal to the charge pump 102 in chronological order based on the clock signal under test, so as to control the operation of the charge pump 102 based on the clock signal under test and the first clock signal respectively.
[0091] In some embodiments, such as Figure 6 As shown, Figure 6 This is a schematic diagram of the structure of a signal processing module provided in some embodiments of this application. The signal processing module 101 includes a first processing unit 1011 and a second processing unit 1012. The first processing unit 1011 receives the clock signal to be measured (…). Figure 6 (represented by "CLK_IN"), and outputs the first clock signal based on the clock signal under test. Figure 6 (represented by "SW_ENB" in Chinese); the second processing unit 1012 receives the clock signal to be tested and outputs the clock signal to be tested ( Figure 6 (In Chinese, it is represented by "SW_ENB").
[0092] In some embodiments, such as Figure 7 As shown, the first processing unit 1011 includes an inverter 301 and a third switching device 302. The second processing unit 1012 includes a fourth switching device 303.
[0093] When the third switching device 302 is turned on, the inverter 301 inverts the clock signal to be tested and outputs the first clock signal to the charge pump 102.
[0094] When the fourth switching device 303 is turned on, it directly outputs the clock signal to be tested to the charge pump 102.
[0095] For example, the input terminal of inverter 301 is used to receive the clock signal to be tested, the output terminal of inverter 301 is coupled to the input terminal of third switching device 302, and the output terminal of third switching device 302 is coupled to the control terminal of first switching device 202 in charge pump 102.
[0096] For example, the input terminal of the third switching device 302 is used to receive the clock signal to be tested, the output terminal of the third switching device 302 is coupled to the input terminal of the inverter 301, and the output terminal of the inverter 301 is coupled to the control terminal of the first switching device 202 in the charge pump 102.
[0097] The input terminal of the fourth switching device 303 is used to receive the clock signal to be tested, and the output terminal of the fourth switching device 303 is coupled to the control terminal of the first switching device 202 in the charge pump 102.
[0098] The input terminals of the first processing unit 1011 and the second processing unit 1012 respectively receive the clock signal to be tested. When the third switching device 302 in the first processing unit 1011 is turned on, the clock signal to be tested flows through the inverter 301 and the third switching device 302, and outputs the inverted signal of the clock signal to be tested, namely the first clock signal, to the control terminal of the first switching device 202 in the charge pump 102.
[0099] When the fourth switching device 303 in the second processing unit 1012 is turned on, the clock signal to be tested flows through the fourth switching device 303 and outputs the clock signal to be tested to the control terminal of the first switching device 202 in the charge pump 102.
[0100] It is understood that the third switch device 302 and the fourth switch device 303 are not turned on at the same time. That is, when the clock signal to be measured is acquired, the fourth switch device 303 is turned on and the third switch device 302 is turned off. When the first clock signal is acquired, the third switch device 302 is turned on and the fourth switch device 303 is turned off, so as to control the charge pump 102 to work using different signals.
[0101] In some embodiments, the first count value is inversely proportional to the high-level time of the clock signal under test, and the second count value is inversely proportional to the low-level time of the clock signal under test. Therefore, the control module 104 obtains the duty cycle of the clock signal under test by dividing the second count value by the sum of the first and second count values.
[0102] For example, the formula relating the first count value to the high-level time of the clock signal under test is as follows:
[0103]
[0104] Where i represents the first count value; k is a constant determined by the current value provided by current source 201, the capacitance value of capacitor 203, and the clock signal period; t high This indicates the high-level duration of the clock signal under test.
[0105] For example, the formula relating the second count value to the low-level time of the clock signal under test is as follows:
[0106]
[0107] Where j represents the second count value; k is a constant determined by the current value provided by current source 201, the capacitance value of capacitor 203, and the clock signal period; t low This indicates the low-level duration of the clock signal under test.
[0108] For example, the formula for defining duty cycle is Under the premise that the duty cycle of the clock signal under test can be determined as follows:
[0109]
[0110] In some embodiments, the first count value is inversely proportional to the low-level time of the clock signal under test, and the second count value is inversely proportional to the high-level time of the clock signal under test. Therefore, the control module 104 obtains the duty cycle of the clock signal under test by dividing the first count value by the sum of the first and second count values.
[0111] For example, the formula relating the first count value to the low-level time of the clock signal under test is as follows:
[0112]
[0113] Where i represents the first count value; k is a constant determined by the current value provided by current source 201, the capacitance value of capacitor 203, and the clock signal period; t low This indicates the low-level duration of the clock signal under test.
[0114] For example, the formula relating the second count value to the high-level time of the clock signal under test is as follows:
[0115]
[0116] Where j represents the second count value; k is a constant determined by the current value provided by current source 201, the capacitance value of capacitor 203, and the clock signal period; t high This indicates the high-level duration of the clock signal under test.
[0117] For example, the formula for defining duty cycle is Under the premise that the duty cycle of the clock signal under test can be determined as follows:
[0118]
[0119] In some embodiments, the first count value is proportional to the high-level time of the clock signal under test, and the second count value is proportional to the low-level time of the clock signal under test. Therefore, the control module 104 obtains the duty cycle of the clock signal under test by dividing the first count value by the sum of the first and second count values.
[0120] For example, the formula relating the first count value to the high-level time of the clock signal under test is as follows:
[0121] i = k × t high
[0122] Where i represents the first count value; k is a constant determined by the current value provided by current source 201, the capacitance value of capacitor 203, and the clock signal period; t high This indicates the high-level duration of the clock signal under test.
[0123] For example, the formula relating the second count value to the low-level time of the clock signal under test is as follows:
[0124] j = k × t low
[0125] Where j represents the second count value; k is a constant determined by the current value provided by current source 201, the capacitance value of capacitor 203, and the clock signal period; t low This indicates the low-level duration of the clock signal under test.
[0126] For example, the formula for defining duty cycle is Under the premise that the duty cycle of the clock signal under test can be determined as follows:
[0127]
[0128] In some embodiments, the first count value is proportional to the low-level time of the clock signal under test, and the second count value is proportional to the high-level time of the clock signal under test. Therefore, the control module 104 obtains the duty cycle of the clock signal under test by dividing the second count value by the sum of the first and second count values.
[0129] For example, the formula relating the first count value to the low-level time of the clock signal under test is as follows:
[0130] i = k × t low
[0131] Where i represents the first count value; k is a constant determined by the current value provided by current source 201, the capacitance value of capacitor 203, and the clock signal period; t low This indicates the low-level duration of the clock signal under test.
[0132] For example, the formula relating the second count value to the high-level time of the clock signal under test is as follows:
[0133] j = k × t high
[0134] Where j represents the second count value; k is a constant determined by the current value provided by current source 201, the capacitance value of capacitor 203, and the clock signal period; t high This indicates the high-level duration of the clock signal under test.
[0135] For example, the formula for defining duty cycle is Under the premise that the duty cycle of the clock signal under test can be determined as follows:
[0136]
[0137] In some embodiments, the control module 104 includes a processor. The processor involved in this application may be referred to as a CPU (Central Processing Unit), which may be an integrated circuit chip, or a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.
[0138] In some embodiments, the control module 104 may also include a controller or other components, which are not limited herein.
[0139] In summary, in an application scenario, such as Figure 8 The above, Figure 8 This is a schematic diagram of the duty cycle detection circuit provided in some embodiments of this application. The duty cycle detection circuit 10 includes a comparator 1031, an AND gate 1032, a counter 1033, a current source 201, a first switching device 202, a capacitor 203, a second switching device 204, an inverter 301, a third switching device 302, a fourth switching device 303, and a processor 1041.
[0140] The input terminal of inverter 301 is used to receive the clock signal to be measured. Figure 8 (represented by "CLK_IN"), the output of inverter 301 is coupled to the input of third switching device 302, the output of third switching device 302 is coupled to the control of first switching device 202, and the output of third switching device 302 outputs the first clock signal to the control of first switching device 202.
[0141] The input terminal of the fourth switching device 303 is coupled to the input terminal of the inverter 301, and the input terminal of the fourth switching device 303 is used to receive the clock signal to be measured. Figure 8(represented by "CLK_IN"), the output terminal of the fourth switching device 303 is coupled to the output terminal of the third switching device 302, that is, the output terminal of the fourth switching device 303 is coupled to the control terminal of the first switching device 202, and the output terminal of the fourth switching device 303 outputs the clock signal to be measured to the control terminal of the first switching device 202.
[0142] The control terminal of the first switching device 202 is used to receive the clock signal to be tested or the first clock signal. Figure 8 In this circuit, "SW_ENB" represents the signal input to the control terminal of the first switching device 202. The first terminal of the first switching device 202 is coupled to the output terminal of the current source 201, and the second terminal of the first switching device 202 is coupled to the first plate of the capacitor 203. The second plate of the capacitor 203 is grounded.
[0143] The first terminal of the second switching device 204 is coupled to the first plate of the capacitor 203, the second terminal of the second switching device 204 is grounded, and the control terminal of the second switching device 204 is used to receive a reset signal. Figure 8 (Used as "RST" in Chinese).
[0144] The inverting input of comparator 1031 ( Figure 8 (Used as a "-") The coupling point between the first switching device 202 and the capacitor 203 is connected. The inverting input of the comparator 1031 receives the first voltage signal and the second voltage signal respectively. Figure 8 (represented by "VC1" in Chinese), the non-inverting input of comparator 1031 ( Figure 8 (Indicated by "+") is coupled to the reference voltage terminal and used to receive the reference voltage signal. Figure 8 (referred to as "VREF" in Chinese).
[0145] The first input terminal of AND gate 1032 is coupled to the output terminal of comparator 1031, and the output terminal of comparator 1031 outputs a third voltage signal and a fourth voltage signal. Figure 8 (Indicated by "CNT_GT"), the second input of AND gate 1032 receives the enable signal ( Figure 8 (This is indicated by "CNT_EN" in Chinese).
[0146] The enable pin of counter 1033 ( Figure 8 The output of AND gate 1032 (indicated by "EN") is used to receive the fifth and sixth voltage signals, and the pulse input of counter 1033 is used to receive the pulse signals. Figure 8 (In Chinese, "CLK" is used to indicate the clock signal of the counter.) Figure 8 (represented by "CLK_CNT" in Chinese), the reset pin of counter 1033 is used to receive the reset signal. Figure 8(Used as "RST" in the diagram), the output of counter 1033 is coupled to processor 1041, and the output of counter 1033 outputs the first count value and the second count value. Figure 8 CNT is used in Chinese.<n:0> (Illustration) and stored in processor 1041.
[0147] based on Figure 8 The duty cycle detection circuit 10 shown is... Figure 8 The timing diagram of the duty cycle detection circuit 10 shown can be found in [reference]. Figure 9 .
[0148] exist Figure 9 In this context, RST represents the reset signal; CLK_IN represents the clock signal to be tested; S1 represents the status signal of the third switching device 302; S2 represents the status signal of the fourth switching device 303; SW_ENB represents the signal input to the control terminal of the first switching device 202. Specifically, SW_ENB during the time period T1 to T2 is the first clock signal output within the first time length mentioned above, and SW_ENB during the time period T3 to T4 is the clock signal to be tested output within the second time length mentioned above; VC1 represents the first voltage signal or the second voltage signal, specifically... VC1 during the time interval T1-T2 is the first voltage signal output within the first time length, and VC1 during the time interval T3-T4 is the second voltage signal output within the second time length; CNT_GT represents the third or fourth voltage signal. Specifically, CNT_GT during the time interval T1-T2 is the third voltage signal output within the first time length, and CNT_GT during the time interval T2-T3 is the fourth voltage signal output within the second time length; CNT_EN represents the enable signal; CLK_CNT represents the counter clock signal; CNT <n:0>This represents the first or second count value, specifically, the CNT within the time period T1 to T2. <n:0>The first count value within the first time period, CNT within the time interval T3 to T4. <n:0>This is the second count value within the second time period.
[0149] Right now, Figure 9 The corresponding duty cycle detection process is as follows:
[0150] S1: Set the initial state, the RST signal is valid, the upper plate of capacitor 203 is discharged, and the count value in counter 1033 is cleared to zero.
[0151] S2: When the third switching device 302 is closed, the inverted signal of the clock signal to be measured, i.e. the first voltage signal, is transmitted to the SW_ENB node. Since the first switching device 202 of the charge pump 102 is a PMOS transistor, during the high level of the clock signal to be measured, SW_ENB controls the current source 201 in the charge pump 102 to charge the capacitor 203, and the voltage VC1 begins to rise.
[0152] S3: The CNT_EN signal goes high. At the same time, since the VC1 voltage is lower than the reference voltage VREF in the initial stage, the CNT_GT output of comparator 1031 is high. After ANDing with CNT_EN, it outputs a high level, enabling counter 1033. The count value increases continuously under the drive of the counter clock signal CLK_CNT.
[0153] S4: VC1 rises under the control of SW_ENB. When the voltage exceeds the reference voltage VREF, the comparator 1031 outputs low, turning off the counter 1033 and storing the current first count value i into the processor 1041. The first count value i is proportional to the time it takes for VC1 to rise from 0 to VREF. The wider the high-level width of the measured clock signal, the greater the rise of voltage VC1 within one measured clock cycle, the faster the rise of VC1, and the shorter the time it takes for VC1 to rise from 0 to VREF. Therefore, the first count value i is proportional to the high-level time t of the measured clock signal. high It is inversely proportional, that is, i = k * (1 / t) high ), where k is a constant (determined by the IREF current value, the C1 capacitance value, and the clock period under test).
[0154] S5: The RST signal becomes valid again, discharging the upper plate of capacitor 203 and simultaneously resetting the count value in counter 1033 to zero.
[0155] S6: The fourth switch 303 is closed, transmitting the clock signal under test to the SW_ENB node. Repeat steps S2 to S4 above to obtain the low-level time t of the clock signal under test. low The second count value j is inversely proportional, i.e., j = k * (1 / t) low ), k is a constant, and the second count value j is stored in processor 1041.
[0156] S7: Clock duty cycle is defined as DR = t high / (t high +t low Based on the results of steps S4 and S6, DR = j / (i+j) can be obtained. The processor 1041 can calculate the duty cycle of the clock signal CLK_IN under test based on this relationship.
[0157] See Figure 10 , Figure 10 This is a schematic diagram of the structure of a memory provided in some embodiments of this application. The memory 100 includes the duty cycle detection circuit 10 described in any of the above embodiments, which will not be repeated here.
[0158] In some embodiments, the memory 100 may be any medium capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), or an optical disc.
[0159] In one application scenario, memory 100 is a double data rate static random-access memory (DDR SRAM).
[0160] In some embodiments of this application, a duty cycle detection circuit 10 is provided in the memory 100. The duty cycle detection circuit 10 can be used to detect the duty cycle when the memory 100 is working, and a high-accuracy duty cycle detection result can be obtained.
[0161] In summary, the duty cycle detection circuit 10 provided in some embodiments of this application can use the same device to detect the duty cycle of the clock signal under test and the first clock signal that is inversely opposite to it during the clock high and low levels. By using the same device for time-division detection, the first count value and the second count value can be affected in the same way when device drift or mismatch occurs. That is, the first count value and the second count value increase or decrease proportionally, but the ratio of the first count value and the second count value remains unchanged. This can avoid the influence of device drift or mismatch on the detection results, thereby improving the detection accuracy.
[0162] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A duty cycle detection circuit, characterized in that, The detection circuit includes: The signal processing module is configured to receive a clock signal under test and output a first clock signal and the clock signal under test based on the clock signal under test; wherein the first clock signal is the inverted signal of the clock signal under test; A charge pump receives a first clock signal and outputs a first voltage signal within a first time length of the first clock signal; and receives the clock signal to be tested and outputs a second voltage signal within a second time length of the clock signal to be tested; wherein the first time length of the first clock signal and the second time length of the clock signal to be tested constitute at least one clock signal period; The counting module receives the first voltage signal, counts based on the first voltage signal, and outputs a first count value; it also receives the second voltage signal, counts based on the second voltage signal, and outputs a second count value. The control module receives the first count value and the second count value, and calculates the duty cycle of the clock signal under test based on the first count value and the second count value.
2. The detection circuit according to claim 1, characterized in that, The counting module includes: A comparator, wherein the inverting input of the comparator is coupled to the output of the charge pump, and receives the first voltage signal and the second voltage signal respectively, and the non-inverting input of the comparator is coupled to a reference voltage; wherein the comparator outputs a third voltage signal based on the first voltage signal, and the comparator outputs a fourth voltage signal based on the second voltage signal; An AND gate, wherein the first input of the AND gate is coupled to the output of the comparator, and the second input of the AND gate receives an enable signal; wherein the AND gate outputs a fifth voltage signal during the high level of the third voltage signal and the enable signal, and outputs a sixth voltage signal during the high level of the fourth voltage signal and the enable signal; The counter, whose enable terminal is coupled to the output terminal of the AND gate, receives the fifth voltage signal and counts based on the fifth voltage signal to output the first count value; and receives the sixth voltage signal and counts based on the sixth voltage signal to output the second count value.
3. The detection circuit according to claim 2, characterized in that, After receiving the first count value, the control module sends a reset signal to the counter and the charge pump; the counter and the charge pump perform a reset operation based on the reset signal.
4. The detection circuit according to claim 2, characterized in that, The charge pump includes: A switching circuit, wherein the control terminal of the switching circuit is coupled to the output terminal of the signal processing module; A charging and discharging circuit, wherein a first terminal of the charging and discharging circuit is coupled to the switching circuit, a second terminal of the charging and discharging circuit is grounded, and a control terminal of the charging and discharging circuit receives a reset signal; wherein the coupling point between the charging and discharging circuit and the switching circuit serves as the output terminal of the charge pump. The switching circuit charges the charging and discharging circuit during the low level of the first clock signal and outputs the first voltage signal during the charging cycle. The switching circuit charges the charging and discharging circuit during the low level of the clock signal under test and outputs the second voltage signal during the charging cycle; wherein, before the switching circuit receives the clock signal under test, the charging and discharging circuit has completed the discharging operation according to the reset signal.
5. The detection circuit according to claim 4, characterized in that, The switching circuit includes: Current source; A first switching device, wherein a first terminal of the first switching device is coupled to the output terminal of the current source, a second terminal of the first switching device is coupled to the charging and discharging circuit, and a control terminal of the first switching device is coupled to the output terminal of the signal processing module; The first switching device is turned on during the low level of the first clock signal, charges the charging and discharging circuit through the current source, and outputs the first voltage signal during the charging cycle. The first switching device is turned on during the low level of the clock signal under test, charging the charging and discharging circuit through the current source, and outputting the second voltage signal during the charging cycle; wherein, before the first switching device receives the clock signal under test, the charging and discharging circuit has completed the discharging operation according to the reset signal.
6. The detection circuit according to claim 4, characterized in that, The charging and discharging circuit includes: A capacitor, wherein the first plate of the capacitor is coupled to the switching circuit, and the second plate of the capacitor is grounded; The second switching device has a first terminal coupled to the first plate of the capacitor, a second terminal grounded, and a control terminal for receiving the reset signal. The switching circuit charges the capacitor during the low level of the first clock signal and outputs the first voltage signal during the charging cycle, while the second switching device is in the off state. The switching circuit charges the capacitor during the low level of the clock signal under test and outputs the second voltage signal during the charging cycle, while the second switching device is in the off state; wherein, before the switching circuit receives the clock signal under test, the second switching device is turned on according to the reset signal to complete the discharge operation of the capacitor.
7. The detection circuit according to claim 1, characterized in that, The signal processing module includes: A first processing unit receives the clock signal to be tested and outputs the first clock signal based on the clock signal to be tested. The second processing unit receives the clock signal under test and outputs the clock signal under test.
8. The detection circuit according to claim 7, characterized in that, The first processing unit includes an inverter and a third switching device. When the third switching device is turned on, the inverter inverts the clock signal under test and outputs the first clock signal.
9. The detection circuit according to any one of claims 1-8, characterized in that, The control module obtains the duty cycle of the clock signal under test by dividing the second count value by the sum of the first count value and the second count value; wherein, the first count value is inversely proportional to the high level time of the clock signal under test, and the second count value is inversely proportional to the low level time of the clock signal under test.
10. A memory, characterized in that, The memory includes the detection circuit according to any one of claims 1-9.