Duty cycle detection circuit and electronic device

Abstract

The application discloses a duty cycle detection circuit and an electronic device. The duty cycle detection circuit comprises a signal processing module, a charge pump, an integrator and a control module. The signal processing module is configured to receive a clock signal to be measured, output a first clock signal and a second clock signal based on an inverted signal of the clock signal to be measured, and output a third clock signal and a fourth clock signal based on the clock signal to be measured. The charge pump is configured to output a first voltage signal based on the first clock signal and the second clock signal, and output a second voltage signal based on the third clock signal and the fourth clock signal. The integrator is configured to output a third voltage signal under control of the first clock signal and the second clock signal, and output a fourth voltage signal under control of the third clock signal and the fourth clock signal. The counting module is configured to count a first count value based on the third voltage signal, and count a second count value based on the fourth voltage signal. The control module is configured to calculate a duty cycle of the clock signal to be measured based on the first count value and the second count value. The duty cycle of the clock signal to be measured can be calculated.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to duty cycle detection circuits and electronic devices. Background Technology

[0002] With the development of electronic technology, clocks are crucial for synchronizing the various modules within high-speed electronic devices and coordinating their actions. Therefore, clock signals can be monitored to correct errors. One method to determine if a clock signal error has occurred is by analyzing the clock duty cycle.

[0003] However, the clock duty cycle detection circuits in related technologies typically use different devices to control and detect the high and low levels of the clock separately, which is extremely easy to affect the accuracy of the duty cycle detection results due to device parameter drift or mismatch. Summary of the Invention

[0004] This application provides a duty cycle detection circuit and electronic device. A first clock signal and a second clock signal are obtained based on the inverted signal of the clock signal under test. A third clock signal and a fourth clock signal are also obtained based on the clock signal under test. The same charge pump, integrator, counting module, and control module are used to detect the duty cycle of the first and second clock signals, as well as the third and fourth clock signals. This avoids device drift or mismatch that occurs when using different charge pumps, integrators, counting modules, and / or control modules for duty cycle detection, thus preventing any impact on the duty cycle detection results and improving detection accuracy.

[0005] To address the aforementioned technical problems, this application provides a duty cycle detection circuit, which includes a signal processing module, a charge pump, an integrator, a counting module, and a control module. The signal processing module is configured to receive a clock signal to be measured, and output a first clock signal and a second clock signal based on the inverted signal of the clock signal to be measured, and to output a third clock signal and a fourth clock signal based on the clock signal to be measured; wherein the first clock signal is the inverted signal of the second clock signal; and the third clock signal is the inverted signal of the fourth clock signal.

[0006] The charge pump receives a first clock signal and a second clock signal, and outputs a first voltage signal based on the first clock signal and the second clock signal; and receives a third clock signal and a fourth clock signal, and outputs a second voltage signal based on the third clock signal and the fourth clock signal.

[0007] The integrator receives a first voltage signal and outputs a third voltage signal under the control of a first clock signal and a second clock signal; and receives a second voltage signal and outputs a fourth voltage signal under the control of a third clock signal and a fourth clock signal; wherein the duration of the first clock signal and the duration of the third clock signal constitute at least one clock signal cycle.

[0008] The counting module receives a third voltage signal, counts based on the third voltage signal, and outputs a first count value; it also receives a fourth voltage signal, counts based on the fourth voltage signal, and outputs a second count value.

[0009] The control module receives the first count value and the second count value, and calculates the duty cycle of the clock signal under test based on the first count value and the second count value.

[0010] In some embodiments, the charge pump includes: a current source; a first input terminal of a first switching circuit coupled to the output terminal of a signal processing module, a second input terminal of the first switching circuit coupled to the output terminal of the current source, the first switching circuit being used to receive a first clock signal or a third clock signal; a first input terminal of a second switching circuit coupled to the output terminal of the signal processing module, a second input terminal of the second switching circuit coupled to the output terminal of the first switching circuit, the output terminal of the second switching circuit being grounded, the second switching circuit being used to receive a second clock signal or a fourth clock signal; wherein, the coupling point between the first switching circuit and the second switching circuit serves as the output terminal of the charge pump; wherein, the first switching circuit outputs a first voltage signal with gradually increasing voltage during the high level of the first clock signal and the low level of the second clock signal; the first switching circuit outputs a second voltage signal with gradually increasing voltage during the high level of the third clock signal and the low level of the fourth clock signal.

[0011] In some embodiments, the integrator has completed the discharge operation based on the reset signal before the second switching circuit receives the third clock signal and the fourth clock signal.

[0012] In some embodiments, the first switching circuit includes a first inverter and a first switching device; the control terminal of the first switching device is coupled to the output terminal of the first inverter, the first terminal of the first switching device is coupled to the output terminal of the current source, and the input terminal of the first inverter is used to receive a first clock signal or a third clock signal.

[0013] The second switching circuit includes a second inverter and a second switching device; the control terminal of the second switching device is coupled to the second inverter, the first terminal of the second switching device is coupled to the second terminal of the first switching device, the second terminal of the second switching device is grounded, and the input terminal of the second inverter is used to receive a second clock signal or a fourth clock signal.

[0014] In some embodiments, the integrator includes: a first terminal of a first switching module for receiving a first voltage signal or a second voltage signal, and a second terminal of the first switching module grounded; a negative input terminal of an amplifier coupled to a third terminal of the first switching module via a first capacitor, a positive input terminal of the amplifier grounded, and an output terminal of the amplifier coupled to a counting module; a first terminal of a negative feedback circuit coupled to the output terminal of the amplifier, and a second terminal of the negative feedback circuit coupled to the negative input terminal of the amplifier.

[0015] The first switching module controls the first and third terminals of the first switching module to conduct when the first clock signal is at a high level and the second clock signal is at a low level, and controls the second and third terminals of the first switching module to conduct when the first clock signal is at a low level and the second clock signal is at a high level, so that the amplifier outputs a third voltage signal.

[0016] The first switching module responds to the third clock signal being at a high level and the fourth clock signal being at a low level by controlling the first terminal and the third terminal of the first switching module to conduct. In response to the third clock signal being at a low level and the fourth clock signal being at a high level, it controls the second terminal and the third terminal of the first switching module to conduct, so that the amplifier outputs the fourth voltage signal.

[0017] In some embodiments, the negative feedback circuit includes: a first terminal of the second switching module coupled to the negative phase input terminal of the amplifier, a second terminal of the second switching module grounded, and a third terminal of the second switching module coupled to the output terminal of the amplifier via a second capacitor; a first terminal of the third switching module coupled to the negative phase input terminal of the amplifier via a third capacitor, and a second terminal of the third switching module coupled to the output terminal of the amplifier.

[0018] The second switching module responds to the first clock signal being at a high level and the second clock signal being at a low level by controlling the first and third terminals of the second switching module to conduct, forming a first negative feedback loop.

[0019] The second switching module responds to the first clock signal being at a low level and the second clock signal being at a high level by controlling the conduction between the second and third terminals of the second switching module. The third switching module responds to the second clock signal being at a high level by controlling the conduction between the first and third terminals of the third switching module, thus forming a second negative feedback loop.

[0020] In some embodiments, the negative feedback circuit further includes: a first terminal of the fourth switching module coupled to the negative inverting input terminal of the amplifier, and a second terminal of the fourth switching module coupled to the output terminal of the amplifier. The fourth switching module, in response to a reset signal, controls the conduction between its first and second terminals, forming a third negative feedback loop.

[0021] In some embodiments, when the first switch module is connected between the second and third terminals, and when the second switch module is connected between the second and third terminals, the first capacitor is discharged, and the second capacitor is charged by the third voltage signal or the fourth voltage signal.

[0022] In some embodiments, a reset signal is generated after the first count value or the second count value stops increasing.

[0023] In some embodiments, the counting module includes: an inverting input of a comparator coupled to the output of an integrator, receiving a third voltage signal and a fourth voltage signal respectively; a non-inverting input of the comparator coupled to a reference voltage terminal; wherein the comparator outputs a fifth voltage signal based on the third voltage signal and a sixth voltage signal based on the fourth voltage signal; a first input of an AND gate coupled to the output of the comparator, and a second input of the AND gate receiving an enable signal; wherein the AND gate outputs a seventh voltage signal during the high levels of the fifth voltage signal and the enable signal, and outputs an eighth voltage signal during the high levels of the sixth voltage signal and the enable signal; an enable terminal of a counter coupled to the output of the AND gate, receiving the seventh voltage signal and counting based on the seventh voltage signal to output a first count value; and receiving the eighth voltage signal and counting based on the eighth voltage signal to output a second count value.

[0024] In some embodiments, after receiving the first count value, the control module sends a reset signal to the counter and integrator; the counter and integrator perform a reset operation based on the reset signal.

[0025] In some embodiments, the signal processing module includes: a third switching circuit for receiving a clock signal under test and outputting a clock signal under test and an inverted signal of the clock signal under test based on the clock signal under test; and a signal processing circuit coupled to the output terminal of the third switching circuit for receiving the inverted signal of the clock signal under test, outputting a first clock signal and a second clock signal, and receiving the clock signal under test and outputting a third clock signal and a fourth clock signal.

[0026] In some embodiments, the signal processing circuit includes: a third inverter, a first NOR gate, and a second NOR gate. The input terminal of the third inverter is coupled to the output terminal of a third switching circuit, and receives the clock signal to be measured and its inverted signal, respectively. The first input terminal of the first NOR gate is coupled to the output terminal of the third inverter, the second input terminal of the first NOR gate is coupled to the output terminal of the second NOR gate, and the output terminal of the first NOR gate is coupled to a charge pump, outputting a first clock signal or a third clock signal. The first input terminal of the second NOR gate is coupled to the output terminal of the third switching circuit, the second input terminal of the second NOR gate is coupled to the output terminal of the first NOR gate, and the output terminal of the second NOR gate is coupled to a charge pump, outputting a second clock signal or a fourth clock signal.

[0027] In some embodiments, the third switching circuit includes: a first processing circuit receiving a clock signal to be tested and outputting a clock signal to be tested based on the clock signal to be tested; and a second processing circuit receiving the clock signal to be tested and outputting an inverted signal of the clock signal to be tested based on the clock signal to be tested.

[0028] In some embodiments, the second processing circuit includes a fourth inverter and a third switching device. When the third switching device is turned on, the fourth inverter inverts the clock signal to be tested and outputs an inverted signal.

[0029] In some embodiments, the control module obtains the duty cycle of the clock signal under test by dividing the second count value by the sum of the first count value and the second count value; wherein the first count value is inversely proportional to the high level time of the clock signal under test, and the second count value is inversely proportional to the low level time of the clock signal under test.

[0030] In order to solve the above-mentioned technical problems, this application provides an electronic device that includes the detection circuit described above.

[0031] The duty cycle detection circuit provided in some embodiments of this application includes a signal processing module, a charge pump, an integrator, a counting module, and a control module. The signal processing module is configured to receive a clock signal to be measured, and output a first clock signal and a second clock signal based on the inverted signal of the clock signal to be measured, and output a third clock signal and a fourth clock signal based on the clock signal to be measured; wherein the first clock signal is the inverted signal of the second clock signal; and the third clock signal is the inverted signal of the fourth clock signal. The charge pump receives the first clock signal and the second clock signal, and outputs a first voltage signal based on the first clock signal and the second clock signal; and receives the third clock signal and the fourth clock signal, and outputs a second voltage signal based on the third clock signal and the fourth clock signal. The integrator receives the first voltage signal and outputs a third voltage signal under the control of the first clock signal and the second clock signal; and receives the second voltage signal and outputs a fourth voltage signal under the control of the third clock signal and the fourth clock signal; wherein the duration of the first clock signal and the duration of the third clock signal constitute at least one clock signal cycle. The counting module receives a third voltage signal, counts based on the third voltage signal, and outputs a first count value. It also receives a fourth voltage signal, counts based on the fourth voltage signal, and outputs a second count value. The control module receives the first and second count values ​​and calculates the duty cycle of the clock signal under test based on them. During the duty cycle detection of the clock signal under test, using the same components (i.e., charge pump, integrator, counting module, and control module) to detect the duty cycle of the first and second clock signals, or the third and fourth clock signals, avoids component drift or mismatch that occurs when using different charge pumps, integrators, counting modules, and / or control modules. This prevents affecting the duty cycle detection results and improves detection accuracy. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0033] Figure 1 This is a schematic diagram of the duty cycle detection circuit in some embodiments of this application;

[0034] Figure 2 This is a schematic diagram of the charge pump structure in some embodiments of this application;

[0035] Figure 3 This is a schematic diagram of the charge pump structure in some embodiments of this application;

[0036] Figure 4 These are schematic diagrams of the integrator structure in some embodiments of this application;

[0037] Figure 5 These are schematic diagrams of the integrator structure in some embodiments of this application;

[0038] Figure 6 These are schematic diagrams of the integrator structure in some embodiments of this application;

[0039] Figure 7 These are schematic diagrams of the counting module in some embodiments of this application;

[0040] Figure 8 This is a schematic diagram of the signal processing module in some embodiments of this application;

[0041] Figure 9 This is a schematic diagram of the signal processing module in some embodiments of this application;

[0042] Figure 10 This is a schematic diagram of the signal processing module in some embodiments of this application;

[0043] Figure 11 These are schematic diagrams of the signal processing circuits in some embodiments of this application;

[0044] Figure 12 This is a schematic diagram of the duty cycle detection circuit in some embodiments of this application;

[0045] Figure 13 yes Figure 12 The timing diagram of the duty cycle detection circuit shown is shown.

[0046] Figure 14 These are schematic diagrams of the structure of electronic devices in some embodiments of this application. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0048] See Figure 1 , Figure 1 This is a schematic diagram of the duty cycle detection circuit in some embodiments of this application. The duty cycle detection circuit 10 includes a signal processing module 101, a charge pump 102, an integrator 103, a counting module 104, and a control module 105.

[0049] The signal processing module 101 is configured to receive the clock signal under test and output a first clock signal and a second clock signal based on the inverted signal of the clock signal under test. The first clock signal is the inverted signal of the second clock signal.

[0050] The signal processing module 101 is configured to receive the clock signal under test and output a third clock signal and a fourth clock signal based on the clock signal under test. The third clock signal is the inverted version of the fourth clock signal. It can be understood that the signal processing module 101 can output a first clock signal and a second clock signal, or output a third clock signal and a fourth clock signal, depending on the requirements.

[0051] The charge pump 102 receives a first clock signal and a second clock signal, and outputs a first voltage signal based on the first clock signal and the second clock signal.

[0052] The charge pump 102 receives a third clock signal and a fourth clock signal, and outputs a second voltage signal based on the third clock signal and the fourth clock signal.

[0053] Integrator 103 receives a first voltage signal and outputs a third voltage signal under the control of a first clock signal and a second clock signal.

[0054] Integrator 103 receives the second voltage signal and outputs the fourth voltage signal under the control of the third and fourth clock signals.

[0055] In some embodiments, the first time length of the clock signal under test and the second time length of the inverted signal of the clock signal under test constitute at least one clock signal cycle.

[0056] In some embodiments, the first time length of the first clock signal and the second time length of the third clock signal constitute at least one clock signal cycle. The first time length of the second clock signal and the second time length of the fourth clock signal constitute at least one clock signal cycle.

[0057] In some embodiments, the ratio between the first time length and the second time length can be determined according to the actual situation.

[0058] In some embodiments, the first time length and the second time length can be determined based on the corresponding reference voltage value in the counting module 104. The first time length ends when the third voltage signal is greater than the reference voltage value. The second time length ends when the fourth voltage signal is greater than the reference voltage value.

[0059] In some embodiments, the first time length is related to the levels of the first clock signal and the second clock signal.

[0060] For example, the first time length is related to the low level of the first clock signal, and since the second clock signal is the inverted signal of the first clock signal, the first time length is related to the high level of the second clock signal.

[0061] For example, the first time length is related to the high level of the first clock signal, and since the second clock signal is the inverted signal of the first clock signal, the first time length is related to the low level of the second clock signal.

[0062] In some embodiments, the second time length is related to the levels of the third and fourth clock signals.

[0063] For example, the second time length is related to the low level of the third clock signal, and since the fourth clock signal is the inverted signal of the third clock signal, the second time length is related to the high level of the fourth clock signal.

[0064] For example, the second time length is related to the high level of the third clock signal, and since the fourth clock signal is the inverted signal of the third clock signal, the second time length is related to the low level of the fourth clock signal.

[0065] The counting module 104 receives a third voltage signal, counts based on the third voltage signal, and outputs a first count value; it also receives a fourth voltage signal, counts based on the fourth voltage signal, and outputs a second count value.

[0066] The control module 105 receives the first count value and the second count value, and calculates the duty cycle of the clock signal under test based on the first count value and the second count value.

[0067] In some embodiments, the first count value is related to the high level of the clock signal under test, and the second count value is related to the low level of the clock signal under test.

[0068] For example, the first count value is inversely proportional to the high level of the clock signal under test, and the second count value is inversely proportional to the low level of the clock signal under test.

[0069] For example, the first count value is inversely proportional to the high level of the clock signal under test, and the second count value is directly proportional to the low level of the clock signal under test.

[0070] For example, the first count value is proportional to the high level of the clock signal under test, and the second count value is proportional to the low level of the clock signal under test.

[0071] For example, the first count value is proportional to the high level of the clock signal under test, and the second count value is inversely proportional to the low level of the clock signal under test.

[0072] In some embodiments, the first count value is related to the high level of the clock signal under test, and the second count value is related to the high level of the clock signal under test.

[0073] For example, the first count value is inversely proportional to the high level of the clock signal under test, and the second count value is inversely proportional to the high level of the clock signal under test.

[0074] For example, the first count value is inversely proportional to the high level of the clock signal under test, and the second count value is directly proportional to the high level of the clock signal under test.

[0075] For example, the first count value is proportional to the high level of the clock signal under test, and the second count value is proportional to the high level of the clock signal under test.

[0076] For example, the first count value is proportional to the high level of the clock signal under test, and the second count value is inversely proportional to the high level of the clock signal under test.

[0077] In some embodiments, the first count value is related to the low level of the clock signal under test, and the second count value is related to the high level of the clock signal under test.

[0078] For example, the first count value is inversely proportional to the low level of the clock signal under test, and the second count value is inversely proportional to the high level of the clock signal under test.

[0079] For example, the first count value is inversely proportional to the low level of the clock signal under test, and the second count value is directly proportional to the high level of the clock signal under test.

[0080] For example, the first count value is proportional to the low level of the clock signal under test, and the second count value is proportional to the high level of the clock signal under test.

[0081] For example, the first count value is proportional to the low level of the clock signal under test, and the second count value is inversely proportional to the high level of the clock signal under test.

[0082] In some embodiments, the first count value is related to the low level of the clock signal under test, and the second count value is related to the low level of the clock signal under test.

[0083] For example, the first count value is inversely proportional to the low level of the clock signal under test, and the second count value is inversely proportional to the low level of the clock signal under test.

[0084] For example, the first count value is inversely proportional to the low level of the clock signal under test, and the second count value is directly proportional to the low level of the clock signal under test.

[0085] For example, the first count value is proportional to the low level of the clock signal under test, and the second count value is proportional to the low level of the clock signal under test.

[0086] For example, the first count value is proportional to the low level of the clock signal under test, and the second count value is inversely proportional to the low level of the clock signal under test.

[0087] In some embodiments of this application, the duty cycle detection circuit 10 uses the same devices (i.e., charge pump 102, integrator 103, counting module 104, and control module 105) to detect the duty cycle of the first clock signal and the second clock signal, or the third clock signal and the fourth clock signal. This avoids device drift or mismatch when using different charge pumps 102, integrators 103, counting modules 104, and / or control modules 105 for duty cycle detection, thus preventing the duty cycle detection results from being affected and improving detection accuracy.

[0088] In some embodiments, such as Figure 2 As shown, Figure 2 This is a schematic diagram of the structure of a charge pump in some embodiments of this application. The charge pump 102 includes a current source 1021, a first switching circuit 1022, and a second switching circuit 1023.

[0089] The first input terminal of the first switching circuit 1022 is coupled to the output terminal of the signal processing module 101, and the second input terminal of the first switching circuit 1022 is coupled to the output terminal of the current source 1021. The first switching circuit 1022 is used to receive a first clock signal or a third clock signal. Figure 2 In this context, "CK1" represents the first clock signal and the third clock signal.

[0090] The first input terminal of the second switching circuit 1023 is coupled to the output terminal of the signal processing module 101, the second input terminal of the second switching circuit 1023 is coupled to the output terminal of the first switching circuit 1022, the output terminal of the second switching circuit 1023 is grounded, and the second switching circuit 1023 is used to receive the second clock signal or the fourth clock signal. Figure 2 (The second clock signal and the fourth clock signal are represented by "CK2" in the text). The coupling point between the first switch circuit 1022 and the second switch circuit 1023 serves as the output terminal of the charge pump 102.

[0091] The first switching circuit 1022 outputs a first voltage signal whose voltage gradually increases during the high level of the first clock signal and the low level of the second clock signal. The second switching circuit 1022 outputs a first voltage signal with an initial voltage value during the low level of the first clock signal and the high level of the second clock signal. Figure 2 (The first voltage signal is referred to as "VSTEP" in the text). Specifically, the voltage value of the first voltage signal output by the first switching circuit 1022 during the high level of the first clock signal and the low level of the second clock signal increases from X1 to X2, and the second switching circuit 1023 outputs a first voltage signal with a voltage value of X1 during the low level of the first clock signal and the high level of the second clock signal.

[0092] It is understood that the first clock signal and the second clock signal actually alternate between high and low levels. The first switching circuit 1022 is turned on during the high level of the first clock signal and the low level of the second clock signal. At this time, the current source 1021 can charge the coupling point between the first switching circuit 1022 and the second switching circuit 1023 through the first switching circuit 1022, and output voltage (i.e., VSTEP). Since the coupling point between the first switching circuit 1022 and the second switching circuit 1023 has been fully charged during the high level of the first clock signal and the low level of the second clock signal, it discharges during the low level of the first clock signal and the high level of the second clock signal, that is, the initial state first voltage signal is output.

[0093] Furthermore, during the high level period of the first clock signal and the low level period of the second clock signal, the integrator 103 can be charged using the output voltage (i.e., the first voltage signal with gradually increasing voltage), so that the integrator 103 can output a third voltage signal with gradually increasing voltage during the low level period of the first clock signal and the high level period of the second clock signal.

[0094] Specifically, the first switching circuit 1022 outputs a second voltage signal with gradually increasing voltage during the high level period of the third clock signal and the low level period of the fourth clock signal. The second switching circuit 1023 outputs a second voltage signal with an initial voltage value during the low level period of the third clock signal and the high level period of the fourth clock signal. Figure 2 In this circuit, "VSTEP" represents the second voltage signal. Specifically, during the high level of the third clock signal and the low level of the fourth clock signal, the voltage value of the second voltage signal output by the first switching circuit 1022 increases from X3 to X4. During the low level of the third clock signal and the high level of the fourth clock signal, the second switching circuit 1023 outputs a second voltage signal with a voltage value of X3. X3 may be the same as or different from X1, and X4 may be the same as or different from X2.

[0095] It is understandable that the third and fourth clock signals actually alternate between high and low levels. The first switching circuit 1022 is turned on during the high level of the third clock signal and the low level of the fourth clock signal. At this time, the current source 1021 can charge the coupling point between the first switching circuit 1022 and the second switching circuit 1023 through the first switching circuit 1022, outputting a voltage (i.e., VSTEP). Since the coupling point between the first switching circuit 1022 and the second switching circuit 1023 has been fully charged during the high level of the third clock signal and the low level of the fourth clock signal, it discharges during the low level of the third clock signal and the high level of the fourth clock signal, i.e., outputting the second voltage signal in the initial state.

[0096] Furthermore, during the high level of the third clock signal and the low level of the fourth clock signal, the integrator 103 can be charged using the output voltage (i.e., the second voltage signal with gradually increasing voltage), so that the integrator 103 can output a gradually increasing fourth voltage signal during the low level of the third clock signal and the high level of the fourth clock signal.

[0097] In some embodiments, before the first switching circuit 1022 receives the first clock signal and the second clock signal output by the signal processing module 101, the first switching circuit 1022 has completed a reset operation, and the integrator 103 has completed a discharge operation according to the reset signal.

[0098] In some embodiments, before the second switching circuit 1023 receives the third clock signal and the fourth clock signal output by the signal processing module 101, the second switching circuit 1023 has completed a reset operation, and the integrator 103 has completed a discharge operation according to the reset signal.

[0099] It is worth noting that before counting different signals, the integrator 103 needs to be reset to its initial state to avoid affecting the magnitude of the output third and fourth voltage signals due to the integrator 103, which would then affect subsequent counting operations.

[0100] In some embodiments, such as Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of a charge pump in some embodiments of this application. The charge pump 102 includes a current source 1021, a first switching circuit 1022, and a second switching circuit 1023.

[0101] The first switching circuit 1022 includes a first inverter 201 and a first switching device 202. The control terminal of the first switching device 202 is coupled to the output terminal of the first inverter 201, and the first terminal of the first switching device 202 is coupled to the output terminal of the current source 1021. The input terminal of the first inverter 201 is used to receive a first clock signal or a third clock signal. Figure 3 In this context, "CK1" represents the first clock signal and the third clock signal.

[0102] The second switching circuit 1023 includes a second inverter 203 and a second switching device 204. The control terminal of the second switching device 204 is coupled to the output terminal of the second inverter 203, the first terminal of the second switching device 204 is coupled to the second terminal of the first switching device 202, the second terminal of the second switching device 204 is grounded, and the input terminal of the second inverter 203 is used to receive a second clock signal or a fourth clock signal. Figure 3 In this context, "CK2" represents the second clock signal and the fourth clock signal.

[0103] In some embodiments, the first switching device 202 is a field-effect transistor. The first switching device 202 is used to control the charging current. Specifically, as shown... Figure 3 As shown, the first switching device 202 is a PMOS (Positive channel Metal Oxide Semiconductor) transistor. The source of the PMOS transistor is coupled to the output terminal of the current source 1021, the gate of the PMOS transistor is coupled to the output terminal of the first inverter 201, and the drain of the PMOS transistor is coupled to the second switching circuit 1023.

[0104] The first switching device 202 is controlled by the inverted signal of CK1. That is, the first switching device 202 controls the current source 1021 to charge the coupling point between the first switching device 202 and the second switching device 204 during the high level of the first clock signal, the low level of the second clock signal, or the high level of the third clock signal and the low level of the fourth clock signal.

[0105] The first switching device 202 outputs a first voltage signal whose voltage gradually increases during the high level of the first clock signal and the low level of the second clock signal. Figure 3 In this context, "VSTEP" represents the first voltage signal.

[0106] The first clock signal and the second clock signal actually alternate between high and low levels. During the high level of the first clock signal and the low level of the second clock signal, the first switching device 202 charges the coupling point between the first switching device 202 and the second switching device 204 through the current source 1021. That is, the first switching circuit 1022 can output a gradually increasing first voltage signal to the integrator 103 when the first clock signal is at a high level and the second clock signal is at a low level. During the low level of the first clock signal and the high level of the second clock signal, the first switching device 202 is turned off. At this time, the coupling point between the first switching device 202 and the second switching device 204 outputs the initial state first voltage signal to the integrator 103. The integrator 103 performs a charging operation during the low level of the first clock signal and the high level of the second clock signal to output a gradually increasing third voltage signal.

[0107] In some embodiments, the second switching device 204 is a field-effect transistor. The second switching device 204 serves as a discharge venting diode. Specifically, as... Figure 3As shown, the second switching device 204 is an NMOS (N-Metal-Oxide-Semiconductor) transistor. The gate of the NMOS transistor is coupled to the output terminal of the second inverter 203, the source of the NMOS transistor is grounded, and the drain of the NMOS transistor is coupled to the first switching circuit 1022. That is, the drain of the NMOS transistor is coupled to the drain of the PMOS transistor.

[0108] The second switching device 204 is controlled by the delay signal of CK2. Specifically, the second switching device 204 discharges at the coupling point between the first switching device 202 and the second switching device 204 during the high level of the first clock signal and slightly after the low level of the second clock signal, or during the high level of the third clock signal and slightly after the low level of the fourth clock signal. In this case, the delay of CK2 is to ensure that the charging charge of the integrator 103 is not mistakenly discharged by the second switching device 204.

[0109] The first switching device 202 outputs a second voltage signal whose voltage gradually increases during the high level of the third clock signal and the low level of the fourth clock signal. Figure 3 In this context, "VSTEP" represents the second voltage signal.

[0110] The third and fourth clock signals actually alternate between high and low levels. During the high level of the third clock signal and the low level of the fourth clock signal, the first switching device 202 charges the coupling point between the first switching device 202 and the second switching device 204 through the current source 1021. That is, the first switching circuit 1022 can output a gradually increasing second voltage signal to the integrator 103 when the third clock signal is high and the fourth clock signal is low. During the low level of the third clock signal and the high level of the fourth clock signal, the first switching device 202 is turned off and the second switching device 204 is turned on. At this time, the coupling point between the first switching device 202 and the second switching device 204 outputs the initial state second voltage signal to the integrator 103. The integrator 103 performs a charging operation during the low level of the third clock signal and the high level of the fourth clock signal to output a gradually increasing fourth voltage signal.

[0111] In some embodiments, such as Figure 4 As shown, Figure 4 This is a schematic diagram of the structure of an integrator in some embodiments of this application. The integrator 103 includes a first switching module 1031, an amplifier 1032, a negative feedback circuit 1033, and a first capacitor C1.

[0112] The first terminal of the first switch module 1031 is used to receive a first voltage signal or a second voltage signal. Figure 4(referred to as "VSTEP" in Chinese), the second terminal of the first switch module 1031 is grounded.

[0113] The negative input terminal of amplifier 1032 is coupled to the third terminal of the first switching module 1031 through the first capacitor C1, the positive input terminal of amplifier 1032 is grounded, and the output terminal of amplifier 1032 is coupled to the counting module 104. The first capacitor C1 can be an electrolytic capacitor, a polarized capacitor, a non-polarized capacitor, or other types; no limitation is made here.

[0114] The first terminal of the negative feedback circuit 1033 is coupled to the output terminal of the amplifier 1032, and the second terminal of the negative feedback circuit 1033 is coupled to the negative phase input terminal of the amplifier 1032.

[0115] For example, such as Figure 4 As shown, the first switch module 1031 includes a fifth switch device ( Figure 4 (S1 is used as a symbol in the text) and the sixth switching device ( Figure 4 (Signed as "S2"), one end of the fifth switching device receives either the first voltage signal or the second voltage signal. That is, one end of the fifth switching device can serve as the first terminal of the first switching module 1031. The other end of the fifth switching device is coupled to the first plate of the first capacitor C1, and one end of the sixth switching device is grounded. That is, one end of the sixth switching device serves as the second terminal of the first switching module 1031. The other end of the sixth switching device is coupled to the first plate of the first capacitor C1. That is, the other ends of the fifth and sixth switching devices can serve as the third terminals of the first switching module 1031. The second plate of the first capacitor C1 is coupled to the negative input terminal of the amplifier 1032, the positive input terminal of the amplifier 1032 is grounded, the output terminal of the amplifier 1032 is coupled to the counting module 104, the first terminal of the negative feedback circuit 1033 is coupled to the output terminal of the amplifier 1032, and the second terminal of the negative feedback circuit 1033 is coupled to the negative input terminal of the amplifier 1032.

[0116] Based on this, the fifth switching device is activated by either the first clock signal or the third clock signal. Figure 4 The sixth switching device is turned on or off under the control of the first clock signal (represented by "CK1") and the third clock signal (represented by "CK1"). Figure 4The device is turned on or off under the control of the second and fourth clock signals (represented by "CK2"). Specifically, since the first and second clock signals are inverted signals, and the third and fourth clock signals are also inverted signals, the sixth switch is off when the fifth switch is on. That is, when the fifth switch is on and the sixth switch is off, the first clock signal is low and the second clock signal is high, and the third clock signal is low and the fourth clock signal is high. When the fifth switch is off and the sixth switch is on, the first clock signal is high and the second clock signal is low, and the third clock signal is high and the fourth clock signal is low.

[0117] Specifically, the first switching module 1031 responds to a first clock signal being high and a second clock signal being low by controlling the first terminal and the third terminal of the first switching module 1031 to conduct (i.e., the fifth switching device is turned on); and responds to a first clock signal being low and a second clock signal being high by controlling the second terminal and the third terminal of the first switching module 1031 to conduct (i.e., the sixth switching device is turned on), so that the amplifier 1032 outputs a third voltage signal. Figure 4 In this context, "VINTG" represents the third voltage signal.

[0118] It is understood that the first clock signal and the second clock signal actually alternate between high and low levels. During the high level of the first clock signal and the low level of the second clock signal, the first switch module 1031 controls the conduction between its first and third terminals, using the input voltage (i.e., VSTEP) to charge the first plate of the first capacitor C1, thereby storing the charge of the integrator 103 (i.e., VSTEP*C1) in the first capacitor C1. Due to the presence of the negative feedback circuit 1033, the level of the second plate of the first capacitor C1 is low at this time, and the charge stored in the first capacitor C1 is also VSTEP*C1.

[0119] During the low level of the first clock signal and the high level of the second clock signal, the first switching module 1031 controls the conduction between its second and third terminals, allowing it to output a gradually increasing third voltage signal during the low level of the first clock signal. Since the first capacitor C1 is already charged during the high level of the first clock signal, during the low level of the first clock signal (when the second clock signal is high), the first plate of the first capacitor C1 is grounded. Due to the presence of the negative feedback circuit 1033, the second plate of the first capacitor C1 is at a low level, causing the first capacitor C1 to discharge and its charge to be transferred to the negative feedback circuit 1033.

[0120] During the high level period of the first clock signal and the low level period of the second clock signal, the voltage value of the third voltage signal will not increase, but will remain at the voltage value of the third voltage signal corresponding to the previous low level period of the first clock signal.

[0121] The first switching module 1031 responds to the third clock signal being at a high level and the fourth clock signal being at a low level by controlling the first terminal and the third terminal of the first switching module 1031 to conduct (i.e., the fifth switching device is turned on). Conversely, responding to the third clock signal being at a low level and the fourth clock signal being at a high level by controlling the second terminal and the third terminal of the first switching module 1031 to conduct (i.e., the sixth switching device is turned on), so that the amplifier 1032 outputs a fourth voltage signal. Figure 4 In this context, "VINTG" represents the fourth voltage signal.

[0122] Specifically, the second switching device 204 discharges at the coupling point between the first switching device 202 and the second switching device 204 during the low level period of the first clock signal and slightly delayed, or during the low level period of the third clock signal and slightly delayed, and during the high level period of the fourth clock signal and slightly delayed. The delay of CK2 is to ensure that when the second and third terminals of the first switching module 1031 in the integrator 103 are turned on (i.e., the sixth switching device is turned on), the output second voltage signal can maintain the voltage signal corresponding to the previous low level period. That is, the charge stored on the first capacitor C1 will not be mistakenly discharged by the second switching device 204.

[0123] It is understandable that the third and fourth clock signals actually alternate between high and low levels. During the high level period of the third clock signal and the low level period of the fourth clock signal, the first switching module 1031 controls the conduction between its first and third terminals, using the input voltage (i.e., VSTEP) to charge the first capacitor C1, thereby storing the charge of the integrator 103 (i.e., VSTEP*C1) in the first capacitor C1. Due to the presence of the negative feedback circuit 1033, the level of the second plate of the first capacitor C1 is low at this time, and the charge stored in the first capacitor C1 is also VSTEP*C1.

[0124] During the low level of the third clock signal and the high level of the fourth clock signal, the first switching module 1031 controls the conduction between its second and third terminals, allowing it to output a gradually increasing fourth voltage signal during the low level of the third clock signal. Since the first capacitor C1 is already charged during the high level of the third clock signal, during the low level of the third clock signal (when the fourth clock signal is high), the first plate of the first capacitor C1 is grounded. Due to the presence of the negative feedback circuit 1033, the second plate of the first capacitor C1 is at a low level, causing the first capacitor C1 to discharge and its charge to be transferred to the negative feedback circuit 1033.

[0125] During the high level period of the third clock signal and the low level period of the fourth clock signal, the voltage value of the fourth voltage signal will not increase, but will remain at the voltage value of the fourth voltage signal corresponding to the previous low level period of the third clock signal.

[0126] It is worth noting that before the first switch module 1031 receives the first voltage signal or the second voltage signal output by the charge pump 102 (i.e., before the counting module 104 operates, or after the counting module 104 outputs the first count value or the second count value), the negative feedback circuit 1033 receives the reset signal sent by the control module 105 or the counting module 104, and performs a reset operation based on the reset signal when the reset signal is valid, so as to set the initial state of the negative feedback circuit 1033 and reset the amplifier 1032.

[0127] It is worth noting that before counting different signals, a reset operation needs to be performed on the negative feedback circuit 1033 to ensure that the negative feedback circuit 1033 is in its initial state. This is to prevent the first switching module 1031 and the negative feedback circuit 1033 from affecting the magnitude of the output third or fourth voltage signal, thereby affecting the subsequent counting operation.

[0128] In some embodiments, such as Figure 5 As shown, Figure 5 This is a schematic diagram of the integrator structure in some embodiments of this application, wherein the negative feedback circuit 1033 includes a second switch module 301, a third switch module 302, a second capacitor C2, and a third capacitor C3.

[0129] In this configuration, the first terminal of the second switching module 301 is coupled to the negative input terminal of the amplifier 1032, the second terminal of the second switching module 301 is grounded, and the third terminal of the second switching module 301 is coupled to the output terminal of the amplifier 1032 through the second capacitor C2. The second capacitor C2 can be an electrolytic capacitor, a polarized capacitor, a non-polarized capacitor, or other types; no restrictions are imposed here.

[0130] The first terminal of the third switching module 302 is coupled to the negative input terminal of the amplifier 1032 via the third capacitor C3, and the second terminal of the third switching module 302 is coupled to the output terminal of the amplifier 1032. The third capacitor C3 can be an electrolytic capacitor, a polarized capacitor, a non-polarized capacitor, or other types; no restrictions are placed here.

[0131] For example, such as Figure 5 As shown, the second switch module 301 includes a seventh switch device ( Figure 5 (Signed as "S3") and the eighth switching device ( Figure 5 (Signed as "S4" in the diagram), the third switch module 302 includes a ninth switch device ( Figure 5 (Signed as "S5" in the diagram). In this circuit, one end of the seventh switching device is coupled to the negative input terminal of amplifier 1032. That is, one end of the seventh switching device can serve as the first terminal of the second switching module 301. The other end of the seventh switching device is coupled to the first plate of the second capacitor C2, and the second plate of the second capacitor C2 is coupled to the output terminal of amplifier 1032. That is, the other end of the seventh switching device can serve as the third terminal of the second switching module 301. One end of the eighth switching device is coupled to the first plate of the second capacitor C2, and the other end of the eighth switching device is grounded. That is, one end of the eighth switching device can serve as the second terminal of the second switching module 301. One end of the ninth switching device is coupled to the negative input terminal of amplifier 1032 through the third capacitor C3. That is, one end of the ninth switching device can serve as the first terminal of the third switching module 302. The other end of the ninth switching device is coupled to the output terminal of amplifier 1032. That is, the other end of the ninth switching device can serve as the second terminal of the third switching module 302.

[0132] Based on this, the seventh switching device is activated in the first clock signal or the third clock signal ( Figure 5 The eighth and ninth switching devices are turned on or off under the control of the first and third clock signals (represented by "CK1"). Figure 5 The clock signals are controlled by "CK2" to turn on or off under the control of the second and fourth clock signals. Specifically, since the first and second clock signals are inverted signals, and the third and fourth clock signals are also inverted signals, when the fifth switch is on and the sixth switch is off, the seventh switch is on, and the eighth and ninth switches are off. At this time, the first clock signal is at a low level, and the second clock signal is at a high level. Conversely, when the sixth switch is on and the fifth switch is off, the seventh switch is off, and the eighth and ninth switches are on. At this time, the first clock signal is at a high level, and the second clock signal is at a low level.

[0133] In this circuit, the second switch module 301 responds to the first clock signal being at a high level and the second clock signal being at a low level by controlling the first and third terminals of the second switch module 301 to conduct, forming a first negative feedback loop.

[0134] The second switch module 301 responds to the first clock signal being at a low level and the second clock signal being at a high level by controlling the second terminal and the third terminal of the second switch module 301 to conduct, and the third switch module 302 responds to the second clock signal being at a high level by controlling the first terminal and the third terminal of the third switch module 302 to conduct, thus forming a second negative feedback loop.

[0135] The first plate of the first capacitor C1 is grounded. Due to the negative feedback, the second plate of the first capacitor C1 is at a low level, and the first capacitor C1 is discharged. After the second negative feedback loop is formed, the charge on the first capacitor C1 is transferred to the third capacitor C3, causing the integrator 103 to output voltage ( Figure 5 When the voltage increases (indicated by "VINTG"), the integrator gain of integrator 103 (i.e., the increase in voltage during this charge transfer) is VSTEP*C1 / C3. The second capacitor C2 is charged as the load of the amplifier 1032 output so that in the next cycle, the voltage corresponding to the third voltage signal when the current second clock signal is low, or the voltage corresponding to the fourth voltage signal when the fourth clock signal is low, can be retained in the second capacitor C2.

[0136] In some embodiments, when the first and third terminals of the first switch module 1031 are connected, and when the first and third terminals of the second switch module 301 are connected, the first capacitor C1 is charged using the input voltage; the third capacitor C3 and the second capacitor C2 retain the voltage corresponding to the third voltage signal when the second clock signal was low, or the third capacitor C3 and the second capacitor C2 retain the voltage corresponding to the fourth voltage signal when the fourth clock signal was low. The capacitance value of the second capacitor C2 is much larger than the capacitance value of the first capacitor C1.

[0137] In some embodiments, when the first switch module 1031 is connected between its second and third terminals, and when the second switch module 301 is connected between its second and third terminals, the first capacitor C1 is discharged, and the second capacitor C2 is charged by a third voltage signal or a fourth voltage signal.

[0138] In some embodiments of this application, the charge pump 102 can output a first voltage signal or a second voltage signal under the drive of the input voltage and overlapping clock signals (i.e., the first clock signal and the second clock signal, or the third clock signal and the fourth clock signal). The integrator 103, driven by the first voltage signal or the second voltage signal, outputs a third voltage signal or a fourth voltage signal that gradually increases with time. Furthermore, within each clock cycle (including the time for implementing a first negative feedback loop and the time for implementing a second negative feedback loop), the third voltage signal or the fourth voltage signal increases by VSTEP*C1 / C3 compared to the input voltage signal. INTG(n) CK2 =V INTG(n-1) CK2 +VSTEP*C1 / C3.

[0139] Among them, V INTG(n-1) CK2 This indicates that the second capacitor C2 and the third capacitor C3 retain the voltage corresponding to the third voltage signal when the previous second clock signal was low, or the voltage corresponding to the fourth voltage signal when the previous fourth clock signal was low, V. INTG(n) CK2 This indicates the voltage values ​​currently held by the second capacitor C2 and the third capacitor C3.

[0140] Where VSTEP represents the first voltage signal or the second voltage signal. Specifically, VSTEP is the voltage (i.e., IREF*tCK1 / C1) corresponding to the completion of charging of the first capacitor C1 by the current source 1021 within tCK1 (i.e., the first time length of the first clock signal or the second clock signal). INTG(n) CK2 =V INTG(n-1) CK2 +IREF*tCK1 / C3. VSTEP is the voltage (i.e., IREF*tCK2 / C1) corresponding to the completion of charging of the first capacitor C1 by current source 1021 within tCK2 (i.e., the second time length of the third or fourth clock signal). At this time, V INTG(n) CK2 =V INTG(n-1) CK2 +IREF*tCK2 / C3.

[0141] Since IREF and the third capacitor C3 are both fixed values, the integrator gain of integrator 103 is proportional to the first time length and the integrator gain of integrator 103 is proportional to the second time length.

[0142] In some embodiments, such as Figure 6 As shown, Figure 6This is a schematic diagram of the integrator structure in some embodiments of this application, wherein the negative feedback circuit 1033 includes a second switch module 301, a third switch module 302, a fourth switch module 303, a second capacitor C2, and a third capacitor C3.

[0143] The first terminal of the fourth switch module 303 is coupled to the negative input terminal of the amplifier 1032, and the second terminal of the fourth switch module 303 is coupled to the output terminal of the amplifier 1032.

[0144] In this circuit, the fourth switch module 303 responds to the reset signal and controls the first and second terminals of the fourth switch module 303 to conduct, forming a third negative feedback loop.

[0145] For example, such as Figure 6 As shown, the fourth switch module 303 includes a tenth switch device ( Figure 6 (Indicated by "S6"), one end of the tenth switching device is coupled to the negative input terminal of amplifier 1032. That is, one end of the tenth switching device can serve as the first terminal of the fourth switching module 303. The other end of the tenth switching device is coupled to the output terminal of amplifier 1032. That is, the other end of the tenth switching device can serve as the second terminal of the fourth switching module 303. Based on this, the tenth switching device, upon receiving a reset signal ( Figure 6 When "RST" is used as a descriptor, the circuit is activated.

[0146] It is understandable that the tenth switching device is turned on or off under the control of the reset signal. When the tenth switching device is turned on, it discharges the third capacitor C3 and sets the initial state of the third voltage signal or the fourth voltage signal to a low level.

[0147] In some embodiments, a reset signal is generated after the first count value or the second count value stops increasing.

[0148] It is understood that the signal processing module 101 is used to receive the clock signal to be tested, and output a first clock signal and a second clock signal based on the inverted signal of the clock signal to be tested, and output a third clock signal and a fourth clock signal based on the clock signal to be tested, and input the first clock signal and the second clock signal, or the third clock signal and the fourth clock signal, to the charge pump 102 in chronological order, so as to control the operation of the charge pump 102 based on the first clock signal and the second clock signal, so that the charge pump 102 outputs a first voltage signal, or controls the operation of the charge pump 102 based on the third clock signal and the fourth clock signal, so that the charge pump 102 outputs a second voltage signal, and then controls the operation of the integrator 103 based on the first voltage signal or the second voltage signal.

[0149] In some embodiments, such as Figure 7 As shown, Figure 7This is a schematic diagram of the structure of the counting module in some embodiments of this application. The counting module 104 includes a comparator 1041, an AND gate 1042 and a counter 1043.

[0150] In this configuration, the inverting input of comparator 1041 is coupled to the output of integrator 103, and receives both a third voltage signal and a fourth voltage signal. The non-inverting input of comparator 1041 is coupled to a reference voltage. Comparator 1041 outputs a fifth voltage signal based on the third voltage signal and a sixth voltage signal based on the fourth voltage signal. In some embodiments, the fourth voltage signal is generated after the third voltage signal has finished.

[0151] The first input of AND gate 1042 is coupled to the output of comparator 1041, and the second input of AND gate 1042 receives an enable signal. Specifically, AND gate 1042 outputs a seventh voltage signal during the high levels of the fifth voltage signal and the enable signal, and outputs an eighth voltage signal during the high levels of the sixth voltage signal and the enable signal.

[0152] The enable terminal of counter 1043 is coupled to the output terminal of AND gate 1042. Counter 1043 receives a seventh voltage signal and counts based on the seventh voltage signal to output a first count value; and counter 1043 receives an eighth voltage signal and counts based on the eighth voltage signal to output a second count value.

[0153] For example, the inverting input of comparator 1041 ( Figure 7 (Used as a "-") for receiving the third or fourth voltage signal. Figure 7 In this context, "VINTG" represents the third and fourth voltage signals. The non-inverting input of comparator 1041 ( Figure 7 (Used as a "+") for receiving reference voltage signals. Figure 7 (represented by "VREF" in Chinese). Based on this, the two inputs of comparator 1041 are used to receive the third voltage signal and the reference voltage signal, and compare the third voltage signal and the reference voltage signal to output the fifth voltage signal. Figure 7 In this context, "CNT_GT" represents the fifth voltage signal.

[0154] The two inputs of comparator 1041 are used to receive a fourth voltage signal and a reference voltage signal, and compare the fourth voltage signal and the reference voltage signal to output a sixth voltage signal. Figure 7 In this context, "CNT_GT" represents the sixth voltage signal.

[0155] The first input of AND gate 1042 is used to receive the fifth voltage signal or the sixth voltage signal, and the second input of AND gate 1042 is used to receive the enable signal. Figure 7(represented as "CNT_EN" in Chinese). Based on this, the two inputs of AND gate 1042 are used to receive the fifth voltage signal and the enable signal, and output the seventh voltage signal during the high level of the fifth voltage signal and the enable signal.

[0156] The two inputs of AND gate 1042 are used to receive the sixth voltage signal and the enable signal, and output the eighth voltage signal during the high level of the sixth voltage signal and the enable signal.

[0157] The enable terminal of counter 1043 (indicated by "EN" in the figure) is used to receive the seventh voltage signal or the eighth voltage signal. The pulse input terminal of counter 1043 ( Figure 7 (In Chinese, "CLK" is used to indicate the clock signal of the counter.) Figure 7 (represented by "CLK_CNT" in Chinese), the reset pin of counter 1043 is used to receive the reset signal. Figure 7 (RST is used as a symbol in the diagram). Based on this, the counter 1043 receives the seventh voltage signal and the enable signal, and when the enable signal is valid, it counts the seventh voltage signal and outputs the first count value to the control module 105.

[0158] Counter 1043 receives the eighth voltage signal and the enable signal, and counts the eighth voltage signal when the enable signal is valid, and outputs the second count value to the control module 105.

[0159] In some embodiments, the third voltage signal ( Figure 7 (Used as "VINTG" in the text) is less than the reference voltage signal ( Figure 7 (Illustrated by "VREF"), the fifth voltage signal output by the comparator 1041 is high. After the fifth voltage signal and the enable signal are input to the AND gate 1042, when the enable signal is valid, the AND gate 1042 outputs a high level, starting the counter 1043. The counter 1043 starts counting, and the count value increases continuously under the drive of the counter clock signal.

[0160] As the third voltage signal increases, when it exceeds the reference voltage signal, the fifth voltage signal output from comparator 1041 becomes low. The fifth voltage signal and the enable signal are input to AND gate 1042, which then outputs low, shutting down counter 1043. Counter 1043 outputs its first count value at this point to control module 105 for storage.

[0161] In some embodiments, the fourth voltage signal ( Figure 7 (Used as "VINTG" in the text) is less than the reference voltage signal ( Figure 7(Illustrated by "VREF"), the sixth voltage signal output by the comparator 1041 is high. After the sixth voltage signal and the enable signal are input to the AND gate 1042, when the enable signal is valid, the AND gate 1042 outputs a high level, starting the counter 1043. The counter 1043 starts counting, and the count value increases continuously under the drive of the counter clock signal.

[0162] As the fourth voltage signal increases, when the fourth voltage signal is greater than the reference voltage signal, the sixth voltage signal output by the comparator 1041 becomes low. After the sixth voltage signal and the enable signal are input to the AND gate 1042, the AND gate 1042 outputs a low level, turning off the counter 1043. The counter 1043 outputs the second count value at this time to the control module 105 for storage.

[0163] It is understandable that the count value in counter 1043 needs to be cleared before detecting the first clock signal and the second clock signal, or the third clock signal and the fourth clock signal.

[0164] It is worth noting that, since the inverting input of comparator 1041 is used to receive the third voltage signal, the first count value is proportional to the time it takes for the third voltage signal to rise from 0 to the reference voltage signal.

[0165] If the increase in the third voltage signal is determined by the high level of the first clock signal and the low level of the second clock signal, then the greater the proportion of the high level period of the first clock signal in a clock signal cycle, or the greater the proportion of the low level period of the second clock signal in a clock signal cycle, the greater the rise amplitude and the faster the rise speed of the third voltage signal. In other words, the time it takes for the third voltage signal to rise from 0 to the reference voltage signal is shorter. Based on this, the first count value is inversely proportional to the high level time of the first clock signal and inversely proportional to the low level time of the second clock signal.

[0166] If the increase in the third voltage signal is determined by the low level of the first clock signal and the high level of the second clock signal, then the greater the proportion of the low level period of the first clock signal within a clock signal cycle, or the greater the proportion of the high level period of the second clock signal within a clock signal cycle, the greater the rise in the third voltage signal and the faster its rise speed. In other words, the time it takes for the third voltage signal to rise from 0 to the reference voltage signal is shorter. Based on this, the first count value is inversely proportional to the low level time of the first clock signal and inversely proportional to the high level time of the second clock signal.

[0167] Furthermore, since the inverting input of comparator 1041 is used to receive the fourth voltage signal, the second count value is proportional to the time it takes for the fourth voltage signal to rise from 0 to the reference voltage signal.

[0168] If the increase in the fourth voltage signal is determined by the high level of the third clock signal and the low level of the fourth clock signal, then the greater the proportion of the high level period of the third clock signal in a clock signal cycle, or the greater the proportion of the low level period of the fourth clock signal in a clock signal cycle, the greater the rise amplitude and the faster the rise speed of the fourth voltage signal. In other words, the time for the fourth voltage signal to rise from 0 to the reference voltage signal is shorter. Based on this, the second count value is inversely proportional to the high level time of the third clock signal and inversely proportional to the low level time of the fourth clock signal.

[0169] If the increase in the fourth voltage signal is determined by the low level of the third clock signal and the high level of the fourth clock signal, then the greater the proportion of the low level period of the third clock signal in a clock signal cycle, or the greater the proportion of the high level period of the fourth clock signal in a clock signal cycle, the greater the rise amplitude and the faster the rise speed of the fourth voltage signal. In other words, the time for the fourth voltage signal to rise from 0 to the reference voltage signal is shorter. Based on this, the second count value is inversely proportional to the low level time of the third clock signal, and the second count value is inversely proportional to the high level time of the fourth clock signal.

[0170] In some embodiments, after receiving the first count value, the control module 105 sends a reset signal to the counter 1043 and the integrator 103; the counter 1043 and the integrator 103 perform a reset operation based on the reset signal. The counter 1043 clears the count value based on the reset signal. The integrator 103 performs a discharge operation based on the reset signal.

[0171] In some embodiments, after receiving the second count value, the control module 105 sends a reset signal to the counter 1043 and the integrator 103; the counter 1043 and the integrator 103 perform a reset operation based on the reset signal. The counter 1043 clears the count value based on the reset signal. The integrator 103 performs a discharge operation based on the reset signal.

[0172] In some embodiments, the control module 105 sends a reset signal to both the counter 1043 and the integrator 103 simultaneously, or the control module 105 sends a reset signal to the counter 1043, and the counter 1043 sends a reset signal to the integrator 103 through the reset terminal.

[0173] It is understandable that after the counter 1043 finishes counting, if it wants to count other signals, it needs to use a reset signal to clear the count value to zero in order to avoid abnormal phenomena such as inaccurate counting or counting interruption.

[0174] In some embodiments, such as Figure 8 As shown, Figure 8This is a schematic diagram of the structure of a signal processing module in some embodiments of this application. The signal processing module 101 includes a third switching circuit 1011 and a signal processing circuit 1012.

[0175] The third switching circuit 1011 is used to receive the clock signal to be measured. Figure 8 (represented by "CLK_IN"), and outputs the clock signal under test and its inverted signal based on the clock signal under test. Figure 8 In this context, "CLK_SW" represents the clock signal under test and its inverted signal.

[0176] Signal processing circuit 1012 is coupled to the output of third switching circuit 1011, receives the inverted signal of the clock signal to be measured, and outputs the first clock signal and the second clock signal. Figure 8 In this code, "CK1" represents the first clock signal. Figure 8 The second clock signal is represented by "CK2" in the code, and the receiver receives the clock signal under test and outputs the third and fourth clock signals. Figure 8 In this context, "CK1" represents the third clock signal. Figure 8 (In this context, "CK2" represents the fourth clock signal).

[0177] In some embodiments, such as Figure 9 As shown, Figure 9 This is a schematic diagram of the signal processing module in some embodiments of this application. The third switching circuit 1011 includes a first processing circuit 401 and a second processing circuit 402.

[0178] The first processing circuit 401 receives the clock signal to be measured. Figure 9 (represented by "CLK_IN"), and outputs the clock signal under test based on the clock signal under test ( Figure 9 (In Chinese, it is represented by "CLK_SW").

[0179] The second processing circuit 402 receives the clock signal to be tested and outputs an inverted signal of the clock signal to be tested based on the clock signal to be tested. Figure 9 (In Chinese, it is represented by "CLK_SW").

[0180] In some embodiments, such as Figure 10 As shown, Figure 10 This is a schematic diagram of the signal processing module in some embodiments of this application, wherein the second processing circuit 402 includes a fourth inverter 4021 and a third switching device ( Figure 10 (Signed as "S7"), the first processing circuit 401 includes a fourth switching device ( Figure 10 (Signed as "S8" in Chinese). When the third switching device is turned on, the fourth inverter 4021 inverts the clock signal under test and outputs an inverted signal.

[0181] For example, the input terminal of the third switching device is coupled to the output terminal of the fourth inverter 4021, the input terminal of the fourth inverter 4021 is used to receive the clock signal to be tested, the output terminal of the third switching device is coupled to the input terminal of the signal processing circuit 1012, and the output terminal of the signal processing circuit 1012 is coupled to the input terminal of the charge pump 102.

[0182] For example, the input terminal of the third switching device is used to receive the clock signal to be tested, the output terminal of the third switching device is coupled to the first terminal of the fourth inverter 4021, the second terminal of the fourth inverter 4021 is coupled to the input terminal of the signal processing circuit 1012, and the output terminal of the signal processing circuit 1012 is coupled to the input terminal of the charge pump 102.

[0183] For example, the input terminal of the fourth switching device is used to receive the clock signal to be tested, and the output terminal of the fourth switching device is coupled to the input terminal of the signal processing circuit 1012, and the output terminal of the signal processing circuit 1012 is coupled to the input terminal of the charge pump 102.

[0184] When the third switching device is turned on, the fourth switching device is turned off. The clock signal to be tested flows through the third switching device and the fourth inverter 4021, and outputs the inverted signal of the clock signal to be tested to the signal processing circuit 1012.

[0185] When the fourth switching device is turned on, the third switching device is turned off, the clock signal to be tested flows through the fourth switching device, and the clock signal to be tested is output to the signal processing circuit 1012.

[0186] It is understandable that the third and fourth switching devices do not conduct at the same time. That is, when acquiring the inverted signal of the clock signal under test, the third switching device is on and the fourth switching device is off, and when acquiring the clock signal under test, the third switching device is off and the fourth switching device is on.

[0187] In some embodiments, the signal processing circuit 1012 is a non-overlapping clock circuit. For example... Figure 11 As shown, Figure 11 This is a schematic diagram of the structure of a signal processing circuit in some embodiments of this application. The signal processing circuit 1012 includes a third inverter 501, a first NOR gate 502, and a second NOR gate 503.

[0188] The input of the third inverter 501 is coupled to the output of the third switching circuit 1011, and receives the clock signal to be measured and its inverted signal, respectively. Figure 11 In this context, "CLK_SW" represents the clock signal under test and its inverted signal.

[0189] The first input terminal of the first NOR gate 502 is coupled to the output terminal of the third inverter 501, the second input terminal of the first NOR gate 502 is coupled to the output terminal of the second NOR gate 503, and the output terminal of the first NOR gate 502 is coupled to the charge pump 102, outputting a first clock signal or a third clock signal. Figure 11 In this context, "CK1" represents the first clock signal and the third clock signal.

[0190] The first input terminal of the second NOR gate 503 is coupled to the output terminal of the third switching circuit 1011, and the second input terminal of the second NOR gate 503 is coupled to the output terminal of the first NOR gate 502. The output terminal of the second NOR gate 503 is coupled to the charge pump 102, outputting a second clock signal or a fourth clock signal. Figure 11 In this context, "CK2" represents the second clock signal and the fourth clock signal.

[0191] It can be understood that when the first NOR gate 502 outputs the first clock signal, the second NOR gate 503 outputs the second clock signal. When the first NOR gate 502 outputs the third clock signal, the second NOR gate 503 outputs the fourth clock signal.

[0192] In some embodiments, when detecting the clock signal under test, the clock signal under test actually alternates between high and low levels. This is because the operating logic of the first NOR gate 502 and the second NOR gate 503 is as follows: input 0, 0, output 1; input 0, 1, output 0; input 1, 0, output 0; input 1, 1, output 0.

[0193] When the clock signal to be tested received at one end of the second NOR gate 503 is high, the inverted signal of the clock signal to be tested received at one end of the first NOR gate 502 is low. At this time, the second NOR gate 503 can only output a low-level second clock signal. Based on this, when the second clock signal received at the other end of the first NOR gate 502 is low, the first NOR gate 502 outputs a high-level first clock signal, that is, the other end of the second NOR gate 503 receives a high-level first clock signal.

[0194] When the clock signal to be tested received at one end of the second NOR gate 503 is low, the inverted signal of the clock signal to be tested received at one end of the first NOR gate 502 is high. At this time, the first NOR gate 502 can only output a low-level first clock signal. Based on this, when the first clock signal received at the other end of the second NOR gate 503 is low, the second NOR gate 503 outputs a high-level second clock signal, that is, the other end of the first NOR gate 502 receives a high-level second clock signal.

[0195] Therefore, after the first clock signal and the second clock signal are input into the integrator 103, the fifth switching device in the integrator 103 is turned on when the first clock signal is at a high level and the second clock signal is at a low level.

[0196] In some embodiments, when detecting the inverted signal of the clock signal under test, the inverted signal of the clock signal under test actually alternates between high and low levels. This is because the operating logic of the first NOR gate 502 and the second NOR gate 503 is as follows: input 0, 0, output 1; input 0, 1, output 0; input 1, 0, output 0; input 1, 1, output 0.

[0197] When the inverted signal of the clock signal under test received at one end of the second NOR gate 503 is high, the clock signal under test received at one end of the first NOR gate 502 is low. At this time, the second NOR gate 503 can only output a low-level fourth clock signal. Based on this, the fourth clock signal received at the other end of the first NOR gate 502 is low, and the first NOR gate 502 outputs a high-level third clock signal, that is, the other end of the second NOR gate 503 receives a high-level third clock signal.

[0198] When the inverted signal of the clock signal under test received at one end of the second NOR gate 503 is low, the clock signal under test received at one end of the first NOR gate 502 is high. At this time, the first NOR gate 502 can only output a low-level third clock signal. Based on this, when the third clock signal received at the other end of the second NOR gate 503 is low, the second NOR gate 503 outputs a high-level fourth clock signal, that is, the other end of the first NOR gate 502 receives a high-level fourth clock signal.

[0199] Therefore, after the third clock signal and the fourth clock signal are input into the integrator 103, the sixth switching device in the integrator 103 is turned on when the third clock signal is at a high level and the fourth clock signal is at a low level.

[0200] In other embodiments, the signal processing circuit 1012 includes a third inverter 501, a first NOR gate 502, and a second NOR gate 503.

[0201] The input terminal of the third inverter 501 is coupled to the output terminal of the third switching circuit 1011, and receives the clock signal under test and the inverted signal of the clock signal under test, respectively.

[0202] The first input terminal of the first NOR gate 502 is coupled to the output terminal of the third switching circuit 1011, the second input terminal of the first NOR gate 502 is coupled to the output terminal of the second NOR gate 503, and the output terminal of the first NOR gate 502 is coupled to the integrator 103 to output a second clock signal or a fourth clock signal.

[0203] The first input terminal of the second NOR gate 503 is coupled to the output terminal of the third inverter 501, the second input terminal of the second NOR gate 503 is coupled to the output terminal of the first NOR gate 502, and the output terminal of the second NOR gate 503 is coupled to the integrator 103, outputting a first clock signal or a third clock signal.

[0204] In some embodiments, the first count value is inversely proportional to the high-level time of the clock signal under test, and the second count value is inversely proportional to the low-level time of the clock signal under test. Therefore, the control module 105 obtains the duty cycle of the clock signal under test by dividing the second count value by the sum of the first and second count values.

[0205] For example, the formula relating the first count value to the high-level time of the clock signal under test is as follows:

[0206]

[0207] Where i represents the first count value; k is a constant determined by the reference voltage value (VREF) and the integrator gain of integrator 103 (VSTEP*C1 / C3); t high This indicates the high-level duration of the clock signal under test.

[0208] For example, the formula relating the second count value to the low-level time of the clock signal under test is as follows:

[0209]

[0210] Where j represents the second count value; k is a constant determined by the reference voltage value (VREF) and the integrator gain of integrator 103 (VSTEP*C1 / C3); t low This indicates the low-level duration of the clock signal under test.

[0211] For example, the formula for defining duty cycle is Under the premise that the duty cycle of the clock signal under test can be determined as follows:

[0212]

[0213] In some embodiments, the first count value is inversely proportional to the low-level time of the clock signal under test, and the second count value is inversely proportional to the high-level time of the clock signal under test. Therefore, the control module 105 obtains the duty cycle of the clock signal under test by dividing the first count value by the sum of the first and second count values.

[0214] For example, the formula relating the first count value to the low-level time of the clock signal under test is as follows:

[0215]

[0216] Where i represents the first count value; k is a constant determined by the reference voltage value (VREF) and the integrator gain of integrator 103 (VSTEP*C1 / C3); t low This indicates the low-level duration of the clock signal under test.

[0217] For example, the formula relating the second count value to the high-level time of the clock signal under test is as follows:

[0218]

[0219] Where j represents the second count value; k is a constant determined by the reference voltage value (VREF) and the integrator gain of integrator 103 (VSTEP*C1 / C3); t high This indicates the high-level duration of the clock signal under test.

[0220] For example, the formula for defining duty cycle is Under the premise that the duty cycle of the clock signal under test can be determined as follows:

[0221]

[0222] In some embodiments, the first count value is proportional to the high-level time of the clock signal under test, and the second count value is proportional to the low-level time of the clock signal under test. Therefore, the control module 105 obtains the duty cycle of the clock signal under test by dividing the first count value by the sum of the first and second count values.

[0223] For example, the formula relating the first count value to the high-level time of the clock signal under test is as follows:

[0224] i = k × t high

[0225] Where i represents the first count value; k is a constant determined by the reference voltage value (VREF) and the integrator gain of integrator 103 (VSTEP*C1 / C3); t high This indicates the high-level duration of the clock signal under test.

[0226] For example, the formula relating the second count value to the low-level time of the clock signal under test is as follows:

[0227] j = k × t low

[0228] Where j represents the second count value; k is a constant determined by the reference voltage value (VREF) and the integrator gain of integrator 103 (VSTEP*C1 / C3); t low This indicates the low-level duration of the clock signal under test.

[0229] For example, the formula for defining duty cycle is Under the premise that the duty cycle of the clock signal under test can be determined as follows:

[0230]

[0231] In some embodiments, the first count value is proportional to the low-level time of the clock signal under test, and the second count value is proportional to the high-level time of the clock signal under test. Therefore, the control module 105 obtains the duty cycle of the clock signal under test by dividing the second count value by the sum of the first and second count values.

[0232] For example, the formula relating the first count value to the low-level time of the clock signal under test is as follows:

[0233] i = k × t low

[0234] Where i represents the first count value; k is a constant determined by the reference voltage value (VREF) and the integrator gain of integrator 103 (VSTEP*C1 / C3); t low This indicates the low-level duration of the clock signal under test.

[0235] For example, the formula relating the second count value to the high-level time of the clock signal under test is as follows:

[0236] j = k × t high

[0237] Where j represents the second count value; k is a constant determined by the reference voltage value (VREF) and the integrator gain of integrator 103 (VSTEP*C1 / C3); t high This indicates the high-level duration of the clock signal under test.

[0238] For example, the formula for defining duty cycle is Under the premise that the duty cycle of the clock signal under test can be determined as follows:

[0239]

[0240] In some embodiments, the first count value is inversely proportional to the high-level time of the clock signal under test, and the second count value is directly proportional to the low-level time of the clock signal under test. Therefore, the control module 105 obtains the duty cycle of the clock signal under test by dividing the second count value by the sum of the first and second count values.

[0241] In some embodiments, the control module 105 includes a processor. The processor involved in this application may be referred to as a CPU (Central Processing Unit), which may be an integrated circuit chip, or a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0242] In some embodiments, the control module 105 may also include a controller or other components, which are not limited herein.

[0243] In summary, in an application scenario, such as Figure 12 As shown, Figure 12 This is a schematic diagram of the duty cycle detection circuit in some embodiments of this application. The duty cycle detection circuit 10 includes a comparator 1041, an AND gate 1042, a counter 1043, a current source 1021, a first inverter 201, a first switching device 202, a second inverter 203, a second switching device 204, and a third switching device (…). Figure 12 (Signed as "S7"), the fourth switching device ( Figure 12 (Signed as "S8"), the fifth switching device ( Figure 12 (S1 is used as a symbol in the diagram) The sixth switching device ( Figure 12 (Signed as "S2"), the seventh switching device ( Figure 12 (Signed as "S3"), the eighth switching device ( Figure 12 (Signed as "S4"), the ninth switching device ( Figure 12 (Signed as "S5"), the tenth switching device ( Figure 12 (Signed as "S6"), amplifier 1032, first capacitor C1, second capacitor C2, third capacitor C3, third inverter 501, first NOR gate 502, second NOR gate 503, fourth inverter 4021 and processor 1051.

[0244] The input of the fourth inverter 4021 is used to receive the clock signal under test. Figure 12 (represented by "CLK_IN"), the output of the fourth inverter 4021 is coupled to the input of the third switching device, the output of the third switching device is coupled to the input of the third inverter 501 and the first input of the second NOR gate 503, and the input of the third inverter 501 and the first input of the second NOR gate 503 are used to receive the inverted signal of the clock signal under test. Figure 12 (represented by "CLK_SW" in the code), the output of the third inverter 501 is coupled to the output of the first NOR gate 502, the second input of the second NOR gate 503 is coupled to the output of the first NOR gate 502, and the first NOR gate 502 outputs the first clock signal ( Figure 12 The second clock signal (represented by "CK1") is input to the first inverter 201, and the second NOR gate 503 outputs the second clock signal. Figure 12 (represented by "CK2") is connected to the input terminal of the second inverter 203.

[0245] The fourth switching device is used to receive the clock signal to be measured. Figure 12 (represented by "CLK_IN"), the fourth switching device is coupled to the input of the third inverter 501 and the first input of the second NOR gate 503. The input of the third inverter 501 and the first input of the second NOR gate 503 are used to receive the clock signal under test. Figure 12 (represented by "CLK_SW" in the code), the output of the third inverter 501 is coupled to the output of the first NOR gate 502, the second input of the second NOR gate 503 is coupled to the output of the first NOR gate 502, and the first NOR gate 502 outputs the third clock signal ( Figure 12 The signal (represented by "CK1") is fed to the input of the first inverter 201, and the second NOR gate 503 outputs the fourth clock signal (…). Figure 12 (represented by "CK2") is connected to the input terminal of the second inverter 203.

[0246] The output terminal of the first inverter 201 is coupled to the control terminal of the first switching device 202, and the control terminal of the first switching device 202 is used to receive a first clock signal or a third clock signal. Figure 12 (represented by "CK1" in Chinese).

[0247] The output terminal of the second inverter 203 is coupled to the control terminal of the second switching device 204, and the control terminal of the second switching device 204 is used to receive the second clock signal or the fourth clock signal. Figure 12 (represented by "CK2" in Chinese).

[0248] The first terminal of the first switching device 202 is coupled to the output terminal of the current source 1021, the second terminal of the first switching device 202 is coupled to the first terminal of the second switching device 204, the second terminal of the second switching device 204 is grounded, the first switching device 202 is used to output a first voltage signal, and the second switching device 204 is used to output a second voltage signal.

[0249] The fifth switching device is used to receive either the first voltage signal or the second voltage signal. Figure 12 The fifth switching device (referred to as "VSTEP") is coupled to the first plate of the first capacitor C1 at the other end. The fifth switching device is connected to the first clock signal and the third clock signal. Figure 12 The first capacitor C1 is turned on or off under the control of the capacitor (represented by "CK1" in the figure). The second plate of the first capacitor C1 is coupled to the negative input terminal of the amplifier 1032. The positive input terminal of the amplifier 1032 is grounded. The output terminal of the amplifier 1032 is coupled to the counting module 104.

[0250] The sixth switching device is used to receive either the first voltage signal or the second voltage signal. Figure 12 The sixth switching device (referred to as "VSTEP") is coupled to the first plate of the first capacitor C1 at the other end. The sixth switching device is connected to the second clock signal and the fourth clock signal. Figure 12 The first capacitor C1 is turned on or off under the control of the capacitor (represented by "CK2" in the figure). The second plate of the first capacitor C1 is coupled to the negative input terminal of the amplifier 1032. The positive input terminal of the amplifier 1032 is grounded. The output terminal of the amplifier 1032 is coupled to the counting module 104.

[0251] One end of the seventh switching device is coupled to the negative input terminal of amplifier 1032, and the other end of the seventh switching device is coupled to the first plate of the second capacitor C2. The second plate of the second capacitor C2 is coupled to the output terminal of amplifier 1032.

[0252] One end of the eighth switching device is coupled to the first plate of the second capacitor C2, and the other end of the eighth switching device is grounded.

[0253] One end of the ninth switching device is coupled to the negative input terminal of amplifier 1032, and the other end of the ninth switching device is coupled to the first plate of the third capacitor C3. The second plate of the third capacitor C3 is coupled to the output terminal of amplifier 1032.

[0254] One end of the tenth switching device is coupled to the negative input terminal of amplifier 1032, and the other end of the tenth switching device is coupled to the output terminal of amplifier 1032. The tenth switching device receives a reset signal ( Figure 12 When "RST" is used as a descriptor, the circuit is activated.

[0255] The inverting input of comparator 1041 ( Figure 12 The output of amplifier 1032 is coupled to the input of comparator 1041 (indicated by "-"). The inverting input of comparator 1041 receives the third voltage signal and the fourth voltage signal respectively. Figure 12 The non-inverting input of comparator 1041 (represented by "VINTG" in Chinese) Figure 12 (Indicated by "+") is coupled to the reference voltage terminal and used to receive the reference voltage signal. Figure 12 (referred to as "VREF" in Chinese).

[0256] The first input terminal of AND gate 1042 is coupled to the output terminal of comparator 1041, and the output terminal of comparator 1041 outputs the fifth voltage signal and the sixth voltage signal. Figure 12(Indicated by "CNT_GT"), the second input of AND gate 1042 receives the enable signal ( Figure 12 (This is indicated by "CNT_EN" in Chinese).

[0257] The enable pin of counter 1043 ( Figure 12 The output of AND gate 1042 (indicated by "EN") is used to receive the seventh and eighth voltage signals, and the pulse input of counter 1043 is used to receive the seventh and eighth voltage signals. Figure 12 (In Chinese, "CLK" is used to indicate the clock signal of the counter.) Figure 12 (represented by "CLK_CNT" in Chinese), the reset pin of counter 1043 is used to receive the reset signal. Figure 12 (Used as "RST" in the diagram), the output of counter 1043 is coupled to processor 1051, and the output of counter 1043 outputs the first count value and the second count value. Figure 12 CNT is used in Chinese.<n:0> (Illustration) and stored in processor 1051.

[0258] based on Figure 12 The duty cycle detection circuit 10 shown is... Figure 12 The timing diagram of the duty cycle detection circuit 10 shown can be found in [reference]. Figure 13 .

[0259] exist Figure 13In this diagram, RST represents the reset signal; CLK_IN represents the clock signal to be tested; S7 represents the status signal of the third switching device; S8 represents the status signal of the fourth switching device; CLK_SW represents the signal of the input signal processing circuit 1012. Specifically, CLK_SW during the time period T1 to T2 is the inverted signal of the clock signal to be tested input within the first time length, and CLK_SW during the time period T3 to T4 is the clock signal to be tested input within the second time length; CK1 represents the signal output of the signal processing circuit 1012. Specifically, CK1 during the time period T1 to T2 is the first clock signal output within the first time length, and CK1 during the time period T3 to T4 is the third clock signal output within the first time length; CK2 represents the signal output of the signal processing circuit 1012. Specifically, CK2 during the time period T1 to T2 is the second clock signal output within the first time length, and CK2 during the time period T3 to T4 is the third clock signal output within the first time length. The fourth clock signal output within the first time length; VSTEP represents the first voltage signal or the second voltage signal. Specifically, VSTEP within the time period T1 to T2 is the first voltage signal output within the first time length, and VSTEP within the time period T3 to T4 is the second voltage signal output within the second time length; VINTG represents the third voltage signal or the fourth voltage signal. Specifically, VINTG within the time period T1 to T2 is the third voltage signal output within the first time length, and VINTG within the time period T3 to T4 is the fourth voltage signal output within the second time length; CNT_GT represents the fifth voltage signal or the sixth voltage signal. Specifically, CNT_GT within the time period T1 to T2 is the fifth voltage signal output within the first time length, and CNT_GT within the time period T2 to T3 is the sixth voltage signal output within the second time length; CNT_EN represents the enable signal; CLK_CNT represents the counter clock signal; CNT <n:0>This represents the first or second count value, specifically, the CNT within the time period T1 to T2. <n:0>The first count value within the first time period, CNT within the time interval T3 to T4. <n:0>This is the second count value within the second time period.

[0260] Right now, Figure 9 The corresponding duty cycle detection process is as follows:

[0261] Step 11: Set the initial state, make the RST signal valid, discharge the third capacitor C3, set the voltage VINTG (i.e. the fifth voltage signal) output by the integrator 103 to a low level, and at the same time clear the count value in the counter 1043.

[0262] Step 12: The third switch is closed, and the inverted signal of the clock signal to be tested is input to the signal processing circuit 1012. The signal processing circuit 1012 outputs CK1 and CK2 (i.e. the first clock signal and the second clock signal) which are related to the inverted signal of the clock signal to be tested. During the high level of CK1 and the low level of CK2, the charge pump 102 is controlled to charge the first capacitor C1. During the low level of CK1 and the high level of CK2, the output voltage VINTG of the integrator 103 is controlled to increase.

[0263] Step 13: The CNT_EN signal goes high. At the same time, since the VINTG voltage is lower than the reference voltage VREF in the initial stage, the CNT_GT output of comparator 1041 is high. After ANDing with CNT_EN, it outputs a high level, enabling counter 1043. The count value increases continuously under the drive of the counter clock signal CLK_CNT.

[0264] Step 14: VINTG rises under the drive of CK1 and CK2. When the voltage exceeds the reference voltage VREF, the comparator 1041 outputs low, turning off the counter 1043 and storing the current first count value i into the processor 1051. The first count value i is directly proportional to the time it takes for VINTG to rise from 0 to VREF. Since the voltage gain of the integrator 103 (i.e., VSTEP*C1 / C3) is higher, the magnitude of the VINTG rise within one measured clock cycle is greater, the VINTG rises faster, and the time for VINTG to rise from 0 to VREF is shorter. That is, the first count value i is inversely proportional to the integrator gain of the integrator 103. Since the voltage gain is directly proportional to the first time length of the first clock signal, the first count value i is inversely proportional to the first time length of the first clock signal, that is, the first count value i is related to the low-level time t of the measured clock signal. low It is inversely proportional, that is, i = k * (1 / t) low ), where k is a constant (determined by the integrator gain VSTEP*C1 / C3 and the reference voltage VREF).

[0265] Step 15: The RST signal becomes valid again, discharging the third capacitor C3. The voltage VINTG (i.e., the sixth voltage signal) output by the integrator 103 is set to a low level, and the count value in the counter 1043 is cleared to zero.

[0266] Step 16: The fourth switch is closed, transmitting the clock signal to be measured to the SW_ENB node. Repeat steps 12-14 above to obtain the high-level time t of the clock signal to be measured. high The second count value j is inversely proportional, i.e., j = k * (1 / t) low ), k is a constant, and the second count value j is stored in processor 1051.

[0267] Step 17: The clock duty cycle is defined as DR = t high / (t high +t low Based on the results of steps 14 and 16, DR = j / (i+j) can be obtained. The processor 1051 can calculate the duty cycle of the clock signal CLK_IN under test based on this relationship.

[0268] See Figure 14 , Figure 14 This is a schematic diagram of the structure of an electronic device in some embodiments of this application. The electronic device 100 includes the duty cycle detection circuit 10 described in any of the above embodiments, which will not be repeated here.

[0269] In some embodiments, electronic device 100 may be a desktop computer, a laptop computer, a smart wearable device, or other smart device, without limitation.

[0270] In some embodiments, the electronic device 100 may be a memory, which may be a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), or an optical disc, or any other medium capable of storing program code.

[0271] In one application scenario, electronic device 100 is a memory, and the memory is a double data rate static random-access memory (DDR SRAM).

[0272] In some embodiments of this application, the electronic device 100 is provided with a duty cycle detection circuit 10, which can be used to detect the duty cycle when the electronic device 100 is working, and can obtain a duty cycle detection result with high accuracy.

[0273] In summary, the duty cycle detection circuit 10 provided in some embodiments of this application can use the same device to detect the duty cycle of the first clock signal and the second clock signal, or the third clock signal and the fourth clock signal, during the clock high level and low level. By continuing to detect in a time-division manner using the same device, the first count value and the second count value can be affected in the same way when device drift or mismatch occurs. That is, the first count value and the second count value increase or decrease proportionally, but the ratio of the first count value and the second count value remains unchanged. This can avoid the impact of device drift or mismatch on the detection results, thereby improving the detection accuracy.

[0274] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A duty cycle detection circuit, characterized in that, The detection circuit includes: The signal processing module is configured to receive a clock signal under test, and output a first clock signal and a second clock signal based on the inverted signal of the clock signal under test, and output a third clock signal and a fourth clock signal based on the clock signal under test; wherein the first clock signal is the inverted signal of the second clock signal; and the third clock signal is the inverted signal of the fourth clock signal. A charge pump receives a first clock signal and a second clock signal, and outputs a first voltage signal based on the first clock signal and the second clock signal; and receives a third clock signal and a fourth clock signal, and outputs a second voltage signal based on the third clock signal and the fourth clock signal. An integrator receives the first voltage signal and outputs a third voltage signal under the control of the first clock signal and the second clock signal; and receives the second voltage signal and outputs a fourth voltage signal under the control of the third clock signal and the fourth clock signal; wherein the duration of the first clock signal and the duration of the third clock signal constitute at least one clock signal period; The counting module receives the third voltage signal, counts based on the third voltage signal, and outputs a first count value; it also receives the fourth voltage signal, counts based on the fourth voltage signal, and outputs a second count value. The control module receives the first count value and the second count value, and calculates the duty cycle of the clock signal under test based on the first count value and the second count value.

2. The detection circuit according to claim 1, characterized in that, The charge pump includes: Current source; A first switching circuit, wherein a first input terminal of the first switching circuit is coupled to the output terminal of the signal processing module, a second input terminal of the first switching circuit is coupled to the output terminal of the current source, and the first switching circuit is used to receive the first clock signal or the third clock signal. The second switching circuit has a first input terminal coupled to the output terminal of the signal processing module, a second input terminal coupled to the output terminal of the first switching circuit, and an output terminal grounded. The second switching circuit is used to receive the second clock signal or the fourth clock signal. The coupling point between the first switching circuit and the second switching circuit serves as the output terminal of the charge pump. Wherein, the first switching circuit outputs a first voltage signal whose voltage gradually increases during the high level period of the first clock signal and the low level period of the second clock signal; The first switching circuit outputs a second voltage signal whose voltage gradually increases during the high level of the third clock signal and the low level of the fourth clock signal.

3. The detection circuit according to claim 2, characterized in that, Before the second switching circuit receives the third clock signal and the fourth clock signal, the integrator has completed the discharge operation according to the reset signal.

4. The detection circuit according to claim 2, characterized in that, The first switching circuit includes a first inverter and a first switching device; the control terminal of the first switching device is coupled to the output terminal of the first inverter, the first terminal of the first switching device is coupled to the output terminal of the current source, and the input terminal of the first inverter is used to receive the first clock signal or the third clock signal. The second switching circuit includes a second inverter and a second switching device; The control terminal of the second switching device is coupled to the second inverter, the first terminal of the second switching device is coupled to the second terminal of the first switching device, the second terminal of the second switching device is grounded, and the input terminal of the second inverter is used to receive the second clock signal or the fourth clock signal.

5. The detection circuit according to claim 1, characterized in that, The integrator includes: A first switch module, wherein a first terminal of the first switch module is used to receive the first voltage signal or the second voltage signal, and a second terminal of the first switch module is grounded; An amplifier, wherein the negative input terminal of the amplifier is coupled to the third terminal of the first switching module through a first capacitor, the positive input terminal of the amplifier is grounded, and the output terminal of the amplifier is coupled to the counting module; A negative feedback circuit, wherein the first terminal of the negative feedback circuit is coupled to the output terminal of the amplifier, and the second terminal of the negative feedback circuit is coupled to the negative phase input terminal of the amplifier; Wherein, the first switching module responds to the first clock signal being at a high level and the second clock signal being at a low level by controlling the first terminal and the third terminal of the first switching module to conduct, and responds to the first clock signal being at a low level and the second clock signal being at a high level by controlling the second terminal and the third terminal of the first switching module to conduct, so that the amplifier outputs the third voltage signal; The first switching module controls the first terminal and the third terminal of the first switching module to conduct when the third clock signal is at a high level and the fourth clock signal is at a low level. When the third clock signal is at a low level and the fourth clock signal is at a high level, it controls the second terminal and the third terminal of the first switching module to conduct, so that the amplifier outputs the fourth voltage signal.

6. The detection circuit according to claim 5, characterized in that, The negative feedback circuit includes: The second switching module has a first terminal coupled to the negative input terminal of the amplifier, a second terminal grounded, and a third terminal coupled to the output terminal of the amplifier through a second capacitor. The third switching module has its first terminal coupled to the negative input terminal of the amplifier via a third capacitor, and its second terminal coupled to the output terminal of the amplifier. The second switching module responds to the first clock signal being at a high level and the second clock signal being at a low level by controlling the first and third terminals of the second switching module to conduct, forming a first negative feedback loop. The second switching module responds to the first clock signal being at a low level and the second clock signal being at a high level by controlling the conduction between the second and third terminals of the second switching module. The third switching module responds to the second clock signal being at a high level by controlling the conduction between the first and third terminals of the third switching module, thus forming a second negative feedback loop.

7. The detection circuit according to claim 6, characterized in that, The negative feedback circuit also includes: The fourth switching module has a first terminal coupled to the negative input terminal of the amplifier and a second terminal coupled to the output terminal of the amplifier. The fourth switch module responds to the reset signal and controls the first and second terminals of the fourth switch module to conduct, forming a third negative feedback loop.

8. The detection circuit according to claim 6, characterized in that, When the first switch module is connected between its second and third terminals, and when the second switch module is connected between its second and third terminals, the first capacitor is discharged, and the second capacitor is charged by the third voltage signal or the fourth voltage signal.

9. The detection circuit according to claim 7, characterized in that, The reset signal is generated after either the first count value or the second count value stops increasing.

10. The detection circuit according to claim 1, characterized in that, The counting module includes: A comparator, wherein the inverting input of the comparator is coupled to the output of the integrator, and receives the third voltage signal and the fourth voltage signal respectively, and the non-inverting input of the comparator is coupled to a reference voltage; wherein the comparator outputs a fifth voltage signal based on the third voltage signal, and the comparator outputs a sixth voltage signal based on the fourth voltage signal; An AND gate, wherein the first input of the AND gate is coupled to the output of the comparator, and the second input of the AND gate receives an enable signal; wherein the AND gate outputs a seventh voltage signal during the high level of the fifth voltage signal and the enable signal, and outputs an eighth voltage signal during the high level of the sixth voltage signal and the enable signal; The counter, whose enable terminal is coupled to the output terminal of the AND gate, receives the seventh voltage signal, counts based on the seventh voltage signal, and outputs the first count value; and receives the eighth voltage signal, counts based on the eighth voltage signal, and outputs the second count value.

11. The detection circuit according to claim 10, characterized in that, After receiving the first count value, the control module sends a reset signal to the counter and the integrator; the counter and the integrator perform a reset operation based on the reset signal.

12. The detection circuit according to claim 1, characterized in that, The signal processing module includes: The third switching circuit is used to receive the clock signal under test and output the clock signal under test and its inverted signal based on the clock signal under test. The signal processing circuit is coupled to the output terminal of the third switching circuit, receives the inverted signal of the clock signal under test, outputs the first clock signal and the second clock signal, and receives the clock signal under test and outputs the third clock signal and the fourth clock signal.

13. The detection circuit according to claim 12, characterized in that, The signal processing circuit includes: a third inverter, a first NOR gate, and a second NOR gate; The input terminal of the third inverter is coupled to the output terminal of the third switching circuit, and receives the clock signal under test and the inverted signal of the clock signal under test, respectively. The first input terminal of the first NOR gate is coupled to the output terminal of the third inverter, the second input terminal of the first NOR gate is coupled to the output terminal of the second NOR gate, and the output terminal of the first NOR gate is coupled to the charge pump, outputting the first clock signal or the third clock signal; The first input terminal of the second NOR gate is coupled to the output terminal of the third switching circuit, the second input terminal of the second NOR gate is coupled to the output terminal of the first NOR gate, and the output terminal of the second NOR gate is coupled to the charge pump, outputting the second clock signal or the fourth clock signal.

14. The detection circuit according to claim 12, characterized in that, The third switching circuit includes: A first processing circuit receives the clock signal to be tested and outputs the clock signal to be tested based on the clock signal to be tested. The second processing circuit receives the clock signal under test and outputs an inverted signal of the clock signal under test based on the clock signal under test.

15. The detection circuit according to claim 14, characterized in that, The second processing circuit includes a fourth inverter and a third switching device. When the third switching device is turned on, the fourth inverter inverts the clock signal under test and outputs the inverted signal.

16. The detection circuit according to any one of claims 1-15, characterized in that, The control module obtains the duty cycle of the clock signal under test by dividing the second count value by the sum of the first count value and the second count value; wherein, the first count value is inversely proportional to the high level time of the clock signal under test, and the second count value is inversely proportional to the low level time of the clock signal under test.

17. An electronic device, characterized in that, The electronic device includes the detection circuit according to any one of claims 1-16.

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