Synchronous dither injection apparatus, method and tester

Abstract

The application relates to a synchronous jitter injection device, method and test machine. A synchronous clock counter counts on the basis of a first preset value according to a received synchronous clock, and a synchronous counter in a channel jitter injection unit counts on the basis of a second preset value according to a received working clock. The synchronous clock and the working clock are both obtained by frequency division of a reference clock output by a main control board and have the same frequency, and the first preset value and the second preset value are respectively set according to transmission path delays of the synchronous clock and the working clock, so that the counting of the synchronous clock counter and the synchronous counter is synchronized. The channel jitter injection unit performs jitter injection on output channels between a test board card and a device to be tested based on the working clock and received adjustment parameters, realizes phase alignment between the channels, realizes accurate synchronous jitter injection across the channels, and supports on-demand selection of channel combination for jitter injection or shutdown, thereby improving test operation convenience.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, and in particular to a synchronous jitter injection device, method and testing machine. Background Technology

[0002] In the field of test equipment technology, jitter injection is used to evaluate the data recovery capability of the receiver of the device under test (DUT), thereby verifying its anti-interference performance. Traditional jitter injection schemes typically use FPGA centralized control to share the same jitter source across all channels. All channels can only be enabled or disabled uniformly, making it impossible to select specific channel combinations for synchronous perturbation according to test requirements. This lack of flexible support for selectable channel combinations results in low convenience of test operation. Summary of the Invention

[0003] Therefore, it is necessary to provide a synchronous jitter injection device, method, and testing machine that can improve the convenience of testing operations in response to the above problems.

[0004] The first aspect of this application provides a synchronous jitter injection device, comprising:

[0005] A synchronous clock counter is installed on the test board. The synchronous clock counter is used to count based on the received synchronous clock and a first preset value.

[0006] Several channel jitter injection units are set on the test board. The synchronization counter in the channel jitter injection unit counts based on the received working clock and a second preset value.

[0007] The synchronous clock and the working clock are both obtained by dividing the reference clock output by the main control board and have the same frequency. The first preset value and the second preset value are set according to the transmission path delay of the synchronous clock and the working clock, respectively, so as to synchronize the counting of the synchronous clock counter and the synchronous counter. The channel jitter injection unit injects jitter into the output channel between the test board and the device under test based on the working clock and the received adjustment parameters. The adjustment parameters are calculated based on the jitter peak value and the modulation frequency. The jitter peak value is the phase difference between the maximum phase offset of the positive jitter injection and the maximum phase offset of the negative jitter injection. The modulation frequency is the reciprocal of the modulation period. The modulation period includes a round trip process from +adjustment amplitude → -adjustment amplitude → +adjustment amplitude.

[0008] In one embodiment, the synchronization counter in the channel jitter injection unit is connected to the synchronization clock counter; the synchronization clock counter is also used to reset after receiving a reset signal and output a reset signal to the synchronization counter, and the synchronization counter is reset after receiving the reset signal output by the synchronization clock counter.

[0009] In one embodiment, the device further includes:

[0010] A buffer is set on the test board. The buffer is connected to the synchronous clock counter and connected to the main control board through a buffer chip. It receives the synchronous clock obtained by dividing the reference clock output by the main control board by the buffer chip and sends the synchronous clock to the synchronous clock counter.

[0011] The working clock buffer unit is set on the test board. The working clock buffer unit is connected to the buffer chip and the channel jitter injection unit respectively. It is used to receive the reference clock output by the buffer chip, divide the frequency and output the working clock to the channel jitter injection unit.

[0012] A reset unit is mounted on the test board. The reset unit is connected to the synchronous clock counter and connected to the main control board through the buffer chip. When the reset unit does not receive the synchronous clock output by the buffer chip, it outputs a reset signal to the synchronous clock counter.

[0013] In one embodiment, the synchronization jitter injection device includes N channel jitter injection units, each channel jitter injection unit includes M channel jitter injection modules and a logic module, the logic module includes the synchronization counter, and the logic modules in the N channel jitter injection units synchronously send adjustment parameters to the corresponding channel jitter injection modules based on the working clock and target address parameters.

[0014] In one embodiment, the channel jitter injection module includes: a jitter injection module, a phase interpolation controller, and a phase adjustment buffer module;

[0015] The jitter injection module is connected to the phase interpolation controller, the phase adjustment buffer module, and the buffer chip. It is used to perform phase modulation according to the instructions of the phase interpolation controller, inject jitter into the reference clock output by the buffer chip, and then send it to the phase adjustment buffer module.

[0016] The phase interpolation controller is connected to the logic module and the jitter injection module, and is used to send instructions to the jitter injection module according to the adjustment parameters to control the jitter injection module to perform phase modulation;

[0017] The phase adjustment buffer module is connected to the logic module and connected to the device under test through its corresponding output channel. It is used to receive the data to be transmitted sent by the logic module and send the data to be transmitted to the device under test through the corresponding output channel according to the clock signal after jitter injection.

[0018] A second aspect of this application provides a test machine including multiple test boards. Each test board includes the aforementioned synchronous jitter injection device and a buffer chip. The buffer chip is connected to the synchronous jitter injection device, divides a received reference clock to obtain a synchronous clock, and sends the synchronous clock and the reference clock to the synchronous jitter injection device so that each test board can achieve inter-board clock synchronization based on the synchronous clock. In each test board, the synchronous jitter injection device divides the reference clock to obtain a working clock, and achieves jitter injection synchronization of the output channels within the board based on the working clock.

[0019] In one embodiment, the test machine further includes a host computer and a main control board. The main control board is connected to the host computer and the buffer chip. The host computer is used to control the main control board to output or stop outputting a reference clock; or, the host computer is used to acquire jitter configuration data, parse the jitter configuration data to obtain target jitter parameters and target address parameters, calculate adjustment parameters based on the target jitter parameters, and send the adjustment parameters to the channel jitter injection unit in the corresponding test board based on the target address parameters. The target jitter parameters include jitter peak-to-peak value and modulation frequency; or, the host computer is used to acquire jitter configuration data, parse the jitter configuration data to obtain target jitter parameters and target address parameters, and calculate adjustment parameters based on the target jitter parameters and target address parameters, and send the adjustment parameters to the channel jitter injection unit in the corresponding test board based on the target address parameters. The target address parameter sends the target jitter parameter to the channel jitter injection unit in the corresponding test board. The channel jitter injection unit calculates the adjustment parameter based on the target jitter parameter. The target jitter parameter includes the jitter peak-to-peak value and the modulation frequency. Alternatively, the host computer acquires jitter configuration data, parses the jitter configuration data to obtain the target jitter parameter and the target address parameter, and sends the target address parameter and the target jitter parameter to the main control board. The main control board calculates the adjustment parameter based on the target jitter parameter and sends the adjustment parameter to the channel jitter injection unit in the corresponding test board based on the target address parameter. The target jitter parameter includes the jitter peak-to-peak value and the modulation frequency.

[0020] In one embodiment, the adjustment parameters include the number of adjustments and the PI value per step; the number of adjustments is calculated using the modulation frequency and the clock cycle of the operating clock used by the channel jitter injection unit, and the PI value per step is calculated based on the jitter peak-to-peak value and the number of adjustments.

[0021] In one embodiment, the test board further includes pin electronics, with each channel dithering injection unit connected to a corresponding pin electronics. The signal input terminal of each pin electronics is connected to the output channel of the channel dithering injection unit, and the output terminal of each pin electronics is connected to the device under test (DUT) via a protocol channel.

[0022] If the pin electronics are compatible with the D-PHY protocol, the jitter injection modules of each channel connected to the two protocol channels occupied by the D-PHY protocol receive the same adjustment parameters, so that each of the channel jitter injection modules performs the same jitter injection synchronously.

[0023] If the pin electronics are compatible with the C-PHY protocol, the jitter injection modules connected to the three protocol channels occupied by the C-PHY receive the same adjustment parameters, so that each of the channel jitter injection modules performs the same jitter injection synchronously.

[0024] A third aspect of this application provides a synchronization jitter injection method, implemented based on the aforementioned test machine, comprising:

[0025] The reference clock output from the main control board is divided to obtain a synchronous clock and a working clock with the same frequency;

[0026] The synchronization clock counter counts based on the received synchronization clock, according to a first preset value.

[0027] The synchronization counter in the channel jitter injection unit counts based on the received working clock, according to a second preset value.

[0028] The channel jitter injection unit injects jitter into the output channel between the test board and the device under test based on the operating clock and adjustment parameters. The adjustment parameters are calculated based on the jitter peak-to-peak value and the modulation frequency. The jitter peak-to-peak value is the phase difference between the maximum phase offset of the positive jitter injection and the maximum phase offset of the negative jitter injection. The modulation frequency is the reciprocal of the modulation period, and the modulation period includes a round trip from +adjustment amplitude → -adjustment amplitude → +adjustment amplitude.

[0029] In one embodiment, the process further includes the following steps prior to the synchronization jitter injection:

[0030] Disconnect the buffer chip from the main control board and stop receiving the reference clock;

[0031] The synchronous clock counter in each test board outputs a high-level signal after the reference clock is disconnected, and also outputs a high-level signal to the synchronous counter, triggering the synchronous clock counter and the synchronous counter reset.

[0032] The aforementioned synchronous jitter injection device, method, and testing machine include a synchronous clock counter mounted on the test board. Based on the received synchronous clock, the counter counts based on a first preset value. Several channel jitter injection units are also mounted on the test board. The synchronous counters in each channel jitter injection unit count based on the received operating clock, based on a second preset value. Both the synchronous clock and the operating clock are obtained by dividing the reference clock output from the main control board and have the same frequency. The first and second preset values ​​are set according to the transmission path delays of the synchronous clock and the operating clock, respectively, to ensure synchronized counting by the synchronous clock counters and the synchronous counters. The channel jitter injection units inject jitter into the output channels between the test board and the device under test based on the operating clock and received adjustment parameters, achieving phase alignment between channels and precise synchronous jitter injection across channels. Furthermore, the system supports selecting channel combinations for jitter injection or disabling as needed, improving the convenience of test operations. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the synchronous jitter injection device in one embodiment;

[0034] Figure 2 This is a structural block diagram of the test machine in one embodiment;

[0035] Figure 3 This is a timing diagram of synchronous jitter injection in one embodiment;

[0036] Figure 4 This is a schematic diagram of the channel jitter injection module in one embodiment;

[0037] Figure 5 This is a schematic diagram illustrating the principle of jitter injection by adjusting the phase interpolator in one embodiment;

[0038] Figure 6 This is a schematic diagram of three-channel synchronous jitter injection in a C-PHY protocol embodiment. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. It is understood that the term "connection" in the following embodiments, if the connected circuits, modules, units, etc., transmit electrical signals or data to each other, should be understood as "electrical connection," "communication connection," etc.

[0041] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0042] In one embodiment, such as Figure 1 As shown, a synchronous jitter injection device is provided, including a channel jitter injection unit 100 and a synchronous clock counter 102 disposed on a test board. The number of channel jitter injection units 100 can be one or more. The synchronous clock counter 102 is used to count based on a first preset value according to the received synchronous clock. The synchronous counter 104 in the channel jitter injection unit 100 counts based on a second preset value according to the received working clock. The synchronous clock and the working clock are both obtained by dividing the reference clock output by the main control board and have the same frequency. The first preset value and the second preset value are set according to the transmission path delay of the synchronous clock and the working clock, respectively, so as to synchronize the counting of the synchronous clock counter 102 and the synchronous counter 104. The channel jitter injection unit 100 injects jitter into the output channel between the test board and the device under test based on the working clock and the received adjustment parameters. The adjustment parameters are calculated based on the jitter peak-to-peak value UIp-p and the modulation frequency. The jitter peak-to-peak value UIp-p is the phase difference between the maximum phase offset of the positive jitter injection and the maximum phase offset of the negative jitter injection. The modulation frequency is the reciprocal of the modulation period. The modulation period includes a round trip from +adjustment amplitude → -adjustment amplitude → +adjustment amplitude.

[0043] Specifically, such as Figure 1As shown, the test machine includes a main control board and test boards, which can specifically be digital test boards. The number of test boards can be one or more. Each test board is equipped with a synchronous jitter injection device and a buffer chip. The buffer chip is connected to both the main control board and the synchronous jitter injection device. In other embodiments, the buffer chip can also be located outside the test board, connecting the main control board and the synchronous jitter injection device within the test board. The main control board has a reference clock source that sends a reference clock to the buffer chip. The buffer chip divides the received reference clock to obtain a synchronous clock and sends both the synchronous clock and the reference clock to the synchronous jitter injection device. The synchronous jitter injection device receives the synchronous clock and divides it based on the reference clock to obtain a working clock. The synchronous clock is used to unify the counting operation of the synchronous clock counter 102 in each test board, enabling clock synchronization between boards based on the synchronous clock. The working clock is used to unify the counting operation of the synchronous counter 104 in each channel jitter injection unit 100. The synchronous counter 104 is synchronized based on the working clock, so that the synchronous jitter injection unit 100 in each test board realizes the channel clock synchronization within the board based on the working clock. Then, the channel jitter injection unit 100 injects jitter into the output channel between the test board and the device under test based on the working clock and the received adjustment parameters. The synchronous clock counter 102 counts based on a first preset value and the synchronous counter 104 counts based on a second preset value, so that the counting of the synchronous clock counter 104 and the synchronous counter 102 is synchronized, thereby realizing the synchronization of channel jitter injection within each test board.

[0044] The synchronous jitter injection device includes N channel jitter injection units 100. Each channel jitter injection unit 100 includes M channel jitter injection modules and a logic module. The logic module includes a synchronization counter 104. The synchronization counter 104 counts based on the received working clock and a second preset value, thereby achieving synchronous counting of the synchronization counters 104 in the N channel jitter injection units 100 to synchronize the working clocks of the N channel jitter injection units 100. The logic modules in the N channel jitter injection units 100 synchronously send adjustment parameters to the corresponding channel jitter injection modules based on the working clock and target address parameters to synchronize the jitter injection of the corresponding channels on the test board, where N is greater than or equal to 1 and M is greater than or equal to 1.

[0045] Furthermore, such as Figure 3As shown, the synchronous jitter injection device also includes a working clock buffer unit BUFG_GT_DIV. The working clock buffer unit BUFG_GT_DIV is connected to the buffer chip and the logic module 110 respectively. The working clock buffer unit BUFG_GT_DIV is used to receive the reference clock output by the buffer chip, divide it and output the working clock to the logic module 110. Specifically, the working clock is output to the synchronous counter.

[0046] like Figure 2 As shown, the test board is a digital test board. The channel jitter injection unit 100 can be a Serdes Quad (serializer / deserializer). The Serdes Quad (serializer / deserializer) includes four output channels, which can be high-speed channels. The Serdes Quad contains four channel jitter injection modules that correspond one-to-one with the output channels. In this embodiment, the digital test board includes N+1 channel jitter injection units 100 Serdes Quad (Quad0, Quad1, ..., QuadN). Each output channel of each Serdes Quad is configured to transmit mode, and the corresponding output channel connected to each Serdes Quad sends the test data to the device under test (DUT). Specifically, each Serdes Quad is equipped with four channel jitter injection modules. The channel jitter injection modules inject jitter into the corresponding output channels between the Serdes Quad and the DUT based on the working clock and the received adjustment parameters, thereby achieving high-precision synchronous jitter injection across channels.

[0047] The buffer chip divides the reference clock sent by the main control board to obtain a synchronization clock. Specifically, to ensure that the obtained synchronization clock and the working clock have the same frequency, the division coefficient of the frequency divider corresponding to the synchronization clock counter 102 in the buffer chip can be set to the same value as the division coefficient of the frequency divider in the working clock buffer unit BUFG_GT_DIV (for example, both can be divided by 2). The synchronization clock and the working clock have the same frequency, which further ensures multi-channel synchronization between test machine boards.

[0048] The test unit may also include a host computer connected to the main control board. The host computer controls the main control board to output or stop outputting a reference clock. Simultaneously, the host computer acquires jitter configuration data, parses the jitter configuration data to obtain target jitter parameters and target address parameters, and selects channel combinations for jitter injection or shutdown based on the target address parameters. Specifically, adjustment parameters are calculated based on the target jitter parameters, and these adjustment parameters are sent to the channel jitter injection module in the corresponding test board based on the target address parameters. The target jitter parameters include the jitter peak-to-peak value UIp-p and the modulation frequency, while the adjustment parameters may include the number of adjustments and the PI value per step.

[0049] Testers can input jitter configuration data through the human-machine interface according to actual testing needs, and select to perform jitter injection on all or some channels of the jitter injection modules on all or some test boards, thereby realizing jitter injection on the corresponding output channels. After the host computer parses the jitter configuration data to obtain the target jitter parameters and target address parameters, it calculates the adjustment parameters based on the target jitter parameters, and sends the adjustment parameters based on the target address parameters to control all or some channels of the jitter injection modules on the corresponding test boards to synchronously perform channel jitter injection, and the jitter injected into each channel can be the same or different. The host computer can communicate directly with the test board to send the adjustment parameters, or it can communicate with the main control board to send the adjustment parameters, which are then forwarded by the main control board to the channel jitter injection modules in the corresponding test boards.

[0050] It is understood that in other embodiments, the host computer may directly send the target address parameters and target jitter parameters to the main control board, which then calculates the adjustment parameters based on the target jitter parameters and sends the adjustment parameters to the channel jitter injection unit 100 in the corresponding test board based on the target address parameters. Alternatively, the host computer may send the target jitter parameters directly or indirectly to the channel jitter injection unit 100 in the corresponding test board based on the target address parameters. The channel jitter injection unit 100 calculates the adjustment parameters based on the target jitter parameters and then injects jitter into the output channel between the channel jitter injection module and the device under test (DUT) based on the operating clock, target address parameters, and adjustment parameters.

[0051] The host computer selects channel combinations for jitter injection or shutdown as needed based on jitter configuration data, enabling some or all channel jitter injection modules to perform jitter injection without wasting channel jitter injection module resources, and performing jitter injection operations on all channels, thus providing high flexibility.

[0052] Furthermore, the test board also includes pin electronics, with a channel dithering injection unit connected to each pin electronics in a one-to-one correspondence. The signal input terminals of the pin electronics are connected to the output channels of the channel dithering injection units, and the output terminals of the pin electronics are connected to the device under test (DUT) via a protocol channel.

[0053] If the pin electronics are compatible with the D-PHY protocol, the jitter injection modules of each channel connected to the two protocol channels occupied by the D-PHY protocol receive the same adjustment parameters, so that each of the channel jitter injection modules performs the same jitter injection synchronously.

[0054] If the pin electronics are compatible with the C-PHY protocol, the jitter injection modules of each channel connected to the three protocol channels occupied by C-PHY receive the same adjustment parameters so that each channel jitter injection module performs the same jitter injection synchronously.

[0055] For example, in practical applications, the D-PHY protocol occupies any two protocol channels to form a differential pair, with one channel serving as the P terminal and the other as the N terminal; the C-PHY protocol occupies any three protocol channels to form a three-wire (Trio) transmission structure, with each channel supporting three-level signals (VIH / VIL / VIT). When performing jitter injection testing, precise phase perturbation can be applied to the multiple protocol channels participating in the protocol to ensure that the jitter edges are aligned in each relevant channel, thereby achieving effective synchronous jitter injection.

[0056] In one embodiment, the host computer has a mapping table, which is used to identify the mapping relationship between the output channel of the channel jitter injection unit and the protocol channel connected to the output terminal of the pin electronics. The dynamic configuration data is determined based on the protocol channel of the pin electronics occupied by the target protocol and the mapping table, so that each channel jitter injection module corresponding to the target protocol performs jitter injection synchronously according to the same target jitter parameters. There are two or more target protocols, and the target jitter parameters of each target protocol are the same or different.

[0057] Specifically, based on the pin electronics adaptation protocol, the corresponding target protocol channel is determined. Based on the mapping table, the corresponding output channel can be determined, and thus the corresponding channel jitter injection module is identified. The target jitter parameters and target address parameters are then combined into jitter configuration data, enabling each channel jitter injection module corresponding to the target protocol to synchronously inject jitter according to the same target jitter parameters. Specifically, the target address parameter can be the identifier of the channel jitter injection module or the identifier of the output channel corresponding to each channel jitter injection module. In this embodiment, the target address parameter is the identifier of the output channel corresponding to each channel jitter injection module.

[0058] The channel jitter injection modules corresponding to the protocol channels occupied by the D-PHY protocol for the pin-mounted electronic device adapter can belong to the same channel jitter injection unit (Serdes Quad), different channel jitter injection units (Serdes Quad), or even different channel jitter injection units (Serdes Quad) on different test boards. Similarly, the three protocol channels occupied by the C-PHY protocol can also belong to the same channel jitter injection unit (Serdes Quad), different channel jitter injection units (Serdes Quad), or different channel jitter injection units (Serdes Quad) on different test boards.

[0059] like Figure 6As shown, taking C-PHY protocol synchronous jitter injection as an example, channel jitter injection unit QUAD0 is connected to the device under test (DUT) via pin electronics PE0, and channel jitter injection unit QUAD1 is connected to the DUT via pin electronics PE1. The output channel of each channel jitter injection unit QUAD transmits data signals DAT0, DAT1, RCV0, and RCV1 to the corresponding pin electronics PE. The pin electronics PE are connected to the DUT via the corresponding protocol channel. The C-PHY protocol requires three protocol channels, specifically including C-PHY... - 1. C-PHY - 2. C-PHY - 3. The three protocol channels of pin electronic devices PE0 and PE1 are occupied respectively. According to the mapping table, the mapping table includes the output channels lane0 and lane1 of pin electronic device QUAD0 and the protocol channel C-PHY of pin electronic device PE0. - Corresponding to 1, the output channels lane2 and lane3 of pin electronics QUAD0 correspond to the protocol channel C-PHY of pin electronics PE0. - Correspondingly, the output channels lane0 and lane1 of pin electronics QUAD1 correspond to the protocol channel C-PHY of pin electronics PE1. - 3 correspondence. In this embodiment, the target address parameter can be QUAD0-lane0, QUAD0-lane1, QUAD0-lane2, QUAD0-lane3, QUAD1-lane0, QUAD1-lane1, QUAD1-lane2, QUAD1-lane3.

[0060] Based on a defined protocol channel C-PHY - 1. C-PHY - 2. C-PHY - 3. Determine the corresponding channel jitter injection unit and channel jitter injection unit module according to the mapping table, that is, determine the target address parameters. Based on the same adjustment parameters, perform jitter injection on the channel jitter injection unit module synchronously. This can synchronously perform the same jitter injection on the protocol channel used by the C-PHY protocol.

[0061] The DATA (including DAT0 and DAT1) and RCV (including RCV0 and RCV1) outputs from the channel jitter injection unit determine the C-PHY output level of the PE, including high, low, and intermediate levels. Through the channel jitter injection modules in QUAD0 and QUAD1, the same jitter injection (with identical adjustment parameters) can be synchronously applied to the channels used by the C-PHY protocol. Of course, multiple C-PHY protocols can be used; the same operation can be applied to jitter injection for multiple C-PHY protocol channels. The adjustment parameters for different C-PHY protocols can be the same or different.

[0062] In one embodiment, the synchronous counting of synchronous clock counter 102 and synchronous counter 104 can be divided into two cases: after the test machine is initially powered on, the host computer controls the main control board to output a reference clock, and synchronous clock counter 102 and synchronous counter 104 can directly perform synchronous counting based on the corresponding clock and preset value; during the test, synchronous clock counter 102 and synchronous counter 104 can also be reset according to actual needs, and then the reset synchronous clock counter 102 and synchronous counter 104 can be controlled to perform synchronous counting based on the corresponding clock and preset value.

[0063] It is understandable that there is no single way to reset the synchronous clock counter 102 and synchronous counter 104. For example, it can be done by controlling the main control board to stop outputting the reference clock to reset the synchronous clock counter 102 and synchronous counter 104, or it can be done by the main control board directly sending a reset signal to the synchronous clock counter 102 and synchronous counter 104 to reset them.

[0064] In one embodiment, continue to refer to Figure 1 The synchronous counter 104 in the channel jitter injection unit 100 is connected to the synchronous clock counter 102; the synchronous clock counter 102 is also used to reset after receiving a reset signal and output a reset signal to the synchronous counter 104, and the synchronous counter 104 is reset after receiving the reset signal output by the synchronous clock counter.

[0065] Furthermore, the synchronous jitter injection device also includes a buffer BUFG and a reset unit 106 mounted on the test board. The buffer BUFG is connected to the synchronous clock counter 102 and connected to the main control board via a buffer chip. It receives the synchronous clock obtained by dividing the reference clock output by the main control board by the buffer chip and sends the synchronous clock to the synchronous clock counter 102. The reset unit 106 is connected to the synchronous clock counter 102 and connected to the main control board via a buffer chip. When the reset unit 106 does not receive the synchronous clock output by the buffer chip, it outputs a reset signal to the synchronous clock counter 102, so that the synchronous clock counter 102 resets upon receiving the reset signal and outputs a reset signal to the synchronous counter 104. The synchronous counter 104 resets upon receiving the reset signal output by the synchronous clock counter 102.

[0066] Specifically, the type of reset signal is not unique; it can be a high-level signal or a low-level signal. In this embodiment, the reset signal is a high-level signal. The channel jitter injection unit 100, the working clock buffer unit BUFG_GT_DIV, the synchronous clock counter 102, the reset unit 106, and the buffer BUFG can be set in the FPGA of the test board. The reset unit 106 adopts the clock management unit in the FPGA, such as MMCM (Mixed Mode Clock Manager). The reset input terminal rst_in of the synchronous clock counter 102 is connected to the reset unit 106 and receives the clk_stop signal output by the reset unit 106. The clock input terminal clk of the synchronous clock counter 102 is connected to the buffer BUFG. The reset output terminal rst_out of the synchronous clock counter 102 is connected to the reset terminal rst of the synchronous counter 104 inside each channel jitter injection unit 100. The clock terminal of the synchronous counter 104 is used to receive the working clock. In this embodiment, the reference clock is accessed through the internal working clock buffer unit BUFG_GT_DIV for buffering and frequency division, and the working clock is output to the clock input terminal clk of the synchronization counter 104.

[0067] like Figure 1 and Figure 3As shown, when resetting the synchronous clock counters 102 and 104, the reference clock output from the main control board is first disconnected. After the reference clock is disconnected, the synchronous clock counter 102 in each test board pulls the clk_stop signal high (i.e., outputs a high-level signal). After the clk_stop signal goes high, the synchronous clock counter 102 outputs a high-level signal to the synchronous counter 104, thereby triggering the reset of both synchronous clock counters 102 and 104. The rising edge of the clk_stop signal is used to asynchronously reset the synchronous clock counters 102 in each test board and the synchronous counter 104 inside each channel jitter injection unit 100, clearing the counts of the synchronous clock counters 102 and 104 to zero. After the main control board restores the output reference clock, the synchronous clock counters 102 and 104 resume counting: the synchronous clock counter 102 increments from the value 2 (to compensate for the 2 cycles lost by the clock path through the buffer chip), that is, the first preset value is 2; the synchronous counter 104 in each channel jitter injection module unit increments from the value 3 (wherein, the buffer chip introduces a 2-cycle delay, and the working clock buffer unit BUFG_GT_DIV introduces another 1-cycle delay, with a cumulative delay of 3 clock cycles), that is, the second preset value is 3.

[0068] After the synchronous clock counters 102 and 104 resume counting, the channel jitter injection modules in each test board inject jitter into the corresponding output channels between the test board and the device under test (DUT) based on the working clock and the received adjustment parameters. By using a unified synchronous count, phase alignment is achieved between the synchronous clock, within each channel jitter injection unit, and between channels across test boards. This allows for the selection of a unified count value for jitter injection during the jitter injection process, achieving precise synchronous control across channel jitter injection module units and across boards. Through this mechanism, channels in different clock domains can maintain consistent counts, achieving high-precision, multi-channel synchronous jitter injection.

[0069] In one embodiment, such as Figure 4 As shown, the channel jitter injection module includes a jitter injection module 120, a phase interpolation controller 130, and a phase adjustment buffer module 140, wherein:

[0070] The logic module 110 is equipped with a synchronization counter 104. The logic module 110 is used to send adjustment parameters to the phase interpolation controller 130 based on the working clock, and to send data to be sent to the phase adjustment buffer module 140. The adjustment parameters are calculated based on the target jitter parameters, and may include the number of adjustments and the PI value per step.

[0071] The jitter injection module 120 is connected to the phase interpolation controller 130, the phase adjustment buffer module 140 and the buffer chip. It is used to perform phase modulation according to the instructions of the phase interpolation controller 130, inject jitter into the reference clock refclk output by the buffer chip and then send it to the phase adjustment buffer module 140.

[0072] The phase interpolation controller 130 connects the logic module 110 and the jitter injection module 120, and is used to send instructions to the jitter injection module 120 according to the adjustment parameters to control the jitter injection module 120 to perform phase modulation.

[0073] The phase adjustment buffer module 140 is connected to the logic module 110 and to the device under test (DUT) through a corresponding output channel. It is used to receive the data to be transmitted sent by the logic module 110 and to send the data to be transmitted to the DUT through the corresponding output channel according to the clock signal after jitter injection.

[0074] Each channel jitter injection module is equipped with a jitter injection module 120, a phase interpolation controller 130, and a phase adjustment buffer module 140. The phase adjustment buffer module 140 is connected to the device under test (DUT) through a corresponding output channel. Each channel jitter injection module of the Serdes Quad channel jitter injection unit in the test board is equipped with an independent jitter injection module 120, a phase interpolation controller 130, and a phase adjustment buffer module 140. By independently controlling phase adjustment, the clock phase of the output channel can be precisely adjusted.

[0075] The specific structure of the jitter injection module 120 is not unique; in one embodiment, refer to... Figure 4The jitter injection module 120 is a Physical Media Adaptor (PMA) module. The jitter injection module 120 includes a phase-locked loop (PLL) unit 122, a transmit phase interpolator (PI) 124, and a frequency divider unit 126. The phase interpolator 124 is connected to the PLL unit 122, the frequency divider unit 126, and the phase interpolation controller 130. The frequency divider unit 126 is connected to the phase adjustment buffer module 140. The PLL unit 122 performs frequency multiplication on the input reference clock refclk and outputs a high-speed PMA clock to the phase interpolator 124. The phase interpolator 124 performs phase modulation according to the instructions of the phase interpolation controller 130 to inject jitter into the high-speed PMA clock and outputs the jitter-injected high-speed PMA clock to the frequency divider unit 126. The frequency divider unit 126 divides the jitter-injected high-speed PMA clock and outputs a low-speed PMA clock to the phase adjustment buffer module 140. The peak-to-peak jitter value UIp-p is determined based on the frequency of the reference clock refclk, the multiplication factor of the phase-locked loop unit 122, the division factor D of the frequency divider unit 126, and the unit interval (1UI) multiple. The division factor D of the frequency divider unit 126 can be 1 or 2, and the unit interval multiple is greater than or equal to 1.

[0076] The phase-locked loop (PLL) unit 122 can be a QPLL (Quarter Rate PLL) unit or other types of PLLs. In this embodiment, the reference clock refclk is first multiplied by the QPLL unit (e.g., A-multiplication, i.e., the multiplication factor is A) to generate a high-speed PMA clock, which is then fed into the phase interpolator 124 for jitter injection. The jittered high-speed PMA clock is then divided by the frequency divider unit 126 to output a low-speed PMA clock to the phase adjustment buffer module 140. The specific frequencies of the high-speed PMA clock and the low-speed PMA clock are not unique. In this embodiment, the frequency of the high-speed PMA clock is greater than the frequency of the reference clock refclk, and the frequency of the low-speed PMA clock is less than or equal to the frequency of the jittered high-speed PMA clock.

[0077] In one embodiment, the jitter injection module 120 further includes a receive clock buffer unit 128, which is connected to the phase adjustment buffer module 140. The receive clock buffer unit 128 receives a reference clock (refclk) for buffering and outputs a high-speed PCS (Physical Coding Sublayer) clock to the phase adjustment buffer module 140. Specifically, the receive clock buffer unit 128 has a frequency multiplication function; receiving the reference clock (refclk) for buffering involves multiplying its frequency. The phase adjustment buffer module 140 reads the data to be transmitted based on the high-speed PCS clock for buffering and reads the data to be transmitted based on the low-speed PMA clock, sending it to the device under test through the corresponding channel. Each channel jitter injection unit (Serdes Quad) can share the same logic module 110.

[0078] In one embodiment, each channel jitter injection unit Serdes Quad can share the same logic module 110, phase-locked loop unit 122, receive clock buffer unit 128, and working clock buffer unit BUFG_GT_DIV. Each channel jitter injection module is equipped with a jitter injection module 120, a phase interpolation controller 130, and a phase adjustment buffer module 140. The jitter injection module 120 includes a phase interpolator 124 and a frequency divider unit 126 to synchronously inject jitter into the corresponding output channel.

[0079] In one embodiment, the phase adjustment buffer module 140 includes a phase adjustment unit 142 and a transmitting unit 144. The phase adjustment unit 142 is connected to the logic module 110, the frequency divider unit 126, the receive clock buffer unit 128, and the transmitting unit 144. The transmitting unit 144 is connected to the device under test (DUT) through a corresponding output channel. The phase adjustment unit 142 reads the data to be transmitted based on the PCS high-speed clock for buffering and reads the data to be transmitted based on the PMA low-speed clock and sends it to the transmitting unit 144. The transmitting unit 144 sends the data to be transmitted to the DUT through the corresponding output channel. The receive clock buffer unit 128 can be a global buffer unit, inputting a reference clock refclk and outputting the PCS high-speed clock to the phase adjustment unit 142. The frequency of the PCS high-speed clock is greater than the frequency of the reference clock refclk, and its frequency can be the same as or different from the frequency of the PMA low-speed clock. In this embodiment, the PCS high-speed clock and the PMA low-speed clock have the same frequency but different phases. The phase adjustment unit can be a FIFO (First In First Out) buffer, or any other memory, as long as it can buffer the data to be sent.

[0080] The working clock buffer unit BUFG_GT_DIV can also be a global buffer unit, connected to the reference clock refclk, and outputting a low-speed PCS clock to the logic module 110 as the working clock of the logic module 110. Specifically, the working clock buffer unit BUFG_GT_DIV has a frequency division function, connected to the reference clock refclk and performing frequency division operation on it, outputting a low-speed PCS clock to the logic module 110. The logic module 110 sends the number of adjustments and the PI value per step to the phase interpolation controller 130 based on the working clock. The frequency of the low-speed PCS clock is lower than the frequency of the high-speed PCS clock. In this embodiment, the frequency of the low-speed PCS clock is half the frequency of the reference clock refclk, and the same as the frequency of the synchronization clock received by the synchronization clock counter 102.

[0081] In one embodiment, such as Figure 1 As shown, a test machine is also provided, including multiple test boards. Each test board includes the aforementioned synchronous jitter injection device and buffer chip. The buffer chip is connected to the synchronous jitter injection device, which divides the received reference clock to obtain a synchronous clock. The synchronous clock and the reference clock are sent to the synchronous jitter injection device so that the test boards can achieve inter-board clock synchronization based on the synchronous clock. The synchronous jitter injection device in each test board divides the reference clock to obtain a working clock, and achieves channel jitter injection synchronization within the board based on the working clock.

[0082] Furthermore, the test unit also includes a host computer and a main control board. The main control board connects the host computer and the buffer chip. The host computer controls the main control board to output or stop outputting a reference clock. Alternatively, the host computer acquires jitter configuration data, parses the jitter configuration data to obtain target jitter parameters and target address parameters, calculates adjustment parameters based on the target jitter parameters, and sends the adjustment parameters to the channel jitter injection unit in the corresponding test board based on the target address parameters. The target jitter parameters include the jitter peak-to-peak value and the modulation frequency. Alternatively, the host computer acquires jitter configuration data, parses the jitter configuration data to obtain target jitter parameters and target address parameters, and sends the target jitter parameters to the channel jitter injection unit in the corresponding test board based on the target address parameters. The channel jitter injection unit calculates the adjustment parameters based on the target jitter parameters, which include the jitter peak-to-peak value and the modulation frequency. Alternatively, the host computer can acquire jitter configuration data, parse the jitter configuration data to obtain target jitter parameters and target address parameters, and send the target address parameters and target jitter parameters to the main control board. The main control board calculates the adjustment parameters based on the target jitter parameters and sends the adjustment parameters to the channel jitter injection unit in the corresponding test board based on the target address parameters. The target jitter parameters include jitter peak-to-peak value and modulation frequency.

[0083] The buffer chip includes a first buffer unit Buffera and a second buffer unit Bufferb. The first buffer unit Buffera is connected to the main control board, the second buffer unit Bufferb, and the synchronous jitter injection device. The second buffer unit Bufferb is connected to the synchronous jitter injection device. The first buffer unit Buffera divides the reference clock output by the main control board to obtain a synchronous clock, outputs the synchronous clock to the synchronous jitter injection device, and sends the reference clock to the second buffer unit Bufferb. The second buffer unit Bufferb sends the reference clock to the synchronous jitter injection device, and the synchronous jitter injection device divides the reference clock sent by the second buffer unit Bufferb to obtain the working clock.

[0084] In one embodiment, the adjustment parameters include the number of adjustments and the PI value per step. The number of adjustments is calculated using the modulation frequency and the clock cycle of the operating clock used by the channel jitter injection unit, and the PI value per step is calculated based on the jitter peak-to-peak value and the number of adjustments.

[0085] like Figure 4 As shown, taking the phase-locked loop unit 122 using a QPLL and the QPLL performing A-fold frequency multiplication as an example, the basic principle of the phase interpolator 124 adjustment is as follows:

[0086] QPLL output frequency = reference clock frequency × A;

[0087] SerDes line rate = QPLL output frequency / D (D is the frequency division factor);

[0088] Unit interval (1UI) = 1 / SerDes linear rate;

[0089] Single-step PI control accuracy (1PI) = 1UI / (B×D).

[0090] The architecture described in this application achieves jitter injection adjustment accuracy within the range of approximately 2 ps. Each PI adjustment supports a maximum phase shift of ±15 PI. If the required jitter injection amplitude exceeds this range, it can be achieved through multiple consecutive adjustments.

[0091] Jitter injection is achieved by adjusting the phase interpolator 124. The phase interpolator 124 dynamically adjusts the phase of the clock signal, thereby generating controllable jitter. For example... Figure 5 As shown, the black curve represents the original PMA high-speed clock, the red curve represents the maximum phase shift (+Δ) injected by positive jitter, and the blue curve represents the maximum phase shift (-Δ) injected by negative jitter. The phase difference between the two is the jitter peak-to-peak value UIp-p. Within the set adjustment range, the time required to complete one full phase modulation is the modulation period, and its reciprocal corresponds to the jitter modulation frequency.

[0092] The peak-to-peak value of jitter, UIp-p, is defined as: UIp-p = (+adjustment amplitude) - (-adjustment amplitude) = 2 × (+adjustment amplitude). A complete modulation cycle consists of a round trip from +adjustment amplitude → -adjustment amplitude → +adjustment amplitude, which completes one full waveform jitter modulation. The time required for this process is defined as the modulation cycle.

[0093] The adjustment operation of logic module 110 is controlled based on the PCS low-speed clock (frequency is the reference clock frequency ÷ 2). Since each PI adjustment requires two PCS low-speed clock cycles, the minimum time interval for each PI value update is 2×M (M is the PCS low-speed clock cycle).

[0094] Assuming the number of adjustments is N (i.e., the number of steps from -adjustment range to +adjustment range or vice versa), the adjustment clock period is M (i.e., the PCS low-speed clock period), and the adjustment step of the phase interpolator 124 is X (unit: PI), then:

[0095] Modulation period = 2 × N × 2 × M (including 2 segments of linear adjustment: +max → -max, -max → +max);

[0096] The peak-to-peak value of jitter, UIp-p, is equal to N×X (unit: PI).

[0097] By reversing the above formula, we can obtain:

[0098] Number of adjustments N = (modulation period / M) / 4;

[0099] The PI step size for each adjustment (PI value per step) X = jitter peak-to-peak value UIp - p / N.

[0100] After setting the target jitter parameters (jitter peak-to-peak value UIp-p and modulation frequency) according to the actual test requirements, the host computer calculates the required number of adjustments N and the PI value X per step using the above formula and sends it to the logic module 110 in the jitter injection unit 100 of the corresponding channel. The logic module 110 sends the number of adjustments N and the PI value X per step to the phase interpolation controller 130 based on the working clock. After receiving the number of adjustments N and the PI value X per step, the phase interpolation controller 130 controls the phase interpolator 124 to perform phase modulation according to the steps and timing, thereby realizing accurate periodic jitter injection.

[0101] Alternatively, the channel jitter injection unit can calculate the adjustment parameters based on the received target jitter parameters using the formula above; or the main control board can calculate the adjustment parameters based on the received target jitter parameters using the formula above, and then send the adjustment parameters to the channel jitter injection unit in the corresponding test board based on the target address parameters.

[0102] In one embodiment, a synchronization jitter injection method is also provided, implemented based on the aforementioned test machine, including:

[0103] The reference clock output from the main control board is divided to obtain a synchronous clock and a working clock with the same frequency. The synchronous clock counter counts based on the received synchronous clock, based on a first preset value. The synchronous counter in the channel jitter injection unit counts based on the received working clock, based on a second preset value. The channel jitter injection unit injects jitter into the output channel between the test board and the device under test based on the working clock and adjustment parameters. The adjustment parameters are calculated based on the jitter peak-to-peak value and the modulation frequency. The jitter peak-to-peak value is the phase difference between the maximum phase offset of the positive jitter injection and the maximum phase offset of the negative jitter injection. The modulation frequency is the reciprocal of the modulation period. The modulation period includes a round trip from +adjustment amplitude → -adjustment amplitude → +adjustment amplitude.

[0104] In one embodiment, before synchronous jitter injection, the method further includes: disconnecting the buffer chip from the main control board and not receiving the reference clock; the synchronous clock counter in each test board outputs a high-level signal after the reference clock is disconnected, and outputs a high-level signal to the synchronous counter to trigger the synchronous clock counter and the synchronous counter reset.

[0105] It is understood that the specific embodiments of the above-mentioned synchronous jitter injection method have been explained in detail in the above-mentioned synchronous jitter injection device and testing machine, and will not be repeated here.

[0106] The aforementioned synchronous jitter injection device, method, and test machine, through independent configuration of the phase interpolator 124 for each channel and coordinated control of the start timing based on the synchronization counter 104, not only achieves precise synchronous jitter injection across channels and boards, but also supports on-demand selection of any channel combination for jitter injection or disabling. Traditional solutions can only globally enable or disable jitter, lacking channel-level control granularity. This proposal significantly improves testing flexibility and synchronization accuracy, meeting the high-precision physical layer testing requirements of interfaces such as D-PHY / C-PHY.

[0107] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0108] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A synchronous jitter injection device, characterized in that, include: A synchronous clock counter is installed on the test board. The synchronous clock counter is used to count based on the received synchronous clock and a first preset value. Several channel jitter injection units are set on the test board. The synchronization counter in the channel jitter injection unit counts based on the received working clock and a second preset value. The synchronous clock and the working clock are both obtained by dividing the reference clock output by the main control board and have the same frequency. The first preset value and the second preset value are set according to the transmission path delay of the synchronous clock and the working clock, respectively, so as to synchronize the counting of the synchronous clock counter and the synchronous counter. The channel jitter injection unit injects jitter into the output channel between the test board and the device under test based on the working clock and the received adjustment parameters. The adjustment parameters are calculated based on the jitter peak value and the modulation frequency. The jitter peak value is the phase difference between the maximum phase offset of the positive jitter injection and the maximum phase offset of the negative jitter injection. The modulation frequency is the reciprocal of the modulation period. The modulation period includes a round trip process from +adjustment amplitude → -adjustment amplitude → +adjustment amplitude.

2. The apparatus according to claim 1, characterized in that, Also includes: A buffer is set on the test board. The buffer is connected to the synchronous clock counter and connected to the main control board through a buffer chip. It receives the synchronous clock obtained by dividing the reference clock output by the main control board by the buffer chip and sends the synchronous clock to the synchronous clock counter. A working clock buffer unit is installed on the test board. The working clock buffer unit is connected to the buffer chip and the channel jitter injection unit respectively. It is used to receive the reference clock output by the buffer chip, divide the frequency and output the working clock to the synchronization counter of the channel jitter injection unit. The synchronization counter is connected to the synchronization clock counter; A reset unit is disposed on the test board. The reset unit is connected to the synchronous clock counter and connected to the main control board through the buffer chip. When the reset unit does not receive the synchronous clock output by the buffer chip, it outputs a reset signal to the synchronous clock counter, so that the synchronous clock counter is reset after receiving the reset signal and outputs a reset signal to the synchronous counter. The synchronous counter is reset after receiving the reset signal output by the synchronous clock counter.

3. The apparatus according to claim 2, characterized in that, The synchronous jitter injection device includes N channel jitter injection units, each channel jitter injection unit includes M channel jitter injection modules and a logic module, the logic module includes the synchronization counter, and the logic modules in the N channel jitter injection units synchronously send adjustment parameters to the corresponding channel jitter injection modules based on the working clock and target address parameters.

4. The apparatus according to claim 3, characterized in that, The channel jitter injection module includes: a jitter injection module, a phase interpolation controller, and a phase adjustment buffer module; The jitter injection module is connected to the phase interpolation controller, the phase adjustment buffer module, and the buffer chip. It is used to perform phase modulation according to the instructions of the phase interpolation controller, inject jitter into the reference clock output by the buffer chip, and then send it to the phase adjustment buffer module. The phase interpolation controller is connected to the logic module and the jitter injection module, and is used to send instructions to the jitter injection module according to the adjustment parameters to control the jitter injection module to perform phase modulation; The phase adjustment buffer module is connected to the logic module and connected to the device under test through its corresponding output channel. It is used to receive the data to be transmitted sent by the logic module and send the data to be transmitted to the device under test through the corresponding output channel according to the clock signal after jitter injection.

5. A testing machine, characterized in that, The system includes multiple test boards, each test board comprising a synchronous jitter injection device and a buffer chip as described in any one of claims 1 to 4. The buffer chip is connected to the synchronous jitter injection device, which divides a received reference clock to obtain a synchronous clock, and sends the synchronous clock and the reference clock to the synchronous jitter injection device so that each test board can achieve inter-board clock synchronization based on the synchronous clock. In each test board, the synchronous jitter injection device divides the reference clock to obtain a working clock, and achieves jitter injection synchronization of the output channels within the board based on the working clock.

6. The testing machine according to claim 5, characterized in that, It also includes a host computer and a main control board. The main control board is connected to the host computer and the buffer chip. The host computer is used to control the main control board to output or stop outputting a reference clock; or, the host computer is used to acquire jitter configuration data, parse the jitter configuration data to obtain target jitter parameters and target address parameters, calculate adjustment parameters based on the target jitter parameters, and send the adjustment parameters to the channel jitter injection unit in the corresponding test board based on the target address parameters. The target jitter parameters include jitter peak-to-peak value and modulation frequency; or, the host computer is used to acquire jitter configuration data, parse the jitter configuration data to obtain target jitter parameters and target address parameters, and calculate adjustment parameters based on the target address parameters. The target jitter parameters are sent to the channel jitter injection unit in the corresponding test board. The channel jitter injection unit calculates adjustment parameters based on the target jitter parameters. The target jitter parameters include jitter peak-to-peak value and modulation frequency. Alternatively, the host computer acquires jitter configuration data, parses the jitter configuration data to obtain target jitter parameters and target address parameters, and sends the target address parameters and target jitter parameters to the main control board. The main control board calculates adjustment parameters based on the target jitter parameters and sends the adjustment parameters to the channel jitter injection unit in the corresponding test board based on the target address parameters. The target jitter parameters include jitter peak-to-peak value and modulation frequency.

7. The testing machine according to claim 6, characterized in that, The adjustment parameters include the number of adjustments and the PI value per step; the number of adjustments is calculated by the modulation frequency and the clock cycle of the working clock used by the channel jitter injection unit, and the PI value per step is calculated based on the jitter peak value and the number of adjustments.

8. The testing machine according to any one of claims 6 to 7, characterized in that, The test board also includes pin electronics. Each channel dithering injection unit is connected to a corresponding pin electronics unit. The signal input terminal of each pin electronics unit is connected to the output channel of the channel dithering injection unit. The output terminal of each pin electronics unit is connected to the device under test (DUT) via a protocol channel. If the pin electronics are compatible with the D-PHY protocol, the jitter injection modules connected to the two protocol channels occupied by the D-PHY protocol receive the same adjustment parameters, so that each of the channel jitter injection modules performs the same jitter injection synchronously. If the pin electronics are compatible with the C-PHY protocol, the jitter injection modules connected to the three protocol channels occupied by the C-PHY receive the same adjustment parameters, so that each of the channel jitter injection modules performs the same jitter injection synchronously.

9. The testing machine according to claim 8, characterized in that, The host computer is equipped with a mapping table, which is used to identify the mapping relationship between the output channel of the channel jitter injection unit and the protocol channel connected to the output terminal of the pin electronics. The dynamic configuration data is determined based on the protocol channel of the pin electronic device occupied by the target protocol and the mapping table, so that the jitter injection modules of each channel corresponding to the target protocol can synchronously perform jitter injection according to the same target jitter parameters; The number of target protocols is two or more, and the target jitter parameters of each target protocol are the same or different.

10. A synchronous jitter injection method, implemented based on the test machine according to any one of claims 5 to 9, characterized in that, include: The reference clock output from the main control board is divided to obtain a synchronous clock and a working clock with the same frequency; The synchronization clock counter counts based on the received synchronization clock, according to a first preset value. The synchronization counter in the channel jitter injection unit counts based on the received working clock, according to a second preset value. The channel jitter injection unit injects jitter into the output channel between the test board and the device under test based on the operating clock and adjustment parameters. The adjustment parameters are calculated based on the jitter peak-to-peak value and the modulation frequency; The jitter peak-to-peak value is the phase difference between the maximum phase offset of the positive jitter injection and the maximum phase offset of the negative jitter injection. The modulation frequency is the reciprocal of the modulation period. The modulation period includes a round trip from +adjustment amplitude → -adjustment amplitude → +adjustment amplitude.

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