Multi-stress synchronous coupling reliability test device and method for power device gate

Abstract

The application provides a kind of power device gate's multiple stress synchronous coupling reliability test device and method, device includes: the power device to be measured is arranged in closed test humid area;Gate voltage waveform output unit is arranged in high voltage control dry area, the output end of gate voltage waveform output unit is connected with the gate of power device to be measured, control instruction is issued to gate voltage waveform output unit and temperature and humidity control unit at the same clock edge, make gate voltage waveform output unit output positive gate voltage in first time length, output negative gate voltage in second time length, output zero voltage in third time length of zero voltage stagnation, make temperature and humidity control unit adjust closed test humid area to first humidity setting value in first time length and second time length, in third time length, closed test humid area is switched to second humidity setting value different from first humidity setting value.The application sets dry and wet partition to isolate water vapor, synchronously couples unification timing, segmented humidity follows gate voltage switch, realizes test precision safety.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device testing technology, and more specifically, to a multi-stress synchronous coupling reliability testing device and method for the gate of a power device. Background Technology

[0002] In related technologies, power device gate reliability testing equipment is divided into two categories: split-type multi-stress testing systems and single-function integrated testing equipment. Split-type systems consist of an independent gate voltage signal generator and an independent constant temperature and humidity aging chamber. Both systems are equipped with independent main control systems, lacking a hardware-level synchronous timing bus. Millisecond-level random time differences exist between gate voltage timing control and temperature and humidity control, making synchronous stress superposition impossible. Furthermore, the humidity control mode is fixed and cannot adaptively adjust in segments according to the gate voltage excitation state. Single-function integrated equipment only has basic static testing functions and cannot output dynamically alternating and intermittently stagnant gate voltage waveforms, resulting in poor equipment versatility. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art or related art.

[0004] Therefore, the first aspect of the present invention provides a multi-stress synchronous coupling reliability testing device for the gate of a power device.

[0005] A second aspect of the present invention provides a method for testing the reliability of multi-stress synchronous coupling of the gate of a power device.

[0006] In view of this, a first aspect of the present invention provides a multi-stress synchronous coupling reliability testing device for the gate of a power device, comprising: a high-voltage control dry area, a sealed test wet area, a unified timing master control unit, a gate voltage waveform output unit, a temperature and humidity control unit, and a sensor network. An insulating and sealed isolation structure is provided between the high-voltage control dry area and the sealed test wet area. The power device under test is disposed within the sealed test wet area. The unified timing master control unit includes a global timing register, a hardware timer, and a unified timing bus. The global timing register includes an electrical stress timing parameter storage area and an environmental stress timing parameter storage area. The hardware timer is used to load timing parameters and generate a counting matching signal. The gate voltage waveform output unit is disposed within the high-voltage control dry area, and the output terminal of the gate voltage waveform output unit is embedded in... The airtight insulating connector in the insulating and sealed isolation structure is connected to the gate of the power device under test; the temperature and humidity control unit is used to control the ambient temperature and humidity in the closed test humid area; the sensor network is used to collect environmental parameters in the closed test humid area; the unified timing bus is used to send control commands to the gate voltage waveform output unit and the temperature and humidity control unit at the same clock edge, using the counting matching signal as the synchronous trigger source, so that the gate voltage waveform output unit outputs a positive gate voltage in the first duration, a negative gate voltage in the second duration, and zero voltage in the third duration when the zero voltage is stagnant, so that the temperature and humidity control unit adjusts the closed test humid area to the first humidity setting value in the first and second durations, and switches the closed test humid area to a second humidity setting value different from the first humidity setting value in the third duration.

[0007] The multi-stress synchronous coupling reliability testing device provided in this application addresses the shortcomings of split-type power device gate reliability testing equipment, such as asynchronous multi-master control, poor stress coupling accuracy, fixed humidity control mode, and single-function integrated equipment with limited waveform coverage and versatility. This power device gate multi-stress synchronous coupling reliability testing device first achieves through-wall transmission of the gate voltage signal by using an insulating and sealed isolation structure between the high-voltage control dry area and the sealed test wet area, along with airtight insulating connectors. This ensures that the high-voltage output terminal and the transmission path are in a dry environment throughout, physically isolating water vapor from direct contact with the high-voltage terminal. This avoids insulation degradation, channel crosstalk, and leakage current drift caused by humid and hot environments, providing basic hardware safety assurance for long-term high-humidity and high-voltage testing. Based on this, the device adopts a unified timing master control architecture that includes a global timing register, a hardware timer, and a unified timing bus. By dividing the global timing register into two independent parameter storage areas for electrical stress and environmental stress, the gate voltage control, timing parameters, and temperature and humidity control parameters are incorporated into the scheduling system of the same hardware register. This unifies the timing references for the two types of stresses from the parameter configuration stage, fundamentally solving the underlying defect of timing reference separation in the dual master control system of split devices. After loading the timing parameters, the hardware timer independently generates a counting matching signal, providing a synchronization trigger source in a pure hardware counting manner. This avoids the time uncertainty caused by software scheduling and interrupt response, providing a deterministic time reference with microsecond-level accuracy for synchronous control. Based on this hardware timing benchmark, the unified timing bus can synchronously send control commands to the gate voltage waveform output unit and the temperature and humidity control unit at the same clock edge. This ensures that the switching of the gate voltage output stages and the switching of the humidity setpoint are strictly aligned on the time axis, eliminating any lead or lag time deviations. This achieves microsecond-level synchronous coupling between the gate voltage electrical stress and the humidity environmental stress, improving the millisecond-level random time difference of traditional split-type equipment to deterministic synchronization accuracy. This effectively improves the reproducibility of device aging failure mechanisms and the consistency of test data. Simultaneously, the humidity setpoint is naturally bound to each stage of the gate voltage timing. The positive and negative gate voltage excitation stages correspond to the first humidity setpoint, while the zero-voltage stagnation stage corresponds to a differentiated second humidity setpoint. This accurately reproduces the alternating humid and hot environment of power devices in real-world service scenarios, where power-on heating generates moisture and moisture diffuses during power-off intervals. This overcomes the limitation of traditional equipment that maintains constant humidity throughout the entire process, significantly improving the correlation between accelerated aging test results and the actual service life of the devices. Furthermore, a single device does not require an external independent signal source or multiple devices to be spliced ​​together. It can achieve various gate voltage waveform outputs, such as static DC, symmetrical alternating, asymmetrical alternating, and zero-voltage stagnation intermittent, as well as humidity coupling control for the corresponding stages, simply by configuring parameters. It can uniformly accommodate various industry standard test items such as high temperature gate bias, high temperature and high humidity gate bias, high accelerated stress test, and dynamic intermittent stress aging. This not only solves the versatility defect of insufficient coverage of working conditions in traditional single-function integrated equipment, but also significantly reduces the equipment procurement cost and space occupation for gate reliability testing of all types of power devices.

[0008] In some technical solutions of this application, the gate voltage waveform output unit includes: a multi-channel digital-to-analog converter and a high-voltage drive amplifier circuit, each digital-to-analog converter corresponding to an independent channel register in the global timing register; the high-voltage drive amplifier circuit is connected to each digital-to-analog converter; each independent channel register is used to store the gate voltage amplitude, waveform mode, and the first duration, second duration, and third duration of the corresponding period of the corresponding test channel.

[0009] In some technical solutions of this application, the unified timing master control unit is used to control multiple test channels to output gate voltage waveforms with different duty cycles, different amplitudes or different waveform modes in parallel based on the parameters in their respective independent channel registers, driven by a synchronous trigger source.

[0010] In some technical solutions of this application, the grid voltage waveform output unit generates a static DC grid voltage waveform, a symmetrical alternating square wave grid voltage waveform, an asymmetrical alternating square wave grid voltage waveform, or an intermittent grid voltage waveform with zero voltage stagnation based on parameter configuration of a first duration, a second duration, and a third duration.

[0011] In some technical solutions of this application, when the first duration is greater than zero and the second and third durations are both zero, a static DC grid voltage waveform is output; when the first duration is equal to the second duration, the absolute values ​​of the positive grid voltage and the negative grid voltage are equal, and the third duration is zero, a symmetrical alternating square wave grid voltage waveform is output; when the first duration is not equal to the second duration, or the absolute values ​​of the positive grid voltage and the negative grid voltage are not equal, and the third duration is zero, an asymmetrical alternating square wave grid voltage waveform is output; when the third duration is greater than zero, an intermittent grid voltage waveform with zero-voltage stagnation is output.

[0012] In some technical solutions of this application, the sensor network includes: a temperature sensor for collecting ambient temperature, a humidity sensor for collecting ambient humidity, and a level sensor for detecting the liquid level in the water tank of the temperature and humidity control unit.

[0013] In some technical solutions of this application, the unified timing master control unit is also used to calculate the real-time dew point temperature based on the collected ambient temperature and ambient humidity, and when the difference between the ambient temperature and the real-time dew point temperature is less than or equal to a preset safety threshold, it controls the temperature and humidity control unit to perform heating and dehumidification operation, and controls the grid voltage waveform output unit to reduce or cut off the voltage output.

[0014] In some technical solutions of this application, the unified timing master control unit is also used to control the gate voltage waveform output unit to perform voltage reduction or voltage cut-off when the ambient humidity exceeds the preset humidity threshold and continues for a preset time, and to generate alarm information.

[0015] In some technical solutions of this application, the unified timing master control unit is also used to cut off the voltage output of the grid voltage waveform output unit and control the temperature and humidity control unit to stop humidification when the liquid level sensor detects an abnormal liquid level state.

[0016] A second aspect of the present invention provides a multi-stress synchronous coupling reliability testing method for the gate of a power device, applied to the multi-stress synchronous coupling reliability testing apparatus as described in any of the above technical solutions. The multi-stress synchronous coupling reliability testing method includes:

[0017] Construct a global timing register that includes a storage area for electrical stress timing parameters and a storage area for environmental stress timing parameters;

[0018] The timing parameters are synchronously loaded into the hardware timer, and the count matching signal of the hardware timer is used as the synchronous trigger source of the unified timing bus.

[0019] Based on a synchronous trigger source, voltage output control commands and humidity output control commands are issued synchronously at the same clock edge.

[0020] The voltage output control command is used to control the grid voltage waveform output unit to output a positive grid voltage in the first duration, switch to output a negative grid voltage in the second duration, and output zero voltage in the third duration when the zero voltage is stagnant.

[0021] The humidity output control command is used to control the temperature and humidity control unit to adjust the test chamber to the first humidity setting value within the first and second time periods, and to switch the test chamber to a second humidity setting value different from the first humidity setting value within the third time period.

[0022] This application constructs a global timing register containing storage areas for electrical stress timing parameters and environmental stress timing parameters. The timing parameters are synchronously loaded into a hardware timer, and the hardware timer's count matching signal serves as the synchronous trigger source for a unified timing bus. The unified timing master control unit can synchronously issue voltage output control commands and humidity output control commands at the same clock edge. The voltage output control command controls the gate voltage waveform output unit to output a positive gate voltage in the first duration, switch to outputting a negative gate voltage in the second duration, and output zero voltage in the third duration when the voltage is stagnant. Simultaneously, the humidity output control command controls the temperature and humidity control unit to adjust the test chamber to a first humidity setting value in the first and second durations, and switch the test chamber to a value different from the first humidity setting value in the third duration. The second humidity setpoint, because the two types of control commands are issued simultaneously on the same clock edge, there is no difference in the order of grid voltage output and humidity adjustment on the time axis. The switching time of the humidity setpoint is strictly aligned with the switching time of the grid voltage output stage. Thus, without changing hardware or external signal sources, microsecond-level synchronous coupling of grid voltage stress and humidity stress is achieved under the same timing reference. At the same time, the humidity adjustment strictly follows the grid voltage excitation state and is executed in segments, forming a closed-loop linkage of "electrical-humidity" stress on the time axis. This solves the problem of time difference in stress coupling caused by the asynchronous operation of multiple master controllers in traditional split-type equipment. It makes the single device fully compatible with various industry standard test items such as high temperature grid bias test, high temperature and high humidity grid bias test, high accelerated stress test and dynamic intermittent stress aging test.

[0023] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0024] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0025] Figure 1 This is a structural block diagram of a multi-stress synchronous coupling reliability testing device for the gate of a power device according to an embodiment of the present invention;

[0026] Figure 2 This is a schematic diagram of a multi-stress synchronous coupling reliability testing device for the gate of a power device according to an embodiment of the present invention;

[0027] Figure 3 This is a flowchart illustrating a multi-stress synchronous coupling reliability testing method for the gate of a power device according to an embodiment of the present invention.

[0028] Figure 4This is a static DC gate voltage waveform output by a power device gate multi-stress synchronous coupling reliability test device according to an embodiment of the present invention.

[0029] Figure 5 The waveform of the symmetrical alternating square wave gate voltage output by the power device gate multi-stress synchronous coupling reliability test device according to an embodiment of the present invention is shown.

[0030] Figure 6 The waveform diagram of the asymmetric alternating square wave gate voltage output by a power device gate multi-stress synchronous coupling reliability test device according to an embodiment of the present invention is shown.

[0031] Figure 7 One of the intermittent gate voltage waveforms with zero-voltage stagnation output by a power device gate multi-stress synchronous coupling reliability test device according to an embodiment of the present invention;

[0032] Figure 8 This is the second of two intermittent gate voltage waveforms with zero-voltage stagnation output by a power device gate multi-stress synchronous coupling reliability test device according to an embodiment of the present invention.

[0033] Figure label:

[0034] The system includes: 100 multi-stress synchronous coupling reliability testing device; 110 high-voltage control dry zone; 120 sealed test wet zone; 122 insulating and sealed isolation structure; 124 airtight insulating connector; 130 power device under test; 140 unified timing master control unit; 142 global timing register; 144 hardware timer; 146 unified timing bus; 150 electrical stress timing parameter storage area; 152 environmental stress timing parameter storage area; 160 grid voltage waveform output unit; 162 digital-to-analog converter; 164 high-voltage drive amplifier circuit; 170 temperature and humidity control unit; 180 sensor network; 182 temperature sensor; 184 humidity sensor; and 186 liquid level sensor. Detailed Implementation

[0035] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0036] The following reference Figures 1 to 8 This invention describes a multi-stress synchronous coupling reliability testing apparatus and method for the gates of some power devices.

[0037] like Figure 1 and Figure 2As shown, an embodiment of this application provides a multi-stress synchronous coupling reliability testing device 100 for the gate of a power device, including: a high-voltage control dry area 110, a sealed test wet area 120, a unified timing master control unit 140, a gate voltage waveform output unit 160, a temperature and humidity control unit 170, and a sensor network 180. An insulating and sealed isolation structure 122 is provided between the high-voltage control dry area 110 and the sealed test wet area 120. The power device under test 130 is disposed in the sealed test wet area 120. The unified timing master control unit 140 includes a global timing register 142, a hardware timer 144, and a unified timing bus 146. The global timing register 142 includes an electrical stress timing parameter storage area 150 and an environmental stress timing parameter storage area 152. The hardware timer 144 is used to load timing parameters and generate a counting matching signal. The gate voltage waveform output unit 160 is disposed in the high-voltage control dry area 110. The output terminal of 160 is connected to the gate of the power device under test 130 through an airtight insulating connector 124 embedded in the insulating and sealed isolation structure 122; the temperature and humidity control unit 170 is used to control the ambient temperature and humidity in the closed test humid area 120; the sensor network 180 is used to collect environmental parameters in the closed test humid area 120; the unified timing bus 146 is used to send control commands to the gate voltage waveform output unit 160 and the temperature and humidity control unit 170 at the same clock edge, using the counting matching signal as a synchronous trigger source, so that the gate voltage waveform output unit 160 outputs a positive gate voltage in the first duration, outputs a negative gate voltage in the second duration, and outputs zero voltage in the third duration when the zero voltage is stagnant, so that the temperature and humidity control unit 170 adjusts the closed test humid area 120 to the first humidity setting value in the first and second durations, and switches the closed test humid area 120 to a second humidity setting value different from the first humidity setting value in the third duration.

[0038] In the multi-stress synchronous coupling reliability testing device 100 provided in this application, the high-voltage control dry zone 110 and the closed test wet zone 120 are completely separated in physical space by an insulating and sealed isolation structure 122 set between them. At the same time, the output terminal of the grid voltage waveform output unit 160 is connected to the gate of the power device under test 130 by means of the airtight insulating connector 124 embedded in the insulating and sealed isolation structure 122. This ensures that the high-voltage output terminal and the high-voltage signal transmission path are in the dry zone environment throughout and do not come into contact with the moisture in the closed test wet zone 120. This prevents the high-voltage terminal from directly contacting the high-humidity environment and avoids the insulation degradation, channel crosstalk and leakage current drift problems caused by the high-voltage test fixture being directly placed inside the humid and hot cavity. This provides basic hardware safety guarantee for long-term uninterrupted high-humidity and high-voltage testing. The unified timing master control unit 140 is equipped with a global timing register 142. The global timing register 142 includes an electrical stress timing parameter storage area 150 and an environmental stress timing parameter storage area 152. These two storage areas are used to store all timing parameters required for gate voltage control and all environmental parameters required for temperature and humidity control in the same hardware register space. This makes the electrical stress parameters and environmental stress parameters belong to the same timing scheduling system at the hardware level. From the parameter configuration stage, the gate voltage control and temperature and humidity control are locked under a common timing reference, which solves the problem of inconsistent timing references caused by the gate voltage device and temperature and humidity device having independent master control systems in split devices. By using hardware timer 144 to load timing parameters from global timing register 142 and generate a count matching signal, and using the count matching signal as the synchronous trigger source of unified timing bus 146, the two types of actions, gate voltage output and temperature and humidity regulation, share the same hardware-level time base. The trigger signal is generated by the precise counting of hardware timer 144 instead of software loop or interrupt, avoiding the time uncertainty caused by task priority differences or interrupt response delays in software scheduling, and providing a precise hardware-level time base for subsequent synchronous triggering. The electrical stress timing parameter storage area 150 stores at least the positive gate voltage amplitude, the negative gate voltage amplitude, the first duration of the positive excitation, the second duration of the negative excitation, and the third duration of zero-voltage stagnation. The environmental stress timing parameter storage area 152 stores at least the temperature setting value, the first humidity setting value corresponding to the first and second durations, and the second humidity setting value corresponding to the third duration, wherein the first humidity setting value is different from the second humidity setting value. The positive gate voltage amplitude, the negative gate voltage amplitude, the first duration, the second duration, and the third duration stored in the electrical stress timing parameter storage area 150 completely define the amplitude parameters and time segmentation parameters of the gate voltage waveform output. The temperature setting value, the first humidity setting value corresponding to the first and second durations, and the second humidity setting value corresponding to the third duration stored in the environmental stress timing parameter storage area 152 completely define the operating parameters of temperature and humidity control.Since the first humidity setting value corresponds to the first and second durations, and the second humidity setting value corresponds to the third duration, and the first humidity setting value is different from the second humidity setting value, the humidity control parameters are naturally bound to each time period of the gate voltage excitation. This enables the humidity setting value to be configured in a segmented manner according to the gate voltage excitation, solving the problem that the humidity setting value is a constant value in traditional equipment and cannot be adjusted in segments according to the gate voltage excitation state. This provides parameter support for the time-series linkage of humidity and gate voltage. The unified timing bus 146 uses the counting matching signal generated by the hardware timer 144 as a synchronous trigger source, and sends control commands to the gate voltage waveform output unit 160 and the temperature and humidity control unit 170 on the same clock edge. This causes the gate voltage waveform output unit 160 to output a positive gate voltage in the first duration, a negative gate voltage in the second duration, and zero voltage in the third duration. The temperature and humidity control unit 170 adjusts the sealed test humidity zone 120 to a first humidity setting value in the first and second durations, and switches the sealed test humidity zone 120 to a second humidity setting value different from the first humidity setting value in the third duration. Because the gate voltage output action and humidity adjustment action are triggered simultaneously on the same clock edge, there is no sequential delay or communication conflict between the two actions on the time axis. The timing difference is eliminated, and since the time boundary of humidity adjustment and the time boundary of gate voltage segment switching are strictly aligned at the same clock edge of the unified timing bus 146, the humidity will synchronously switch to the set value corresponding to the gate voltage every time it switches to a time period. There is no time deviation in which one is ahead or behind the other. This achieves microsecond-level synchronous coupling output of gate voltage stress and humidity stress under the same timing reference, improving the synchronization accuracy from millisecond-level random time difference in traditional split devices to microsecond-level deterministic synchronization. This solves the problem that in split devices, gate voltage timing control and humidity control belong to two independent control systems, and the millisecond-level random time difference during operation causes the stress to not be synchronously superimposed. This significantly improves the reproducibility of device aging failure mechanism and the consistency of test data. Within a single complete cycle, the gate voltage waveform output unit 160 sequentially outputs three waveforms: positive gate voltage, negative gate voltage, and zero voltage. The temperature and humidity control unit 170 maintains high humidity stress during the positive and negative excitation phases and automatically switches to low humidity stress during the zero-voltage stagnation phase. This causes the power device to experience a stress cycle from positive pressure and high humidity to negative pressure and high humidity, and then to zero pressure and low humidity in each cycle. On the time axis, this reproduces the alternating humid and hot environment that the power device experiences in real automotive and industrial service conditions: during power-on, the device heats up, causing moisture to accumulate inside the package and resulting in high humidity and high thermal stress; during power-off intervals, the device cools down, causing moisture to diffuse outward and humidity to decrease. This achieves accelerated aging assessment that is closer to the actual working conditions of the device than constant humidity aging test. It solves the problem that the equipment cannot simulate the real alternating humid and hot service environment of the device due to the fixed humidity control mode and constant humidity output throughout the process. This significantly improves the correlation between the accelerated aging test results and the actual service life of the device.Through the coordinated operation of the unified timing master control unit 140, global timing register 142, hardware timer 144, unified timing bus 146, gate voltage waveform output unit 160, and temperature and humidity control unit 170 in a single test device, positive gate voltage output, negative gate voltage output, zero-voltage stagnation output, and humidity segment switching corresponding to each stage can be fully realized without the need for external independent signal sources or multiple devices splicing. This allows a single device to simultaneously cover all gate voltage waveforms and humidity coupling conditions required for static DC gate bias testing, symmetrical alternating stress testing, asymmetrical alternating stress testing, and intermittent stagnation aging testing. It solves the problem of poor equipment versatility of single-function integrated devices that only support basic static gate voltage plus constant temperature and humidity testing and cannot adapt to scenarios such as high temperature and high humidity gate bias and dynamic stress accelerated aging. It makes it possible for a single device to be uniformly compatible with various industry standard test items such as high temperature gate bias testing, high temperature and high humidity gate bias testing, high accelerated stress testing, and dynamic intermittent stress aging testing, which greatly reduces the equipment procurement cost and space occupation required for the gate reliability testing of all types of power devices in laboratories and production lines.

[0039] In one embodiment, the insulating and sealing isolation structure 122 is a composite structure of a metal partition and an insulating sealing material. The metal partition provides structural strength and electromagnetic shielding, while the insulating sealing material fills the gap between the partition and the airtight insulating connector 124, ensuring airtightness and insulation performance at the wall penetration location. The airtight insulating connector 124 is an integrated wall-penetrating connector formed by pressing ceramic insulating terminals and a metal shell together. The ceramic terminals provide high-voltage insulation, while the metal shell provides structural support and shielding grounding. The integrated structure eliminates assembly seams, improving airtightness and insulation reliability.

[0040] The global timing register 142 is a dual-port random access memory block integrated by a field-programmable gate array. The electrical stress and environmental stress timing parameter storage areas are two independently divided blocks within this memory. The two blocks share the address and data bus and have independent write enable signals. They can write the two types of parameters separately in the same clock cycle, improving the parallelism and efficiency of parameter configuration.

[0041] The hardware timer 144 is a dedicated timer chip independent of the main control unit's central processing unit. It uses an external high-precision crystal oscillator as its clock source, and the output period of the count matching signal is determined by the loaded timing parameters. After the parameters are written to the comparison register, the timer independently generates the count matching signal without occupying the main control unit's computing resources, ensuring the real-time performance and stability of synchronous triggering.

[0042] The humidity parameters are configured as follows: the first humidity setting is a high humidity range of 85%RH (relative humidity) to 95%RH, and the second humidity setting is a low humidity range of 20%RH to 50%RH. During the first and second periods, the humidification actuator operates at full power to quickly stabilize the humidity to the first setting value; during the third period, the dehumidification and heating actuators start simultaneously. The dehumidification mechanism reduces the absolute moisture content of the air, while the heating mechanism raises the temperature to prevent condensation, ensuring smooth humidity switching.

[0043] Temperature settings are configured according to device type and test standards: 125℃~150℃ for silicon-based MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), 150℃~175℃ for silicon carbide power devices, and 150℃ for gallium nitride power devices; the ambient temperature deviation is controlled within ±2℃ throughout the test to eliminate temperature fluctuation interference.

[0044] The units for the three duration parameters can be selected as ms (milliseconds), s (seconds), min (minutes), and h (hours), and matched according to the test type: the first and second durations are in the ms or s level in dynamic alternating stress test, and in the h level in static bias aging test; the third duration is set to s to min level when simulating intermittent work, and set to 0 when no intermittent work is required.

[0045] The same clock edge is the rising edge of the counting matching signal of the hardware timer 144. The unified timing bus 146 simultaneously latches the waveform generation register of the gate voltage waveform output unit 160 and the set value register of the temperature and humidity control unit 170 at the same rising edge. Both start the state switching on the first clock cycle after the rising edge, with consistent response delay and synchronization accuracy on the order of clock cycles.

[0046] The Unified Timing Bus 146 is a synchronous serial bus based on low-voltage differential signaling technology, with low propagation delay and stable transmission. The counting and matching signals are transmitted to each functional module simultaneously via the bus, and the arrival time difference of each node signal is less than 1 clock cycle, ensuring reliable synchronous triggering.

[0047] The device is also equipped with a human-machine interface panel, which is connected to the unified timing main control unit 140. After the operator inputs the positive and negative grid voltage amplitude, three-segment duration, temperature setpoint and two types of humidity setpoint, the main control unit automatically generates the corresponding waveform and timing parameters and writes them into the corresponding storage area. At the same time, it automatically completes the parameter logic association and constraint verification, eliminating the need for manual matching and reducing the complexity of operation.

[0048] In one embodiment, a multi-standard gate reliability coupling test with wide-range temperature and humidity adaptation is described below:

[0049] This embodiment is based on the above-mentioned multi-stress synchronous coupling reliability testing device. Relying on the temperature and humidity control unit's ability to continuously adjust the temperature from -20℃ to +180℃ and the humidity from 20%RH to 98%RH, it is compatible with mainstream power device reliability evaluation standards such as dual 85 high temperature and high humidity gate bias test and multi-level high temperature dry state gate bias test, so as to realize the stress coupling test requirements of a single device covering multiple levels and multiple operating conditions.

[0050] (1) Implementation method of dual 85 high temperature and high humidity grid offset test;

[0051] This embodiment corresponds to the high temperature and high humidity gate bias (H3TRB) test standard for power devices. The test conditions are an ambient temperature of 85°C and a relative humidity of 85%RH, with continuous application of gate bias stress to evaluate the long-term reliability of the gate oxide layer of the device in a humid and hot environment.

[0052] Parameter configuration stage: The operator sets the environmental stress parameters and electrical stress parameters through the human-machine interface panel. The environmental stress parameters are written into the environmental stress timing parameter storage area of ​​the global timing register: the temperature setting is 85℃, and the first humidity setting is 85%RH. The electrical stress parameters are written into the electrical stress timing parameter storage area: the static DC gate voltage mode is selected, the positive gate voltage amplitude is set to the rated gate bias voltage of the device under test, the first duration is configured as a standard test cycle of 1000 hours, and the second and third durations are both set to 0.

[0053] Test execution phase: The hardware timer loads the corresponding timing parameters and generates a counting matching signal. The unified timing bus uses this counting matching signal as a synchronization trigger source, synchronously sending control commands to the gate voltage waveform output unit and the temperature and humidity control unit on the same clock edge. The temperature and humidity control unit stabilizes the ambient temperature of the sealed test humid area at 85℃±2℃ and the relative humidity at 85%RH±3%RH. The gate voltage waveform output unit is located in the high-voltage control dry area, and its output terminal continuously outputs a constant positive gate voltage to the power device under test in the sealed test humid area through an airtight insulating connector embedded in the insulating and sealed isolation structure.

[0054] Throughout the test, the temperature and humidity sensors of the sensor network collect environmental parameters in real time, and the unified timing master control unit calculates the dew point temperature in real time based on the collected data. When the difference between the ambient temperature and the real-time dew point temperature is less than or equal to a preset safety threshold, the temperature and humidity control unit automatically controls the temperature and humidity control unit to perform a heating and dehumidification operation, and simultaneously controls the grid voltage waveform output unit to reduce the output voltage. This proactively avoids risks before condensation occurs, ensuring the long-term operational safety of the high humidity and high pressure test.

[0055] (2) Implementation method of multi-level high-temperature dry state grid bias test;

[0056] This implementation corresponds to the High Temperature Gate Bias (HTGB) test standard, using a high-temperature dry environment above 100°C combined with gate electrical stress. It can be adapted to commonly used test temperature ranges in the industry, such as 125°C, 150°C, and 175°C, respectively, which correspond to the conventional aging evaluation needs of silicon-based MOSFETs, silicon carbide power devices, and gallium nitride power devices.

[0057] Parameter configuration stage: Configure the corresponding temperature setting value according to the type of device under test. The corresponding temperature setting value for silicon-based MOSFET testing is 125℃, for silicon carbide power device testing it is 150℃, and for gallium nitride power device testing it is 175℃. The humidity is uniformly set to a dry low-humidity condition of 20%RH to eliminate the interference of the damp-heat coupling effect on the pure high-temperature gate bias test results. The electrical stress parameter can be flexibly configured as static DC mode or symmetrical alternating square wave mode: In static mode, the first duration is configured as the total test duration of 500 hours, and the second and third durations are both 0; in alternating mode, the first and second durations are both 100ms, the absolute values ​​of the positive and negative gate voltage amplitudes are equal, the third duration is 0, and a symmetrical alternating square wave with a duty cycle of 50% is output.

[0058] Based on a multi-channel independent time-sharing scheduling mechanism, differentiated parameters can be configured for different test channels under the same temperature environment in the same closed test humid zone. For example, channels 1-3 can be configured with a 125℃ static DC grid bias, channels 4-6 with a 150℃ symmetrical alternating grid bias, and channels 7-8 with a 175℃ intermittent grid bias with zero-voltage stagnation. The parameters of each channel are stored in their respective independent channel registers and do not interfere with each other.

[0059] During the test execution phase: The temperature and humidity control unit stabilizes the ambient temperature of the sealed test humidification zone within the target set value ±2℃, and maintains the humidity at a dry environment of 20%RH. The unified timing bus, based on the same synchronous trigger source, controls the parallel output of the grid voltage waveforms of each channel by the multi-channel grid voltage waveform output unit, realizing synchronous aging test of a single chamber under multiple operating conditions. Throughout the test, the water tank status of the temperature and humidity control unit is monitored by a liquid level sensor. If water shortage or overflow is detected, the grid voltage output of all channels is immediately cut off and humidification is stopped to ensure the safety of the equipment during 24 / 7 uninterrupted high-temperature testing.

[0060] (3) Implementation method of wide-range gradient stress coupling aging test;

[0061] Relying on the device's wide-range controllability of temperature adjustable from -20℃ to +180℃ and humidity adjustable from 20%RH to 98%RH, this implementation method can carry out continuous accelerated aging tests with multi-stage gradient stress to simulate different service environments experienced by power devices throughout their entire life cycle.

[0062] Parameter configuration stage: Configure a three-segment cyclic timing in the global timing register: the first duration is 200 hours, corresponding to high humidity and high temperature stress at a temperature of 125℃ and a first humidity setting of 85%RH, with the gate voltage configured as +20V static positive bias; the second duration is 200 hours, corresponding to medium temperature and medium humidity stress at a temperature of 150℃ and a humidity setting of 50%RH, with the gate voltage configured as ±15V symmetrical alternating square wave; the third duration is 200 hours, corresponding to high temperature and dry stress at a temperature of 175℃ and a second humidity setting of 20%RH, with the gate voltage configured as an intermittent waveform with a 100ms zero-voltage pause.

[0063] During the test execution phase: the hardware timer generates counting matching signals sequentially according to segmented timing sequences. At the clock edge of each time segment switch, the unified timing bus synchronously issues gate voltage waveform switching commands and temperature / humidity setpoint switching commands, achieving segmented synchronous coupling of electrical stress parameters and environmental stress parameters. The entire test process requires no manual parameter adjustments midway; all timing switching actions are precisely scheduled by the unified timing master control unit according to pre-stored parameters in the registers, and test data and timing logs are automatically retained throughout the process.

[0064] This implementation method can continuously apply multiple gradients of temperature, humidity and gate coupling stress within a single test cycle, which is closer to the alternating operating conditions of the device in actual service. Compared with a single constant stress test, the aging data obtained has higher reference value for device life assessment.

[0065] In some embodiments of this application, the gate voltage waveform output unit 160 includes: a multi-channel digital-to-analog converter 162 and a high-voltage drive amplifier circuit 164. Each digital-to-analog converter 162 corresponds to an independent channel register in the global timing register 142. The high-voltage drive amplifier circuit 164 is connected to each digital-to-analog converter 162. Each independent channel register is used to store the gate voltage amplitude, waveform mode, and the first, second, and third durations of the corresponding period of the corresponding test channel.

[0066] In the above embodiments, the multiple digital-to-analog converters 162 configured in the gate voltage waveform output unit 160, and an independent channel register in the global timing register 142 corresponding to each digital-to-analog converter 162, enable each test channel to have its own dedicated parameter storage space in the global timing register 142. The gate voltage amplitude, waveform mode, first duration, second duration, and third duration of different channels are stored in their respective independent channel registers, achieving mutual isolation at the storage level and preventing data conflicts or parameter crosstalk. With the help of the high-voltage drive amplifier circuit 164 connected to each digital-to-analog converter 162, the gate voltage amplitude stored in each independent channel register is converted into an analog voltage signal by its corresponding digital-to-analog converter 162, and then amplified by its respective independent high-voltage drive amplifier circuit 164 to drive the gate of the power device under test 130 of the corresponding channel. This forms a fully independent channel structure from register parameter storage to digital-to-analog conversion to high-voltage drive. The signal links of each channel are completely parallel and uncoupled in hardware, and there is no inter-channel waiting delay caused by shared bus bandwidth or time-division multiplexing of hardware resources. Each independent channel register is used to store the gate voltage amplitude, waveform mode, and the first, second, and third durations of the corresponding period for the corresponding test channel. This allows all waveform definition parameters for each test channel to be freely configured in their own independent register space. Adjusting the parameters of any channel will not affect the parameter values ​​already stored in the registers of other channels, providing complete underlying hardware support for multi-channel independent parallel testing.

[0067] In one embodiment, the multiplexed digital-to-analog converter 162 is integrated into a single digital-to-analog converter chip. This chip allocates independent input registers and control logic to each channel, enabling independent data writing and conversion triggering for each channel through chip select signals and channel addressing. The digital-to-analog conversion processes of each channel are executed in complete parallel, eliminating mutual waiting time between channel conversions and further improving the synchronization accuracy of the multi-channel parallel output. The high-voltage drive amplifier circuit 164 employs a combination of a high-voltage operational amplifier and a push-pull output stage. The high-voltage operational amplifier amplifies the low-voltage analog signal output from the digital-to-analog converter 162 to the required gate voltage amplitude range. The push-pull output stage provides sufficient drive current to match the rapid charging and discharging requirements of the power device's gate capacitor, ensuring that the steepness of the square wave edge meets the requirement that the rising and falling edges are no greater than one hundred nanoseconds. The waveform patterns stored in the independent channel registers are represented in binary code form. For example, "00" represents static DC mode, "01" represents symmetrical alternating square wave mode, "10" represents asymmetrical alternating square wave mode, and "11" represents intermittent mode with zero-voltage pause. The unified timing master control unit 140 reads the waveform pattern code of each channel and automatically calls the corresponding waveform generation logic, eliminating the need for operators to configure waveform generation algorithms separately for each channel.

[0068] In some embodiments of this application, the unified timing master control unit 140 is used to control multiple test channels to output gate voltage waveforms with different duty cycles, different amplitudes or different waveform modes in parallel based on the parameters in their respective independent channel registers, driven by a synchronous trigger source.

[0069] In the above embodiments, the unified timing master control unit 140, driven by a synchronous trigger source, controls multiple test channels to output gate voltage waveforms with different duty cycles, amplitudes, or waveform modes in parallel based on parameters in their respective independent channel registers. Since the triggering action of each channel originates from the same counting matching signal, this counting matching signal arrives simultaneously at the control logic input terminals of all channels. Although the duty cycle, amplitude, or waveform mode of the output waveforms of each channel are different, their start times start simultaneously at the same clock edge, their segment switching times occur simultaneously at the same clock edge, and their cycle termination times arrive simultaneously at the same clock edge, ensuring complete alignment on the time axis and eliminating time deviations between channels. Because the waveform parameters of each channel originate from their respective independent channel registers, the duty cycle of each channel is independently determined by the proportional relationship between the first, second, and third durations stored in each channel. The amplitude of each channel is independently determined by the positive and negative gate voltage amplitudes stored in each channel, and the waveform mode of each channel is independently determined by the waveform mode parameters stored in each channel. Therefore, each channel can output its own independently configured waveforms without being constrained by the parameters of other channels. The aforementioned multi-channel parallel independent output mechanism under synchronous triggering enables parallel testing under various operating conditions, such as static DC aging test, symmetrical alternating stress test, asymmetrical alternating stress test, and intermittent stagnation aging test, to be carried out simultaneously within the same sealed test chamber. All tests are conducted under the same ambient temperature and humidity sequence within the same chamber, ensuring that environmental variables remain consistent across different operating conditions. This achieves simultaneous testing of multiple operating conditions within a single chamber without increasing the number of devices or floor space, resulting in a significant improvement in the efficiency of batch differentiated testing. It solves the problems of traditional equipment, which can only perform one type of operating condition test within the same chamber, and the high equipment procurement cost and large floor space required for batch differentiated testing due to the need for multiple devices in parallel.

[0070] In some embodiments, driven by the same counting and matching signal, the eight test channels output a static DC grid voltage waveform for high-temperature grid bias testing, an intermittent grid voltage waveform with zero-voltage stagnation for intermittent aging testing, and asymmetric alternating square wave grid voltage waveforms with different duty cycles or amplitudes, respectively. All channels start synchronously, switch in segments synchronously, and cycle synchronously. Users can independently configure test parameters for each channel via the human-machine interface panel according to the type of the power device under test 130 and the test standards. After configuration, the unified timing control unit 140 writes the parameters of all channels into the corresponding independent channel registers at once, and then starts the synchronous test process. During testing, users can perform independent start / stop operations on any single channel without affecting the continuous operation of other channels. When a device on a certain channel reaches its test cycle, the high-voltage output of that channel can be stopped and the device removed, while other channels continue testing, improving the operational flexibility and equipment utilization of batch testing.

[0071] In some embodiments of this application, the gate voltage waveform output unit 160 generates a static DC gate voltage waveform, a symmetrical alternating square wave gate voltage waveform, an asymmetrical alternating square wave gate voltage waveform, or an intermittent gate voltage waveform with zero voltage stagnation based on parameter configurations of a first duration, a second duration, and a third duration.

[0072] In the above embodiments, the grid voltage waveform output unit 160, based on the parameter configuration of the first duration, the second duration, and the third duration, can generate static DC grid voltage waveforms, symmetrical alternating square wave grid voltage waveforms, asymmetrical alternating square wave grid voltage waveforms, or intermittent grid voltage waveforms with zero-voltage stagnation within a single main control system without replacing any hardware or connecting an external signal source. Since the first duration, the second duration, and the third duration are three core independent variables defining the waveform time structure, different combinations of these three variables can cover all waveform time structures from no time segmentation to two-segment time segmentation to three-segment time segmentation: the static DC mode corresponds to a state with only positive voltage output and no periodic jumps or time segments; the symmetrical and asymmetrical alternating square wave mode corresponds to a state containing two time segments, positive and negative, which alternate continuously; and the intermittent mode with zero-voltage stagnation corresponds to a state containing three time segments, positive, negative, and zero-voltage stagnation, which cycle sequentially. Through the flexibility of the above parameter configuration, a single device can output all gate stress waveforms covering static to dynamic, symmetrical to asymmetrical, and continuous alternating to intermittent pauses. It is fully compatible with the gate excitation conditions specified by various test standards, such as the static DC gate voltage required for high-temperature gate bias testing, the symmetrical or asymmetrical alternating gate voltage required for high-temperature and high-humidity gate bias testing, and the gate voltage with pause required for dynamic intermittent stress aging testing. It realizes waveform coverage of all gate reliability test scenarios on a single hardware platform, solving the industry status quo where static DC output devices and dynamic waveform generation devices are independent, a single device can only output one or two fixed waveforms, and test institutions need to purchase multiple dedicated devices to complete full-scenario testing. It significantly reduces the equipment purchase and maintenance costs required for gate reliability testing of all types of power devices.

[0073] In some embodiments of this application, when the first duration is greater than zero and both the second and third durations are zero, a static DC grid voltage waveform is output; when the first duration is equal to the second duration, the absolute values ​​of the positive and negative grid voltages are equal, and the third duration is zero, a symmetrical alternating square wave grid voltage waveform is output; when the first duration is not equal to the second duration, or the absolute values ​​of the positive and negative grid voltages are not equal, and the third duration is zero, an asymmetrical alternating square wave grid voltage waveform is output; when the third duration is greater than zero, an intermittent grid voltage waveform with zero-voltage stagnation is output.

[0074] In the above embodiments, when the first duration > 0 and the second and third durations are both 0, the gate voltage waveform output unit outputs a constant positive gate voltage. The waveform has no periodic changes or jumps, and is a horizontal straight line parallel to the time axis. It is suitable for conventional dry gate bias aging tests and can provide stable long-term gate bias stress.

[0075] When the first duration is equal to the second duration, the absolute values ​​of the positive and negative gate voltage amplitudes are equal, and the third duration is 0, a symmetrical alternating square wave with a duty cycle of 50% is output. The device is subjected to equal electrical stress in both positive and negative directions, which is suitable for evaluating the threshold voltage drift and interface state degradation characteristics under symmetrical alternating gate voltage.

[0076] When the first duration is not equal to the second duration, or the absolute values ​​of the positive and negative gate voltage amplitudes are not equal and the third duration is 0, an asymmetric alternating square wave is output; its amplitude and duration can be adjusted independently, which can accurately simulate the asymmetric gate voltage stress caused by threshold voltage asymmetry, output impedance mismatch, etc. in the actual driving circuit.

[0077] When the third duration is greater than 0, the output is an intermittent gate voltage waveform with zero-voltage stagnation. After each positive and negative excitation cycle, a zero-voltage stagnation segment is forcibly inserted. The stagnation duration is independently adjustable by the third duration. The effective excitation duty cycle can be set arbitrarily within the range of 0 to 100%, breaking through the limitation of the traditional fixed 50% duty cycle. It can accurately simulate the gate voltage stress in the intermittent working mode of the device.

[0078] The generation conditions for the four waveform modes are uniquely determined by the combination of parameters, with no overlapping or ambiguous areas, and are precisely matched with the test scenario. Operators only need to input three duration parameters and positive and negative amplitude values, and the system can automatically identify and generate the corresponding waveforms without the need for manual mode selection, reducing operational complexity and the risk of misoperation.

[0079] In one embodiment, when performing an asymmetric alternating square wave test, the operator sets the positive gate voltage amplitude to +18V and the negative gate voltage amplitude to -5V, respectively, according to the positive gate drive voltage and negative gate turn-off voltage recommended in the datasheet of the power device under test 130. Simultaneously, based on the device switching frequency, the operator sets the first duration to 50 microseconds, the second duration to 50 microseconds, and the third duration to zero. At this time, the output is an alternating square wave with asymmetric positive and negative amplitudes but symmetrical durations. When performing an intermittent gate voltage waveform test with zero-voltage pause, the operator sets the third duration to 1000 milliseconds. At this time, the gate voltage waveform output unit 160 pauses for 1000 milliseconds after each complete cycle containing both positive and negative excitation. The effective excitation duty cycle is determined by the ratio of the sum of the first and second durations to the sum of the first, second, and third durations. When a static DC test is required but the device under test (DUT) is a normally open power device that requires negative gate voltage shutdown, the operator can set the positive gate voltage amplitude to 0V, the negative gate voltage amplitude to -15V, the first duration to any positive integer, and the second and third durations to zero. The gate voltage waveform output unit 160 will continuously output a -15V DC voltage, achieving negative static DC gate voltage output. When all three duration parameters are zero, the system determines that the parameter configuration is invalid and prompts the operator to re-enter them, avoiding accidental startup in a no-output state.

[0080] In some embodiments of this application, the sensor network 180 includes: a temperature sensor 182 for collecting ambient temperature, a humidity sensor 184 for collecting ambient humidity, and a level sensor 186 for detecting the liquid level in the water tank of the temperature and humidity control unit 170.

[0081] In the above embodiment, the ambient temperature within the sealed test wet zone 120 is collected by a temperature sensor 182 in the sensor network 180, the ambient humidity within the sealed test wet zone 120 is collected by a humidity sensor 184, and the liquid level status of the water tank in the temperature and humidity control unit 170 is detected by a liquid level sensor 186. The unified timing master control unit 140 can obtain the ambient temperature data, ambient humidity data, and water tank liquid level status data of the sealed test wet zone 120 in real time. With the help of the real-time feedback data provided by the temperature sensor 182 and the humidity sensor 184, the unified timing master control unit 140 compares the real-time collected ambient temperature value with the temperature setpoint and the real-time collected ambient humidity value with the humidity setpoint corresponding to the current stage. Based on the deviation value, it dynamically adjusts the output power or duty cycle of the humidification actuator, dehumidification actuator, and heating actuator in the temperature and humidity control unit 170, so that the temperature and humidity of the sealed test wet zone 120 are always maintained within the allowable deviation range of the target setpoint, thus realizing precise closed-loop control of the temperature and humidity of the sealed test wet zone 120. Meanwhile, the ambient temperature data collected by temperature sensor 182 and the ambient humidity data collected by humidity sensor 184 serve as two necessary input parameters for dew point temperature calculation. The unified timing main control unit 140 calculates the current ambient dew point temperature based on the real-time collected temperature and humidity values, and then compares the calculated real-time dew point temperature with the ambient temperature to execute condensation prediction and protection logic. This allows the same set of temperature and humidity sensor data to simultaneously serve both closed-loop control and safety protection functions. The liquid level status data provided by liquid level sensor 186 is the sole basis for determining water circuit fault protection. The unified timing main control unit 140 determines whether the water tank is in a water shortage or overflow state based on the level signal or continuous liquid level height value fed back by liquid level sensor 186, and executes corresponding protection actions such as cutting off high-pressure output and stopping humidification accordingly. Through the coordinated deployment and data fusion of the above three types of sensors, temperature sensor 182, humidity sensor 184 and liquid level sensor 186 together form a comprehensive sensing layer covering closed-loop feedback of temperature and humidity control, condensation prediction calculation and water circuit safety monitoring. This provides complete real-time data support for the precise control and three-level active protection of the unified timing main control unit 140, and solves the functional limitations of the equipment's single sensor configuration, which can only realize basic temperature and humidity detection or simple overcurrent protection and cannot support intelligent active protection.

[0082] In one embodiment, the temperature sensor 182 is a platinum resistance temperature sensor 182, and the humidity sensor 184 is a capacitive humidity sensor 184. Both are integrated into a single temperature and humidity transmitter, evenly distributed at three locations: the air inlet, air outlet, and center of the test area in the sealed test humidity zone 120. The unified timing control unit 140 takes the weighted average of the three sets of data as the final measured values ​​of the ambient temperature and humidity to improve measurement accuracy and resistance to local disturbances. The liquid level sensor 186 is a float-type liquid level switch or an ultrasonic liquid level sensor 186, installed inside the water tank of the temperature and humidity control unit 170. The liquid level sensor 186 outputs a continuous liquid level height signal or a high / low liquid level switch signal to the analog-to-digital conversion input port of the unified timing control unit 140. The sensor network 180 also includes a dew point detection unit, which is an independent dew point transmitter that directly outputs the dew point temperature value. The unified timing main control unit 140 reads the dew point temperature value and compares it with the ambient temperature value. It does not need to calculate the dew point temperature itself, which reduces the computational load of the main control unit and improves the response speed of dew point detection.

[0083] In some embodiments of this application, the unified timing master control unit 140 is also used to calculate the real-time dew point temperature based on the collected ambient temperature and ambient humidity, and when the difference between the ambient temperature and the real-time dew point temperature is less than or equal to a preset safety threshold, control the temperature and humidity control unit 170 to perform a heating and dehumidification operation, and control the gate voltage waveform output unit 160 to reduce or cut off the voltage output.

[0084] In the above embodiment, the unified timing master control unit 140 calculates the real-time dew point temperature based on the ambient temperature collected by the temperature sensor 182 and the ambient humidity collected by the humidity sensor 184. Since the dew point temperature is the critical temperature at which water vapor in the air begins to condense into liquid water, the difference between the ambient temperature and the dew point temperature reflects the degree of air saturation. The smaller the difference, the closer the air is to saturation, and the higher the risk of condensation. When the difference between the ambient temperature calculated by the unified timing master control unit 140 and the real-time dew point temperature is less than or equal to a preset safety threshold, it is determined that the closed test wet area 120 is currently in a critical state of condensation. At this time, the unified timing master control unit 140 immediately intercepts the current environmental stress timing command, preventing the command that may further increase humidity or decrease temperature from continuing to be executed. At the same time, it controls the temperature and humidity control unit 170 to start the heating actuator to increase the ambient temperature and start the dehumidification actuator to reduce the absolute humidity of the environment, so that the difference between the ambient temperature and the dew point temperature expands and returns to above the preset safety threshold, eliminating the thermodynamic conditions for condensation from the source. During the heating and dehumidification operation, the unified timing main control unit 140 synchronously controls the grid voltage waveform output unit 160 to reduce the output voltage or completely cut off the high-voltage output. This ensures that the high-voltage circuit is in a low-voltage or completely de-energized state before the risk of condensation is completely eliminated, preventing short circuits or electric shocks caused by contact between the high voltage and any water film that may form. Through the aforementioned real-time dew point calculation, difference comparison, and condition-triggered control logic, the risk is identified and actively intervened before condensation actually occurs. This upgrades condensation protection from a passive response method, such as triggering overcurrent protection only after condensation has occurred in traditional equipment, to a proactive prediction and avoidance method based on thermodynamic principles. This ensures test safety and minimizes test interruptions and device failures caused by condensation.

[0085] In one specific implementation, the preset safety threshold is five degrees Celsius. When the ambient temperature is 85 degrees Celsius and the ambient humidity is 85%, the calculated real-time dew point temperature is approximately 82 degrees Celsius. The difference between the ambient temperature and the dew point temperature is three degrees Celsius, which is less than the preset safety threshold of five degrees Celsius. At this time, the unified timing control unit 140 determines that there is a risk of condensation and immediately intercepts the current environmental stress timing command, controlling the temperature and humidity control unit 170 to start the dehumidifier to reduce the humidity to below 70%, and simultaneously start the heater to raise the temperature to above 90 degrees Celsius, until the difference between the ambient temperature and the dew point temperature recovers to above five degrees Celsius. During the above process, the grid voltage waveform output unit 160 simultaneously performs a voltage reduction operation, reducing the grid voltage amplitude from 20 volts to 5 volts. After the condensation risk is eliminated, it automatically recovers to the preset amplitude, and the test process is uninterrupted. When the difference between the ambient temperature and the dew point temperature is less than or equal to the preset safety threshold, the unified timing main control unit 140 prioritizes the heating and dehumidification operation. Only when the difference has not recovered to above the safety threshold after the heating and dehumidification operation has been performed for a preset time will the grid voltage waveform output unit 160 perform the complete voltage cut-off operation to avoid unnecessary test interruption.

[0086] In some embodiments of this application, the unified timing master control unit 140 is also used to control the gate voltage waveform output unit 160 to perform voltage reduction or voltage cut-off when the ambient humidity exceeds a preset humidity threshold and continues for a preset time, and to generate alarm information.

[0087] In the above embodiment, when the humidity sensor 184 detects that the ambient humidity exceeds the preset humidity threshold and continues for a preset time, the unified timing main control unit 140 controls the gate voltage waveform output unit 160 to perform voltage reduction or voltage cut-off and generates alarm information. Because the dual-condition judgment logic of "humidity exceeding the threshold" and "continuously reaching the preset time" is adopted, when the ambient humidity value fed back by the humidity sensor 184 exceeds the system's preset humidity threshold, the unified timing main control unit 140 does not immediately perform voltage reduction or voltage cut-off, but starts a timer to start counting. Only after the humidity continuously exceeds the threshold for a preset time is it confirmed that the humidity abnormality is not a false alarm caused by instantaneous fluctuations or sensor signal glitches during the normal adjustment process of the temperature and humidity control unit 170, but a continuous fault. This effectively avoids false triggering caused by instantaneous disturbances and improves the reliability and accuracy of safety protection actions. When both conditions are met, the unified timing master control unit 140 confirms that the sealed test wet zone 120 is in a continuous ultra-high humidity abnormal state. It then controls the high-voltage drive amplifier circuit 164 of the corresponding test channel to perform a gate voltage reduction operation to lower the gate voltage amplitude below a safe value, or to perform a complete voltage cut-off operation to cut off the high-voltage output of the aforementioned channel. Simultaneously, it generates alarm information including a timestamp, channel number, measured humidity value, and duration, and displays it on the human-machine interface panel. This information is also stored in the master control unit's non-volatile memory in the format of a timing fault log. Through the above dual-condition judgment and linkage execution logic, accurate identification and targeted high-voltage linkage protection for continuous ultra-high humidity abnormal conditions are achieved. This solves the problem that traditional equipment lacks a dedicated high-voltage linkage protection mechanism when humidity is out of control, relying solely on passive circuit breaking of hardware fuses, resulting in delayed protection actions and no fault data retention. This provides complete and traceable data records for subsequent fault diagnosis and equipment maintenance.

[0088] In one specific implementation, the preset humidity threshold is 95% relative humidity and the preset duration is 10 seconds. When the humidity sensor 184 detects that the humidity in the sealed test wet area 120 reaches 97% and lasts for more than 10 seconds, the unified timing main control unit 140 confirms the humidity abnormality and controls the high-voltage drive amplifier circuit 164 of the corresponding channel to perform gate voltage reduction, lowering the gate voltage amplitude to below the preset safety value of 5 volts. At the same time, an alarm log containing the channel number "CH03", the measured humidity "97%", the duration "12 seconds", and the action type "voltage reduction to 5 volts" is generated and stored in the non-volatile memory of the main control unit. For the power device under test 130, which is particularly sensitive to humidity, the preset humidity threshold is set to 90% relative humidity and the preset duration is set to 3 seconds. When the humidity exceeds the threshold for 3 seconds, a complete voltage cut-off operation is performed to maximize the protection of the device. The alarm information pops up a prompt window through the human-machine interface panel and displays a flashing red alarm status in the panel indicator light of the main control unit. The timing fault log can be exported to an external storage device through the universal serial bus interface for subsequent analysis.

[0089] In some embodiments of this application, the unified timing master control unit 140 is also used to cut off the voltage output of the gate voltage waveform output unit 160 and control the temperature and humidity control unit 170 to stop humidifying when the liquid level sensor 186 detects an abnormal liquid level state.

[0090] In the above embodiment, when the liquid level sensor 186 detects an abnormal liquid level state, the unified timing main control unit 140 cuts off the voltage output of the grid voltage waveform output unit 160 and controls the temperature and humidity control unit 170 to stop humidification. Since the abnormal liquid level state includes two situations: water tank shortage state and water overflow state, the water tank shortage state means that the water level in the water tank is lower than the minimum water level line for the humidification actuator to work normally. If the humidification actuator continues to operate in the water shortage state, it may cause the ultrasonic atomizing sheet or electric heating evaporator to burn out and be damaged, or even cause a fire. The water overflow state means that the water level in the water tank exceeds the maximum safe water level line, which may be caused by inlet valve failure, drain pipe blockage or liquid level sensor 186 failure. Water overflow may cause water to overflow into the high pressure control dry area 110 or the electrical circuit area, causing short circuit and leakage accidents. When the signal from the level sensor 186 indicates that the water tank is in a state of water shortage or overflow, the unified timing main control unit 140 simultaneously executes two control actions: The first control action is to cut off all voltage outputs of the grid voltage waveform output unit 160, so that the high voltage drive amplifier circuit 164 of all channels is completely de-energized, ensuring that the high voltage circuit is completely isolated from the water body in the event of a possible flood, and avoiding short circuit or electric shock hazards caused by high voltage contact with the water body; The second control action is to control the temperature and humidity control unit 170 to immediately stop the humidification operation, cut off the power supply to the humidification actuator and close the water inlet valve, to prevent the equipment from burning out and being damaged due to continued operation in the state of water shortage, or to prevent the flood from expanding due to continued water intake in the state of overflow. Through the parallel execution of the above two-way linkage control, the unified timing main control unit 140 completes two protection actions of high-voltage power cut-off and humidification stop at the same time as detecting abnormal liquid level, realizing rapid response and protection against water circuit faults, completely eliminating the two types of water-related risks of dry burning due to water shortage and overflow short circuit, and further improving the three-level safety protection system from condensation prediction to ultra-high humidity linkage to water circuit fault protection.

[0091] In one specific implementation, the water tank is equipped with two liquid level sensors, an upper one located at the highest safe water level line and a lower one located at the lowest working water level line. When the lower liquid level sensor detects no water signal, the unified timing main control unit determines that the water is insufficient, immediately cuts off the high-voltage output of the grid voltage waveform output unit of all channels, and simultaneously controls the temperature and humidity control unit to stop the operation of the humidification actuator and displays the message "Water shortage alarm - please add pure water" on the human-machine interface panel. When the upper liquid level sensor continuously detects a water signal for more than three seconds, the unified timing main control unit determines that the water overflows, similarly cutting off the high-voltage output and stopping humidification, and displays the message "Overflow alarm - please check drainage". The liquid level sensor is a continuous liquid level sensor, and the unified timing main control unit reads the liquid level height value in real time. When the liquid level height value is lower than the first preset threshold or higher than the second preset threshold, a protection action is triggered. The above method can provide early warning of trend anomalies in the liquid level deviating from the normal range but not yet reaching the alarm threshold. When the main control unit detects that the liquid level change rate exceeds the normal range, it will actively adjust the opening of the inlet valve or the working status of the drain pump to achieve preventive maintenance.

[0092] In one embodiment, the high-temperature and high-humidity gate bias aging test of power devices is used as an example. The operator configures the gate voltage and humidity parameters via the human-machine interface panel: positive gate voltage amplitude +20V, negative gate voltage amplitude -10V, first duration (positive excitation phase) 500 hours, second duration (negative excitation phase) 500 hours, and third duration (zero-voltage stagnation phase) zero. The first humidity setting is 60% RH relative humidity, corresponding to the positive excitation phase; the second humidity setting is 70% RH relative humidity, corresponding to the negative excitation phase. After the unified timing master control unit writes the above parameters into the global timing register, it starts the test process: During the 500 hours of positive excitation, the gate voltage waveform output unit continuously outputs a +20V gate voltage, and the temperature and humidity control unit adjusts and maintains the humidity of the sealed test humid area at 60%RH; during the 500 hours of negative excitation, the gate voltage waveform output unit switches to output a -10V gate voltage, and the temperature and humidity control unit steps the humidity of the sealed test humid area from 60%RH to 70%RH and maintains it at this set value. Since both the first and second durations are on the order of hours, which is much longer than the response time of humidity control (on the order of seconds to minutes), the temperature and humidity control unit has sufficient time to complete the humidity adjustment during the stage switching, realizing the synchronous coupling of electrical stress and environmental stress on the aging stage scale, rather than the synchronous switching on the gate voltage cycle scale.

[0093] In another embodiment, the operator configures a multi-stage stepped humidity aging test scheme: the first duration (positive excitation phase) is set to 300 hours, with the humidity setpoint incremented in 100-hour increments within that 300 hours, successively reaching 60%RH-70%RH-80%RH; the second duration (negative excitation phase) is set to 300 hours, with the humidity setpoint incremented in 100-hour increments within that 300 hours, successively reaching 80%RH-70%RH-60%RH; the third duration is zero. The unified timing control unit adjusts the humidity setpoint three times within the 300-hour positive excitation phase according to preset time nodes and sends the adjustments to the temperature and humidity control unit for execution, simulating the real-world operating conditions of power devices under different humidity stresses at different service stages.

[0094] In one embodiment, an eight-channel test setup is used to simultaneously perform gate reliability testing on multiple models of gallium nitride power devices. The operator configures differentiated channel parameters via a human-machine interface panel: Channel 1 is set to a first duration of 720 hours, second and third durations of 0 seconds, and a positive gate voltage of +20V, outputting a static DC waveform for high-temperature gate bias testing; Channel 2 is set to a first and second duration of 100ms each, a third duration of 0 seconds, and positive and negative gate voltages of ±15V, outputting a symmetrical alternating square wave for symmetrical alternating stress testing; Channels 3 and 4 are configured with positive gate voltages of +20V / +18V and negative gate voltages of -5V / -8V, respectively, and a first duration of 80ms. Channels 5-8 are configured with first and second durations of 100ms, third durations of 100ms, 200ms, 500ms, and 1000ms respectively, and positive and negative gate voltages of +18V / -12V. These channels output intermittent gate voltage waveforms with different stagnation durations to evaluate the impact of stagnation duration on the device aging rate.

[0095] The unified timing master control unit synchronously writes the parameters of each channel into the independent address space corresponding to the global timing register, reads all channel parameters in parallel on the same clock edge, and synchronously drives the corresponding waveforms of each digital-to-analog converter and high-voltage drive amplifier circuit. The temperature in the closed test humid area is kept constant at 125℃ throughout the test; the temperature and humidity control unit maintains the humidity at 88%RH during the excitation phase and switches to 40%RH during the zero-voltage stagnation phase. The humidity switching and the gate voltage switching are synchronously aligned on the same clock edge.

[0096] This solution can simultaneously conduct multi-condition aging tests within a single chamber, with a test cycle of 1000 hours, without the need to replace hardware or external signal sources; all channels have consistent environmental variables, eliminating environmental fluctuation system errors in traditional split-type equipment time-sharing tests, and improving batch testing efficiency by approximately 4 times compared to item-by-item testing.

[0097] like Figure 3 As shown, embodiments of this application provide a multi-stress synchronous coupling reliability testing method for the gate of a power device, applied to the multi-stress synchronous coupling reliability testing apparatus as described in any of the above embodiments. The multi-stress synchronous coupling reliability testing method includes:

[0098] Step 202: Construct a global timing register that includes an electrical stress timing parameter storage area and an environmental stress timing parameter storage area;

[0099] Step 204: The timing parameters are synchronously loaded into the hardware timer, and the count matching signal of the hardware timer is used as the synchronous trigger source of the unified timing bus.

[0100] Step 206: Based on the synchronous trigger source, voltage output control command and humidity output control command are synchronously issued at the same clock edge;

[0101] Step 208: The voltage output control command is used to control the grid voltage waveform output unit to output a positive grid voltage in the first duration, switch to output a negative grid voltage in the second duration, and output zero voltage in the third duration when the zero voltage is stagnant.

[0102] Step 210: The humidity output control command is used to control the temperature and humidity control unit to adjust the test chamber to the first humidity setting value within the first and second time periods, and to switch the test chamber to a second humidity setting value different from the first humidity setting value within the third time period.

[0103] This method constructs a partitioned global timing register to incorporate electrical stress and environmental stress parameters into the same hardware timing scheduling system, fundamentally solving the problems of parameter separation and inconsistent timing references in split devices. It also relies on a hardware timer to generate a counting matching signal as a synchronization trigger source, providing a deterministic hardware-level time reference that is not affected by software scheduling and avoiding jitter at the trigger moment.

[0104] Based on this trigger source, voltage and humidity control commands are synchronously issued on the same clock edge, ensuring strict time alignment between the segmented switching of the gate voltage waveform and the switching of the humidity setpoint. This achieves microsecond-level synchronous coupling of gate voltage electrical stress and humidity stress, resolving the shortcomings of traditional split-type devices with asynchronous multi-master control and time differences in stress coupling. Simultaneously, the humidity setpoint automatically switches in segments according to the gate voltage excitation stage, forming a closed-loop linkage of "electrical-humidity" stress timing, accurately reproducing the actual alternating damp and hot service environment of the device. Furthermore, this method can achieve four types of gate voltage waveform output simply through parameter configuration, without requiring hardware replacement or external signal sources. It can comprehensively cover the gate reliability testing standards of various power devices, significantly expanding the test scenario coverage of a single device.

[0105] In one embodiment, the above method is used to perform dynamic damp-heat coupling test of high temperature and high humidity grid bias test: the first test channel is selected through the human-machine interface panel, the positive grid voltage amplitude is configured as +20V, the negative grid voltage amplitude is configured as -10V, the first duration is 500h, the second duration is 500h, the third duration is 0, the temperature setting is 85℃, the first humidity setting is 85%RH, and the second humidity setting is 85%RH; at this time, the humidity setting values ​​of the two stages are consistent, the device maintains constant damp-heat stress throughout the process, and outputs symmetrical alternating square wave grid voltage.

[0106] The above method can also perform intermittent aging tests with pauses to simulate the intermittent operation of power devices: a positive gate voltage amplitude of +15V and a negative gate voltage amplitude of -5V are configured, with a first duration of 100ms, a second duration of 100ms, and a third duration of 500ms. The temperature setting is 125℃, and the first humidity setting is 90%RH and the second humidity setting is 40%RH. The device maintains high temperature and high humidity stress during each 200ms positive and negative excitation cycle, and reduces the humidity to 40%RH during the 500ms pause period, replicating the alternating hot and humid conditions of device condensation during power-on and dehumidification during power-off. During the test, if the difference between the ambient temperature and the dew point temperature calculated by the unified timing control unit is less than or equal to the preset safety threshold, condensation prediction protection is automatically triggered, intercepting the environmental stress timing command and performing heating and dehumidification. The test automatically resumes after the difference recovers to above the safety threshold.

[0107] Figure 4 The waveform diagram is a static DC gate voltage: the horizontal axis is the time axis, and the vertical axis is the gate voltage, covering the positive and negative gate voltage amplitude range; the waveform is a horizontal straight line parallel to the time axis, without jumps, periodic changes, or zero-voltage pauses. When the first duration > 0, and the second and third durations are both 0, the corresponding DC gate voltage is output, supporting any constant voltage output within 0~±20V. Figure 5 The waveform diagram is a symmetrical alternating square wave grid voltage: the waveform is a periodic standard square wave with steep edges and no distortion. Each cycle contains two continuous periods, one positive and one negative, with no zero-voltage stagnation interval. The absolute values ​​of the positive and negative voltage amplitudes are equal, the first duration is equal to the second duration, the duty cycle is 50%, and the cycle repeats.

[0108] Figure 6 The waveform diagram is for an asymmetric alternating square wave grid voltage: the waveform is a periodic asymmetric square wave with regular edges and no stagnation intervals; the positive and negative voltage amplitudes are independently adjustable (0~+20V, 0~-20V continuously adjustable), and the first duration and the second duration can be set independently without symmetrical matching.

[0109] Figure 7 , Figure 8The waveform diagram shows the intermittent gate voltage with zero-voltage stagnation, corresponding to two operating conditions: symmetrical and asymmetrical positive and negative amplitudes. A single waveform cycle includes three continuous periods: positive voltage, negative voltage, and zero-voltage stagnation, with steep edges and stable zero-level. The positive and negative periods correspond to the first and second durations, respectively, while the stagnation period corresponds to the third duration. The third duration is infinitely adjustable from 0 to 10000 ms, allowing for flexible changes to the effective excitation duty cycle. After each positive and negative excitation cycle ends, the third duration is forcibly paused before restarting the next excitation cycle. Figure 7 For the amplitude symmetry condition, Figure 8 For asymmetric amplitude operation, it can achieve triple independent control of amplitude, duration, and dwell time.

[0110] Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 In the table, Vgs is the threshold voltage, t1 is the first duration, t2 is the second duration, and t3 is the third duration.

[0111] This embodiment specifically includes:

[0112] 1. Grid voltage output specifications: The grid voltage output range is continuously adjustable from ±0V to ±20V, with an output accuracy of ≤±0.1V; the ripple voltage in static DC mode is ≤5mV, and there is no drift during long-term operation; in alternating square wave mode, the rise and fall times are ≤100ns, with no edge distortion or overshoot.

[0113] 2. Timing and duty cycle control: The intermittent pause duration t3 is continuously adjustable from 0ms to 10000ms with an adjustment accuracy of 1ms; the effective excitation duty cycle can be freely configured through parameters, and the calculation formula is: effective excitation duty cycle = (t1+t2) / (t1+t2+t3)×100%, which can break through the limitation of the traditional fixed 50% duty cycle.

[0114] 3. Environmental control accuracy: The ambient temperature deviation is controlled within ±2℃ throughout the test, and the humidity control accuracy meets the testing requirements of various industry standards such as HTGB, H3TRB, and HAST. It supports multi-scale stress synchronous coupling of hour-level aging cycle and millisecond-level dynamic cycle.

[0115] This embodiment follows a standardized six-step execution process to achieve fully automated scheduling:

[0116] 1. Parameter configuration: Select the target test channel through the human-machine interface panel, configure the positive and negative amplitude of the grid voltage, the positive excitation duration t1, the negative excitation duration t2, the zero pressure stagnation duration t3, and simultaneously preset the excitation stage humidity RH1, the stagnation stage humidity RH2 and the ambient temperature setting values.

[0117] 2. Parameter solidification: The unified timing master control unit synchronously writes voltage, timing, and humidity parameters into the corresponding storage partition of the global timing register to complete parameter initialization and logical constraint verification.

[0118] 3. Environmental pretreatment: The main control unit issues temperature and humidity control commands, and the temperature and humidity control unit stabilizes the environment of the sealed test humid area to the preset temperature and humidity values ​​of the excitation stage.

[0119] 4. Synchronous timing test: The hardware timer loads timing parameters and generates a counting matching signal. Using this signal as the synchronous trigger source, the unified timing bus synchronously issues control commands on the same clock edge and executes them in a segmented closed-loop cycle: during the period 0~t1, a positive gate voltage is output and the humidity is maintained at RH1; during the period t1~t1+t2, a negative gate voltage is switched and the humidity is maintained at RH1; during the period t1+t2~t1+t2+t3, the gate voltage returns to zero and switches to the humidity at RH2, realizing the synchronous coupling of gate voltage electrical stress and humidity environmental stress throughout the entire process.

[0120] 5. Real-time safety monitoring: Throughout the test, the sensor network collects real-time data on chamber temperature, humidity, dew point, and water tank level. When any of the protection thresholds for condensation warning, ultra-high humidity anomaly, or water circuit failure is triggered, the system automatically performs linked protection actions such as heating up and dehumidifying, grid pressure reduction / break, and stopping humidification. Simultaneously, a time-series fault log with timestamps and channel numbers is generated.

[0121] 6. Test Completion: After manual stop or the end of the test cycle, all channel grid voltage outputs are simultaneously cut off, and the temperature and humidity control unit automatically performs dehumidification and cooling operations; the system retains all test data and time sequence logs completely, supporting subsequent analysis.

[0122] The core protection points of this solution are timing coupling control, waveform generation, linkage protection, and time-sharing scheduling algorithm. The hardware carrier can be flexibly expanded. The following alternative solutions all fall within the protection scope of this invention:

[0123] 1. Channel expansion: The number of test channels can be expanded from 8 to 10, 16 or more, only adding the corresponding digital-to-analog conversion and high-voltage drive hardware paths, while the core unified timing scheduling and stress linkage control logic remain unchanged.

[0124] 2. Humidity segmentation expansion: The two-stage humidity control can be expanded into three or more stepped humidity timing, adapting to multi-gradient accelerated aging test scenarios, while the core synchronous triggering and timing linkage scheduling logic remains unchanged.

[0125] 3. Hardware module replacement: Hardware units such as humidification and dehumidification actuators, temperature and humidity sensors, and liquid level sensors can be replaced with devices of the same function but different structures without affecting the core software control logic and synchronous coupling effect.

[0126] 4. Cavity structure expansion: It can be expanded into a multi-independent sub-cavity structure, with each sub-cavity sharing the same unified timing bus, supporting single-channel independent temperature and humidity environment and gate stress coupling test.

[0127] 5. Parameter range expansion: The gate voltage output range, stagnation time range, and temperature and humidity control range can be adaptively adjusted according to test requirements, while the core four-segment waveform generation and multi-stress synchronous coupling mechanism remain unchanged.

[0128] This device is equipped with parameter power-off memory and automatic fault tracing functions: test parameters are not lost after being written to the global timing register and can be quickly restored to the test state after the device is restarted; when a fault occurs, the trigger time, associated channel, measured parameters and protection action type are automatically recorded, supporting automatic fault tracing analysis, adapting to 24 / 7 uninterrupted batch aging test scenarios, and reducing manual operation and maintenance costs.

[0129] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A multi-stress synchronous coupling reliability testing device for the gate of a power device, characterized in that, include: High-voltage control dry area; A sealed test wet zone is provided, with an insulating and sealed isolation structure between the high-voltage control dry zone and the sealed test wet zone, and the power device under test is placed in the sealed test wet zone; The unified timing master control unit includes a global timing register, a hardware timer, and a unified timing bus. The global timing register includes an electrical stress timing parameter storage area and an environmental stress timing parameter storage area. The hardware timer is used to load timing parameters and generate a counting matching signal. A grid voltage waveform output unit is disposed in the high voltage control dry area. The output terminal of the grid voltage waveform output unit is connected to the gate of the power device under test through an airtight insulating connector embedded in the insulating and sealed isolation structure. Temperature and humidity control unit is used to control the ambient temperature and humidity in the sealed test wet area; A sensor network is used to collect environmental parameters within the closed test wet zone; The unified timing bus is used to send control commands to the gate voltage waveform output unit and the temperature and humidity control unit at the same clock edge, using the counting matching signal as a synchronous trigger source. This causes the gate voltage waveform output unit to output a positive gate voltage in the first duration, a negative gate voltage in the second duration, and zero voltage in the third duration when the zero voltage is stagnant. The temperature and humidity control unit adjusts the sealed test humidity zone to a first humidity setting value in the first and second durations, and switches the sealed test humidity zone to a second humidity setting value different from the first humidity setting value in the third duration.

2. The multi-stress synchronous coupling reliability testing device according to claim 1, characterized in that, The gate voltage waveform output unit includes: A multi-channel digital-to-analog converter, wherein each of the digital-to-analog converters corresponds to an independent channel register in the global timing register; A high-voltage drive amplifier circuit is connected to each of the digital-to-analog converters described above. Each of the independent channel registers is used to store the gate voltage amplitude, waveform mode, and the first duration, second duration, and third duration of the corresponding period for the corresponding test channel.

3. The multi-stress synchronous coupling reliability testing device according to claim 2, characterized in that, The unified timing master control unit is used to control multiple test channels to output gate voltage waveforms with different duty cycles, different amplitudes or different waveform modes in parallel, based on the parameters in their respective independent channel registers, under the drive of the synchronous trigger source.

4. The multi-stress synchronous coupling reliability testing device according to claim 1, characterized in that, The grid voltage waveform output unit generates static DC grid voltage waveforms, symmetrical alternating square wave grid voltage waveforms, asymmetrical alternating square wave grid voltage waveforms, or intermittent grid voltage waveforms with zero voltage stagnation based on the parameter configuration of the first duration, the second duration, and the third duration.

5. The multi-stress synchronous coupling reliability testing device according to claim 4, characterized in that: When the first duration is greater than zero, and the second duration and the third duration are both zero, the static DC gate voltage waveform is output; When the first duration is equal to the second duration, the absolute values ​​of the positive gate voltage and the negative gate voltage are equal, and the third duration is zero, the symmetrical alternating square wave gate voltage waveform is output. When the first duration is not equal to the second duration, or the absolute values ​​of the positive gate voltage and the negative gate voltage are not equal, and the third duration is zero, the asymmetric alternating square wave gate voltage waveform is output. When the third duration is greater than zero, the intermittent gate voltage waveform with zero-voltage pause is output.

6. The multi-stress synchronous coupling reliability testing device according to claim 1, characterized in that, The sensor network includes: a temperature sensor for collecting ambient temperature, a humidity sensor for collecting ambient humidity, and a level sensor for detecting the liquid level in the water tank of the temperature and humidity control unit.

7. The multi-stress synchronous coupling reliability testing device according to claim 6, characterized in that, The unified timing master control unit is also used to calculate the real-time dew point temperature based on the collected ambient temperature and ambient humidity, and when the difference between the ambient temperature and the real-time dew point temperature is less than or equal to a preset safety threshold, control the temperature and humidity control unit to perform a heating and dehumidification operation, and control the gate voltage waveform output unit to reduce or cut off the voltage output.

8. The multi-stress synchronous coupling reliability testing device according to claim 6, characterized in that, The unified timing master control unit is also used to control the gate voltage waveform output unit to perform voltage reduction or voltage cut-off when the ambient humidity exceeds the preset humidity threshold and continues for a preset time, and to generate alarm information.

9. The multi-stress synchronous coupling reliability testing device according to claim 6, characterized in that, The unified timing master control unit is also used to cut off the voltage output of the grid voltage waveform output unit and control the temperature and humidity control unit to stop humidifying when the liquid level sensor detects an abnormal liquid level state.

10. A method for testing the reliability of multi-stress synchronous coupling of a power device gate, characterized in that, The multi-stress synchronous coupling reliability testing method, applied to the multi-stress synchronous coupling reliability testing apparatus as described in any one of claims 1 to 9, comprises: Construct a global timing register that includes a storage area for electrical stress timing parameters and a storage area for environmental stress timing parameters; The timing parameters are synchronously loaded into the hardware timer, and the count matching signal of the hardware timer is used as the synchronous trigger source of the unified timing bus. Based on the synchronous trigger source, voltage output control commands and humidity output control commands are synchronously issued at the same clock edge. The voltage output control command is used to control the grid voltage waveform output unit to output a positive grid voltage in the first time period, switch to output a negative grid voltage in the second time period, and output zero voltage in the third time period when the zero voltage is stagnant. The humidity output control command is used to control the temperature and humidity control unit to adjust the test chamber to a first humidity setting value within the first and second durations, and to switch the test chamber to a second humidity setting value different from the first humidity setting value within the third duration.

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