A junction temperature correction monitoring method and system for decoupling of power device dual aging

Abstract

The application relates to the technical field of data processing, in particular to a junction temperature correction monitoring method and system for decoupling of double aging of a power device. The method comprises the following steps: calibrating a temperature-sensitive reference curve, distributing coefficients of initial thermal resistance parameters of a hierarchical thermal network model and increments of thermal resistances of a chip and a substrate solder layer; obtaining power loss and shell temperature of the device, inputting the hierarchical thermal network model to output a predicted junction temperature value; monitoring an operating state of an inverter, collecting steady-state conduction parameters when a steady-state constraint condition is met, and obtaining standard conduction parameters according to the temperature-sensitive reference curve; determining an electrical aging drift amount by combining the standard conduction parameters and the steady-state conduction parameters, updating an electrical aging coefficient, and compensating to obtain a target junction temperature value; comparing the predicted junction temperature value and the target junction temperature value to determine a total thermal resistance increment, and updating thermal resistance parameters of two solder layers; and after correction, using the hierarchical thermal network model to estimate the junction temperature under load. The method realizes decoupling correction of wire bonding electrical aging and solder layer thermal aging, and reduces the accumulation of junction temperature monitoring errors.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a junction temperature correction and monitoring method and system for dual aging decoupling of power devices. Background Technology

[0002] IGBTs and SiC are core power semiconductor devices in the power conversion system of new energy vehicles. The junction temperature of these devices is a key indicator for overload protection, lifespan prediction, fault diagnosis, and functional safety management.

[0003] In the existing solution, the junction temperature reference curve of the power device is pre-calibrated and fixed to the controller. During the operation of the equipment, the on-state voltage of the device is collected by an external discrete sampling circuit. A single bias coefficient is used to compensate for the voltage drift caused by the aging of the bonding wire, so as to improve the monitoring accuracy of long-term operation.

[0004] However, since the electrical aging of bonding wires and the thermal aging of solder layers are coupled and superimposed in the conduction voltage signal, single voltage compensation cannot distinguish between the two different aging mechanisms, which can easily lead to over-compensation or under-compensation. At the same time, the thermal network model adopts the parameter design of overall offline solidification, which does not distinguish the differentiated aging rates of chip solder layers and substrate solder layers. The thermal resistance correction lacks physical layering basis, resulting in long-term accumulation of junction temperature monitoring errors. Summary of the Invention

[0005] Based on this, this application provides a junction temperature correction monitoring method and system for power devices with dual aging decoupling, aiming to solve the technical problems in related technologies where single compensation for bonding wire electrical aging causes conduction voltage drop drift, which cannot distinguish the temperature rise deviation caused by thermal aging of chip solder layer and substrate solder layer; and where electrical aging and thermal aging are simultaneously superimposed and coupled, leading to long-term accumulation of junction temperature monitoring errors.

[0006] In a first aspect, embodiments of this application provide a junction temperature correction and monitoring method for dual aging decoupling of power devices, including: The temperature-sensitive reference curve of the calibrated power device, the initial thermal resistance parameters of the layered thermal network model, and the thermal resistance increment distribution coefficient between the chip solder layer and the substrate solder layer. Obtain the power loss and case temperature of the power device, input them into the calibrated layered thermal network model, and output the predicted junction temperature value; Monitor the operating status of the inverter to determine whether the preset steady-state constraint conditions are met. If so, collect the steady-state conduction parameters of the power devices and obtain the standard conduction parameters under the corresponding operating conditions based on the temperature-sensitive reference curve. The electrical aging drift is determined based on the standard conduction parameters and the steady-state conduction parameters. The electrical aging coefficient is updated according to the electrical aging drift, and the steady-state conduction parameters are offset compensated to obtain the target junction temperature value. By comparing the predicted junction temperature with the target junction temperature, when there is a steady-state temperature difference, the total thermal resistance increment of the power device is determined. Based on the thermal resistance increment allocation coefficient, the total thermal resistance increment is allocated and the thermal resistance parameters of the two solder layers in the layered thermal network model are updated. After the correction was completed, the updated thermal resistance parameters and electrical aging coefficients of the two solder layers were frozen, and the junction temperature under load was estimated based on the updated layered thermal network model.

[0007] In some embodiments, the steps of calibrating the temperature-sensitive reference curve of the power device, the initial thermal resistance parameters of the layered thermal network model, and the thermal resistance increment allocation coefficients of the chip solder layer and the substrate solder layer include: The thermal impedance cooling curve of the power device is collected, and the structure function is obtained by performing differential and integral transformation on the thermal impedance cooling curve. Determine the step inflection point in the structure function, divide the heat transfer segments corresponding to the chip active layer, chip bonding layer, DBC ceramic layer, substrate bonding layer and copper substrate based on the step inflection point, and extract the initial thermal resistance value corresponding to each segment. The initial thermal resistance of the chip active layer, DBC ceramic layer, and copper substrate is set to the thermal resistance of the cured substrate. The initial thermal resistance of the chip solder layer and substrate solder layer is set to the solder layer thermal resistance that can be iteratively updated, thus completing the initial thermal resistance parameter configuration of the layered thermal network model.

[0008] In some embodiments, the steps of calibrating the temperature-sensitive reference curve of the power device, the initial thermal resistance parameters of the layered thermal network model, and the thermal resistance increment distribution coefficient between the chip solder layer and the substrate solder layer further include: Power cycling accelerated aging test was conducted on power devices. Steady-state junction-shell temperature difference was collected at multiple preset aging nodes, and the total thermal resistance increment corresponding to each node was calculated. Based on the structure function, the independent thermal resistance changes of the chip solder layer and the substrate solder layer at each aging node are determined. The thermal resistance increment allocation coefficient is obtained according to the proportion of the thermal resistance increment of the two types of solder layers to the total thermal resistance increment.

[0009] In some embodiments, the step of obtaining the power loss and case temperature of the power device, inputting them into a calibrated layered thermal network model, and outputting a predicted junction temperature value includes: Based on the thermal resistance parameters of the solidified substrate in the hierarchical thermal network model, and the thermal resistance parameters of the chip solder layer and the substrate solder layer, the cascade heat transfer topology from the chip junction to the shell is determined. The power loss is used as the heat source excitation input to the chip junction of the cascaded heat transfer topology, and the case temperature is used as the heat dissipation boundary condition of the cascaded heat transfer topology. The real-time temperature of each interface is calculated iteratively according to the heat transfer level. The real-time temperature of the chip junction at the top layer of the cascaded heat transfer topology is used as the predicted junction temperature value output by the hierarchical thermal network model.

[0010] In some embodiments, the steps of determining the electrical aging drift based on the standard conduction parameters and the steady-state conduction parameters, updating the electrical aging coefficient according to the electrical aging drift, and performing offset compensation on the steady-state conduction parameters to obtain the target junction temperature value include: The difference between the steady-state conduction parameter and the standard conduction parameter is used as the electrical aging drift amount; The conduction parameter drift is substituted into a preset first-order low-pass recursive formula to iteratively update the electrical aging coefficient. The iterative process does not modify the inherent slope and curvature of the temperature-sensitive reference curve. Based on the electrical aging coefficient, the steady-state conduction parameters are offset in reverse to obtain the target temperature-sensitive parameters. The target temperature-sensitive parameters are then substituted into the temperature-sensitive reference curve to obtain the target junction temperature value.

[0011] In some embodiments, in the step of substituting the conduction parameter drift into a preset first-order low-pass recursive formula to iteratively update the electrical aging coefficient, the expression of the first-order low-pass recursive formula is:

[0012] In the formula, The updated electrical aging factor. This represents the electrical aging factor stored in the previous cycle. The convergence coefficient is . This represents the drift of the conduction parameters.

[0013] In some embodiments, the step of comparing the predicted junction temperature value with the target junction temperature value, determining the total thermal resistance increment of the power device when a steady-state temperature difference exists, and allocating and updating the thermal resistance parameters of the two solder layers in the layered thermal network model according to the thermal resistance increment allocation coefficient includes: Based on the predicted junction temperature value and the target junction temperature value at multiple sampling times, the junction temperature deviation value is calculated one by one. When all junction temperature deviation values ​​in the corresponding sampling interval tend to the same temperature difference value, the average value of all junction temperature deviation values ​​is used as the steady-state temperature difference value. Based on the power loss value under the current steady-state operating conditions and the steady-state temperature difference value, determine the total thermal resistance increment of the power device; According to the thermal resistance increment allocation coefficient, the total thermal resistance increment is divided into the chip solder layer thermal resistance increment and the substrate solder layer thermal resistance increment according to the calibrated allocation ratio. The thermal resistance increments of the two types of weld layers are respectively superimposed on the current weld layer thermal resistance parameters corresponding to the layered thermal network model, while keeping the substrate thermal resistance in the layered thermal network model unchanged, thus completing the layered adaptive update of the thermal resistance parameters.

[0014] Compared with the prior art, the technical solution provided in the first aspect of this application includes at least the following beneficial effects or advantages: The junction temperature correction and monitoring method provided in this application predicts the junction temperature by calling a calibrated layered thermal network model with power loss and case temperature as inputs. Simultaneously, it continuously monitors the operating status to determine steady-state conditions. Multi-level correction is performed only when all constraints of the no-load steady-state self-test are met. During the correction process, the electrical aging drift of the conduction parameters is first calculated based on the calibrated temperature-sensitive reference curve. After offset compensation, the target junction temperature is obtained. Then, the thermal resistance deviation is calculated using this target junction temperature as a reference. This ensures that the calculation of the thermal resistance increment corresponds only to the change in heat transfer characteristics caused by solder layer thermal aging, achieving decoupling between bond wire electrical aging and solder layer thermal aging, and avoiding the compensation deviation caused by the coupling and superposition of the two types of aging. The layered thermal network model divides the heat transfer structure into a substrate layer and two types of solder layers. Combined with a pre-calibrated thermal resistance increment allocation coefficient, the total thermal resistance increment can be divided into the chip solder layer and the substrate solder layer according to the aging contribution ratio. This employs layered thermal resistance adaptive updating to specifically correct solder layer thermal aging deviations, avoiding the accumulation of errors from long-term operation of a fixed thermal model and improving the accuracy of online junction temperature monitoring for power devices.

[0015] Secondly, embodiments of this application provide a junction temperature correction monitoring system for power devices with dual aging decoupling, comprising: The parameter calibration module is used to calibrate the temperature-sensitive reference curve of the power device, the initial thermal resistance parameters of the layered thermal network model, and the thermal resistance increment distribution coefficient between the chip solder layer and the substrate solder layer. The model prediction module is used to obtain the power loss and case temperature of the power devices, input the calibrated layered thermal network model, and output the predicted junction temperature value. The steady-state judgment module is used to monitor the operating status of the inverter and determine whether the preset steady-state constraint conditions are met. If so, it collects the steady-state conduction parameters of the power devices and obtains the standard conduction parameters under the corresponding operating conditions based on the temperature-sensitive reference curve. An electrical compensation module is used to determine the electrical aging drift based on the standard conduction parameters and the steady-state conduction parameters, update the electrical aging coefficient according to the electrical aging drift, and perform offset compensation on the steady-state conduction parameters to obtain the target junction temperature value. The thermal resistance correction module is used to compare the predicted junction temperature value with the target junction temperature value. When there is a steady-state temperature difference, it determines the total thermal resistance increment of the power device and allocates and updates the thermal resistance parameters of the two solder layers in the layered thermal network model according to the thermal resistance increment allocation coefficient. The junction temperature estimation module is used to freeze the updated thermal resistance parameters and electrical aging coefficients of the two solder layers after calibration, and to estimate the junction temperature under load based on the updated layered thermal network model.

[0016] Thirdly, this application also provides an electronic device, comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the steps of the junction temperature correction monitoring method for dual aging decoupling of power devices provided in the first aspect above.

[0017] Fourthly, this application also provides a computer-readable storage medium storing computer program instructions thereon, which, when executed by a processor, implement the steps of the junction temperature correction and monitoring method for dual aging decoupling of power devices provided in the first aspect.

[0018] It is understood that the beneficial effects of the technical solutions provided in the second, third and fourth aspects above can be found in the relevant descriptions in the first aspect above, and will not be repeated here.

[0019] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A flowchart of the junction temperature correction and monitoring method for dual aging decoupling of power devices provided in this application embodiment; Figure 2 The flowchart of sub-step S400 in the junction temperature correction and monitoring method for dual aging decoupling of power devices provided in the embodiments of this application; Figure 3 The flowchart of sub-step S500 in the junction temperature correction and monitoring method for dual aging decoupling of power devices provided in the embodiments of this application; Figure 4 This is a structural block diagram of a junction temperature correction and monitoring system for dual aging decoupling of power devices provided in an embodiment of this application; Figure 5A structural block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0022] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate several embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0023] It should be noted that, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0024] Please see Figures 1 to 3 This embodiment provides a junction temperature correction and monitoring method for dual aging decoupling of power devices, specifically including steps S100 to S600.

[0025] Step S100: Calibrate the temperature-sensitive reference curve of the power device, the initial thermal resistance parameters of the layered thermal network model, and the thermal resistance increment distribution coefficient between the chip solder layer and the substrate solder layer.

[0026] In this step, the calibration of the temperature-sensitive reference curve can be achieved by selecting a brand-new, unaged power device of the same model as the target application, placing it in a high-low temperature constant temperature test platform with compliant temperature control accuracy, stabilizing the device casing temperature at multiple preset temperature nodes, and passing multiple sets of constant-level test currents at each temperature node. After the internal thermal equilibrium of the device is reached, the on-state voltage drop parameters of the power device under the corresponding operating conditions are collected. With junction temperature as the independent variable and on-state voltage drop as the dependent variable, polynomial fitting is performed on multiple sets of test data to generate a temperature-sensitive reference curve covering the corresponding operating temperature range and test current range.

[0027] In one embodiment, the calibration of the initial thermal resistance parameters of the layered thermal network model includes: acquiring the thermal impedance cooling curves of the power devices; performing differential and integral transformations on the thermal impedance cooling curves to obtain the structure function; determining the step inflection points in the structure function; dividing the heat transfer segments corresponding to the chip active layer, chip solder layer, DBC ceramic layer, substrate solder layer, and copper substrate based on the step inflection points; extracting the initial thermal resistance values ​​corresponding to each segment; setting the initial thermal resistance of the chip active layer, DBC ceramic layer, and copper substrate to the thermal resistance of the cured substrate; setting the initial thermal resistance of the chip solder layer and substrate solder layer to the solder layer thermal resistance that can be iteratively updated; and completing the initial thermal resistance parameter configuration of the layered thermal network model.

[0028] Specifically, the transient thermal impedance method can be used to obtain the original thermal characteristic parameters of the device. Similarly, a brand new, unaged power device of the same model as the target application is selected. During the test, a constant heating power is applied to the power device. After the junction temperature of the device rises to a thermally stable state, the heating power is cut off and the cooling change curve of the device junction temperature over time is collected simultaneously to obtain the original transient thermal impedance data. Differential operation is performed on the transient thermal impedance cooling curve to obtain the corresponding time constant spectrum. Then, cumulative integral transformation is performed on the time constant spectrum to generate a cumulative structure function. Multiple step feature points on the cumulative structure function are identified. Based on the step position, the chip active layer, chip solder layer, DBC ceramic layer, substrate solder layer, and copper substrate are divided into multiple heat transfer segments. The initial thermal resistance and initial thermal capacity values ​​corresponding to each segment are extracted respectively.

[0029] In this embodiment, after extracting the layering parameters, the thermal resistance and thermal capacity parameters corresponding to the chip active layer, DBC ceramic layer, and copper substrate are set as the parameters of the cured substrate. The thermal resistance parameters corresponding to the chip solder layer and substrate solder layer are set as iteratively updatable initial values. The layering method based on structure functions can realize the correspondence between thermal resistance parameters and physical packaging structure. By distinguishing between the design of cured substrate parameters and updatable solder layer parameters, it can avoid erroneous correction of parameters without aging during subsequent calibration at the model architecture level.

[0030] In one embodiment, the calibration of the thermal resistance increment allocation coefficient between the chip solder layer and the substrate solder layer includes: conducting a power cycling accelerated aging test on the power device, collecting steady-state junction-to-shell temperature differences at multiple preset aging nodes, calculating the total thermal resistance increment corresponding to each node; determining the independent thermal resistance changes of the chip solder layer and the substrate solder layer at each aging node based on the structure function, and obtaining the thermal resistance increment allocation coefficient according to the proportion of the thermal resistance increments of the two types of solder layers to the total thermal resistance increment.

[0031] Specifically, a power cycling accelerated aging test can be conducted on brand-new power devices from the same batch. The junction temperature fluctuation amplitude, average junction temperature, and cycle period are set to match the device's operating conditions. At multiple preset aging cycle nodes, the transient thermal resistance data of the devices are tested to obtain the delamination thermal resistance values ​​for each aging stage. The total package thermal resistance increment relative to the initial state is calculated for each aging node. Simultaneously, the thermal resistance increments of the chip solder layer and the substrate solder layer are calculated separately. The proportions of the thermal resistance increments of the two types of solder layers to the total thermal resistance increment are statistically analyzed at all aging nodes. The average of these proportions across multiple nodes is taken as the curing thermal resistance increment allocation coefficient.

[0032] In this way, by pre-calibrating and fixing the allocation coefficients, the subsequent online calibration stage does not need to perform complex layer identification calculations. The thermal resistance of the two solder layers can be separated by the total thermal resistance increment and a fixed ratio, reducing the computational load of the online controller.

[0033] It should be noted that the power device can be either an IGBT or a SiC power device. However, in practical applications, due to the different temperature sensing principles of IGBTs and SiC power devices, conventional solutions require separate sampling and conditioning circuits designed to adapt to both types of devices. The method provided in this embodiment, however, is based on the Infineon 1EDI3040AS automotive-grade single-channel isolated gate driver chip to build the overall hardware system architecture. This chip is compatible with the full range of 600V / 750V / 1200V IGBTs and SiC power devices and has built-in... The compensation circuit can directly calibrate and calculate the on-resistance of power devices. It also comes with multiple high-voltage isolation analog acquisition channels, and its hardware resources can simultaneously adapt to the temperature-sensitive parameter acquisition needs of two types of power devices.

[0034] Step S200: Obtain the power loss and case temperature of the power device, input them into the calibrated layered thermal network model, and output the predicted junction temperature value.

[0035] In one embodiment, based on the thermal resistance parameters of the substrate solidified in the hierarchical thermal network model, and the thermal resistance parameters of the chip solder layer and the substrate solder layer, the cascaded heat transfer topology from the chip junction to the housing is determined; power loss is used as the heat source excitation input to the chip junction end of the cascaded heat transfer topology, and the housing temperature is used as the heat dissipation boundary condition of the cascaded heat transfer topology; the real-time temperature of each interface is calculated iteratively according to the heat transfer level; the real-time temperature of the chip junction at the top layer of the cascaded heat transfer topology is used as the predicted junction temperature value output by the hierarchical thermal network model.

[0036] Specifically, the controller collects the bus voltage, output phase current, and switching frequency of the power devices. Combining this with the power devices' loss characteristics, the conduction loss and switching loss are calculated separately, and then summed to obtain the total power loss of the power devices. This total power loss serves as the heat source excitation input for the hierarchical thermal network model. Simultaneously, the casing temperature is acquired through a temperature acquisition unit integrated on the power device casing, serving as the heat dissipation boundary condition input for the hierarchical thermal network model. The power loss corresponds to the heat flow input of the heat transfer path, and the casing temperature corresponds to the low-temperature boundary of the heat transfer path; together, they constitute the heat conduction calculation boundary, providing an accurate excitation basis for subsequent junction temperature calculations.

[0037] In this embodiment, the layered thermal network adopts a cascaded Cauer thermal network architecture corresponding to the physical packaging of the power module. During the model calculation process, the pre-calibrated thermal resistance of the cured substrate and the thermal resistance parameters of the currently effective chip solder layer and substrate solder layer are retrieved to construct a heat transfer calculation link from the chip junction through each packaging layer to the shell. The model performs iterative calculations at a fixed period. In each calculation period, the total power loss is used as the heat flow injected into the chip junction end of the link. The temperature rise value of each interface under the current heat flow is calculated based on the steady-state temperature rise relationship of the thermal resistance. At the same time, the change in heat storage and release of the heat capacity is calculated by combining the transient thermal balance equation of each layer. The real-time temperature of each interface is obtained by recursively deducing along the heat transfer path layer by layer. Finally, the chip junction temperature at the front end of the link is extracted as the predicted junction temperature value output by the layered thermal network model.

[0038] It should be noted that, because all thermal resistance parameters in existing thermal network models are offline-cured values, the model's heat transfer calculation logic becomes mismatched with the actual heat transfer path of the device as the solder layer thermal resistance continues to increase with device operation. Furthermore, the lack of a layered thermal resistance update mechanism makes it impossible to accurately distinguish the differentiated aging and degradation levels of the chip solder layer and the substrate solder layer, leading to long-term accumulation of junction temperature monitoring errors. This embodiment employs a layered architecture mapped to the physical structure for calculation. Compared to existing lumped parameter thermal networks, this more accurately reflects the temperature distribution characteristics inside the package. Simultaneously, a layered thermal resistance adaptive update mechanism is used to specifically correct solder layer thermal aging deviations, ensuring the substrate parameters are cured and accurate, thus preventing the accumulation of errors over long-term operation.

[0039] Step S300: Monitor the operating status of the inverter and determine whether the preset steady-state constraint conditions are met. If so, collect the steady-state conduction parameters of the power devices and obtain the standard conduction parameters under the corresponding operating conditions based on the temperature-sensitive reference curve.

[0040] In one embodiment, the inverter's multi-dimensional operating parameters are acquired in real time through the controller's status acquisition port. These parameters include five categories: DC bus load power, bridge arm output phase current amplitude, PWM drive channel enable status, power module housing temperature, and radiator coolant temperature. All parameters are acquired synchronously at a fixed sampling period to form a dataset for judging steady-state constraints.

[0041] In this embodiment, the preset steady-state constraints include the determination of electrical steady-state and thermal steady-state. The electrical steady-state determination condition is: the inverter is in an unloaded standby state and the fluctuation amplitude of the output phase current is lower than the preset current deviation threshold, while the PWM drive channel is in a ready state that can be controlled to be turned off; the thermal steady-state determination condition is: the change in the temperature of the power device casing per unit time is lower than the preset temperature change rate threshold, and the coolant temperature is within the preset stable operating range.

[0042] It should be noted that during the judgment process, all constraints are compared logically. Only when all conditions are simultaneously met is the system determined to enter a correctable steady-state operating condition. If any condition is not met, the system continues to monitor the operating status in a loop, without initiating subsequent conduction parameter acquisition procedures. By adopting electrical and thermal judgment rules, sampling interference from conditions such as sudden load changes and transient temperature fluctuations can be eliminated, ensuring that the electrical and thermal states of devices within the identification window are stable. When conditions are not met, the system continues to monitor in a loop without performing corrections, thus avoiding invalid correction operations under non-steady-state conditions and preventing abnormal deviations in aging parameters due to dynamic operating condition interference.

[0043] Step S400: Determine the electrical aging drift amount based on the standard conduction parameters and the steady-state conduction parameters, update the electrical aging coefficient according to the electrical aging drift amount, and perform offset compensation on the steady-state conduction parameters to obtain the target junction temperature value.

[0044] In this step, the aging of the bonding wires of the power device is manifested as the peeling of the bonding points and the reduction of the effective conductive cross-sectional area, which ultimately results in an increase in the series ohmic impedance of the conduction circuit. This impedance change will only cause an overall unidirectional shift in the conduction parameters and will not change the temperature-sensitive characteristic change law of the device itself.

[0045] In some embodiments, the process of obtaining the target junction temperature value may include the following steps: Step S410: The difference between the steady-state conduction parameters and the standard conduction parameters is used as the electrical aging drift amount; In this step, the steady-state conduction parameters under the same operating conditions are compared with the standard conduction parameters. The difference obtained is the conduction parameter drift caused by the electrical aging of the bond wire. This drift only corresponds to the increase in conduction parameters caused by electrical aging. Based on the drift obtained by comparing the steady-state parameters under the same operating conditions, the interference of operating condition fluctuations and thermal state differences on the parameter difference can be eliminated, allowing the electrical aging effect to be independently separated from the composite conduction parameter signal, providing input for subsequent aging coefficient updates.

[0046] Step S420: Substitute the conduction parameter drift into the preset first-order low-pass recursive formula and iteratively update the electrical aging coefficient. During the iteration process, the inherent slope and curvature of the temperature-sensitive reference curve are not modified. In this step, after the conduction parameter drift is input, a first-order low-pass recursive algorithm is used to iteratively update the electrical aging coefficient. The iterative process is based on the historical electrical aging coefficient stored in the previous correction cycle, combined with the drift obtained in this calculation, and the coefficient is smoothly updated according to the preset convergence coefficient. The convergence coefficient can be between 0.1 and 0.2, taking into account both the convergence speed and stability of the coefficient update, and avoiding coefficient jumps caused by single sampling fluctuations.

[0047] The expression for the first-order low-pass recursive formula is as follows:

[0048] In the formula, The updated electrical aging factor. This represents the electrical aging factor stored in the previous cycle. The convergence coefficient is . This represents the drift of the conduction parameters.

[0049] It should be noted that the updated electrical aging coefficient corresponds to the overall parallel offset of the temperature-sensitive reference curve. The iterative process only adjusts the vertical offset of the curve, without modifying the inherent slope and curvature of the temperature-sensitive reference curve. This aligns with the physical failure mechanism of bond wire aging, avoids erroneous corrections to the intrinsic temperature-sensitive characteristics of the device, and the recursive smoothing mechanism can adapt to the slowly changing characteristics of the aging process, ensuring the long-term stability of the aging coefficient.

[0050] Step S430: Perform reverse offset compensation on the steady-state conduction parameters based on the electrical aging coefficient to obtain the target temperature-sensitive parameters. Substitute the target temperature-sensitive parameters into the temperature-sensitive reference curve to obtain the target junction temperature value.

[0051] In this step, after updating the electrical aging coefficient, a reverse offset compensation is performed on the measured steady-state conduction parameters using the updated electrical aging coefficient. This involves subtracting the parameter increment caused by electrical aging from the steady-state conduction parameters to obtain the target temperature-sensitive parameters free from electrical aging interference. Subsequently, the target temperature-sensitive parameters are substituted into a pre-calibrated temperature-sensitive reference curve, and the corresponding junction temperature value is obtained through inverse interpolation calculation; this is the target junction temperature value. This compensation method removes the electrical aging component from the conduction parameters, ensuring that the final target junction temperature reflects only the true thermal state of the device. This avoids junction temperature calculation deviations caused by bond wire aging and improves the accuracy of junction temperature measurements based on conduction parameters.

[0052] Step S500: Compare the predicted junction temperature value with the target junction temperature value. When there is a steady-state temperature difference, determine the total thermal resistance increment of the power device. Based on the thermal resistance increment allocation coefficient, allocate the total thermal resistance increment and update the thermal resistance parameters of the two solder layers in the layered thermal network model.

[0053] In this step, the steady-state temperature difference is obtained by comparing the target junction temperature after electrical aging interference has been removed with the predicted junction temperature output by the layered thermal network model. Based on this, the total thermal resistance increment inside the package is calculated. Then, according to the pre-calibrated thermal resistance increment allocation coefficient, the total thermal resistance increment is split and the parameters are updated for the chip solder layer and the substrate solder layer. The thermal resistance correction is based on physical layering, avoiding the defect that the overall thermal resistance correction cannot distinguish the different aging rates of the two types of solder layers, thereby suppressing the continuous accumulation of junction temperature monitoring errors over the running time.

[0054] In some embodiments, the allocation of the total thermal resistance increment in this step specifically includes the following steps: Step S510: Calculate the junction temperature deviation value one by one based on the predicted junction temperature value and the target junction temperature value at multiple sampling times. When all junction temperature deviation values ​​in the corresponding sampling interval tend to the same temperature difference value, the average value of all junction temperature deviation values ​​is used as the steady-state temperature difference value. In this step, the predicted junction temperature and the target junction temperature are obtained from multiple consecutive sampling times within the steady-state window. The deviation between the two sets of junction temperatures at the same time is calculated point by point to obtain the junction temperature deviation sequence of the corresponding sampling sequence. Then, the range of all values ​​in this deviation sequence is calculated. When the range stabilizes at the same value, it is determined that the current junction temperature deviation has reached a stable state, and the arithmetic mean of all deviation values ​​is taken as the final steady-state temperature difference. In this way, it is ensured that the obtained temperature difference corresponds to the true deviation under steady-state heat transfer, rather than the transient difference caused by instantaneous operating condition fluctuations; at the same time, the electrical aging component has been removed from the input target junction temperature, so the obtained steady-state temperature difference only corresponds to the temperature rise deviation caused by the change in thermal resistance of the package heat transfer path.

[0055] Step S520: Based on the power loss value under the current steady-state operating condition and the steady-state temperature difference value, determine the total thermal resistance increment of the power device; In this step, after obtaining the steady-state temperature difference, based on the total power loss of the power devices under the current steady-state operating conditions and according to the definition of thermal resistance for steady-state heat transfer, the ratio of the steady-state temperature difference to the total power loss is used as the total thermal resistance increment of the heat transfer path from the chip junction to the housing. This limits the heat transfer path to the chip junction to the housing, perfectly corresponding to the physical boundary of the layered thermal network model. This eliminates the interference of characteristic fluctuations from external heat transfer components such as external heat sinks and coolant circuits on the thermal resistance calculation results, ensuring that the thermal resistance increment only reflects aging changes within the module package.

[0056] Step S530: According to the thermal resistance increment allocation coefficient, the total thermal resistance increment is divided into the chip solder layer thermal resistance increment and the substrate solder layer thermal resistance increment according to the calibrated allocation ratio. In this step, after calculating the total thermal resistance increment, the pre-calibrated thermal resistance increment allocation coefficients for the chip solder layer and substrate solder layer are called. According to the fixed ratio obtained from the calibration, the total thermal resistance increment is divided into the thermal resistance increments of the chip solder layer and the substrate solder layer. These allocation coefficients correspond to the proportion of thermal resistance contribution of the two types of solder layers during the aging process. Using a fixed-ratio split, the independent quantification of the thermal resistance of the two layers can be achieved through simple proportional calculations, reducing the computational load on the online controller and adapting to the computing power constraints of automotive-grade embedded chips. Simultaneously, the layered split design can distinguish the aging degree of different interfaces, providing more refined physical-level support compared to overall thermal resistance correction.

[0057] Step S540: The thermal resistance increments of the two types of weld layers are respectively superimposed on the current weld layer thermal resistance parameters corresponding to the layered thermal network model, while keeping the substrate thermal resistance in the layered thermal network model unchanged, thus completing the layered adaptive update of the thermal resistance parameters.

[0058] In this step, after obtaining the thermal resistance increments of the two types of solder layers, the thermal resistance increments of the chip solder layer are superimposed on the current thermal resistance parameters corresponding to the chip solder layer in the layered thermal network model, and the thermal resistance increments of the substrate solder layer are superimposed on the current thermal resistance parameters corresponding to the substrate solder layer in the layered thermal network model. During the parameter update process, the thermal resistance parameters of all substrates in the layered thermal network model remain unchanged. During the operation of the power module, the material thermal properties of substrates such as the chip active layer, DBC ceramic layer, and copper substrate do not change significantly with service time. Only the interface between the chip solder layer and the substrate solder layer is prone to deterioration such as delamination due to temperature cycling, which leads to an increase in thermal resistance. By updating only the thermal resistance of the solder layer, erroneous corrections to parameters without aging can be avoided, parameter drift caused by model overfitting can be suppressed, and the stability and accuracy of the thermal network model operation can be guaranteed.

[0059] Step S600: After completing the correction, freeze the updated thermal resistance parameters and electrical aging coefficients of the two solder layers, and estimate the junction temperature under load based on the updated layered thermal network model.

[0060] In this step, under the parameter freeze state, the updated thermal resistance parameters and electrical aging coefficients of the two weld layers remain fixed at their current values. No iterative correction operations are performed in subsequent continuous load operation cycles. The next parameter update will only be initiated when the system determines again that the preset steady-state constraint conditions are met and triggers a new round of correction process. The setting of the corrected frozen parameters works in conjunction with the pre-set steady-state trigger multi-level correction mechanism to build an operating architecture in which aging identification is completed centrally in the steady-state window and the entire load operation is based on fixed parameter estimation, thus achieving a balance between parameter identification accuracy and real-time estimation stability.

[0061] In some embodiments, after entering the parameter freeze state, the controller synchronously writes the chip solder layer thermal resistance, substrate solder layer thermal resistance, and electrical aging coefficient obtained from the current correction into a non-volatile storage unit for persistent storage. Simultaneously, it loads the updated parameters into the real-time calculation register as fixed calculation parameters for junction temperature estimation under load conditions. During load operation, the layered thermal network model uses only the real-time collected power loss and casing temperature as input variables, performs layer-by-layer heat transfer calculations according to a preset discrete iteration cycle, and outputs a real-time predicted junction temperature value. Fixed thermal resistance and heat capacity parameters are used throughout all calculation cycles, without introducing parameter correction-related calculation logic. Separating parameter correction and real-time estimation into two independent operating phases allows controller resources to be more focused on temperature sampling and loss calculation, ensuring the real-time performance and sampling frequency of junction temperature estimation.

[0062] In the junction temperature correction and monitoring method steps provided in the above embodiments, the junction temperature is predicted by calling the calibrated layered thermal network model with power loss and shell temperature as inputs. At the same time, the steady-state condition is determined by continuously monitoring the operating status. Multi-level correction is performed only when all constraints of no-load steady-state self-test are met. During the correction process, the electrical aging drift of the conduction parameters is first calculated based on the calibrated temperature-sensitive reference curve. After offset compensation, the target junction temperature is obtained. Then, the thermal resistance deviation is calculated with the target junction temperature as a reference. This allows the calculation of the thermal resistance increment to correspond only to the change in heat transfer characteristics caused by the thermal aging of the solder layer. This decouples the electrical aging of the bonding wire and the thermal aging of the solder layer, avoiding the compensation deviation caused by the superposition of the two types of aging.

[0063] Meanwhile, the layered thermal network model divides the heat transfer structure into a substrate layer and two types of solder layers. With the pre-calibrated thermal resistance increment allocation coefficient, the total thermal resistance increment can be split into chip solder layers and substrate solder layers according to the aging contribution ratio. That is, layered thermal resistance adaptive update is adopted to specifically correct the thermal aging deviation of the solder layers, avoid the accumulation of errors in the long-term operation of the fixed thermal model, and improve the accuracy of online monitoring of junction temperature of power devices.

[0064] Please see Figure 4 , Figure 4 This embodiment illustrates a junction temperature correction monitoring system for dual aging decoupling of power devices. In this embodiment, the junction temperature correction monitoring system for dual aging decoupling of power devices is used to perform the above-described... Figure 1 The steps in the corresponding embodiments. Please refer to the details. Figure 1 as well as Figure 1 The relevant descriptions in the corresponding embodiments are shown below. For ease of explanation, only the parts relevant to this embodiment are shown. See also... Figure 4 The junction temperature correction monitoring system 200 for dual aging decoupling of power devices includes: The parameter calibration module 210 is used to calibrate the temperature-sensitive reference curve of the power device, the initial thermal resistance parameters of the layered thermal network model, and the thermal resistance increment distribution coefficient between the chip solder layer and the substrate solder layer. The model prediction module 220 is used to obtain the power loss and case temperature of the power device, input the calibrated layered thermal network model, and output the predicted junction temperature value. The steady-state judgment module 230 is used to monitor the operating status of the inverter and determine whether the preset steady-state constraint conditions are met. If so, it collects the steady-state conduction parameters of the power devices and obtains the standard conduction parameters under the corresponding operating conditions based on the temperature-sensitive reference curve. The electrical compensation module 240 is used to determine the electrical aging drift amount based on the standard conduction parameters and the steady-state conduction parameters, update the electrical aging coefficient according to the electrical aging drift amount, and perform offset compensation on the steady-state conduction parameters to obtain the target junction temperature value. The thermal resistance correction module 250 is used to compare the predicted junction temperature value with the target junction temperature value. When there is a steady-state temperature difference, it determines the total thermal resistance increment of the power device and allocates and updates the thermal resistance parameters of the two solder layers in the layered thermal network model according to the thermal resistance increment allocation coefficient. The junction temperature estimation module 260 is used to freeze the updated thermal resistance parameters and electrical aging coefficients of the two solder layers after the correction is completed, and to estimate the junction temperature under load conditions based on the updated layered thermal network model.

[0065] The junction temperature correction and monitoring system provided in this embodiment uses power loss and case temperature as inputs to call the output of a calibrated layered thermal network model to predict the junction temperature. Simultaneously, it continuously monitors the operating status to determine steady-state conditions. Multi-level correction is performed only when all constraints of the no-load steady-state self-test are met. During the correction process, the electrical aging drift of the conduction parameters is first calculated based on the calibrated temperature-sensitive reference curve. After offset compensation, the target junction temperature is obtained. Then, the thermal resistance deviation is calculated using this target junction temperature as a reference. This ensures that the calculation of the thermal resistance increment corresponds only to the change in heat transfer characteristics caused by solder layer thermal aging, achieving decoupling between bond wire electrical aging and solder layer thermal aging, and avoiding the compensation deviation caused by the superposition of the two types of aging. The layered thermal network model distinguishes the heat transfer structure into a substrate layer and two types of solder layers. Combined with a pre-calibrated thermal resistance increment allocation coefficient, the total thermal resistance increment can be divided into the chip solder layer and the substrate solder layer according to the aging contribution ratio. This employs layered thermal resistance adaptive updating to specifically correct solder layer thermal aging deviations, avoiding the accumulation of errors from long-term operation of a fixed thermal model and improving the accuracy of online junction temperature monitoring for power devices.

[0066] It should be understood that the modules in the system provided in this embodiment are used to execute... Figure 1 The steps in the corresponding embodiments, and for Figure 1 The steps in the corresponding embodiments have been explained in detail in the above embodiments. Please refer to them for details. Figure 1 as well as Figure 1 The relevant descriptions in the corresponding embodiments will not be repeated here.

[0067] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 5 As shown, the electronic device provided in this embodiment includes at least one processor 901 and a memory 902. Optionally, the electronic device further includes a communication component 903. The processor 901, memory 902, and communication component 903 are connected via a bus 904.

[0068] In the specific implementation process, at least one processor 901 executes computer execution instructions stored in memory 902, causing at least one processor 901 to execute the above-mentioned junction temperature correction and monitoring method for dual aging decoupling of power devices.

[0069] The specific implementation process of processor 901 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0070] In the above embodiments, it should be understood that the processor 901 may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0071] The memory 902 can be an internal storage unit of an electronic device, such as a hard drive or memory in a server. The memory 902 can also be an external storage terminal device of an electronic device, such as a plug-in hard drive, smart media card (SMC), secure digital (SD) card, flash card, etc.

[0072] Furthermore, the memory 902 may include both internal storage units of the electronic device and external storage terminal devices. The memory 902 is used to store computer programs and other programs and data required by the turntable terminal device. The memory 902 can also be used to temporarily store data that has been output or will be output.

[0073] Bus 904 can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0074] Those skilled in the art will understand that Figure 5This is merely an example of an electronic device and does not constitute a limitation on the electronic device. It may include more or fewer components than shown, or combine certain components, or different components. For example, a turntable terminal device may also include input / output terminal devices, network access terminal devices, etc.

[0075] In one embodiment, a computer-readable storage medium is also provided, the computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the junction temperature correction monitoring method for dual aging decoupling of power devices as described in the above embodiments.

[0076] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0077] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in application-specific integrated circuits (ASICs). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0078] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0079] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0080] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. The computer-readable storage medium can be non-volatile or volatile. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable storage medium can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc.

[0081] The terms "first," "second," "third," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects and not to describe a particular order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, it may include a series of steps or units, or optionally, steps or units not listed, or other steps or units inherent to these processes, methods, products, or devices.

[0082] The accompanying drawings show only the portions relevant to this application, not all of them. Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe operations (or steps) as sequential processes, many of these operations may be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the operations may be rearranged. The process may be terminated when its operation is completed, but may also have additional steps not included in the drawings. The process may correspond to a method, function, procedure, subroutine, subprogram, etc.

[0083] The terms “component,” “module,” “system,” “unit,” etc., used in this specification are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a unit can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a thread of execution, a program, and / or distributed between two or more computers. Furthermore, these units can be executed from various computer-readable media on which various data structures are stored. Units can communicate, for example, via signals having one or more data packets (e.g., data from a second unit interacting with another unit between a local system, a distributed system, and / or a network; for example, the Internet interacting with other systems via signals).

[0084] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0085] Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The reference to "embodiment" herein means that a specific feature, structure, or characteristic described in connection with an embodiment can be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily indicate the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

Claims

1. A method for monitoring junction temperature correction in power devices with dual aging decoupling, characterized in that, include: The temperature-sensitive reference curve of the calibrated power device, the initial thermal resistance parameters of the layered thermal network model, and the thermal resistance increment distribution coefficient between the chip solder layer and the substrate solder layer. Obtain the power loss and case temperature of the power device, input them into the calibrated layered thermal network model, and output the predicted junction temperature value; Monitor the operating status of the inverter to determine whether the preset steady-state constraint conditions are met. If so, collect the steady-state conduction parameters of the power devices and obtain the standard conduction parameters under the corresponding operating conditions based on the temperature-sensitive reference curve. The electrical aging drift is determined based on the standard conduction parameters and the steady-state conduction parameters. The electrical aging coefficient is updated according to the electrical aging drift, and the steady-state conduction parameters are offset compensated to obtain the target junction temperature value. By comparing the predicted junction temperature with the target junction temperature, when there is a steady-state temperature difference, the total thermal resistance increment of the power device is determined. Based on the thermal resistance increment allocation coefficient, the total thermal resistance increment is allocated and the thermal resistance parameters of the two solder layers in the layered thermal network model are updated. After the correction was completed, the updated thermal resistance parameters and electrical aging coefficients of the two solder layers were frozen, and the junction temperature under load was estimated based on the updated layered thermal network model.

2. The junction temperature correction and monitoring method according to claim 1, characterized in that, The steps of calibrating the temperature-sensitive reference curve of the power device, the initial thermal resistance parameters of the layered thermal network model, and the thermal resistance increment distribution coefficients between the chip solder layer and the substrate solder layer include: The thermal impedance cooling curve of the power device is collected, and the structure function is obtained by performing differential and integral transformation on the thermal impedance cooling curve. Determine the step inflection point in the structure function, divide the heat transfer segments corresponding to the chip active layer, chip bonding layer, DBC ceramic layer, substrate bonding layer and copper substrate based on the step inflection point, and extract the initial thermal resistance value corresponding to each segment. The initial thermal resistance of the chip active layer, DBC ceramic layer, and copper substrate is set to the thermal resistance of the cured substrate. The initial thermal resistance of the chip solder layer and substrate solder layer is set to the solder layer thermal resistance that can be iteratively updated, thus completing the initial thermal resistance parameter configuration of the layered thermal network model.

3. The junction temperature correction and monitoring method according to claim 2, characterized in that, The steps of calibrating the temperature-sensitive reference curve of the power device, the initial thermal resistance parameters of the layered thermal network model, and the thermal resistance increment distribution coefficient between the chip solder layer and the substrate solder layer also include: Power cycling accelerated aging test was conducted on power devices. Steady-state junction-shell temperature difference was collected at multiple preset aging nodes, and the total thermal resistance increment corresponding to each node was calculated. Based on the structure function, the independent thermal resistance changes of the chip solder layer and the substrate solder layer at each aging node are determined. The thermal resistance increment allocation coefficient is obtained according to the proportion of the thermal resistance increment of the two types of solder layers to the total thermal resistance increment.

4. The junction temperature correction and monitoring method according to claim 2, characterized in that, The step of obtaining the power loss and case temperature of the power device, inputting them into the calibrated layered thermal network model, and outputting the predicted junction temperature value includes: Based on the thermal resistance parameters of the solidified substrate in the hierarchical thermal network model, and the thermal resistance parameters of the chip solder layer and the substrate solder layer, the cascade heat transfer topology from the chip junction to the shell is determined. The power loss is used as the heat source excitation input to the chip junction of the cascaded heat transfer topology, and the case temperature is used as the heat dissipation boundary condition of the cascaded heat transfer topology. The real-time temperature of each interface is calculated iteratively according to the heat transfer level. The real-time temperature of the chip junction at the top layer of the cascaded heat transfer topology is used as the predicted junction temperature value output by the hierarchical thermal network model.

5. The junction temperature correction and monitoring method according to claim 1, characterized in that, The steps of determining the electrical aging drift based on the standard conduction parameters and the steady-state conduction parameters, updating the electrical aging coefficient according to the electrical aging drift, and performing offset compensation on the steady-state conduction parameters to obtain the target junction temperature value include: The difference between the steady-state conduction parameter and the standard conduction parameter is used as the electrical aging drift amount; The conduction parameter drift is substituted into a preset first-order low-pass recursive formula to iteratively update the electrical aging coefficient. The iterative process does not modify the inherent slope and curvature of the temperature-sensitive reference curve. Based on the electrical aging coefficient, the steady-state conduction parameters are offset in reverse to obtain the target temperature-sensitive parameters. The target temperature-sensitive parameters are then substituted into the temperature-sensitive reference curve to obtain the target junction temperature value.

6. The junction temperature correction and monitoring method according to claim 5, characterized in that, In the step of substituting the conduction parameter drift into a preset first-order low-pass recursive formula to iteratively update the electrical aging coefficient, the expression of the first-order low-pass recursive formula is: In the formula, The updated electrical aging factor. This represents the electrical aging factor stored in the previous cycle. The convergence coefficient is . This represents the drift of the conduction parameters.

7. The junction temperature correction and monitoring method according to claim 1, characterized in that, The step of comparing the predicted junction temperature value with the target junction temperature value, determining the total thermal resistance increment of the power device when a steady-state temperature difference exists, and allocating and updating the thermal resistance parameters of the two solder layers in the layered thermal network model according to the thermal resistance increment allocation coefficient includes: Based on the predicted junction temperature value and the target junction temperature value at multiple sampling times, the junction temperature deviation value is calculated one by one. When all junction temperature deviation values ​​in the corresponding sampling interval tend to the same temperature difference value, the average value of all junction temperature deviation values ​​is used as the steady-state temperature difference value. Based on the power loss value under the current steady-state operating conditions and the steady-state temperature difference value, determine the total thermal resistance increment of the power device; According to the thermal resistance increment allocation coefficient, the total thermal resistance increment is divided into the chip solder layer thermal resistance increment and the substrate solder layer thermal resistance increment according to the calibrated allocation ratio. The thermal resistance increments of the two types of weld layers are respectively superimposed on the current weld layer thermal resistance parameters corresponding to the layered thermal network model, while keeping the substrate thermal resistance in the layered thermal network model unchanged, thus completing the layered adaptive update of the thermal resistance parameters.

8. A junction temperature correction and monitoring system for dual aging decoupling of power devices, characterized in that, include: The parameter calibration module is used to calibrate the temperature-sensitive reference curve of the power device, the initial thermal resistance parameters of the layered thermal network model, and the thermal resistance increment distribution coefficient between the chip solder layer and the substrate solder layer. The model prediction module is used to obtain the power loss and case temperature of the power devices, input the calibrated layered thermal network model, and output the predicted junction temperature value. The steady-state judgment module is used to monitor the operating status of the inverter and determine whether the preset steady-state constraint conditions are met. If so, it collects the steady-state conduction parameters of the power devices and obtains the standard conduction parameters under the corresponding operating conditions based on the temperature-sensitive reference curve. An electrical compensation module is used to determine the electrical aging drift based on the standard conduction parameters and the steady-state conduction parameters, update the electrical aging coefficient according to the electrical aging drift, and perform offset compensation on the steady-state conduction parameters to obtain the target junction temperature value. The thermal resistance correction module is used to compare the predicted junction temperature value with the target junction temperature value. When there is a steady-state temperature difference, it determines the total thermal resistance increment of the power device and allocates and updates the thermal resistance parameters of the two solder layers in the layered thermal network model according to the thermal resistance increment allocation coefficient. The junction temperature estimation module is used to freeze the updated thermal resistance parameters and electrical aging coefficients of the two solder layers after calibration, and to estimate the junction temperature under load based on the updated layered thermal network model.

9. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the steps of the junction temperature correction monitoring method for dual aging decoupling of power devices according to any one of claims 1-7.

10. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the steps of the junction temperature correction and monitoring method for dual aging decoupling of power devices according to any one of claims 1-7.

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