An authentication module, and an integrated circuit testing device and method applying the same

Abstract

The application discloses an authentication module, and an integrated circuit testing device and method applying the same. The authentication module comprises an authentication execution unit and an output logic unit. The authentication execution unit is used for receiving authentication parameters, performing authentication operations according to the authentication parameters, and generating test control information. The output logic unit is used for generating and outputting test control signals according to the test control information, so that the integrated circuit testing device determines whether to start integrated circuit testing operations according to the test control signals. Part or all of the logic subunits in the authentication execution unit are connected to a scan chain, and the output logic unit is not connected to the scan chain. Thus, the application divides the logic in the authentication module into on-chain logic and off-chain logic, so that part of the registers in the authentication module can participate in the test, and the test coverage of the chip is improved while effectively isolating the interference of the test chain on the test control signals and ensuring the stability of the test.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to an authentication module and an integrated circuit testing apparatus and method using the same. Background Technology

[0002] In the integrated circuit testing process, the system dynamically manages debugging functions through test control signals (such as the dft_enable signal for DFT testing): when the test control signal is 1, integrated circuit test operations are allowed; when the test control signal is 0, test access is strictly prohibited. However, in actual testing, some uplink registers may unexpectedly flip, affecting the reliability of the test control signal and thus impacting test stability. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide an authentication module and an integrated circuit testing apparatus and method using the same, so as to improve the chip's test coverage by precisely dividing the logic in the authentication module into on-chain logic and off-chain logic, effectively isolating the interference of the test link on the test control signal to ensure test stability, while enabling some registers in the authentication module to participate in the test.

[0004] In a first aspect, embodiments of the present invention provide an authentication module applied to an integrated circuit testing apparatus, the authentication module comprising: The authentication execution unit is used to receive authentication parameters and perform authentication operations according to the authentication parameters, and generate test control information. An output logic unit is used to generate and output a test control signal based on the test control information, so that the integrated circuit test device can determine whether to start the integrated circuit test operation based on the test control signal. In this configuration, some or all of the logic subunits in the authentication execution unit are connected to the scan chain, while the output logic unit is not connected to the scan chain.

[0005] Furthermore, the authentication module also includes: At least one latch unit is connected to the input terminal of the output logic unit for latching a received quasi-static signal, wherein the quasi-static signal is used to characterize a signal that remains unchanged after power-on reset; Each of the latching units is not connected to the scan chain.

[0006] Furthermore, the input terminal of the latch unit is connected to the corresponding external logic unit to receive the quasi-static signal output by the corresponding external logic unit.

[0007] Furthermore, the authentication module also includes: At least one clamping unit is connected to the input terminal of the output logic unit and is used to clamp the received dynamic signal according to the clamping control signal.

[0008] Furthermore, the authentication module also includes: A clamping control unit is used to generate the clamping control signal.

[0009] Furthermore, the clamp control unit is used to output a low-level clamp control signal during the authentication operation, and to output a high-level clamp control signal after the authentication operation is completed and before the scan chain test begins.

[0010] Furthermore, the input terminal of the clamping unit is connected to the output terminal of the authentication execution unit, and is used to receive the dynamic signal output by the authentication execution unit.

[0011] Furthermore, the authentication execution unit includes: The interface logic subunit is used to receive authentication parameters; The arithmetic logic subunit is used to perform authentication operations according to a predetermined authentication algorithm and the authentication parameters, and obtain authentication results; A control logic subunit is used to generate the test control information based on the authentication result.

[0012] In a second aspect, embodiments of the present invention provide an integrated circuit testing apparatus, the integrated circuit testing apparatus comprising: The authentication module as described above; The test signal generation module is used to generate test signals based on the test control signals and test instructions output by the authentication module; The test module is used to perform corresponding integrated circuit test operations in response to the validity of the test signal.

[0013] Thirdly, embodiments of the present invention provide an integrated circuit testing method applied to an integrated circuit testing apparatus, the integrated circuit testing apparatus including an authentication module, the authentication module including an authentication execution unit and an output logic unit, the method including: In response to a test command, a scan chain is constructed, which includes some or all of the logical sub-units in the authentication execution unit, but does not include the output logical unit. The test control signal is obtained through the authentication module; A test signal is generated based on the test control signal and the test command; In response to the test signal being valid, the integrated circuit test operation corresponding to the scan chain is executed.

[0014] The authentication module of this invention includes an authentication execution unit and an output logic unit. The authentication execution unit receives authentication parameters and performs authentication operations according to the parameters, generating test control information. The output logic unit generates and outputs test control signals according to the test control information, enabling the integrated circuit testing device to determine whether to initiate integrated circuit testing based on the test control signals. Some or all of the logic subunits in the authentication execution unit are connected to the scan chain, while the output logic unit is not connected to the scan chain. Therefore, by precisely dividing the logic in the authentication module into on-chain logic and off-chain logic, this application effectively isolates the interference of the test link on the test control signal, ensuring test stability, while also allowing some registers in the authentication module to participate in the test, thus improving the chip's test coverage. Attached Figure Description

[0015] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 This is a schematic diagram of the integrated circuit testing process in related technologies; Figure 2 This is a schematic diagram of an authentication module according to an embodiment of the present invention; Figure 3 This is a schematic diagram of another authentication module according to an embodiment of the present invention; Figure 4 This is a schematic diagram of another authentication module according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the latch unit according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the clamping unit according to an embodiment of the present invention; Figure 7 This is a schematic diagram of an integrated circuit testing apparatus according to an embodiment of the present invention; Figure 8 This is a flowchart of an integrated circuit testing method according to an embodiment of the present invention. Detailed Implementation

[0016] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0017] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0018] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0019] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0021] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0022] DFT (Design for Testability): Used to effectively detect physical defects introduced during the manufacturing process after integrated circuit manufacturing is completed.

[0023] Authentication refers to the process of verifying the authenticity and legitimacy of a chip through a specific mechanism in a communication or security system. The purpose is to prevent malicious personnel from accessing the system and stealing sensitive chip information.

[0024] JTAG: The test access mechanism and boundary scan structure specified in the IEEE 149.1 standard is the technical foundation for achieving board-level and chip-level testability.

[0025] APB: Advanced Peripheral Bus.

[0026] Scan test: A structure testing method based on scan chain, which connects internal state elements (such as flip-flops) into a serially accessible shift register, and achieves complete control and observation of combinational logic paths in test mode, thereby efficiently detecting physical defects introduced during the manufacturing process.

[0027] scan-logic: A serially connected scan chain used to replace conventional timing components in a design in test mode to achieve controllability and observability of internal nodes.

[0028] no-scan-logic: Logical units that are not connected to the scan chain during testing will reduce test coverage.

[0029] eFuse: Electronic fuse, which is programmed once to control the testing process.

[0030] Based on the above explanation of the nouns and terms involved in the embodiments of this application, the authentication module provided in the embodiments of this application and the integrated circuit testing device and method using it are described.

[0031] Figure 1 This is a schematic diagram of the integrated circuit testing process in related technologies. For example... Figure 1 As shown, integrated circuits are tested and verified by issuing test commands through the external hardware debugging interface JTAG. It should be understood that other types of test interfaces can also be used, and there are no restrictions on them here.

[0032] Before testing and verifying integrated circuits through the external hardware debugging interface JTAG, for security reasons, the authentication process must first be completed through the authentication module 11 based on the authentication parameters to avoid malicious intrusion, theft of sensitive chip information, and chip cracking.

[0033] Furthermore, after successful authentication, the corresponding access control signal is activated, allowing the execution of integrated circuit testing operations. Specifically, such as... Figure 1 As shown, after the authentication module 11 confirms successful authentication, it outputs a valid test control signal enable1, indicating that the hardware debugging interface JTAG has been authorized for access. JTAG can then perform corresponding test operations, such as scan test, scan dump, and mbist test. When dft_enable is low, it indicates that the external debugging interface access permission is closed, JTAG-related test capabilities are prohibited, and the above test operations cannot be performed. Specifically, as shown... Figure 1 As shown, the test control signal enable1 and the test instruction t1 from the external debugging interface JTAG can be logically ANDed by the logic unit to ensure that when the test control signal enable1 is valid, a valid test signal s1 is output to execute the corresponding test operation, and when the test control signal enable1 is invalid, an invalid test signal s1 is output to disable the corresponding test operation.

[0034] During testing, the authentication module 11 may cause the test control signal enable1 to change due to unexpected flipping of some on-chain registers. This makes the test control signal enable1 unreliable during testing, potentially leading to test interruption and instability. Related technologies address this by ensuring that none of the logic units in the authentication module 11 are connected to the scan chain, thus guaranteeing the stability of the test process. However, this approach obviously significantly reduces the overall test coverage.

[0035] Based on this, embodiments of the present invention provide an authentication module and an integrated circuit testing apparatus and method using it, so as to improve the chip's test coverage by accurately dividing the logic in the authentication module into on-chain logic and off-chain logic, effectively isolating the interference of the test link on the test control signal to ensure test stability, while enabling some registers in the authentication module to participate in the test.

[0036] Figure 2 This is a schematic diagram of an authentication module according to an embodiment of the present invention. Figure 3 This is a schematic diagram of another authentication module according to an embodiment of the present invention. Figure 2 As shown, the authentication module 2 of this embodiment includes an authentication execution unit 21 and an output logic unit 22. The authentication execution unit 21 receives authentication parameters and performs authentication operations based on these parameters, generating test control information. The output logic unit 22 generates and outputs a test control signal enable2 based on the test control information, enabling the integrated circuit testing device to determine whether to initiate integrated circuit testing based on the test control signal enable2. Some or all of the logic subunits in the authentication execution unit 21 are connected to the scan-logic, while the output logic unit 22 is not connected to the scan-logic. Therefore, this embodiment allows the authentication processing portion of the authentication module 2 to be connected to the scan-logic, ensuring it can be included in the test and guaranteeing chip test coverage. Furthermore, the output logic unit 22, which controls changes in the test control signal enable2 directly within the authentication module 2, is not connected to the scan-logic, effectively isolating the test link from interference with the test control signal enable2 during testing, ensuring the reliability of the test control signal enable2, and thus guaranteeing test stability. Meanwhile, since this embodiment of the invention only excludes logic units directly related to the output test control signal enable2 from the scan chain, it ensures high overall chip test coverage while maintaining test stability.

[0037] Furthermore, the authentication execution unit 21 sends the generated test control information to the corresponding control register, and the output logic unit 22 generates and outputs the test control signal enable2 based on the signal sequence in the control register. Optionally, the generation of the test control signal enable2 may also be related to an external logic unit (such as eFuse), and the control register may also store the signal values ​​output by the external logic unit.

[0038] In one optional implementation, when the signal sequence in the control register matches the first predetermined sequence, the output logic unit 22 controls the generation of a valid test control signal enable2. When the signal sequence in the control register matches the second predetermined sequence, the output logic unit 22 controls the generation of an invalid test control signal enable2. Further, when the signal sequence in the control register does not match either the first or second predetermined sequence, the output logic unit 22 controls the maintenance of the test control signal enable2 without change. In other optional implementations, when the value of at least one predetermined bit in the signal sequence in the control register changes to a preset value, the output logic unit 22 ignores the change, i.e., controls the test control signal enable2 to remain unchanged. Further optionally, one or more of the first and second predetermined sequences may exist; this embodiment does not limit this and can configure them based on actual circumstances.

[0039] In one alternative implementation, such as Figure 3 As shown, the authentication execution unit 21 includes an interface logic subunit 211, an arithmetic logic subunit 212, and a control logic subunit 213. The interface logic subunit 211 is used to receive authentication parameters. Optionally, the interface logic subunit 211 can receive authentication parameters via the APB bus or other communication interfaces. In this embodiment, after the integrated circuit testing device receives a test command, the interface logic subunit 211 captures and temporarily stores the authentication parameters from the APB bus or other communication interfaces, and routes them to the corresponding authentication register or arithmetic logic subunit 212.

[0040] The arithmetic logic subunit 212 is used to perform authentication operations according to a predetermined authentication algorithm and the authentication parameters, and obtain authentication results.

[0041] The following example illustrates authentication using ECDSA-521 (a 521-bit elliptic curve digital signature algorithm). The arithmetic logic subunit 212 receives authentication parameters from the interface logic subunit 211 (or retrieves authentication parameters from the authentication register). These authentication parameters include the original message, the public key required for the signature verification protocol, and the signature value to be verified. Further, the arithmetic logic subunit 212 performs an elliptic curve signature verification operation based on the authentication parameters, obtaining an output value. If the output value matches the signature value in the authentication parameters, authentication is successful; if the output value does not match the digital signature value in the authentication parameters, authentication fails.

[0042] It should be understood that the above-described ECDSA-521 is merely exemplary, and this embodiment does not limit the specific authentication algorithm. Other cryptographic verification algorithms (such as SM3 or other hash algorithms, encryption algorithms), multiple timing and signal verification algorithms, or fixed key value comparison algorithms can all be applied to this embodiment. Examples will not be provided here.

[0043] Furthermore, the control logic subunit 213 is used to generate the test control information based on the authentication result. Specifically, in response to an authentication result indicating successful authentication, the control logic subunit 213 generates a signal sequence indicating successful authentication, so that the output logic unit 22 generates a valid test control signal based on the signal sequence, that is, enabling access control and executing the corresponding test operation. In response to an authentication result indicating unsuccessful authentication, the control logic subunit 213 generates a signal sequence indicating unsuccessful authentication, so that the output logic unit 22 generates an invalid test control signal based on the signal sequence, that is, prohibiting access control and thus prohibiting the execution of the corresponding test operation, thereby ensuring chip security.

[0044] Figure 3 The structure of the authentication execution unit 21 and the specific authentication process are merely exemplary. In practical applications, different authentication algorithms may be configured with different logical units. This embodiment will not provide examples of each one. However, it should be understood that regardless of the internal structure of the authentication execution unit 21, if it controls at least some of the logical subunits in the authentication execution unit 21 to access the scan chain when constructing the scan chain, and controls the logical units that directly affect the test control signal not to access the scan chain, then it is within the protection scope of this embodiment.

[0045] Furthermore, after authentication by authentication module 2 is successful, a valid test control signal enable2 is output to initiate the execution of the corresponding test operation.

[0046] Since the authentication execution unit 21 is connected to the scan chain, after the test operation is started, the output logic unit 22 will receive the output signal of the external logic unit (such as eFuse) and the output signal of the authentication execution unit 21. In order to avoid the interference of these received signals to the test control signal enable2, this embodiment isolates the output signal of the external logic unit and the output signal of the authentication execution unit 21 in a predetermined manner to ensure the reliability of the test control signal enable2 and thus maintain the stability of the test process.

[0047] Furthermore, in this embodiment, the output signals of the external logic unit and the output signals of the authentication execution unit 21 are latched or clamped so that their input to the output logic unit 22 will not affect the test control signal enable2.

[0048] Furthermore, in this embodiment, quasi-static signals input to the output logic unit 22 are isolated using a latching method, while dynamic signals input to the output logic unit 22 are isolated using a clamping method. Quasi-static signals are used to characterize signals that remain unchanged after power-on reset, such as eFuse. Dynamic signals are used to characterize signals that change during testing.

[0049] Figure 4 This is a schematic diagram of another authentication module according to an embodiment of the present invention. Figure 4 As shown, the authentication module 2 in this embodiment also includes at least one latch unit 23 (only one is shown in the figure; it should be understood that its quantity is determined based on the number of quasi-static signals in the input-to-output logic unit 22). The latch unit 23 is connected to the input terminal of the output logic unit 22 and is used to latch the received quasi-static signals, thereby maintaining the signals in the input-to-output logic unit 22 unchanged, and thus avoiding affecting the test control signal enable2. In this embodiment, taking the signal output by the external logic unit 40 as a quasi-static signal as an example, the input terminal of the latch unit 23 is connected to the output terminal of the external logic unit 40 and is used to receive the corresponding quasi-static signal output by the external logic unit 40.

[0050] Furthermore, the authentication module 2 in this embodiment also includes at least one clamping unit 24 (only one is shown in the figure; it should be understood that its quantity is determined based on the number of dynamic signals in the input-to-output logic unit 22), connected to the input terminal of the output logic unit 22, for clamping the received dynamic signals according to the clamping control signal clamp, so that the signals input to the output logic unit 22 are clamped by a predetermined value, thereby avoiding affecting the test control signal enable2. In this embodiment, taking the signal output by the authentication execution unit 21 as a dynamic signal as an example, the input terminal of the clamping unit 24 is connected to the output terminal of the authentication execution unit 21, for receiving the dynamic signal output by the authentication execution unit 21.

[0051] Furthermore, the authentication module 2 also includes a clamp control unit 25, connected to the corresponding clamp unit 24, for generating a clamp control signal. Optionally, the clamp control unit 25 outputs a low-level clamp control signal during the authentication operation to avoid clamping the signal output by the authentication execution unit 21, ensuring the accuracy of the authentication result. After the authentication operation is completed and before the scan chain test begins, it outputs a high-level clamp control signal to isolate the signal generated by the authentication execution unit 21 during the test, avoiding affecting the test control signal enable2, ensuring the reliability of avoiding affecting the test control signal enable2, and thus maintaining the stability of the test process.

[0052] In an optional implementation, the latch unit 23 in this embodiment is implemented using a latch register. When creating a scan chain, this embodiment controls the latch unit 23 not to connect to the scan chain to avoid affecting the output value of the latch unit 23 during the test, thereby preventing interference from the test chain to the test control signal enable2.

[0053] Figure 5 This is a schematic diagram of the latch unit according to an embodiment of the present invention. Figure 5 As shown, in this embodiment, latch register FF0 is used as the latching unit. The quasi-static signal Qa is pulled high during power-on reset, outputting the corresponding signal Qa'. Afterward, the quasi-static signal Qa is pulled low, and latch register FF0 locks the output signal, thus keeping the data state of signal Qa' unchanged. Therefore, in this embodiment, the latch register latches the quasi-static signal, ensuring that the corresponding signal (e.g., signal Qa') received by the output logic unit 22 remains unchanged.

[0054] Figure 6 This is a schematic diagram of the clamping unit according to an embodiment of the present invention. Figure 6 As shown, for the dynamic signal Qb, when the clamp control signal clamp is low (i.e., 0), it is inverted and input to the AND logic unit. At this time, the output signal Qb' of the clamp unit is the same as the input dynamic signal Qb. After the clamp control signal clamp is pulled high (i.e., 1), it is inverted and input to the AND logic unit. At this time, the output signal Qb' of the clamp unit is always 0. Therefore, in this embodiment, the clamp control signal clamp can be pulled high before the test operation starts, so that the clamp unit clamps the received dynamic signal to 0. This ensures that the value of the dynamic signal received by the output logic unit 22 during the test is clamped to 0, avoiding the interference of the dynamic signal changes on the test control signal enable2 during the test, ensuring the reliability of the test control signal enable2, and thus maintaining the test stability.

[0055] It should be understood that this embodiment describes the clamping unit clamping the value of the dynamic signal to 0 as an example, but it should be understood that this embodiment does not limit this, and it may achieve the corresponding function.

[0056] Furthermore, the latch unit shown in Figure 5 and Figure 6 The specific structure of the clamping unit shown is merely exemplary. Other structures capable of implementing latching and clamping functions can also be applied to this embodiment, and will not be described in detail here.

[0057] Furthermore, in this embodiment, all signals received by the output logic unit 22 are stored in the corresponding control register. The output logic unit 22 generates the test control signal enable2 by scanning the signal sequence in the control register. Optionally, when the signal sequence in the control register matches the first predetermined sequence, the output logic unit 22 controls the generation of a valid test control signal enable2. One or more first predetermined sequences may exist; this embodiment does not limit this and it can be configured based on actual conditions. Furthermore, since the quasi-static signal is latched and the dynamic signal is clamped during the test, the signal sequence in the control register remains unchanged during the test, and its value can be set to one of the first predetermined sequences. This ensures the reliability of the test control signal enable2 during the test.

[0058] In this embodiment, when the signal sequence in the control register matches the second predetermined sequence, the output logic unit 22 controls the generation of an invalid test control signal enable2. In another optional implementation, when the signal sequence in the control register does not match either the first or second predetermined sequence, the output logic unit 22 controls the maintenance of the test control signal enable2 without change. Based on this, if a dynamic signal has a value of 1 during the authentication process, it is clamped to 0 during the test process by the clamping unit. Since the signal sequence in the pre-configured control register does not match either the first or second predetermined sequence, the test control signal enable2 remains valid. Thus, this embodiment can maintain the reliability of the test control signal enable2.

[0059] In other alternative implementations, when the value of at least one pre-defined bit in the signal sequence in the control register changes to a preset value, the output logic unit 22 ignores the change, that is, the control test signal enable2 remains unchanged. For example, if a dynamic signal has a value of 1 during the authentication process, it may be clamped to 0 during the test by a clamping unit. In this embodiment, the output logic unit 22 ignores the change to maintain the reliability of the test control signal enable2.

[0060] The authentication module of this invention includes an authentication execution unit and an output logic unit. The authentication execution unit receives authentication parameters and performs authentication operations according to the parameters, generating test control information. The output logic unit generates and outputs test control signals according to the test control information, enabling the integrated circuit testing device to determine whether to initiate integrated circuit testing based on the test control signals. Some or all of the logic subunits in the authentication execution unit are connected to the scan chain, while the output logic unit is not connected to the scan chain. Therefore, by precisely dividing the logic in the authentication module into on-chain logic and off-chain logic, this application effectively isolates the interference of the test link on the test control signal, ensuring test stability, while also allowing some registers in the authentication module to participate in the test, thus improving the chip's test coverage.

[0061] Figure 7 This is a schematic diagram of an integrated circuit testing apparatus according to an embodiment of the present invention. Figure 7 As shown, the integrated circuit testing apparatus 7 of this embodiment includes an authentication module 71, a test signal generation module 72, and a testing module 73. The authentication module 71 is used to authenticate the corresponding test interface, and generates a valid test control signal after successful authentication to ensure chip security. It should be understood that the structure and operation of the authentication module 71 are similar to those in the above embodiments, and will not be described in detail here.

[0062] The test signal generation module 72 is used to generate test signals based on the test control signals and test instructions output by the authentication module 71. The test signal generation module 72 can be an AND logic unit to generate valid test signals based on valid test control signals and valid test instructions, and to control the execution of corresponding test operations based on valid test signals. The test module 73 is used to execute corresponding integrated circuit test operations in response to valid test signals. Optionally, the integrated circuit test operations can be scan test, scan dump, MIST test, etc. This embodiment does not limit the specific test operation type, and it can be configured based on actual application conditions.

[0063] The integrated circuit testing apparatus of this embodiment improves the authentication module. Specifically, the authentication module includes an authentication execution unit and an output logic unit. The authentication execution unit receives authentication parameters and performs authentication operations according to the parameters, generating test control information. The output logic unit generates and outputs test control signals according to the test control information, enabling the integrated circuit testing apparatus to determine whether to start the integrated circuit test operation based on the test control signals. Some or all of the logic subunits in the authentication execution unit are connected to the scan chain, while the output logic unit is not connected to the scan chain. Therefore, by precisely dividing the logic in the authentication module into on-chain logic and off-chain logic, this application effectively isolates the interference of the test link on the test control signal, ensuring test stability, while also allowing some registers in the authentication module to participate in the test, thus improving the chip's test coverage.

[0064] Figure 8 This is a flowchart of an integrated circuit testing method according to an embodiment of the present invention. The integrated circuit testing method of the present invention is applied to the aforementioned integrated circuit testing apparatus, such as... Figure 8 As shown, the integrated circuit testing method of this invention includes the following steps: Step S110: In response to the test command, a scan chain is constructed. The scan chain includes some or all of the logical sub-units in the authentication execution unit of the authentication module, but excludes the output logical units of the authentication module. That is, in this embodiment, when constructing the scan chain, at least some of the logical sub-units in the authentication execution unit of the authentication module are controlled to be connected to the scan chain, while the output logical units of the authentication module are controlled not to be connected to the scan chain.

[0065] Step S120: Obtain the test control signal through the authentication module. In this embodiment, a valid test control signal is generated when the authentication of the corresponding test interface passes, and an invalid test control signal is generated when the authentication of the corresponding test interface fails, so as to ensure chip security.

[0066] Step S130: Generate a test signal based on the test control signal and the test command. In this embodiment, a valid test signal is generated if both the test control signal and the test command are valid; an invalid test signal is generated if either the test control signal or the test command is invalid.

[0067] In step S140, in response to the test signal being valid, the integrated circuit test operation corresponding to the scan chain is executed.

[0068] This embodiment controls the connection of at least some logic subunits in the authentication execution unit of the authentication module to the scan chain during the scan chain construction, while controlling the output logic units in the authentication module to be excluded from the scan chain. This allows logic units in the authentication module that are not directly related to the test control signal to be connected to the scan chain, while logic units directly related to the test control signal are excluded. This effectively isolates interference from the test link to the test control signal during testing, ensuring the reliability of the test control signal and thus guaranteeing test stability. Simultaneously, this embodiment also ensures a high overall chip test coverage.

[0069] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An authentication module, applied in an integrated circuit testing device, characterized in that, The authentication module includes: The authentication execution unit is used to receive authentication parameters and perform authentication operations according to the authentication parameters, and generate test control information. An output logic unit is used to generate and output a test control signal based on the test control information, so that the integrated circuit test device can determine whether to start the integrated circuit test operation based on the test control signal. In this configuration, some or all of the logic subunits in the authentication execution unit are connected to the scan chain, while the output logic unit is not connected to the scan chain.

2. The authentication module according to claim 1, characterized in that, The authentication module also includes: At least one latch unit is connected to the input terminal of the output logic unit for latching a received quasi-static signal, wherein the quasi-static signal is used to characterize a signal that remains unchanged after power-on reset; Each of the latching units is not connected to the scan chain.

3. The authentication module according to claim 2, characterized in that, The input terminal of the latch unit is connected to the corresponding external logic unit and is used to receive the quasi-static signal output by the corresponding external logic unit.

4. The authentication module according to claim 1, characterized in that, The authentication module also includes: At least one clamping unit is connected to the input terminal of the output logic unit and is used to clamp the received dynamic signal according to the clamping control signal.

5. The authentication module according to claim 4, characterized in that, The authentication module also includes: A clamping control unit is used to generate the clamping control signal.

6. The authentication module according to claim 5, characterized in that, The clamp control unit is used to output a low-level clamp control signal during the authentication operation and a high-level clamp control signal after the authentication operation is completed and before the scan chain test begins.

7. The authentication module according to claim 4, characterized in that, The input terminal of the clamping unit is connected to the output terminal of the authentication execution unit, and is used to receive the dynamic signal output by the authentication execution unit.

8. The authentication module according to claim 5, characterized in that, The authentication execution unit includes: The interface logic subunit is used to receive authentication parameters; The arithmetic logic subunit is used to perform authentication operations according to a predetermined authentication algorithm and the authentication parameters, and obtain authentication results; A control logic subunit is used to generate the test control information based on the authentication result.

9. An integrated circuit testing device, characterized in that, The integrated circuit testing apparatus includes: The authentication module as described in any one of claims 1-8; The test signal generation module is used to generate test signals based on the test control signals and test instructions output by the authentication module; The test module is used to perform corresponding integrated circuit test operations in response to the validity of the test signal.

10. An integrated circuit testing method, applied to an integrated circuit testing apparatus, the integrated circuit testing apparatus comprising an authentication module, the authentication module comprising an authentication execution unit and an output logic unit, characterized in that, The method includes: In response to a test command, a scan chain is constructed, which includes some or all of the logical sub-units in the authentication execution unit, but does not include the output logical unit. The test control signal is obtained through the authentication module; A test signal is generated based on the test control signal and the test command; In response to the test signal being valid, the integrated circuit test operation corresponding to the scan chain is executed.

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