Chip failure analysis structure and method of forming the same

Abstract

A chip failure analysis structure and a forming method thereof, the forming method comprising: providing a substrate, a plurality of conductive layers on the substrate and a thin film layer on the conductive layers; forming a groove in the thin film layer, the groove bottom retaining a part of the thickness of the thin film layer, and the sidewall of the groove being stepped; determining the conductive layers in the groove bottom which need to be electrically connected, and marking the conductive layers as external conductive layers; removing the thin film layer on the external conductive layers; forming a metal connection layer; forming a test terminal on the thin film layer outside the groove; and connecting the metal connection layer to the test terminal from the external conductive layers. The embodiment of the present application is beneficial to improve the yield of the chip failure analysis structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a chip failure analysis structure and its formation method. Background Technology

[0002] In chip design, in order to find clues to failure, it is usually necessary to form a failure analysis structure and electrically connect it to the failed chip to determine the possible causes of chip failure.

[0003] However, the existing fabrication processes for chip failure analysis structures reduce their fabrication yield. Therefore, providing a technical solution to improve the fabrication yield of chip failure analysis structures has become a pressing technical problem for those skilled in the art. Summary of the Invention

[0004] The technical problem solved by the present invention is to improve the manufacturing yield of chip failure analysis structures by providing a chip failure analysis structure and a method for forming the same.

[0005] This invention provides a method for forming a chip failure analysis structure, comprising: providing a substrate, a plurality of conductive layers on the substrate, and a thin film layer on the conductive layers; forming a groove in the thin film layer, wherein a portion of the thickness of the thin film layer is retained at the bottom of the groove, and the sidewalls of the groove are stepped; identifying a conductive layer among the plurality of conductive layers at the bottom of the groove that requires electrical external connection, denoted as the external conductive layer; removing the thin film layer on the external conductive layer; forming a metal interconnect layer; and forming a test terminal on the thin film layer outside the groove; wherein the metal interconnect layer is connected from the external conductive layer to the test terminal.

[0006] Optionally, the step of forming a groove in the thin film layer, wherein a portion of the thickness of the thin film layer is retained at the bottom of the groove, and the sidewalls of the groove are stepped, includes: using a focused ion beam to define etching regions sequentially, and removing the thin film layer within the etching region by the focused ion beam, wherein the planar dimension of each defined etching region is smaller than the planar dimension of the previously defined etching region, so that the step sidewalls of each step are successively recessed downward toward the axis of the groove in a direction perpendicular to the surface of the thin film layer, and the depth of the bottom surface of the groove relative to the surface of the thin film layer after each etching is greater than the depth after the previous etching, and a portion of the thickness of the thin film layer is retained at the bottom of the groove.

[0007] Optionally, by focusing ion beam imaging, the conductive layer that needs to be electrically connected to the outside among the multiple conductive layers at the bottom of the groove can be determined and denoted as the external conductive layer.

[0008] Optionally, the metal interconnect layer can be formed by focused ion beam-induced deposition.

[0009] Optionally, before forming the test terminal and after forming the metal interconnect layer, the forming method further includes: forming a protective dielectric layer covering the metal interconnect layer, the protective dielectric layer extending to the groove. On the outer thin film layer.

[0010] Optionally, the process for forming a protective dielectric layer covering the metal interconnect layer includes atomic layer deposition or chemical vapor deposition.

[0011] Optionally, the material of the metal interconnect layer includes platinum or tungsten.

[0012] This invention provides a chip failure analysis structure, comprising: a substrate; a plurality of conductive layers on the substrate, the plurality of conductive layers including an external conductive layer; a thin film layer on the conductive layers; a groove located within the thin film layer, wherein the sidewalls of the groove are stepped; a metal interconnect layer; and test terminals located on the thin film layer outside the groove; wherein the metal interconnect layer is connected from the external conductive layer to the test terminals.

[0013] Optionally, the heights of the steps on the sidewalls of the groove decrease or remain equal as the direction perpendicular to the surface of the thin film layer is directed downwards.

[0014] Optionally, the step width of each step in the groove increases or remains equal along a direction perpendicular to the surface of the thin film layer downwards.

[0015] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages: The method for forming a chip failure analysis structure provided in this invention includes: providing a substrate, a plurality of conductive layers on the substrate, and a thin film layer on the conductive layers; forming a groove in the thin film layer, wherein the sidewalls of the groove are stepped; determining a conductive layer that needs to be electrically connected to the outside of the plurality of conductive layers at the bottom of the groove, denoted as the external conductive layer; forming a metal interconnect layer; forming a test terminal on the thin film layer outside the groove; and connecting the metal interconnect layer to the test terminal from the external conductive layer. By setting the sidewalls of the groove to be stepped, the adhesion and continuity of the metal interconnect layer at the stepped sidewall positions are improved, the risk of open circuit in the metal interconnect layer is reduced, thereby improving the fabrication yield of the chip failure analysis structure. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0017] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a chip failure analysis structure.

[0018] Figures 4 to 15 This is a schematic diagram of the structure corresponding to each step in the method for forming the chip failure analysis structure according to an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] As the background technology shows, existing technologies suffer from reduced yield in the fabrication of chip failure analysis structures. The following section will discuss this further. Figures 1 to 3 This study analyzes the reasons for the reduced yield in the fabrication of chip failure analysis structures. The method for forming this chip failure analysis structure mainly includes the following steps: refer to Figures 1 to 3 This is a schematic diagram of the structural steps corresponding to each step in a method for forming a chip failure analysis structure; among which... Figure 3 yes Figure 2 A top view structural diagram.

[0021] refer to Figure 1 A substrate 100 is provided, the substrate 100 having a metal conductive layer 102 and a dielectric layer 104 located on the metal conductive layer 102; the metal conductive layer 102 is electrically connected to the chip (not shown).

[0022] The dielectric layer 104 is etched to form a first groove 106 and a second groove 108 connected to the bottom of the second groove.

[0023] refer to Figure 2 A metal layer 110 is formed to fill the first groove 106 and the second groove 108. The metal layer 110 covers the sidewall of the first groove 106 and is electrically connected to the metal conductive layer 102.

[0024] The above-mentioned method for forming the chip failure analysis structure has the following problems: First, because the first groove 106 is relatively deep (e.g., 1.1 μm), the metal layer 110 is formed using a focused ion beam (FIB) system (FIB equipment). The metal layer 110 on the sidewall of the first groove 106 has poor adhesion and is prone to falling off and breaking. Furthermore, the metal layer 110 in the first groove 106 and the second groove 108 has poor density, which reduces the fabrication yield of the chip failure analysis structure.

[0025] Second, the first groove 106 is formed using a FIB device. Since the first groove 106 is relatively deep (e.g., 1.1 μm), it takes a long time to form the first groove 106, and it also takes a long time to fill the metal layer 110 in the first groove 106, which reduces the manufacturing efficiency.

[0026] In summary, the above-mentioned method for forming chip failure analysis structures reduces the yield and manufacturing efficiency of the chip failure analysis structures.

[0027] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0028] refer to Figures 4 to 15 This is a schematic diagram of the structure corresponding to each step in the method for forming the chip failure analysis structure according to an embodiment of the present invention.

[0029] refer to Figure 4 A substrate 200, a plurality of conductive layers on the substrate 200, and a thin film layer 208 on the conductive layers are provided.

[0030] The substrate 200 is used to provide a process platform for the formation of chip failure analysis structures.

[0031] The chip failure analysis structure is used to analyze the causes of chip failure; the chip failure analysis includes: short circuit analysis, open circuit analysis, on-state current analysis, off-state current analysis, threshold analysis, and other electrical performance analysis of the chip.

[0032] In this embodiment, the substrate 200 is a silicon substrate 200, and the material of the substrate 200 is single-crystal silicon. In other embodiments, the material of the substrate 200 may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium dihydrogen nitride. The substrate 200 may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. In other embodiments, an epitaxial layer (not shown) with the same crystal structure as the substrate 200 may also be formed on the surface of the substrate 200 to improve the pattern transfer quality.

[0033] refer to Figure 9 In this embodiment, multiple conductive layers located on the substrate 200 are electrically connected to a chip (not shown) on the substrate 200 for analyzing chip failure conditions.

[0034] For the sake of brevity and clarity of the accompanying drawings, in this embodiment of the application, the number of the plurality of conductive layers is three, namely conductive layer 202, conductive layer 204 and conductive layer 206, which is not intended to limit this application.

[0035] In one specific embodiment, the conductive layer is made of tungsten, and the conductive layer 204 is formed together with the gate plug of the chip during the chip manufacturing process; the conductive layer 202 and the conductive layer 206 are formed together with the source and drain plugs of the chip during the chip manufacturing process; in this embodiment, only the connection of the conductive layer 204 to the test terminal 270 (i.e., the gate test terminal) through the metal interconnect layer is used as an example for explanation. The formation methods of the conductive layer 202, the conductive layer 206, the source test terminal 270 connected to the conductive layer 202, and the drain test terminal 270 connected to the conductive layer 206 can be derived by referring to the relevant description in the conductive layer 204, and will not be repeated here.

[0036] The thin film layer 208 located on the conductive layer includes a metal layer and a non-metal layer. In this embodiment, the thin film layer 208 located on the conductive layer is a non-metal layer. In a specific embodiment, the thin film layer 208 is an interlayer dielectric layer formed during the chip manufacturing process.

[0037] refer to Figures 5 to 9 , combined Figure 4 ,in, Figure 9 yes Figure 8The diagram shows a top view of the structure. A groove is formed within the thin film layer 208, with a portion of the thickness of the thin film layer 208 retained at the bottom of the groove, and the sidewalls of the groove are stepped. The steps of forming a groove within the thin film layer 208, with a portion of the thickness of the thin film layer 208 retained at the bottom of the groove, and the sidewalls of the groove being stepped include: using a focused ion beam to successively define etching regions, and removing the thin film layer 208 within the etching region using the focused ion beam. The planar dimension of each defined etching region is smaller than the planar dimension of the previously defined etching region, so that the step sidewalls of each layer of the steps are sequentially recessed downwards towards the axis of the groove in a direction perpendicular to the surface of the thin film layer 208, and the depth of the bottom surface of the groove relative to the surface of the thin film layer 208 after each etching is greater than the depth after the previous etching, and a portion of the thickness of the thin film layer 208 is retained at the bottom of the groove.

[0038] In this embodiment, the sidewall of the groove is stepped, which can improve the coverage of the subsequently formed metal interconnect layer on the step and reduce the risk of the metal interconnect layer falling off at the sidewall of the step, thereby improving the manufacturing yield of the chip failure analysis structure.

[0039] In this embodiment, a portion of the thickness of the thin film layer 208 is retained at the bottom of the groove to reduce damage to the conductive layer (e.g., the exposed conductive layer surface is easily oxidized or burned) during the step of determining the conductive layer that needs to be electrically connected among the multiple conductive layers at the bottom of the groove.

[0040] The thickness of the thin film layer 208 retained at the bottom of the groove is selected from [50nm, 200nm], preferably [80nm, 100nm], so that the position of the conductive layer 204 at the bottom of the groove can be identified by the focused ion beam system (FIB device).

[0041] For ease of understanding and for the sake of clarity in the accompanying drawings, this embodiment of the application uses five steps as an example to illustrate the steps of forming a groove in the thin film layer 208 and the step-shaped sidewalls of the groove.

[0042] refer to Figure 8 The number of steps is five, namely steps 210, 220, 230, 240, and 252. Each step includes a step surface and a step sidewall. Specifically, step 210 includes a step surface 212 and a step sidewall 214, step 220 includes a step surface 222 and a step sidewall 224, step 230 includes a step surface 232 and a step sidewall 234, step 240 includes a step surface 242 and a step sidewall 244, and step 252 includes a step surface 254 and a step sidewall 256. Those skilled in the art can deduce the steps for forming the remaining number of steps based on the method of forming the five steps, without limiting this application.

[0043] The angle between the sidewall of each step and the corresponding step surface is greater than or equal to 90 degrees and less than or equal to 95 degrees. In some embodiments, the angle between the sidewall of each step and the corresponding step surface is greater than 90 degrees and less than or equal to 95 degrees.

[0044] In one specific embodiment, the angle between the step sidewall 214 and the step surface 212 is greater than 90 degrees and less than or equal to 95 degrees.

[0045] refer to Figure 9 , combined Figure 8 The shape formed by each step sidewall includes one or more of the following: cylinder, prism, elliptical cylinder, rectangular cylinder, square cylinder and polygonal cylinder. In this embodiment, the shape formed by each step sidewall is a cylinder, that is, step sidewall 214 forms cylinder 216, step sidewall 224 forms cylinder 226, step sidewall 234 forms cylinder 236, step sidewall 244 forms cylinder 246, and step sidewall 256 forms cylinder 258.

[0046] In this embodiment, the shape formed by the sidewalls of each step is a cylinder, which is perpendicular to the surface of the thin film layer 208 and downwards. The diameters of the upper and lower bases of each cylinder decrease, and all cylinders are coaxial and have the same height.

[0047] The shape formed by the sidewalls of each step is a cylinder, which matches the beam spot diameter of the focused ion beam. This makes the sidewalls of the cylinder smoother, reduces the risk of breakage in the metal interconnect layer subsequently formed on the sidewalls of the cylinder, and improves the fabrication yield of the chip failure analysis structure.

[0048] In this embodiment, the diameter of cylinder 216 is 1 μm (the beam spot diameter of the focused ion beam output by the selected FIB device is 1 μm), the diameter of cylinder 226 is 0.8 μm (the beam spot diameter of the focused ion beam output by the selected FIB device is 0.8 μm), the diameter of cylinder 236 is 0.6 μm (the beam spot diameter of the focused ion beam output by the selected FIB device is 0.6 μm), the diameter of cylinder 246 is 0.4 μm (the beam spot diameter of the focused ion beam output by the selected FIB device is 0.4 μm), and the diameter of cylinder 258 is 0.2 μm (the beam spot diameter of the focused ion beam output by the selected FIB device is 0.2 μm).

[0049] The height of each step sidewall 214 to step sidewall 256 is 200 nanometers, or the length of each step sidewall 214 to step sidewall 256 is 200 nanometers.

[0050] In this embodiment, the steps for forming the five steps include: The substrate 200 is placed in a focused ion beam system (FIB device), and the position of the substrate 200 in the FIB device is adjusted so that the surface of the substrate 200 is perpendicular to the transmission direction of the focused ion beam.

[0051] Based on the height (or length) of each step sidewall and the diameter of each cylinder, the parameters for fabricating the chip failure analysis structure using the FIB equipment are set, including etching time, focused ion beam voltage, and focused ion beam current.

[0052] Continue to refer to Figure 4 and Figure 9 The FIB device (not shown) outputs a focused ion beam with a spot diameter of 1 μm to the upper surface of the substrate 200, that is, the planar dimension A11 (area) of the etched region is defined as approximately 0.785 μm. 2 The focused ion beam etches the thin film layer 208 for a duration of t1, forming a cylinder 216 with a diameter of 1 μm and a height of 200 nanometers corresponding to the step 210. The cylinder 216 corresponds to a sub-groove 218, which includes a step sidewall 214 and a step surface 212.

[0053] refer to Figure 5 and Figure 9 The FIB device outputs a focused ion beam with a beam spot diameter of 0.8 μm to the bottom surface of the cylinder 216. Therefore, the planar dimension A22 (area) of the etched region is defined as approximately 0.5024 μm. 2 And smaller than the previously defined planar dimension A11 of the etched area; the focused ion beam etches the bottom thin film layer 208 of the cylinder 216 for a duration of t1, forming a cylinder 226 with a diameter of 0.8 μm and a height of 200 nanometers corresponding to the step 220; the cylinder 226 is coaxial with the cylinder 216, and the cylinder 226 corresponds to a sub-groove 228, the sub-groove 228 including a step sidewall 224 and a step surface 222.

[0054] refer to Figure 6 and Figure 9 The FIB device outputs a focused ion beam with a beam spot diameter of 0.6 μm to the bottom surface of the cylinder 226. Therefore, the planar dimension A33 (area) of the etched region is defined as approximately 0.2826 μm. 2And smaller than the previously defined planar dimension A22 of the etched area; the focused ion beam etches the bottom thin film layer 208 of the cylinder 226 for a duration of t1, forming a cylinder 236 with a diameter of 0.6 μm and a height of 200 nanometers corresponding to the step 230; the cylinder 236 is coaxial with the cylinder 226, and the cylinder 236 corresponds to a sub-groove 238, the sub-groove 238 including a step sidewall 234 and a step surface 232.

[0055] refer to Figure 7 and Figure 9 The FIB device outputs a focused ion beam with a beam spot diameter of 0.4 μm to the bottom surface of the cylinder 236. Therefore, the planar dimension A44 (area) of the etched region is defined as approximately 0.1256 μm. 2 And smaller than the previously defined planar dimension A33 of the etched area; the focused ion beam etches the bottom thin film layer 208 of the cylinder 236 for a duration of t1, forming a cylinder 246 with a diameter of 0.4 μm and a height of 200 nanometers corresponding to the step 240; the cylinder 246 is coaxial with the cylinder 236, and the cylinder 246 corresponds to a sub-groove 248, the sub-groove 248 including a step sidewall 244 and a step surface 242.

[0056] refer to Figure 8 and Figure 9 The FIB device outputs a focused ion beam with a beam spot diameter of 0.2 μm to the bottom surface of the cylinder 246. That is, the planar dimension A55 (area) of the etched region defined this time is approximately 0.2 μm, which is smaller than the planar dimension A44 of the previously defined etched region. The etching time for the thin film layer 208 on the bottom surface of the cylinder 246 is t1, forming a cylinder 258 with a diameter of 0.2 μm and a height of 200 nanometers corresponding to the step 252. The cylinder 258 is coaxial with the cylinder 246, and the cylinder 258 corresponds to a sub-groove 260. The sub-groove 260 includes a step sidewall 256 and a step surface 254.

[0057] In this embodiment, after the step 252 is formed, a portion of the thickness of the thin film layer 208 is retained at the bottom of the groove. That is, a portion of the thickness of the thin film layer 208 is retained at the bottom of the sub-groove 260. In other words, a portion of the thickness of the thin film layer 208 covers the surface of the conductive layer 202, conductive layer 204, and conductive layer 206 at the bottom of the sub-groove 260.

[0058] Continue to refer to Figure 8, the step sidewalls of each layer of steps gradually taper inwards toward the axis of the groove sequentially downward along a direction perpendicular to the surface of said thin film layer 208; in this embodiment, the distance between the bottom end of the step sidewall 214 of step 210 and the axis of said groove is d1, the distance between the bottom end of the step sidewall 224 of step 220 and the axis of said groove is d2, the distance between the bottom end of the step sidewall 234 of step 230 and the axis of said groove is d3, the distance between the bottom end of the step sidewall 244 of step 240 and the axis of said groove is d4, the distance between the bottom end of the step sidewall 256 of step 252 and the axis of said groove is d5, and along the direction downward perpendicular to the surface of said thin film layer 208, d5<d4<d3<d2<d1, that is, from step sidewall 214 to step sidewall 256, they gradually taper inwards toward the axis of the groove sequentially downward along the direction perpendicular to the surface of said thin film layer 208, that is, from step sidewall 214 to step sidewall 256, they gradually approach the axis of the groove.

[0059] after each etching, the depth of the bottom surface of said groove relative to the surface of said thin film layer 208 is greater than the depth after the previous etching; in this embodiment, as Figure 4 shows, the distance between the bottom end of the sub-groove 218 and the top surface of the thin film layer 208 outside said groove is d11, as Figure 5 shows, the distance between the bottom end of the sub-groove 228 and the top surface of the thin film layer 208 outside said groove is d22, as Figure 6 shows, the distance between the bottom end of the sub-groove 238 and the top surface of the thin film layer 208 outside said groove is d33, as Figure 7 shows, the distance between the bottom end of the sub-groove 248 and the top surface of the thin film layer 208 outside said groove is d44, as Figure 8 shows, the distance between the bottom end of the sub-groove 260 and the top surface of the thin film layer 208 outside said groove is d55, d11<d22<d33<d44<d55, that is, after each etching, the depth of the bottom surface of said groove relative to the surface of said thin film layer 208 is greater than the depth after the previous etching.

[0060] In some embodiments, the figure enclosed by each step sidewall is a square cylinder, the focused ion beam spot output by the FIB apparatus is selected to be circular (i.e., a circular beam spot), and the description is given by taking forming a square cylinder as an example. The steps for forming a square cylinder (such as a square cylinder) by using a circular beam spot include: Step S1: In the software of said FIB apparatus, set the width of the square etching area as W, and the etching depth as H; the diameter of the circular beam spot is set as d; the movement step distance of the circular beam spot is 0.8d (the movement step distances in the positive X direction, negative X direction, positive Y direction and negative Y direction are all 0.8d) (to ensure overlap between adjacent scanning steps); Step S2: Divide the square etching area into m (columns) × n (rows) pixels, such as 2 (columns) × 2 (rows) pixels; first, position the circular spot at pixel (1, 1) for etching, with an etching depth H; the circular spot moves with a step size of 0.8d (along the positive X-axis), and etches pixel (1, 2) according to the etching parameters of pixel (1, 1); after etching pixel (1, 2), the circular spot moves with a step size of 0.8d (along the negative Y-axis), jumps to pixel (2, 2), and etches pixel (2, 2) according to the etching parameters of pixel (1, 1); after etching pixel (2, 2), the circular spot moves with a step size of 0.8d (along the negative X-axis), jumps to pixel (2, 1), forming a square cylindrical groove.

[0061] The steps for forming square column grooves of other sizes can be derived by those skilled in the art by following the methods of steps S1 and S2.

[0062] In some embodiments, the focused ion beam spot shape is rectangular or square, and square or rectangular cylindrical grooves of the required width and length can be formed according to steps S1 and S2. If the size of the rectangle or square is the same as the size and shape of the focused ion beam spot, the required square or rectangular cylindrical groove is formed directly in one step; if the size of the rectangle or square is larger than the size and shape of the focused ion beam spot, a moving step distance is set, and the required square or rectangular cylindrical groove is formed multiple times.

[0063] If the focused ion beam spot is circular and the groove is cylindrical, and the diameter of the cylinder is larger than the diameter of the beam spot, the groove can be formed by referring to steps S1 and S2 above.

[0064] In some embodiments, the pattern formed by the sidewalls of each step further includes a frustum (larger at the top and smaller at the bottom) and a prism (larger at the top and smaller at the bottom), which are used to further improve the coverage of the subsequent metal interconnect layer on the sidewalls of the groove, thereby improving the fabrication yield of the chip failure analysis structure. The planar dimensions of the frustum (larger at the top and smaller at the bottom) or the prism (larger at the top and smaller at the bottom) correspond to the areas of the smaller base of the frustum and the smaller base of the prism.

[0065] Continue to refer to Figure 8 and Figure 9 The conductive layer that needs to be electrically connected to the outside among the multiple conductive layers at the bottom of the groove is identified and denoted as the external conductive layer.

[0066] By selecting one of multiple conductive layers as the external conductive layer, the failure analysis chip connected to the external conductive layer can be accurately analyzed.

[0067] For the sake of brevity and clarity in the accompanying drawings and for ease of description, in this embodiment of the application, there are three conductive layers: conductive layer 202, conductive layer 204, and conductive layer 206, wherein conductive layer 204 is an external conductive layer.

[0068] The external conductive layer is determined using a FIB (Film Injection Blower) device, a SEM (Scanning Electron Microscope), or a combination of both. In this embodiment, a focused ion beam system is used for focused ion beam imaging to locate and determine the conductive layer requiring external electrical connection among the multiple conductive layers at the bottom of the groove; this layer is denoted as the external conductive layer. Specifically: In a focused ion beam system, the step of magnifying the bottom of the groove to determine the external conductive layer includes: placing the substrate 200 with the groove into the sample stage of the FIB device; manually moving the sample stage along the X and Y directions to bring the bottom of the groove (sub-groove 260) into the center of the field of view; increasing the magnification by rotating the rollers of the FIB device and inputting the magnification, the software in the FIB device automatically reduces the scanning field size, for example, the field width is about 20 μm when the magnification is ×5000, and it is reduced to about 2 μm when it is increased to ×50000; after magnification, the software in the FIB device re-executes autofocus and auto-astigmatism correction to ensure that the bottom of the groove is clear; then displaying multiple conductive layers at the bottom of the groove on a display connected to the FIB device to determine the conductive layer that needs to be electrically externalized among the multiple conductive layers at the bottom of the groove, denoted as the external conductive layer; the external conductive layer covers a portion of the thickness of the thin film layer 208, that is, the bottom of the groove retains a portion of the thickness of the thin film layer 208.

[0069] In this embodiment, the external conductive layer is referred to as conductive layer 204.

[0070] refer to Figure 10 and Figure 11 ,in, Figure 11 yes Figure 10 A top view of the structure; remove the thin film layer 208 on the external conductive layer to expose the external conductive layer.

[0071] In this embodiment, a focused ion beam system is used to remove the thin film layer 208 on the external conductive layer, that is, to remove part or all of the thin film layer 208 retained at the bottom of the groove. Specifically, an opening 261 is formed on the external conductive layer (the size of the opening 261 is set according to actual needs) to expose part or all of the external conductive layer at the bottom of the groove. In this embodiment, a focused ion beam system is used to remove the thin film layer 208 on the external conductive layer, that is, to remove part of the thin film layer 208 retained at the bottom of the groove. Specifically: The substrate 200 with the groove is positioned in the field of view of the focused ion beam. The location of the window 261 to be opened is confirmed by focused ion beam imaging of the focused ion beam system. An etching pattern of the corresponding shape (usually rectangular or circular) is drawn in the focused ion beam software, and the etching depth, focused ion beam voltage, focused ion beam current, etc. are set to etch the thin film layer 208 at the location of the window 261. In one embodiment, the thin film layer 208 is silicon oxide. When etching the silicon oxide on the external conductive layer, xenon fluoride (XeF2) gas is simultaneously introduced to assist etching and improve the removal rate of silicon oxide. After etching is completed, the external conductive layer is confirmed to be exposed by imaging of the focused ion beam system, which means that the removal process of part of the thin film layer 208 on the external conductive layer at the bottom of the groove is completed.

[0072] refer to Figure 12 and Figure 13 , combined Figure 11 ,in, Figure 13 yes Figure 12 A top view of the structure; forming a metal interconnect layer.

[0073] One end of the metal interconnect layer is electrically connected to the external conductive layer, and is used to transmit test signals from external test equipment to the chip connected to the external conductive layer for chip failure analysis.

[0074] The material of the metal interconnect layer includes platinum or tungsten. In this embodiment, the material of the metal interconnect layer is platinum (Pt).

[0075] The deposition thickness of the metal interconnect layer is selected from [50nm, 400nm]. In this embodiment, the thickness of the metal interconnect layer is 300nm. Along the direction perpendicular to the step surface, the thickness of the metal interconnect layer is not less than the maximum value among the distances from the bottom of each step sidewall to the step surface corresponding to that step sidewall. Specifically, along the direction perpendicular to the step surface, the thickness of the metal interconnect layer is defined as H, and the vertical distance from the bottom of each step sidewall to the step surface corresponding to that step sidewall is defined as hi. The maximum value among them is denoted as H_max. Then, H≥H_max is satisfied.

[0076] The metal interconnect layer is formed by focused ion beam induced deposition in a focused ion beam system. In this embodiment, the steps for forming the metal interconnect layer include: After opening a window 261 on the external conductive layer and partially exposing the external conductive layer, the grooved substrate 200 is positioned in the field of view of the focused ion beam system. By focusing ion beam imaging, the exposed area of ​​the external conductive layer (the first exposed area, i.e., the window 261) and the trace path of the metal interconnect extending from the first exposed area to the free area on the upper surface of the thin film layer 208 (the first trace path 263) are confirmed. The gas injection system on the focused ion beam system is turned on, and the platinum precursor gas methylcyclopentadienyltrimethylplatinum (chemical formula (CH3)3CH3C5H4Pt or MeCpPtMe3) is introduced into the surface of the first trace path 263. A suitable focused ion beam current (usually in the pA to 100 pA range) is selected to scan the trace path. The focused ion beam current decomposes and reduces the platinum precursor gas adsorbed on the trace path to form a platinum metal interconnect layer 262 on the trace path.

[0077] The platinum metal interconnect layer 262 starts from the exposed area of ​​the external conductive layer and extends along the predetermined first trace path 263 to the top surface of the thin film layer 208 outside the groove. After deposition, the imaging mode is switched to confirm that the metal interconnect layer is continuous, uninterrupted and in good contact with the surface areas of the external conductive layer and the thin film layer 208. This completes the metal interconnect layer formation process.

[0078] In this embodiment, one end of the platinum metal interconnect layer 262 is electrically connected to the external conductive layer, and the platinum metal interconnect layer 262 covers the step sidewalls 214 to 256 of the groove, as well as the step surfaces 212 to 254; the other end of the platinum metal interconnect layer 262 is located on the surface of the thin film layer 208 outside the groove.

[0079] Continue to refer to Figure 12 In forming test terminal 270 (e.g. Figure 14Before forming the metal interconnect layer (as shown), the forming method further includes forming a protective dielectric layer 264 covering the metal interconnect layer, wherein the protective dielectric layer 264 extends onto the thin film layer 208 outside the groove.

[0080] The protective dielectric layer 264 is used to insulate the groove and prevent moisture from entering the chip.

[0081] The material of the protective dielectric layer 264 includes silicon oxide or silicon nitride. In this embodiment, the material of the protective dielectric layer 264 is silicon oxide.

[0082] The process for forming the protective dielectric layer 264 covering the metal interconnect layer includes atomic layer deposition (ALD) or chemical vapor deposition (CVD). In this embodiment, the process for forming the protective dielectric layer 264 covering the metal interconnect layer is ALD.

[0083] In this embodiment, the step of forming the protective dielectric layer 264 includes: A protective dielectric layer 264 is formed by atomic layer deposition (ALD) to cover the metal interconnect layer (platinum metal interconnect layer 262). The protective dielectric layer 264 covers the surface and sidewalls of the metal interconnect layer. The protective dielectric layer 264 also covers the step sidewalls and step surfaces of each step of the groove, that is, the protective dielectric layer 264 covers the step sidewalls 214 to 256 and the step surfaces 212 to 254. The protective dielectric layer 264 also extends to cover the thin film layer 208 outside the groove.

[0084] refer to Figure 14 and Figure 15 , combined Figure 13 ,in, Figure 15 yes Figure 14 A top view of the structure; forming a test terminal 270 on the thin film layer 208 outside the groove; wherein the metal interconnect layer is connected to the test terminal 270 from the external conductive layer.

[0085] The test terminal 270 is electrically connected to the other end of the metal interconnect layer, and the test signal of the external test equipment is transmitted to the chip to be analyzed for failure through the test terminal 270, the metal interconnect layer and the external conductive layer.

[0086] The test terminal 270 is made of platinum or tungsten. In this embodiment, the test terminal 270 is made of platinum (Pt).

[0087] The area of ​​the test terminal 270 is set according to actual needs.

[0088] The test terminal 270 is formed by focused ion beam induced deposition using a focused ion beam system. In this embodiment, the steps for forming the test terminal 270 include: Continue to refer to Figure 13 A via 266 is formed within the thin film layer 208 outside the groove, with a portion of the metal interconnect layer exposed at the bottom of the via 266. Specifically, a portion of the protective dielectric layer 264 on the surface of the metal interconnect layer on the thin film layer 208 outside the groove is removed using a focused ion beam from a focused ion beam system to form the via 266. The substrate 200 with the groove is positioned in the field of view of the focused ion beam, and the via area where the via 266 is formed is confirmed by focused ion beam imaging. A via 266 pattern of the corresponding shape (usually rectangular or circular) is drawn in the focused ion beam software, and the etching depth of the via 266, the focused ion beam voltage, etc., are set to etch the protective dielectric layer 264 in the via area to form the via 266. After etching, the external conductive layer at the bottom of the via 266 is confirmed to be exposed by focused ion beam imaging, which completes the process of forming the via 266.

[0089] The size and location of via 266 should be set according to actual needs and should not be used to limit this application.

[0090] After completing the via 266 and exposing the metal interconnect layer (platinum metal interconnect layer 262) at the bottom of the via 266, the grooved substrate 200 is positioned in the field of view of the focused ion beam system. The exposed area (second exposed area) of the metal interconnect layer at the bottom of the via 266 is confirmed by focused ion beam imaging. The gas injection system on the focused ion beam system is turned on, and the platinum precursor gas methylcyclopentadienyltrimethylplatinum (chemical formula (CH3)3CH3C5H4Pt or MeCpPtMe3) is introduced into the via 266. A suitable focused ion beam is selected to scan the via 266. The focused ion beam decomposes and reduces the platinum precursor gas adsorbed in the via 266 to form a via metal layer 268 in the via 266.

[0091] After completing the via metal layer 268, the grooved substrate 200 is positioned in the field of view of the focused ion beam system. The test terminal formation area is confirmed by focused ion beam imaging. The gas injection system on the focused ion beam system is turned on, and the platinum precursor gas methylcyclopentadienyltrimethylplatinum (chemical formula (CH3)3CH3C5H4Pt or MeCpPtMe3) is introduced into the test terminal formation area. A suitable focused ion beam is selected to scan the test terminal formation area. The focused ion beam decomposes and reduces the platinum precursor gas adsorbed in the test terminal formation area to form the test terminal 270 in the test terminal formation area.

[0092] After completing the test terminal 270, the grooved substrate 200 is positioned in the field of view of the focused ion beam system. The test terminal formation area and the trace path (second trace path) extending from the test terminal formation area to the via metal layer 268 are confirmed by focused ion beam imaging. The gas injection system on the focused ion beam system is turned on, and the platinum precursor gas methylcyclopentadienyltrimethylplatinum (chemical formula (CH3)3CH3C5H4Pt or MeCpPtMe3) is introduced into the surface of the second trace path. A suitable focused ion beam is selected to scan the trace path. The focused ion beam decomposes and reduces the platinum precursor gas adsorbed on the second trace path to form a terminal interconnect layer 272 on the trace path. The terminal interconnect layer 272 connects the test terminal 270 and the via metal layer 268.

[0093] It should be noted that the dimensions, positions, thicknesses, and shapes of the via metal layer 268, the test terminal 270, and the terminal interconnect layer 272 can be selected according to actual needs and are not intended to limit this application.

[0094] It should be noted that the order in which the via metal layer 268, the test terminal 270, and the terminal interconnect layer 272 are formed can be adjusted according to actual needs and is not intended to limit this application.

[0095] It should be noted that the focused ion beam system can form windows or grooves in a specified area, and can form the required metal film layer in a specified area.

[0096] The chip failure analysis structure can be formed near the cut path of the substrate 200 and near the edge of the substrate 200.

[0097] This application provides a chip failure analysis structure, including: a substrate; a plurality of conductive layers on the substrate, the plurality of conductive layers including an external conductive layer; a thin film layer on the conductive layers; a groove located within the thin film layer, the sidewalls of the groove being stepped; a metal interconnect layer; and test terminals located on the thin film layer outside the groove; wherein the metal interconnect layer is connected from the external conductive layer to the test terminals.

[0098] refer to Figure 14 This is a schematic diagram of a chip failure analysis structure according to an embodiment of this application.

[0099] refer to Figure 14 The chip failure analysis structure includes: substrate 200.

[0100] For a description of the substrate 200, please refer to the description in the foregoing embodiments.

[0101] refer to Figure 14 The chip failure analysis structure includes: a plurality of conductive layers located on the substrate 200, the plurality of conductive layers including an external conductive layer; For a description of the plurality of conductive layers and the external conductive layer, please refer to the relevant descriptions in the foregoing embodiments.

[0102] refer to Figure 14 The chip failure analysis structure includes a thin film layer 208 located on the conductive layer.

[0103] For a description of the thin film layer 208, please refer to the description in the foregoing embodiments.

[0104] refer to Figure 14 The chip failure analysis structure includes a groove located within the thin film layer 208, and the sidewalls of the groove are stepped.

[0105] refer to Figure 14 , combined Figure 8 In this embodiment, the height of each step on the sidewall of the groove decreases or remains equal as it descends in a direction perpendicular to the surface of the thin film layer 208. That is, the distance between the bottom end of each step sidewall of the groove and the corresponding step surface remains equal as it descends in a direction perpendicular to the surface of the thin film layer 208. Specifically, the distance between the bottom end of step sidewall 214 and step surface 212 is d21, the distance between the bottom end of step sidewall 224 and step surface 222 is d22, the distance between the bottom end of step sidewall 234 and step surface 232 is d23, the distance between the bottom end of step sidewall 244 and step surface 242 is d24, and the distance between the bottom end of step sidewall 256 and step surface 254 is d25, and d21=d22=d23=d24=d25.

[0106] In some embodiments, the height of each step on the sidewall of the groove decreases downward along the direction perpendicular to the surface of the thin film layer 208. This can improve the coverage of the metal interconnect layer on the step sidewall at the bottom of the groove and improve the fabrication yield of the chip failure analysis structure because the size of the sub-groove at the bottom of the groove is smaller (both horizontally and vertically). Specifically, the distance between the bottom end of the step sidewall 214 and the step surface 212 is d31, the distance between the bottom end of the step sidewall 224 and the step surface 222 is d32, the distance between the bottom end of the step sidewall 234 and the step surface 232 is d33, the distance between the bottom end of the step sidewall 244 and the step surface 242 is d34, and the distance between the bottom end of the step sidewall 256 and the step surface 254 is d35, and d31>d32>d33>d34>d35.

[0107] refer to Figure 14 , combined Figure 8 Along the direction perpendicular to the surface of the thin film layer 208 downwards, the step widths of each step in the groove either increase progressively or remain equal. In this embodiment, along the direction perpendicular to the surface of the thin film layer 208 downwards, the step widths of each step in the groove remain equal; specifically, the width of step surface 212 is w11, the width of step surface 222 is w12, the width of step surface 232 is w13, the width of step surface 242 is w14, and the width of step surface 254 is w15, and w11=w12=w13=w14=w15.

[0108] In other embodiments, the step width of each step in the groove increases downwards along a direction perpendicular to the surface of the thin film layer 208. This improves the coverage of the metal interconnect layer on the step surface at the bottom of the groove, thereby increasing the fabrication yield of the chip failure analysis structure because the size of the sub-grooves at the bottom of the groove is smaller (both horizontally and vertically). Specifically, the width of step surface 212 is w21, the width of step surface 222 is w22, the width of step surface 232 is w23, the width of step surface 242 is w24, and the width of step surface 254 is w25, and w21... <w22<w23<w24<w25。

[0109] For further information regarding the groove, please refer to the relevant descriptions in the foregoing embodiments.

[0110] refer to Figure 14 The chip failure analysis structure includes a metal interconnect layer.

[0111] For a description of the metal interconnect layer, please refer to the description in the foregoing embodiments.

[0112] refer to Figure 14 The chip failure analysis structure includes: a test terminal 270 located on a thin film layer 208 outside the groove; wherein the metal interconnect layer is connected from the external conductive layer to the test terminal 270.

[0113] For a description of the test terminal 270, please refer to the description in the foregoing embodiments.

[0114] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes, modifications and combinations of the technical solutions of the present invention by using the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for forming a chip failure analysis structure, characterized in that, include: A substrate, a plurality of conductive layers on the substrate, and a thin film layer on the conductive layers are provided; A groove is formed within the thin film layer, the bottom of the groove retains a portion of the thickness of the thin film layer, and the sidewalls of the groove are stepped. The conductive layer that needs to be electrically connected to the outside among the multiple conductive layers at the bottom of the groove is identified and denoted as the external conductive layer; Remove the thin film layer on the external conductive layer; Forming a metal interconnect layer; Test terminals are formed on the thin film layer outside the groove; The metal interconnect layer is connected to the test terminal from the external conductive layer.

2. The forming method as described in claim 1, characterized in that, The step of forming a groove within the thin film layer, wherein the bottom of the groove retains a portion of the thickness of the thin film layer, and the sidewalls of the groove are stepped, includes: A focused ion beam is used to define etching regions one by one, and the thin film layer in the etching region is removed by the focused ion beam. The planar size of the etching region defined each time is smaller than the planar size of the etching region defined in the previous time, so that the step sidewalls of each layer step are successively recessed inward toward the axis of the groove along the direction perpendicular to the surface of the thin film layer. After each etching, the depth of the bottom surface of the groove relative to the surface of the thin film layer is greater than the depth after the previous etching, and a portion of the thickness of the thin film layer is retained at the bottom of the groove.

3. The forming method as described in claim 1, characterized in that, By using focused ion beam imaging to locate and determine the conductive layer that needs to be electrically connected to the outside among the multiple conductive layers at the bottom of the groove, it is denoted as the external conductive layer.

4. The forming method as described in claim 1, characterized in that, The metal interconnect layer is formed by focused ion beam-induced deposition.

5. The forming method as described in claim 1, characterized in that, Before forming the test terminals, and after forming the metal interconnect layer, the forming method further includes: A protective dielectric layer is formed covering the metal interconnect layer, the protective dielectric layer extending into the groove. On the outer thin film layer.

6. The forming method as described in claim 5, characterized in that, The process for forming a protective dielectric layer covering the metal interconnect layer includes atomic layer deposition or chemical vapor deposition.

7. The forming method as described in claim 1, characterized in that, The material of the metal interconnect layer includes platinum or tungsten.

8. A chip failure analysis structure, characterized in that, include: Base; A plurality of conductive layers located on the substrate, the plurality of conductive layers including an external conductive layer; A thin film layer located on the conductive layer; A groove located within the thin film layer, wherein the sidewalls of the groove are stepped; Metal interconnect layer; The test terminal is located on the thin film layer outside the groove; The metal interconnect layer is connected to the test terminal from the external conductive layer.

9. The failure analysis structure as described in claim 8, characterized in that, As the groove extends downwards in a direction perpendicular to the surface of the thin film layer, the heights of each step on the sidewall decrease or remain equal.

10. The failure analysis structure as described in claim 9, characterized in that, Along a direction perpendicular to the surface of the thin film layer downwards, the step width of each step in the groove either increases or remains equal.

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