Chip data reading test method and electronic device

Abstract

The embodiment of the application discloses a chip data reading test method and electronic equipment, and relates to the technical field of integrated circuit testing. The method comprises the following steps: acquiring the number of commands received by the chip when the chip receives the wake-up command sent in a cycle; sending the wake-up command to the chip again in a cycle based on the number of commands, sampling and reading the receiving end of the chip to obtain sampling data; performing alignment and analysis processing on the sampling data to obtain a chip serial number; and verifying the chip serial number to obtain verification information. The application can realize accurate triggering by dynamically adjusting the number of times of sending the wake-up command, and can solve the problem of unstable data grabbing caused by uncertain response timing of asynchronous communication by combining the oversampling and alignment analysis algorithm, thereby realizing automatic and accurate reading of the chip serial number.

Description

Technical Field

[0001] This application relates to the field of integrated circuit testing technology, and in particular to a method and electronic device for reading and testing chip data. Background Technology

[0002] In the mass production of integrated circuits, reading and verifying the unique identification information burned into the chip, namely the chip's serial number (SN), is a crucial step in ensuring product traceability and quality consistency. Among these, the Universal Asynchronous Receiver / Transmitter (UART), as a basic serial communication interface, is widely used in debugging interfaces and data output channels for various chips due to its simple hardware structure, low resource consumption, and lack of clock synchronization signals.

[0003] However, in actual large-scale production testing scenarios, due to the inherent asynchronous nature of the UART communication mechanism and the discreteness of response delays among different individual chips, testing equipment often struggles to accurately capture the moment when the chip begins to output data. This causes the testing equipment to easily miss the data start point, resulting in incomplete data frames or parsing errors. Consequently, the testing process cannot achieve efficient, fully automated batch operations while ensuring a high pass rate, becoming a major bottleneck restricting testing efficiency and data reliability. Summary of the Invention

[0004] Based on this, this application provides a chip data reading test method and electronic device, which can solve the technical problem in the prior art that the ATE cannot stably and batch capture chip SN data due to the uncertainty of UART response timing.

[0005] Firstly, this application provides a method for testing chip data reading, including: The number of wake-up commands received by the chip when it responds to the wake-up commands sent in a loop; Based on the number of commands, wake-up commands are sent to the chip again in a loop, and the chip's receiver is sampled and read to obtain sampled data; The sampled data is aligned and parsed to obtain the chip serial number. The chip serial number is verified to obtain the verification information.

[0006] Secondly, this application also provides a chip data reading and testing device, comprising: The acquisition unit is used to acquire the number of wake-up commands received by the chip when responding to the wake-up commands sent in a loop. The sampling unit is used to send wake-up commands to the chip again in a loop based on the number of commands, and to sample and read the data from the chip's receiver to obtain sampled data. The alignment and parsing unit is used to perform alignment and parsing processing on the sampled data to obtain the chip serial number; The verification unit is used to verify the chip serial number and obtain the verification information of the chip serial number.

[0007] Thirdly, this application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the chip data reading test method provided in the first aspect above.

[0008] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program that, when executed by a processor, causes the processor to perform the chip data reading test method provided in the first aspect.

[0009] Fifthly, embodiments of this application also provide a computer program product, including a computer program or instructions, wherein the computer program or instructions are executed by a processor using the chip data reading test method provided in the first aspect.

[0010] The chip data reading and testing method provided in this application obtains the number of wake-up commands sent by the chip in response to the loop, and then sends the wake-up commands again in a loop based on the number of commands. At a precise moment, the receiving end is sampled at high speed to obtain sampled data. This allows the test equipment to actively adapt to the response delay differences of different chips, thereby starting data acquisition at the critical moment when the chip is about to respond. The sampled data is aligned and parsed using the number of samples and level information to restore the chip serial number, and finally the chip serial number is verified to obtain verification information. This effectively overcomes the bit boundary jitter problem caused by clock asynchrony in asynchronous communication, achieves accurate alignment and complete restoration of data frames, and performs conversion and legality verification on the parsed byte array to ensure that the final output chip serial number is accurate. This effectively solves the problem that the automatic test equipment cannot stably and batch capture chip SN data due to the uncertainty of UART response timing, avoids data loss or parsing errors caused by missing the data start point, and significantly improves the data capture stability, parsing accuracy and overall automated testing efficiency in the chip mass production test process. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is an application scenario diagram of the chip data reading and testing method provided in the embodiments of this application; Figure 2 A flowchart illustrating the chip data reading and testing method provided in this application embodiment; Figure 3 A schematic block diagram of a chip data reading and testing device provided in the embodiments of this application; Figure 4 A schematic block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0013] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0014] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0015] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0016] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0017] In addition, unless otherwise explicitly specified or defined in the embodiments in this application, the terms "mounting", "connected", "connection" and "fixed" appearing in the embodiments shall be understood in a broad sense. For example, connection may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection, which can be understood. Of course, it may also be a direct connection, or an indirect connection through an intermediate medium, or an internal communication between two elements, or an interaction relationship between two elements. Those skilled in the art can understand the specific meanings of the above terms in this application according to specific implementation circumstances.

[0018] Please refer to Figure 1 , the chip data reading test method provided by the embodiments of the present application can be applied to the terminal of test equipment 110. A UART communication protocol can be adopted for communication between the test equipment 110 and the chip 120, and the chip data reading test method can be executed by an application installed in the terminal of the test equipment 110. Wherein, the terminal can be a server, a desktop computer, a laptop computer, a tablet computer, a mobile phone, etc. The test equipment 110 may be Chroma automatic test equipment.

[0019] It should be noted that the application scenarios described in the following embodiments of the present application are intended to illustrate the technical solutions of the embodiments of the present application more clearly, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art will understand that as new application scenarios emerge, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0020] The following is a detailed description of the chip data reading test method provided by the present application.

[0021] as shown in Figure 2 , the method includes the following steps S210 to S240.

[0022] S210: Obtain the number of wake-up commands received by the chip when the chip responds to cyclically sent wake-up commands.

[0023] In this embodiment, the test equipment can cyclically send wake-up commands to the chip under test, and the wake-up commands can be used to activate the specific instruction sequence of the internal communication logic of the chip. Wherein, the wake-up command may be a set of predefined bytecodes.

[0024] Specifically, due to differences in the chip's internal state, clock synchronization accuracy or processing delay, the number of commands required for response to wake-up varies uncertainly for different chips or the same chip under different working conditions. In the present application, by continuously sending wake-up commands and monitoring the feedback state of the chip in real time, the exact number of received commands required for the chip to successfully switch from the sleep or idle state to the data transmission state can be detected.

[0025] The number of commands can reflect the timing reference for the chip to establish a communication link, providing a basis for accurate data capture later. For example, the test equipment continuously sends wake-up commands at preset time intervals until the expected electrical change or protocol handshake signal is detected at the chip receiver. At this point, the number of commands sent can be counted.

[0026] In some embodiments, step S210, obtaining the number of wake-up commands received by the chip when responding to the wake-up commands sent cyclically, includes: executing an initial test sequence to send wake-up commands to the chip cyclically; and obtaining the number of wake-up commands received by the chip when responding to the wake-up commands.

[0027] Specifically, this application can use test equipment to execute an initial test sequence to cyclically send wake-up commands to the chip. The test equipment can be an Automatic Test Equipment (ATE).

[0028] In this embodiment, the test device can load and execute a set of basic test vectors, i.e., the initial test sequence, during the test initiation phase to build a deterministic communication environment to probe the response characteristics of the device under test (DUT).

[0029] The initial test sequence is configured to continuously send wake-up commands to the chip, for example, by cyclically sending a stream of instructions with a specific byte order (such as 0xF8) through the ATE transmitter until a preset interrupt or termination condition is met.

[0030] Meanwhile, during the initial test sequence, the Pattern comparison logic within the ATE monitors the signal level of the chip's receiver (RX) in real time. Since the Universal Asynchronous Receiver / Transmitter (UART) bus is high by default in idle mode, the Compare H instruction in the Pattern will continue to evaluate until a chip response is detected. The UART communication format can be: 1 start bit (low level), 8 data bits, 1 parity bit, and 1 stop bit (high level), with the bus being high when idle.

[0031] When the chip is woken up and begins transmitting data, its start bit pulls the RX pin low, causing the Compare H logic to fail. This failure event can serve as a critical synchronization signal, used to accurately capture the time inflection point when the chip transitions from a silent state to a responsive state, thus providing a time reference for subsequent quantization of the chip's receive delay.

[0032] The number of commands can characterize the total number of wake-up commands actually issued by the ATE from the start of the initial test sequence to the generation of a valid response signal by the chip. It can reflect the clock cycle or instruction cycle delay required for the chip to process the wake-up request.

[0033] Specifically, in the process of obtaining the number of wake-up commands received by the chip when the chip responds to the wake-up command, this application can obtain the specific number of commands by reading the number of Pattern lines or test cycles executed cumulatively from the initial test sequence to the time when the Compare H logic fails, and converting them according to the sending frequency of the wake-up command in the Pattern. In this way, the asynchronous level transition event monitored by the hardware can be converted into a quantified statistical parameter, thereby realizing the accurate measurement of the randomness of the chip response.

[0034] Meanwhile, based on a defined number of commands, the test process can identify the unique response timing characteristics of each chip and feed this parameter back to the test control logic to dynamically adjust the command sending strategy in subsequent test steps. This ensures that the ATE can perform data interaction when the chip is ready, effectively avoiding data sampling loss due to timing mismatch.

[0035] In some embodiments, executing an initial test sequence to cyclically send wake-up commands to the chip includes: powering on the chip to close the communication switch between the test device and the chip, and setting the voltage level input by the test device to the chip's transmitting end; executing the initial test sequence to cyclically send wake-up commands to the chip.

[0036] Specifically, in the process of powering on the chip to close the communication switch between the test equipment and the chip, and setting the voltage level input from the test equipment to the chip's transmitting end, the chip under test (DUT) can be started first, and a power supply voltage conforming to the specification can be applied to the chip's power pin through the power channel of the test equipment, driving the internal circuit of the chip to switch from a power-off state to a standby or ready state.

[0037] Once the chip power supply is stable, close the communication switch between the test equipment and the chip to achieve physical connection between the test equipment transmitter and the chip receiver, as well as between the test equipment receiver and the chip transmitter, thereby establishing a bidirectional signal link. The communication switch can be a relay or analog switch matrix inside the test equipment used to connect the signal channel to the chip pins.

[0038] Furthermore, this application can also configure the level voltage output by the test equipment to the chip transmitter to match the electrical interface standard of the chip. By setting the signal level parameters to logic level standards such as 1.8V, 3.3V or 5V, it can ensure that the amplitude of the signal transmitted subsequently meets the recognition threshold of the chip input pin and avoid communication errors or failures caused by level mismatch.

[0039] Furthermore, this application can also execute an initial test sequence to cyclically send wake-up commands to the chip. Specifically, this application can invoke a pre-programmed test vector (Pattern) stored in the test device memory to execute the initial test sequence to initiate communication interaction.

[0040] The testing equipment can continuously and repeatedly send specific wake-up commands to the chip through an established signal link according to preset timing logic. The wake-up command is a specific byte sequence that triggers the chip's response; for example, it can be hexadecimal 0xF8.

[0041] Meanwhile, this application sends wake-up commands to the chip in a loop, which can ensure that the test equipment continuously applies excitation signals to the chip before reaching the preset maximum number of loops or meeting specific interrupt conditions. This ensures that the chip can receive the wake-up command within any time window allowed by its internal processing logic, thereby providing sufficient time margin for subsequent capture of the chip's random response actions.

[0042] Meanwhile, the testing equipment can also maintain real-time monitoring of the chip receiver's status and record status changes during communication, laying a data foundation for subsequent statistics on the number of valid commands and analysis of response timing.

[0043] In this application, by performing power-on initialization, communication link activation, and level matching operations on the chip, the environmental determinism during the execution of the initial test sequence is established. At the same time, the electrical state and signal transmission specifications of the chip are locked within a preset working range, effectively eliminating the risk of abnormal data transmission caused by power supply fluctuations or link disconnections. This ensures that the repeatedly sent wake-up commands can be accurately identified and received by the chip, thereby ensuring the accuracy and reliability of subsequent command quantity calculation based on response timing.

[0044] In some embodiments, when obtaining the number of wake-up commands received by the chip in response to the wake-up command, the process includes: monitoring the receiver of the chip; if a start bit transition is detected at the receiver, determining that the chip is responding to the wake-up command, and obtaining the number of wake-up commands received by the chip.

[0045] Specifically, when monitoring the receiving end of the chip, this application can continuously monitor the receiving end of the chip through a test device during the process of sending wake-up commands to the chip in a loop during the execution of the initial test sequence.

[0046] In this application, the receiving end of the monitoring chip relies on the difference in voltage levels between the idle state and the data transmission state. In the UART communication protocol, the bus is usually kept at a high level when idle, while the start of data transmission must be marked by a low-level start bit.

[0047] The testing equipment, by configuring comparators or digital input channels, monitors the level changes of the receiving end pins in real time. Utilizing hardware interrupts or real-time level comparison logic, it can capture nanosecond-level level transition events, thus ensuring the real-time performance and accuracy of the monitoring. The monitoring action can coexist with the wake-up command transmission action on the timeline, and monitoring can continue throughout the entire command transmission process.

[0048] In this embodiment, if a start bit transition is detected at the receiving end, it can be determined that the chip is responding to a wake-up command, and the number of wake-up commands received by the chip can be obtained. Real-time detection based on level transitions can accurately identify the start time of the chip's response, avoiding data loss or truncation caused by blind sampling.

[0049] The start bit transition serves as a crucial physical signal for determining the chip's response state. When the chip has completed processing the previously received wake-up command and is ready to send data, its transmitting circuit actively pulls the corresponding signal line at the receiving end low, creating a falling edge from high to low. Once a start bit transition is detected, it indicates that the chip has transitioned from standby to response state, and the internal mechanism has been triggered. At this point, the execution progress of the current test sequence can be immediately locked. By reading the number of test cycles or the number of executed operation instructions recorded internally by the test equipment, the actual number of wake-up commands received by the chip before making this response can be accurately calculated.

[0050] The number of commands can characterize the chip's response latency to a command sequence of a specific length, providing a time reference for accurately capturing the data stream returned by the chip.

[0051] In some embodiments, step S210, obtaining the number of wake-up commands received by the chip when responding to the wake-up commands sent cyclically, includes: determining the number of execution lines of the initial test sequence when the chip responds to the wake-up commands sent cyclically; and determining the number of wake-up commands received by the chip based on the number of execution lines.

[0052] Specifically, during the execution of the test vector sequence, the test equipment can monitor the chip's response status to the repeatedly sent wake-up commands in real time. When a response signal from the chip is detected, the value corresponding to the test program counter or loop counter at that moment is locked and recorded as the execution line number of the initial test sequence. The process of the automated test equipment executing the test vector sequence can be implemented based on the ATE's internal hardware state machine, without relying on external instruments for observation.

[0053] In this embodiment, the test equipment can send wake-up commands to the chip line by line according to the preset test sequence. Once the chip is successfully woken up and sends a start signal by pulling the receiver level low, the hardware of the test equipment immediately captures the row number corresponding to the currently completed test cycle.

[0054] Among them, the number of execution lines can characterize the precise timing position in the interaction process between the test equipment and the chip, which can map the random response time of the chip into deterministic coordinates in the test sequence.

[0055] In this application, since the test sequence is usually designed so that each line corresponds to sending one wake-up command, or each line corresponds to a fixed sending cycle, there is a preset linear mapping relationship or a direct equality relationship between the number of commands and the number of executed lines. By reading the number of executed lines and based on this mapping relationship, the number of wake-up commands actually received and responded to by the chip can be directly obtained. This can provide a data basis for the subsequent dynamic adjustment of test parameters, enabling the test equipment to accurately grasp the response latency characteristics of the chip. Furthermore, personalized adaptation for different chips can be achieved through operations such as writing back the number of loops, effectively solving the test synchronization problem caused by the randomness of chip response timing.

[0056] S220: Based on the number of commands, send wake-up commands to the chip again in a loop, and sample and read the chip's receiver to obtain sampled data.

[0057] In this embodiment, the test equipment can reconstruct the test process by increasing the number of commands, thereby sending wake-up commands to the chip cyclically again. The number of wake-up commands sent this time strictly corresponds to the number of detected commands, ensuring that data capture is initiated at the critical moment when the chip is about to output data. Simultaneously with or immediately after sending the wake-up commands, the test equipment also performs high-speed sampling on the chip's receiving end.

[0058] Furthermore, during the sampling and reading process of the chip's receiving end, the test equipment can use an analog-to-digital converter or a digital input / output interface to record the level changes on the chip's receiving pin in real time at a preset frequency, thereby obtaining the raw data stream reflecting the chip's output signal waveform. This converts the analog or digital signal output by the chip into a digital sampling sequence that can be processed by the test equipment, thus stably capturing a complete data frame including the chip's serial number.

[0059] In some embodiments, step S220 involves sending wake-up commands to the chip again in a loop based on the number of commands, including: writing the wake-up name corresponding to the number of commands to the loop count register to generate a target test sequence; powering on the chip again and executing the target test sequence to send wake-up commands to the chip again in a loop.

[0060] In this embodiment, the loop count register can be used as a dedicated register unit in the automatic testing equipment to control the number of times the test sequence is executed in a loop. The value stored inside it can determine the number of times the subsequent test vector loops are iterated.

[0061] Specifically, this application generates the target test sequence by writing the wake-up name corresponding to the number of commands into the loop count register. In this case, the target test sequence is not a fixed test procedure, but rather an execution logic specifically tailored to the response characteristics of the chip under test. This ensures that the test equipment sends the final wake-up command at the critical moment when the chip is about to respond, thereby accurately triggering the chip's data output action.

[0062] Meanwhile, after completing the statistics of the number of chip response commands, this application can write the calculated command count value into the loop count register through the program interface of the test device. As the loop count register is updated, the original initial test sequence is reconfigured into the target test sequence, and the loop termination condition of the target test sequence is set to the new command count. This allows the test device to accurately stop sending at the boundary where the chip is ready to respond, creating the best time window for subsequent data capture.

[0063] It should be noted that after the target test sequence is generated, its internal logic structure remains unchanged, and only the total number of loop executions is customized for the specific chip.

[0064] Furthermore, this application can power on the chip again to reset the chip's internal state, ensuring that the chip is in a known initial ready state and eliminating the influence of register states or cached data that may have been left over from the previous test.

[0065] Based on this, the execution of the target test sequence utilizes dynamically configured loop counts to precisely control the sending rhythm of wake-up commands, enabling precise synchronization between the sending timing of the test equipment and the internal response logic of the chip.

[0066] Specifically, this application can first control the power module to power off the chip and then power it back on. After the chip power supply stabilizes, the generated target test sequence steps are then called and executed.

[0067] During execution, the total number of wake-up commands sent to the chip can be strictly controlled according to the value set in the loop count register. This ensures that after sending a specified number of wake-up commands, the data reception or sampling stage is entered immediately. This enables the test equipment to adapt to the response latency differences of different individual chips and achieve precise timing alignment in batch testing without manual intervention. It effectively solves the problem of data capture failure caused by random response timing in asynchronous communication and ensures high reliability and automated testing efficiency for chip serial number reading in a mass production environment.

[0068] In some embodiments, step S220, sampling and reading the receiving end of the chip to obtain sampled data, includes: if the test device and the chip communicate using the UART communication protocol, determining the sampling rate of the receiving end of the chip according to the baud rate of the UART communication protocol; and sampling and reading the receiving end of the chip based on the sampling rate to obtain sampled data.

[0069] In this embodiment, when the test equipment establishes a communication connection with the chip under test, a general heterogeneous UART communication protocol can be used for communication, and the sampling rate of the receiving end is set according to the baud rate of the UART communication protocol. The baud rate characterizes the number of symbols transmitted per second and can serve as a key indicator for measuring data transmission rate.

[0070] Because asynchronous communication mechanisms lack a shared clock signal, clock frequency deviations or phase drifts may exist between the transmitter and receiver, causing jitter at data bit boundaries. To overcome timing uncertainties, the sampling rate must be set significantly higher than the communication baud rate. For example, the sampling rate can be configured as an integer multiple of the baud rate (such as 4 times or higher).

[0071] Specifically, this application determines the sampling rate of the chip's receiver based on the baud rate of the UART communication protocol, which can ensure that multiple discrete data points can be collected within the continuous period of each data bit. This provides a time resolution guarantee for subsequent precise positioning of data bit boundaries through algorithms and elimination of the risk of misjudgment caused by sampling points falling near signal transition edges.

[0072] Furthermore, this application can sample and read the receiving end of the chip based on the sampling rate to perform periodic detection and recording of the level state of the chip's receiving pin, thereby obtaining sampled data.

[0073] Specifically, this application can be completed by the hardware capture module inside the test equipment under clock drive. Taking a sampling rate of 4 times the baud rate as an example, within the time window of a single standard UART data bit, 4 consecutive level sampling points can be acquired, so that the raw data stream completely maps the trajectory of the received signal in the time domain, which can cover the falling edge transition of the start bit, the level holding state of the data bit, and the rising edge recovery characteristics of the stop bit.

[0074] In this application, by improving the time resolution to capture complete signal waveform details, the signal distortion problem caused by clock asynchrony in asynchronous communication is effectively suppressed, thereby ensuring the integrity and accuracy of the sampled data and providing reliable data support for subsequent accurate analysis of chip serial numbers.

[0075] S230. Perform alignment and parsing processing on the sampled data to obtain the chip serial number.

[0076] Specifically, during the alignment and parsing process of the sampled data, this application can perform signal reconstruction and decoding to identify the start bit, stop bit, and boundaries of each data bit in the data frame. Simultaneously, by analyzing the level transition characteristics of the sampled data, the center position of each data bit can be determined, eliminating phase shifts caused by asynchronous communication clock deviations or signal jitter.

[0077] Meanwhile, this application can map continuous sampling points to corresponding binary bits, and assemble the binary bits into bytes according to the frame format specified by the communication protocol (such as data bit length, check bit, etc.) to extract the field representing the identity identifier from the parsed byte stream, that is, to obtain the chip serial number, ensuring that even if there is noise or timing jitter in the signal, the original information sent by the chip can be accurately restored.

[0078] In some embodiments, step S230 involves performing alignment and parsing processing on the sampled data to obtain the chip serial number, including: determining the number of samples in the data frames within the sampled data and the level information of the sampled data; and performing alignment and parsing processing on each data frame within the sampled data according to the number of samples and the level information to obtain the chip serial number.

[0079] In this embodiment, after acquiring the sampling data from the chip receiver (RX), the sampling data is presented as a continuous bit stream containing multiple complete UART data frames. In order to achieve accurate parsing of subsequent data, it is necessary to first determine the number of data frames sampled within the sampling data and the level information of the sampling data.

[0080] In this context, a data frame can serve as a complete transmission unit in the UART communication protocol, consisting of a structured sequence of 1 start bit, 8 data bits, and 1 stop bit. The number of samples represents the number of sampling points occupied by a single data frame or a single data bit during oversampling, and its value directly reflects the relative phase relationship between the sampling clock and the data clock. The level information can be understood as the high or low level state (such as logic 1 or logic 0) corresponding to each sampling point, forming the original basis for reconstructing the data content.

[0081] Specifically, in determining the number of samples and the level information of the data frames within the sampled data, this application can be executed by a test device or processor. The starting bit is located by scanning the transition edges in the sampled data stream, and the sampling point density after the starting bit is counted to obtain the number of samples. This can provide the necessary parameter input for the subsequent alignment algorithm, thereby achieving accurate positioning and measurement of asynchronous data frames.

[0082] For example, when using a sampling rate four times the baud rate, ideally each standard data bit should contain four sampling points; however, in practical applications, due to clock drift, the number of samples may fluctuate between three or four.

[0083] Furthermore, after determining the number of data frames and the level information of the sampled data, each data frame in the sampled data can be aligned and parsed according to the number of samples and the level information to obtain the chip serial number. This can solve the bit boundary jitter problem caused by the asynchrony between the sampling clock and the data clock. At the same time, by dynamically adjusting the parsing window, a clear and accurate bit sequence can be reconstructed from the ambiguous sampling points.

[0084] Specifically, this application can determine the actual width and boundary position of the current data bit based on the distribution pattern of sampling points at different level widths, and then slide the parsing window to extract valid data bits accordingly.

[0085] For common bit offset situations, the following logic can be used for judgment and compensation: When the bit width is normal (i.e., containing 4 sampling points) and the data is 0 or 1, the parsing window can be moved forward by 4 bits; when the current bit width is too small (i.e., containing 3 sampling points) and the next bit data is reversed, the parsing window can be moved forward by 3 bits; when the previous bit width is too large, the data is reversed, and the current bit width is too small (the total width after compensation is 4 bits), the parsing window can be moved forward by 4 bits.

[0086] It should be noted that if an abnormal situation occurs that does not conform to the preset distribution characteristics, it will be judged as a frame error or noise interference, the parsing of the current frame will be terminated and the abnormal state will be recorded to prevent erroneous data from polluting the final result.

[0087] In this application, by performing alignment parsing processing on each data frame, interference caused by clock jitter can be effectively filtered out, the 8-bit valid data inside the data frame can be accurately restored, the start bit and stop bit can be removed, the continuous data frames can be spliced ​​and converted into a byte sequence, and finally the chip serial number of the chip can be obtained. This ensures that the chip identification information can be stably and completely extracted from the original sampled waveform in an asynchronous communication environment, providing a reliable data foundation for subsequent verification steps.

[0088] Meanwhile, by analyzing the number of samples and level information of data frames within the sampled data, a precise mapping relationship from the original waveform to digital symbols was constructed, overcoming the limitations of the traditional fixed-period sampling method in asynchronous communication scenarios. This enables the test equipment to adapt to the response timing differences of different chips, significantly improving the robustness of decoding and the accuracy of data acquisition.

[0089] In some embodiments, the chip serial number of the chip is obtained by performing alignment and parsing processing on each data frame in the sampled data according to the number of samples and level information. This includes: performing alignment and parsing processing on each data frame in the sampled data according to the number of samples and level information to obtain multiple frames of data; extracting multiple bytes from the multiple frames of data and combining the multiple bytes to obtain a byte array; and converting the byte array to obtain the chip serial number of the chip.

[0090] In this embodiment, the multi-frame data is not a simple set of raw sampling points, but a structured sequence that represents independent communication units after alignment and calibration. Its internal logic strictly corresponds to the frame format of the UART communication protocol.

[0091] Under the UART protocol standard, each complete data frame consists of 1 start bit (low level), 8 data bits, 1 parity bit, and 1 stop bit (high level). The sampling number can refer to the number of sample points obtained by oversampling each data bit (e.g., 4x oversampling), while the level information represents the logic level state (high level or low level) corresponding to each sample point.

[0092] Specifically, this application summarizes the process of aligning and parsing each data frame in the sampled data according to the number of samples and level information to obtain multiple frames of data. First, the starting boundary of the frame can be located based on the low level feature of the start bit. Then, the subsequent sampling point sequence is extracted in sequence according to the preset number of samples. Next, the ending boundary of the frame is checked using the high level feature of the stop bit, so as to transform the timing waveform that is originally difficult to read directly into a set of data frames with clear semantics.

[0093] Furthermore, after obtaining multiple frames of data, multiple bytes can be extracted from the multiple frames of data and combined to obtain a byte array.

[0094] Specifically, this application can extract the payload portion from each frame of structured multi-frame data. Furthermore, according to the frame structure definition of the UART communication protocol, the payload is the 8 data bits located between the start and stop bits. Each parsed data frame is traversed, the start bit at the beginning and the stop bit at the end are identified and removed, retaining the continuous 8-bit data bit sequence in the middle.

[0095] Each reserved 8-bit sequence can be regarded as an independent byte unit. This byte serves as the smallest addressable unit for data storage and transmission, representing the encoded information actually sent by the chip.

[0096] Furthermore, this application can linearly combine multiple extracted bytes according to the receiving order of the data frame on the timeline to generate a continuous byte array. Specifically, this application can use the first byte as the first element of the array, the second byte as the second element, and so on, according to the parsed order, until all valid bytes are stored, ultimately forming a logically continuous memory data structure to completely preserve the timing characteristics of the chip's transmitted sequence number and ensure that the integrity of the data stream is not compromised.

[0097] Furthermore, after obtaining the byte array, this application can convert the byte array to obtain the chip serial number.

[0098] Specifically, this application can perform the final conversion from binary data to a readable identifier. A byte array can consist of a set of binary values, and chip serial numbers are typically represented in a specific string format (such as hexadecimal strings or ASCII encoded strings). Therefore, it is necessary to map each byte element in the byte array to its corresponding character representation, thereby elevating the binary bitstream transmitted by the underlying hardware into a unique chip identifier with business logic attributes. This provides a directly usable information carrier for subsequent authentication and data recording.

[0099] If the chip serial number is stored in hexadecimal format, each byte is converted into two corresponding hexadecimal characters (e.g., byte 0xAB is converted into string AB); if it is stored in ASCII code, the corresponding ASCII character is directly looked up based on the byte value.

[0100] After the byte array conversion is complete, characters can be concatenated to obtain the final chip serial number string.

[0101] S240. Verify the chip serial number to obtain the chip serial number verification information.

[0102] Specifically, in the process of verifying the chip serial number, this application can compare the parsed chip serial number with a preset standard format, legal range or records in the database, thereby eliminating invalid serial numbers caused by communication errors, chip defects or data corruption, ensuring the accuracy and reliability of the test results, and thus completing the full test of the chip data reading function.

[0103] Verifying the chip serial number can involve checking whether the serial number length conforms to the specifications, whether the check digit is correct, or whether the serial number belongs to the set of allocated valid serial numbers.

[0104] As an example, this application can write the chip serial number into the datalog and determine whether the chip serial number is within a preset legal range. If it exceeds the range, it is judged as FAIL. Finally, the chip is powered off to end the reading and verification of the chip serial number.

[0105] Verification information can indicate whether the chip serial number has passed verification. It can be in the form of a Boolean value (success / failure) or descriptive data containing error codes or detailed verification results.

[0106] In this application, the number of commands required for the chip to respond is detected by sending wake-up commands in the initial loop. This number is then used as a precise trigger condition to synchronously initiate sampling during the second loop, effectively solving the data capture problem caused by the uncertain response timing in asynchronous communication. Furthermore, by combining alignment and parsing processing of the sampled data, the chip serial number can be accurately reconstructed from the high-speed sampled waveform. A verification process ensures the authenticity of the data. The entire process achieves automated and batch testing of chip data reading, significantly improving testing efficiency and data acquisition stability.

[0107] In the chip data reading test method provided in this application embodiment, the number of wake-up commands sent by the chip in response loop is obtained, and the wake-up command is sent again in loop according to the number of commands. At a precise moment, the receiving end is sampled at high speed to obtain sampled data. This allows the test equipment to actively adapt to the response delay differences of different chips, thereby starting data acquisition at the critical moment when the chip is about to respond. The sampled data is aligned and parsed using the sampling quantity and level information to restore the chip serial number, and finally the chip serial number is verified to obtain verification information. This effectively overcomes the bit boundary jitter problem caused by clock asynchrony in asynchronous communication, achieves accurate alignment and complete restoration of data frames, and performs conversion and legality verification on the parsed byte array to ensure that the final output chip serial number is accurate. This effectively solves the problem that the automatic test equipment cannot stably and batch capture chip SN data due to the uncertainty of UART response timing, avoids data loss or parsing errors caused by missing the data start point, and significantly improves the data capture stability, parsing accuracy and overall automated test efficiency in the chip mass production test process.

[0108] In some embodiments, this application also provides a chip data reading test apparatus 300, which is used to perform any embodiment of the aforementioned chip data reading test method.

[0109] For details, please refer to Figure 3 , Figure 3 This is a schematic block diagram of the chip data reading and testing device 300 provided in the embodiments of this application.

[0110] like Figure 3 As shown, the chip data reading and testing device 300 provided in this application includes: an acquisition unit 310, a sampling unit 320, an alignment and parsing unit 330, and a verification unit 340.

[0111] The acquisition unit 310 is used to acquire the number of wake-up commands received by the chip when responding to the wake-up commands sent in a loop; the sampling unit 320 is used to send wake-up commands to the chip again in a loop based on the number of commands, and to sample and read the chip's receiving end to obtain sampled data; the alignment and parsing unit 330 is used to perform alignment and parsing processing on the sampled data to obtain the chip serial number; and the verification unit 340 is used to verify the chip serial number to obtain the verification information of the chip serial number.

[0112] The chip data reading test device 300 provided in this application embodiment can obtain the number of wake-up commands received by the chip when responding to the wake-up commands sent in a loop; based on the number of commands, send wake-up commands to the chip again in a loop, and sample and read the chip's receiving end to obtain sampled data; perform alignment and parsing processing on the sampled data to obtain the chip serial number; and verify the chip serial number to obtain the chip serial number verification information.

[0113] It should be noted that those skilled in the art can clearly understand that the specific implementation process of the chip data reading and testing device and each unit can be referred to the corresponding description in the foregoing method embodiments. For the sake of convenience and brevity, it will not be repeated here.

[0114] In some embodiments, the chip data reading and testing apparatus can be implemented as a computer program, which can perform tasks such as... Figure 4 It runs on the electronic device shown.

[0115] Please see Figure 4 , Figure 4 This is a schematic block diagram of the electronic device provided in the embodiments of this application.

[0116] See Figure 4 The device 400 includes a processor 402, a memory, and a network interface 405 connected via a system bus 401, wherein the memory may include a storage medium 403 and internal memory 404.

[0117] The storage medium 403 can store the operating system 4031 and the computer program 4032. When the computer program 4032 is executed, it enables the processor 402 to perform a chip data reading test method.

[0118] The processor 402 provides computing and control capabilities to support the operation of the entire device 400.

[0119] The internal memory 404 provides an environment for the operation of the computer program 4032 in the non-volatile storage medium 403. When the computer program 4032 is executed by the processor 402, the processor 402 can execute a chip data reading test method.

[0120] This network interface 405 is used for network communication, such as providing the transmission of definition information. Those skilled in the art will understand that... Figure 4 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the device 400 to which the present application is applied. The specific device 400 may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0121] The processor 402 is used to run the computer program 4032 stored in the memory to perform the following functions: obtain the number of wake-up commands received by the chip when responding to the wake-up commands sent in a loop; based on the number of commands, send wake-up commands to the chip again in a loop, and sample and read the chip's receiving end to obtain sampled data; perform alignment and parsing processing on the sampled data to obtain the chip serial number; and verify the chip serial number to obtain the chip serial number verification information.

[0122] Those skilled in the art will understand that Figure 4 The embodiments of device 400 shown do not constitute a limitation on the specific configuration of device 400. In other embodiments, device 400 may include more or fewer components than shown, or combine certain components, or have different component arrangements. For example, in some embodiments, device 400 may include only memory and processor 402. In such embodiments, the structure and function of memory and processor 402 are similar to those shown. Figure 4 The embodiments shown are consistent and will not be described again here.

[0123] It should be understood that in the embodiments of this application, the processor 402 may be a central processing unit (CPU), or it may be other general-purpose processors 402, digital signal processors 402 (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor 402 may be a microprocessor 402, or it may be any conventional processor 402, etc.

[0124] According to one aspect of this application, a computer program product or computer program is also provided, comprising computer instructions stored in a computer-readable storage medium. A processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform the following steps: obtaining the number of wake-up commands received by the chip in response to cyclically sent wake-up commands; based on the number of commands, cyclically sending wake-up commands to the chip again and sampling the chip's receiving end to obtain sampled data; performing alignment and parsing processing on the sampled data to obtain the chip serial number; and verifying the chip serial number to obtain verification information for the chip serial number.

[0125] It will be understood by those skilled in the art that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program includes program instructions and can be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the process steps of the embodiments of the above methods.

[0126] In another embodiment of this application, a computer storage medium is provided. This storage medium can be a non-volatile computer-readable storage medium or a volatile storage medium. The storage medium stores a computer program 4032, which, when executed by a processor 402, performs the following steps: obtaining the number of wake-up commands received by the chip in response to cyclically sent wake-up commands; based on the number of commands, cyclically sending wake-up commands to the chip again, and sampling and reading the chip's receiving end to obtain sampled data; performing alignment and parsing processing on the sampled data to obtain the chip serial number; and verifying the chip serial number to obtain verification information for the chip serial number.

[0127] The storage medium can be any computer-readable storage medium that can store program code, such as a USB flash drive, external hard drive, read-only memory (ROM), magnetic disk, or optical disk.

[0128] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0129] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of each unit is merely a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0130] The steps in the methods of this application embodiment can be adjusted, merged, or deleted according to actual needs. The units in the apparatus of this application embodiment can be merged, divided, or deleted according to actual needs. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0131] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a personal computer, a terminal, or a network device, etc.) to execute all or part of the steps of the methods provided in the various embodiments of this application.

[0132] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and such modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for reading and testing chip data, characterized in that, include: The number of wake-up commands received by the chip when it receives the wake-up commands sent in a loop. Based on the number of commands, the wake-up command is sent to the chip again in a loop, and the receiving end of the chip is sampled and read to obtain sampled data; The sampled data is aligned and parsed to obtain the chip serial number of the chip; The chip serial number is verified to obtain verification information for the chip serial number.

2. The chip data reading and testing method according to claim 1, characterized in that, When the chip receives the wake-up command sent cyclically in response to the chip, the number of wake-up commands received by the chip includes: Execute an initial test sequence to cyclically send the wake-up command to the chip; The number of commands received by the chip when it responds to the wake-up command is obtained.

3. The chip data reading and testing method according to claim 2, characterized in that, The execution of the initial test sequence to cyclically send the wake-up command to the chip includes: Power on the chip to close the communication switch between the test device and the chip, and set the voltage level input from the test device to the transmitting end of the chip; An initial test sequence is executed to cyclically send the wake-up command to the chip.

4. The chip data reading and testing method according to claim 2, characterized in that, When the chip responds to the wake-up command, the number of commands the chip receives includes: Monitor the receiving end of the chip; If a start bit transition is detected at the receiving end, it is determined that the chip is responding to the wake-up command, and the number of commands received by the chip from the wake-up command is obtained.

5. The chip data reading and testing method according to claim 2, characterized in that, When the chip receives the wake-up command sent cyclically in response to the chip, the number of wake-up commands received by the chip includes: The number of execution lines of the initial test sequence is determined when the chip responds to the wake-up command sent cyclically; Based on the number of execution lines, determine the number of commands the chip receives from the wake-up command.

6. The chip data reading test method according to any one of claims 1-5, characterized in that, The step of sending the wake-up command to the chip again in a loop based on the number of commands includes: Write the wake-up name corresponding to the number of commands to the loop count register to generate the target test sequence; The chip is powered on again, and the target test sequence is executed to send the wake-up command to the chip again in a loop.

7. The chip data reading test method according to any one of claims 1-5, characterized in that, The step of sampling and reading the data at the receiving end of the chip to obtain sampled data includes: If the test equipment and the chip communicate using the UART communication protocol, the sampling rate of the chip's receiving end is determined according to the baud rate of the UART communication protocol. Based on the sampling rate, the receiving end of the chip is sampled and read to obtain the sampled data.

8. The chip data reading test method according to any one of claims 1-5, characterized in that, The step of performing alignment and parsing processing on the sampled data to obtain the chip serial number includes: Determine the number of data frames sampled within the sampled data and the level information of the sampled data; Based on the sampling quantity and the level information, each data frame within the sampled data is aligned and parsed to obtain the chip serial number of the chip.

9. The chip data reading and testing method according to claim 8, characterized in that, The step of performing alignment and parsing processing on each data frame within the sampled data according to the sampling quantity and the level information to obtain the chip serial number of the chip includes: Based on the number of samples and the level information, each data frame in the sampled data is aligned and parsed to obtain multiple frames of data. Multiple bytes are extracted from the multi-frame data, and the multiple bytes are combined to obtain a byte array; The byte array is converted to obtain the chip serial number of the chip.

10. An electronic device, characterized in that, The device includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the chip data reading and testing method according to any one of claims 1 to 9.

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