A relay driving chip testing device and chip testing method for an electric energy meter

Abstract

The present application relates to the technical field of test tool, and relates to a relay driving chip testing device for electric energy meter and a chip testing method.The testing device comprises a testing mainboard, an adapter card and a relay, wherein the testing mainboard is provided with a hot plug interface and a testing circuit.The one end of the adapter card is electrically connected with the relay driving chip, and the other end is plug-in electrically connected with the hot plug interface.The pins of the adapter card are provided with fixed physical position arrangement and network protocol function, and are one-to-one mapped with the hot plug interface.The decoupling design of the testing mainboard and the adapter card not only realizes the high integration of testing power supply, control, communication and data storage, but also realizes the high compatible and rapid testing by only replacing the adapter card with the corresponding chip patch board at low cost when testing chips with different packaging models or pin definitions, which significantly reduces the tool development cost, shortens the verification period and greatly improves the testing efficiency.

Description

Technical Field

[0001] This invention relates to the field of testing tooling technology, and in particular to a testing device and method for a relay driver chip for an electricity meter. Background Technology

[0002] Relay driver chips are key components in various smart meters (including single-phase and three-phase meters) used for strong and weak current isolation and controlling the internal magnetic latching relay to achieve the opening and closing of user circuits. With the development of smart grids and the accelerated pace of domestic chip substitution, various models and package types (such as the common SOP8, DIP8, and SOT23) of small meter relay driver chips have emerged on the market. The pin definitions and distribution methods of different IC design and manufacturing manufacturers are not entirely the same. In the early stages of R&D performance parameter testing, large-scale advanced incoming material inspection (IQC alignment), or production batch testing, the traditional approach is to develop a separate, complete test board (jig board) for each type or package of driver chip. However, due to the customization of test boards caused by differences in driver chip models, adopting the traditional "one type, one board" design approach clearly presents the following technical problems: 1. Long test board development cycle: Each test for a new model requires redesigning, prototyping, and soldering and debugging complex peripheral circuit components (such as communication modules and isolation power supplies). 2. Wasteful use of test resources: The main chip MCU, communication components, and peripheral power supply configurations should be highly consistent and reusable for most chip models. Redevelopment not only brings redundant management costs but also increases the hardware cost per board production. 3. Low test operation efficiency: When it is necessary to conduct comparative tests on chips from different manufacturers (e.g., during the replacement selection process), testers are forced to repeatedly plug and unplug different motherboards and connect complex test harnesses. This cumbersome operation has a low error tolerance, which severely delays the efficiency of inspection and verification. Summary of the Invention

[0003] To address the technical problems of long development cycles, wasted testing team members, and low testing efficiency in existing single-board testing solutions for testing different types of driver chips, this invention provides a relay driver chip testing device and chip testing method for electricity meters.

[0004] This invention is achieved through the following technical solution: In a first aspect, the present invention provides a relay driver chip testing device, comprising: a test motherboard, several adapter cards, and a relay. The test motherboard is equipped with a hot-swappable interface. The hot-swappable interface is configured as a multi-pin physical slot port. The test motherboard is equipped with a test circuit electrically connected to the hot-swappable interface and used for testing the performance of the relay driver chip. One end of each adapter card is electrically connected to the relay driver chip, and the other end is pluggably electrically connected to the hot-swappable interface. The pins of each adapter card are configured with fixed physical positions and network protocol functions, and are mapped one-to-one with the hot-swappable interface. The adapter cards are used to force different types of relay driver chips to switch routes through the wiring between their pins and the relay driver chip. The relay is configured to change its opening and closing state under the control of the relay driver chip.

[0005] Secondly, the present invention proposes a method for testing relay driver chips, which uses the relay driver chip testing device described in the first aspect. This testing method includes: First, install relay driver chips with different package types or pin definitions onto the corresponding adapter cards. Then, plug the adapter cards into the hot-swappable interface to test the relay driver chips. When testing different relay driver chips, only replace the adapter card on the test motherboard that contains the corresponding relay driver chip.

[0006] The beneficial effects of this invention are as follows: 1. This invention, through the decoupled design of the test motherboard and the adapter card, not only achieves a high degree of integration of test power supply, control, communication and data storage, but also enables highly compatible and rapid testing when testing chips with different package types or pin definitions by simply replacing the adapter card with the corresponding chip surface mount board at low cost. This significantly reduces fixture development costs, shortens the verification cycle and greatly improves testing efficiency.

[0007] 2. This invention overturns the traditional development model of single-unit assembly fixtures. By introducing a binary hardware topology assembly structure of "rich large motherboard basic platform + passive low-cost small adapter card", it successfully gathers and settles all complex, time-consuming and costly public testing resources on the motherboard side for unified lifelong management.

[0008] 3. This invention decouples the hardware requirements that are frequently changing, highly iterative, and low-cost, requiring only short-circuiting of different pins, and transfers them to a palm-sized adapter card. This significantly reduces the development time and complexity of the new product testing toolchain from the development introduction (NPI) stage to the production and shipment stage. It truly achieves the effect of completing the hardware environment switching in seconds with just two seconds of "card swapping" for testing different types of relay driver chips. This results in a qualitative leap in the overall compatibility of the new component introduction testing system and also greatly reduces the long-term material consumable wear and reconstruction costs of factory testing and inspection. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a system block diagram of a relay driver chip testing device; Figure 2 This is a schematic diagram of the relay driver chip testing device in use; Figure 3 This is a schematic diagram of the network connection points for the hot-swappable interface acquisition end; Figure 4 This is a waveform diagram of inputs A and B sent by the main control chip to the relay-driven chuck.

[0011] In the diagram: Test motherboard 1, hot-swappable interface 11, adapter card 2, baseboard 21, chip package socket 22, connector pin header 23. Detailed Implementation

[0012] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0013] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0014] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0015] This embodiment provides a relay driver chip testing device, which mainly includes two levels of decoupled components: a general-purpose test motherboard 1 and a flexibly replaceable adapter card 2, as well as a relay for verifying test results. In this embodiment, the testing device is used to test the relay driver chip in an electricity meter. Please refer to... Figure 1 The following is a detailed introduction to these three components: 1. Testing the motherboard.

[0016] This test motherboard 1 serves as a unified underlying test platform, housing all highly reusable peripheral fixed hardware and test circuits. It highly integrates the common functions and interfaces required for testing, including but not limited to: (1) MCU Main Control Chip. The main control chip acts as the brain unit, coordinating the overall test timing, real-time digital / analog data acquisition, and pin logic level judgment. Specifically, this main control chip outputs pulse drive signals to the relay driver chip and statistically analyzes the test data of the relay driver chip. The pulse drive signal is sent to the relay driver chip according to a preset frequency and duty cycle. The main control chip model can be a commonly used chip model in existing smart meters.

[0017] (2) Storage Unit. The storage unit is connected to the main control chip and is used to store the test data of the relay driver chip. This storage unit can use EEPROM or SPI Flash, and can safely store the unique parameter tolerance thresholds, test formula cases, and historical test error code records of the relay driver chip under test in a power-loss protected manner.

[0018] (3) Communication Unit. The communication unit can use an RS485 communication chip to undertake standard industrial-grade remote serial communication protocol transmission and reception tasks. One end of the communication unit is connected to the UART interface of the main control chip, and the other end is connected to an external host computer through a terminal block. The main control chip can upload the test data and current test status of the relay driver chip to the host computer through the communication unit.

[0019] (4) Power Supply Unit. The power supply unit provides operating power to the main control chip, storage unit, and communication unit. It is responsible for connecting external industrial test power supplies (such as 12V, 24V, etc.), voltage regulation and buffering, and smoothing multi-channel LDO step-down. In this embodiment, the input terminal of the power supply unit is connected to an external 24V DC power supply, and the output terminal is connected to the power supply terminals of the main control chip, storage unit, and communication unit, respectively, and converts the 24V DC power to 5V DC power.

[0020] (5) Hot-swappable interface 11. The hot-swappable interface 11 is configured as a multi-pin physical slot port and is electrically connected to the main control chip.

[0021] II. Adapter Card 2.

[0022] In this embodiment, the adapter card 2 serves as a passive physical wiring routing consumable, which is inexpensive and easy to print and issue individually on a large scale. For example... Figure 2 As shown, the adapter card 2 includes: a substrate 21, a chip package socket 22, and a connector pin header 23. The chip package socket 22 is disposed on the substrate 21 and is used to fix and electrically connect the relay driver chip. It can be a test socket spring holder or the relay driver chip can be directly soldered through surface mount pads. The connector pin header 23 is fixed at the edge of the substrate 21, with one end electrically connected to the chip package socket 22 and the other end electrically connected to the hot-swappable interface 11. It is worth mentioning that one of the key innovations of this invention is the forced normalization of the pin signals of the relay driver chip. Specifically, the diverse relay driver chips all have essential basic circuit pins with strong commonality, including: positive power supply pin (VCC), ground pin (GND), first input control pin (IA), second input control pin (IB), first output drive pin (OA), second output drive pin (OB), and current limiting control pin (RLIM). Based on these essential basic circuit pins, such as Figure 3As shown, the acquisition network of the hot-swappable interface 11 is equipped with connection points for connecting to the pins of the aforementioned basic circuit. For example, point P1 of the hot-swappable interface 11 is the VCC terminal, point P2 is the GND terminal, and point P3 is the IA terminal, etc. Meanwhile, the pins of the connector header 23 have fixed physical position arrangements and network protocol functions. All pins on the connector header 23 are spatially defined to fixed position numbers, corresponding one-to-one with the acquisition network points of the hot-swappable interface 11. That is, if point P1 of the hot-swappable interface 11 is the VCC terminal, then point P1 of the connector header 23 is also the VCC terminal. Regarding the connection between the adapter card 2 and the relay driver chip, since the adapter card 2 is a custom design for the relay driver chip, its surface mount pads are directly connected to the pins of the relay driver chip. The routing of the surface mount pads and the connector header 23 is designed according to the actual pin positions of the relay driver chip, ensuring that the pins of the relay driver chip are connected to the corresponding points of the hot-swappable interface 11. For example, if the P1 pin of the relay driver chip is GND and the P2 pin is VCC, and the P1 pin of the hot-swappable interface 11 is VCC and the P2 pin is GND, then the P1 pin of the corresponding connector pin 23 is also VCC and the P2 pin is GND. In this case, the surface mount pad of the adapter connects the P1 pin of the relay driver chip to the P2 pin of the connector pin 23 through the trace, thereby realizing the forced connection of the pin signals of the relay driver chip. This allows the adapter card 2 to force the routing change regardless of how the chip manufacturer places the pin positions of the relay driver chip in different package forms such as SOT23 and SOP8.

[0023] III. Relays.

[0024] The relay is electrically connected to the relay driver chip via an external interface. Specifically, a magnetic latching relay can be used. The external interface is located on the test motherboard 1, with one end electrically connected to the adapter card 2 and the other end electrically connected to the relay. The relay is configured to change its opening and closing state under the control of the relay driver chip. The purpose of setting up the relay is to use a real magnetic latching relay as a dynamic physical inductive load in daily testing and extreme evaluation under real operating conditions (similar to the aging screening environment stage) to test whether the relay driver chip can smoothly pull the actual pull-in resistance. At this time, the external 24V DC power supply is directly transmitted to the adapter card 2 through the hot-swappable interface 11 as the relay driving voltage. The main control chip sends pulse drive signals to the relay driver chip according to a preset frequency and duty cycle. The relay driver chip controls the relay to continuously open and close based on the pulse drive signals. The main control chip counts the number of times the relay opens and closes and uploads the number of relay opening and closing to the host computer through the communication unit. The storage unit records the number of times the relay driven by the pulse drive signals opens and closes.

[0025] The working principle of this invention is as follows: When the adapter card 2, equipped with a relay driver chip, is plugged into the hot-swappable interface 11, the main control chip sends a pulse drive signal to the relay driver chip according to a preset frequency and duty cycle. The waveform of the pulse drive signal is as follows: Figure 4 As shown, the signal includes two different phase high and low level signals, input A and input B. After receiving the pulse drive signal, the relay driver chip generates a corresponding control signal to control the relay's opening and closing. Upon receiving the control signal, the relay activates and sends a status word, which is transmitted to the main control chip via status A and status B signals. The main control chip analyzes the status word to determine whether the relay is in a closed or open state. Specifically, when the relay driver chip receives alternating high and low level signals, it generates a corresponding opening or closing action. The number of times the relay opens and closes can be used to determine whether the relay driver chip meets the test standards. The host computer can display the number of successful openings, failed openings, successful closings, and failed closings.

[0026] In another embodiment, the relay driver chip testing device also includes a housing. This housing covers and encloses the test motherboard 1 and adapter card 2, aiming to achieve moisture-proof isolation of the internal components and to provide a high / low temperature testing environment. Specifically, the housing has an access port corresponding to the hot-swappable interface 11. A transparent cover is hinged inside the access port. A quick-locking latch is provided on the other side of the cover. Furthermore, the edge of the cover is provided with a sealing ring that fits snugly against the access port, such as a high / low temperature resistant silicone sealing ring. When the latch is locked to close the cover, the sealing ring is pressed tightly against the edge of the access port, achieving moisture-proof isolation and sealing of the interior of the housing. When the relay driver chip needs to be tested in a high / low temperature environment, a heater or cooler can be directly installed inside the housing to regulate the internal temperature. Combined with the quick-opening design of the transparent cover, rapid chip replacement is possible, greatly improving the efficiency of multi-chip testing in complex environments.

[0027] In summary, the relay driver chip testing device provided by this invention not only achieves a high degree of integration of power supply, control, communication, and data storage, but also, through a unified motherboard physical interface design, enables highly compatible and rapid testing of chips with different package types or pin definitions by simply replacing the adapter card 2 with the corresponding chip surface mount board at low cost. This significantly reduces fixture development costs, shortens the verification cycle, and greatly improves testing efficiency. Furthermore, the housing design allows for testing in high and low temperature environments, and the quick-opening transparent cover enables rapid chip replacement, greatly improving the efficiency of multi-chip testing in complex environments.

[0028] In another embodiment, a method for testing a relay driver chip is also proposed, which uses the relay driver chip testing device described in the above embodiment to test the relay driver chip. The relay driver chip testing method includes the following steps: First, relay driver chips with different package types or pin definitions are installed on corresponding adapter cards 2. Then, adapter cards 2 are plugged into hot-swappable interface 11 to test the relay driver chips. When testing different relay driver chips, only the adapter card 2 with the corresponding relay driver chip on the test motherboard 1 needs to be replaced. In this way, when testing relay driver chips with different package types or pin definitions, only the adapter card 2 with the corresponding chip surface mount board needs to be replaced at low cost to achieve highly compatible and rapid testing, significantly reducing fixture development costs, shortening the verification cycle, and greatly improving testing efficiency.

[0029] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0030] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A relay driver chip testing device, characterized in that, It includes: The test motherboard is equipped with a hot-swappable interface; the hot-swappable interface is configured as a multi-pin physical slot port; the test motherboard is equipped with a test circuit that is electrically connected to the hot-swappable interface and is used to test the performance of the relay driver chip. Several adapter cards, one end of which is electrically connected to a relay driver chip, and the other end is pluggable electrically connected to a hot-swappable interface; wherein, the pins of the several adapter cards are provided with fixed physical position arrangement and network protocol functions, and are mapped one-to-one with the hot-swappable interface; the adapter cards are used to force different types of relay driver chips to switch routes through the wiring between their pins and the relay driver chip. A relay is configured to change its opening and closing state under the control of a relay driver chip.

2. The relay driver chip testing device according to claim 1, characterized in that, The test circuit includes: The main control chip is used to output pulse drive signals to the relay driver chip and to count the number of times the relays open and close. A storage unit for storing the number of times the relay is opened and closed by the pulse drive signal; The power supply unit is used to provide operating power to the main control chip and the storage unit.

3. The relay driver chip testing device according to claim 2, characterized in that, The main control chip is configured to send pulse drive signals to the relay driver chip according to a preset frequency and duty cycle.

4. The relay driver chip testing device according to claim 2, characterized in that, The test circuit also includes: The communication unit has one end connected to the main control chip and the other end connected to the host computer. The power supply unit provides operating power to the communication unit; the main control chip uploads the number of times the relays open and close to the host computer through the communication unit.

5. The relay driver chip testing device according to claim 1, characterized in that, The adapter card includes: substrate; A chip package holder, which is mounted on a substrate, is used to fix and electrically connect the relay driver chip; The connector has a pin header, one end of which is electrically connected to the chip package socket, and the other end is electrically connected to a hot-swappable interface.

6. The relay driver chip testing device according to claim 5, characterized in that, The pins of the connection header include at least: a positive power supply pin, a ground power supply pin, a first input control pin, a second input control pin, a first output drive pin, a second output drive pin, and a current limiting control pin.

7. The relay driver chip testing device according to claim 1, characterized in that, When testing relay driver chips with different package types or pin definitions, only the adapter card with the corresponding relay driver chip on the test motherboard needs to be replaced.

8. The relay driver chip testing device according to claim 1, characterized in that, The relay driver chip testing device also includes: a housing; the housing covers and encloses the test motherboard and adapter card.

9. The relay driver chip testing device according to claim 8, characterized in that, The outer casing has an access port corresponding to the hot-swappable interface; a hatch is hinged inside the access port; and a sealing ring is provided on the edge of the hatch to fit the access port.

10. A method for testing a relay driver chip, characterized in that, It uses the relay driver chip testing apparatus as described in any one of claims 1 to 9; the relay driver chip testing method includes: First, install relay driver chips of different package types or pin definitions on the corresponding adapter cards; then plug the adapter cards into the hot-swappable interface to test the relay driver chips. When testing different relay driver chips, only the adapter card with the corresponding relay driver chip on the test motherboard needs to be replaced.

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