Chip hardware function testing method and system

Abstract

The application provides a chip hardware function test method and system, and relates to the technical field of chip testing. The method comprises the following steps: under dynamic voltage stress, the actual voltage response of the key nodes of the internal power supply network of the chip is synchronously collected; the voltage change rate is extracted, and the starting point of the ringing transition stage is determined when the threshold value of over-drift is exceeded; then the response fluctuation envelope is extracted, and compared with the steady-state tolerance; when the standard is always met in the continuous verification window, the end boundary of the transition state is determined; according to this, the effective stress data interval is divided, and the transition state data is isolated; finally, the feature vector in the effective interval is extracted, which is used for hardware function stability evaluation. The method of the application aims to solve the problems of capture window misplacement, false abnormal signal interference and repeated jumping of evaluation results caused by the fact that the external trigger mechanism cannot perceive the real response delay of the internal power supply network of the chip, can eliminate the transition state interference, and significantly improves the accuracy of stability evaluation.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and more specifically, to a chip hardware functional testing method and system. Background Technology

[0002] After chip design is completed, the process of verifying its hardware functionality and conformity with standard specifications typically involves building a programmable hardware test platform to apply dynamic voltage stress tests to the chip. This is combined with power consumption analysis and fuzzy logic to capture functional anomalies under extreme conditions in real time and evaluate hardware stability. In this routine test execution, the test platform outputs a voltage waveform with a preset slope through a dynamic voltage stress application module. The anomaly capture module usually uses the voltage edge at the stress application point as the sampling trigger, simultaneously starting the recording of voltage and power consumption data at key nodes. Subsequently, fuzzy logic units extract and judge stability characteristics.

[0003] In the extreme voltage slope test scenario of chip engineering verification, to induce potential timing violation-related physical effects, testers significantly increase the rise rate of the stress voltage, causing the chip to quickly enter its extreme operating state. At this point, the conversion between the voltage slope parameter output by the stress application module and the transient response of the chip's internal power supply network becomes a critical point affecting test accuracy. When the dynamic voltage stress rise rate exceeds the ideal following capability of the chip's internal power supply network and on-chip decoupling capacitors, significant delays and ringing phenomena occur in the internal voltage build-up process. Because the anomaly capture module still opens the sampling window according to the preset external stress start edge, it fails to consider the actual physical delay of the internal power supply response. This causes the capture window to start recording data during the period when the internal voltage has not yet stabilized and is still in a ringing state. The captured initial sampling data corresponds to the internal voltage transition process rather than the steady-state extreme stress state, thus generating a large number of false anomaly signals. Simultaneously, when the real extreme stress-related timing violation event occurs, the sampling window is already misaligned, causing the true anomaly waveform to be placed too far back in the window or even not captured completely. Furthermore, the real-time power consumption calculated by the power analysis sliding window is mixed with abnormal power consumption spikes caused by ringing, further obfuscating the input characteristics of the fuzzy logic.

[0004] Existing conventional methods for performing dynamic voltage stress testing rely heavily on externally set waveform edges for triggering, making it difficult to automatically detect and adapt to the spatiotemporal differences caused by the chip's internal physical network response to rapid slopes. This rigid synchronization strategy, when faced with severe internal transient fluctuations caused by extreme slopes, easily misinterprets physical transition state disturbances as functional failures. This leads to distorted input characteristics received by the fuzzy logic, resulting in boundary oscillations in membership function judgments and frequent jumps in stability assessment conclusions. Therefore, in chip extreme voltage slope testing scenarios, when the dynamic voltage stress rises to a level that causes significant ringing and delay in the chip's internal power supply network, the anomaly capture module, still using the voltage edge at the stress application point as the sampling trigger, fails to consider internal power supply response delays. This causes the capture window to cover non-steady-state transition signals, resulting in misaligned sampling data when true anomalies occur. This distorts the input signal for fuzzy logic stability assessment, leading to repeated jumps in assessment results.

[0005] To address the aforementioned issues, existing technologies urgently need improvement. Summary of the Invention

[0006] The purpose of this invention is to provide a chip hardware function testing method and system, which aims to solve the problems of capture window misalignment, false abnormal signal interference, and repeated jumps in evaluation results caused by the inability of external triggering mechanisms to perceive the actual response delay of the chip's internal power supply network. It can dynamically identify the ringing stage and accurately locate the effective stress range based on the actual voltage response inside the chip, thereby eliminating transitional interference and significantly improving the accuracy of stability assessment.

[0007] In a first aspect, the present invention provides a method for testing chip hardware functions, comprising the following steps: S1. Obtain the actual voltage response signal of the key node of the power supply network inside the chip under test under dynamic voltage stress; the actual voltage response signal is consistent with the time reference of the dynamic voltage stress; S2. Extract the voltage change rate from the actual voltage response signal, and when the voltage change rate exceeds a preset drift threshold, determine that the internal response of the chip under test has entered the ringing transition stage, and determine the determination time as the response start point; S3. Extract the fluctuation envelope characteristics of the actual voltage response signal after the response start point; S4. The fluctuation envelope feature is compared with the preset steady-state tolerance range in real time, and when the fluctuation envelope feature remains within the steady-state tolerance range within the continuously set verification time window, the start time of the verification time window is determined as the transition state end boundary. S5. Based on the transition state termination boundary, divide the effective stress data range from the actual voltage response signal, and isolate the transition state data outside the effective stress data range; S6. Extract the feature vector within the effective stress data range, and evaluate the hardware functional stability of the chip under test based on the feature vector.

[0008] The chip hardware function testing method provided by this invention has the technical advantage of being able to automatically sense and adapt to the spatiotemporal differences caused by the chip's internal power supply network's response to rapid voltage slope, effectively eliminating transitional interference signals, ensuring the accuracy of the input characteristics for hardware function stability assessment, and thus avoiding repeated jumps in assessment results.

[0009] Secondly, the present invention provides a chip hardware functional testing system, comprising: The signal receiving unit is used to acquire the actual voltage response signal of the key node of the power supply network inside the chip under test under dynamic voltage stress; the actual voltage response signal is consistent with the time reference of the dynamic voltage stress. The determination unit is used to extract the voltage change rate from the actual voltage response signal, and when the voltage change rate exceeds a preset drift threshold, determine that the internal response of the chip under test has entered the ringing transition stage, and at the same time determine the determination time as the response start point; The feature extraction unit is used to extract the fluctuation envelope features of the actual voltage response signal after the response start point; The comparison unit is used to compare the fluctuation envelope feature with the preset steady-state tolerance range in real time, and when the fluctuation envelope feature remains within the steady-state tolerance range within a continuously set verification time window, the start time of the verification time window is determined as the transition state end boundary. The data processing unit is used to divide the effective stress data range from the actual voltage response signal according to the transition state end boundary, and to isolate the transition state data outside the effective stress data range. An evaluation unit is used to extract feature vectors within the effective stress data range and to evaluate the hardware functional stability of the chip under test based on the feature vectors.

[0010] As can be seen from the above, the chip hardware functional testing method provided by this invention automatically identifies and locks the ringing transition start point of the internal power supply network by introducing the voltage change rate as a criterion, and locks the transition end boundary by using the fluctuation envelope comparison result as a trigger basis. This method abandons the traditional fixed triggering mode that relies on external voltage edges, and instead adopts a dynamic synchronization strategy based on the chip's internal physical response, effectively shielding the interference of non-steady-state transition signals caused by ringing on subsequent stability assessments. This technical solution can dynamically adapt to internal delay changes under different slope stresses in real time, ensuring the accurate division of the effective stress data range. It not only completely eliminates the problem of repeated jumps in evaluation results caused by sampling window misalignment, but also significantly improves the accuracy and reliability of hardware functional stability assessment under extreme conditions.

[0011] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing embodiments of the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings. Attached Figure Description

[0012] Figure 1 This is a flowchart of a chip hardware function testing method provided in an embodiment of the present invention.

[0013] Figure 2 This is a schematic diagram of the first structure of the chip hardware function testing system provided in an embodiment of the present invention.

[0014] Figure 3 This is a schematic diagram of a second structure of the chip hardware function testing system provided in an embodiment of the present invention.

[0015] Label Explanation: 100. Signal receiving unit; 200. Decision unit; 300. Feature extraction unit; 400. Comparison unit; 500. Data processing unit; 600. Evaluation unit; 700. Correction unit. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0017] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0018] In the field of chip design verification, the evaluation of hardware functionality and standard specifications typically employs a programmable hardware test platform to apply dynamic voltage stress. During this test, the test platform outputs a voltage waveform with a preset slope through a dynamic voltage stress application module, and uses the voltage edge at the stress application point as the sampling trigger, simultaneously initiating the recording of voltage and power consumption data at key nodes. Subsequently, fuzzy logic units extract and judge stability characteristics. However, when the dynamic voltage stress rises to a slope exceeding the following capability of the chip's internal power supply network and on-chip decoupling capacitors, delays and ringing phenomena occur in the internal voltage build-up process. Because the anomaly capture module still opens the sampling window at the external stress initiation edge, failing to consider the physical delay of the internal power supply response, the capture window begins recording data when the internal voltage is in a ringing state. This results in the captured initial sampling data corresponding to the internal voltage transition process rather than the steady-state ultimate stress state, thus generating a large number of false anomaly signals. Meanwhile, when a timing violation event related to ultimate stress occurs, the sampling window has been misaligned, causing the true abnormal waveform to be placed at the back of the window or not captured completely. Furthermore, the real-time power consumption calculated by the power consumption analysis sliding window is mixed with abnormal power consumption spikes caused by ringing, resulting in distortion of the fuzzy logic input features, which in turn triggers boundary oscillations and jumps in stability assessment conclusions in the membership function judgment.

[0019] Specifically, in the extreme voltage slope test scenario for chip engineering verification, testers significantly increase the rise rate of the stress voltage to induce potential timing violation-related physical effects, causing the chip to quickly enter its extreme operating state. At this point, the transition between the voltage slope parameter output by the stress application module and the transient response of the chip's internal power supply network becomes a critical point affecting test accuracy. During this process, because the anomaly detection module is highly dependent on externally set waveform edges, it struggles to automatically perceive and adapt to the spatiotemporal differences caused by the rapid slope response of the chip's internal physical network. This rigid synchronization strategy, when faced with severe internal transient fluctuations caused by the extreme slope, easily misinterprets physical transition state disturbances as functional failures, leading to distorted input characteristics received by fuzzy logic and consequently causing repeated jumps in stability assessment results.

[0020] If the above problems are not addressed, the testing system will be unable to accurately distinguish between transient fluctuations and steady-state ultimate stress states within the chip. This will result in a large number of non-steady-state transition signals being mixed into the test data, causing timing misalignment in the capture of genuine anomalies. This data distortion will directly lead to the failure of stability assessment logic, failing to accurately reflect the chip's hardware performance under ultimate stress, thereby affecting the reliability and accuracy of chip design verification and increasing the risk of missing hardware functional defects.

[0021] For reference, see the appendix. Figure 1 This invention provides a chip hardware function testing method, comprising the following steps: S1. Obtain the actual voltage response signal of the key node of the power supply network inside the chip under test under dynamic voltage stress; the actual voltage response signal is consistent with the time reference of the dynamic voltage stress. S2. Extract the voltage change rate from the actual voltage response signal, and when the voltage change rate exceeds the preset drift threshold, determine that the internal response of the chip under test has entered the ringing transition stage, and determine the determination time as the response start point. S3. Extract the fluctuation envelope features of the actual voltage response signal after the response start point; the fluctuation envelope features include the peak-to-peak sequence of the envelope; S4. Compare the fluctuation envelope feature with the preset steady-state tolerance range in real time, and when the fluctuation envelope feature remains within the steady-state tolerance range within the continuously set verification time window, determine the start time of the verification time window as the transition state end boundary. S5. Based on the transition state termination boundary, divide the effective stress data range from the actual voltage response signal, and isolate the transition state data outside the effective stress data range; S6. Extract the feature vector within the effective stress data range, and evaluate the hardware functional stability of the chip under test based on the feature vector.

[0022] For ease of understanding, the following explains some key terms in this embodiment: Dynamic voltage stress refers to a voltage waveform where the voltage applied to a chip's power supply pin is not constant, but rather changes rapidly with a preset slope and amplitude. This stress is designed to simulate power fluctuations that a chip may encounter in real-world operating environments, in order to test its stability under extreme conditions.

[0023] Critical nodes in the internal power supply network: These refer to specific physical locations within the chip's internal power distribution network that significantly impact the chip's functionality and performance. These nodes are typically located near the core logic circuitry, and the stability of their voltage directly affects the chip's normal operation.

[0024] Actual voltage response signal: This refers to the signal of voltage change over time, actually measured from key nodes of the chip's internal power supply network using probes or dedicated test fixtures under dynamic voltage stress. This signal reflects the true transient behavior of the chip's internal power supply network.

[0025] Rate of change of voltage: refers to the amount of voltage change in the actual voltage response signal per unit time, i.e., the first derivative of the voltage signal with respect to time. A sudden increase in the rate of change of voltage usually indicates that the internal power network has entered a violent transient response phase.

[0026] Drift threshold: This refers to a preset value used to determine whether the voltage change rate deviates significantly from the static baseline. When the voltage change rate exceeds this threshold, it indicates that the chip's internal response has entered the ringing transition phase.

[0027] Ringing transition phase: refers to the stage in which the internal voltage of a chip exhibits periodic decay oscillations after being subjected to rapid dynamic voltage stress, due to the interaction of parasitic inductance and decoupling capacitor.

[0028] Response start point: This refers to the moment when the rate of change of the actual voltage response signal of a key node in the chip's internal power supply network first exceeds a preset drift threshold. This point marks the official entry of the internal response into the ringing transition phase.

[0029] Fluctuation envelope characteristics: These refer to the characteristics describing the oscillation amplitude of the actual voltage response signal during the ringing transition phase. In this embodiment, it is specifically represented by the peak-to-peak sequence of the envelope, i.e., the difference between the upper and lower envelopes.

[0030] Steady-state tolerance range: This refers to the preset range within which the internal voltage of the chip is allowed to fluctuate. When the fluctuation envelope characteristic remains within this range, it indicates that the internal voltage of the chip has stabilized and entered a steady-state operating state.

[0031] Verification time window: This refers to a continuous time period used to confirm whether the fluctuation envelope characteristics remain within the steady-state tolerance range. By setting this window, misjudgments caused by instantaneous fluctuations can be avoided.

[0032] Transition state end boundary: This refers to the starting point of the verification time window, at which point the fluctuation envelope characteristics have remained within the steady-state tolerance range throughout the continuously set verification time window. This point marks the end of the internal voltage ringing transition phase and is also the starting point for the effective ultimate stress to be reached.

[0033] Effective stress data range: This refers to the actual voltage response signal data range starting from the transition state end boundary and continuing for a preset ultimate stress duration. The data within this range is considered the chip's true response under steady-state ultimate stress.

[0034] Transitional state data: refers to the data segment from the global synchronization zero point to the transition state end boundary. This data segment contains non-steady-state signals such as undershoot, overshoot, and ringing during the internal voltage build-up process of the chip.

[0035] Eigenvector: refers to a quantitative indicator extracted from the effective stress data range to characterize the stability of chip hardware functions, such as average steady-state power consumption, root mean square error of power consumption fluctuation, and maximum transient power consumption peak value.

[0036] Hardware functional stability assessment: refers to the process of comprehensively judging the functional performance and reliability of a chip under extreme stress conditions based on the extracted feature vectors.

[0037] This application proposes a chip hardware function testing method, which aims to solve the problems in chip limit voltage slope testing, where the spatiotemporal difference between the external stress triggering mechanism and the actual physical response of the chip's internal power supply network leads to sampling window coverage of unsteady transition signals, mis-capture of true abnormal events, and distortion of stability evaluation results.

[0038] In step S1, the actual voltage response signal of the key nodes of the internal power supply network of the chip under test is acquired under dynamic voltage stress; the actual voltage response signal is synchronized with the time reference of the dynamic voltage stress. This step can be achieved in various ways. For example, one implementation involves configuring a multi-channel high-speed analog-to-digital converter at the hardware level on the test platform and strictly phase-locking the sampling clock with the reference clock of the stress waveform generator to ensure absolute synchronization between the external stimulus and the internal response on the time axis. Before the test, the tester uses a probe station or a dedicated test fixture to bring out the power supply grid nodes near the core logic area inside the chip to the sampling channel of the test platform. When the test platform issues a dynamic voltage stress application command, the external stress application link begins to output a voltage waveform with a preset extremely high rise slope. Simultaneously, the state-aware link no longer relies solely on the starting edge of the external waveform to trigger a single fixed-length sampling window, but instead uses the application command as a global synchronization zero point to initiate continuous high-frequency sampling of the externally applied voltage and the internal key node voltage. In terms of data organization and correlation, the continuously sampled data stream is written in real-time into a deep circular buffer built within the field-programmable gate array (FPGA). This buffer is implemented using a dual-port random access memory, allowing the write pointer to continuously overwrite old data according to the sampling clock, while the read pointer can flexibly locate and retrieve data for specific time periods based on subsequent state identification results. To eliminate thermal noise and electromagnetic interference introduced during high-frequency sampling, the internal node voltage data passes through a low-latency finite impulse response digital low-pass filter before entering the buffer. The filter's cutoff frequency is set slightly higher than the maximum ringing frequency that may occur in the chip's internal power supply network, thus filtering out irrelevant high-frequency glitches while preserving the true physical transition state characteristics. Each piece of data stored in the buffer is appended with a high-precision timestamp relative to the global synchronization zero, forming a triplet data stream consisting of the timestamp, external voltage value, and internal voltage value.

[0039] In step S2, the voltage change rate is extracted from the actual voltage response signal. When the voltage change rate exceeds a preset drift threshold, the internal response of the chip under test is determined to have entered the ringing transition phase, and this determination time is set as the response start point. Specifically, based on the continuous voltage data stream with timestamps formed in the ring buffer, starting from the global synchronization zero point, the internal voltage data is read point by point along the time axis, and the first derivative of the voltage signal, i.e., the voltage change rate, is calculated using a sliding differential window. The digital signal processing module inside the test platform compares the current voltage change rate with the preset static baseline drift threshold in real time. Once the voltage change rate exceeds the drift threshold, it indicates that the internal node voltage has begun to deviate significantly from the initial static operating point, and the digital signal processing module marks the corresponding timestamp as the internal response start point.

[0040] In step S3, the fluctuation envelope characteristics of the actual voltage response signal after the response start point are extracted; the fluctuation envelope characteristics include the peak-to-peak sequence of the envelope. After entering the response start point, the internal voltage rises rapidly due to the forced injection of external limiting slope stress, and inevitably produces severe damped oscillations due to the interaction of parasitic inductance of the on-chip power supply path and decoupling capacitor. To accurately identify this ringing transition stage, the processing logic initiates an envelope extraction algorithm. This algorithm searches for local maxima and local minima of the internal voltage sequence in real time within a sliding time window, connecting them to form an upper envelope and a lower envelope, respectively. By calculating the difference between the upper and lower envelopes, the peak-to-peak sequence of the envelope, which reflects the ringing amplitude in real time, is obtained.

[0041] In step S4, the fluctuation envelope feature is compared with the preset steady-state tolerance range in real time. When the fluctuation envelope feature remains within the steady-state tolerance range within a continuously set verification time window, the start time of the verification time window is determined as the transition state end boundary (i.e., the effective ultimate stress reaches the starting point). The test platform is preset with a steady-state tolerance band, which is usually defined as a positive or negative specific percentage of the target ultimate stress voltage value, representing the voltage range within which the internal logic gates of the chip can operate stably without pseudo-timing violations caused by power supply fluctuations. The judgment logic compares the currently calculated peak-to-peak value of the envelope with the width of the steady-state tolerance band in real time. When the peak-to-peak value of the envelope first shrinks to less than the width of the steady-state tolerance band, it indicates that the oscillation amplitude of the internal voltage has decayed to an acceptable range. To prevent misjudgment due to local waveform distortion, the system does not immediately declare the end of the transition state, but instead starts a duration verification counter. The judgment logic will only confirm that the ringing process has truly converged when the peak-to-peak value of the envelope remains within the tolerance band throughout the continuously set verification time window, and the instantaneous average value of the internal voltage stabilizes near the target ultimate stress level. At this time, the start time of the verification time window is precisely located as the "transition state end boundary", and this time is also defined as the "effective ultimate stress reaches the starting point".

[0042] In step S5, based on the transition state end boundary, the effective stress data interval is divided from the actual voltage response signal, and the transition state data outside the effective stress data interval is isolated. After receiving the "effective limit stress reaches the starting point" timestamp, the core action of this step is to retime and segment the anomaly capture data originally triggered by the external edge. The processing objects are the original continuous voltage data stream stored in the ring buffer and the synchronously recorded chip functional logic output data stream. The system divides the data segment from the global synchronization zero point to the "effective limit stress reaches the starting point" into the "transition state data area", and divides the part after the "effective limit stress reaches the starting point" and continues for the preset limit stress duration into the "effective anomaly capture data area".

[0043] In step S6, feature vectors within the effective stress data range are extracted, and the hardware functional stability of the chip under test is evaluated based on these feature vectors. In the power consumption analysis link, the system abandons the original fixed power consumption sliding window that started with an externally applied command, and instead uses the "effective limit stress reaching the starting point" as the absolute zero point of the power consumption feature extraction window. Within the "transitional state data area," due to the violent charging and discharging of the decoupling capacitors and the parasitic oscillations of the power supply network, huge reactive current spikes are generated. If these spikes are not indiscriminately included in the power consumption characteristics, they will severely distort the fuzzy logic's understanding of the chip's true load state. Therefore, the power consumption analysis module only initiates the integral calculation of transient power consumption within the "effective anomaly capture data area." The system calculates the product of the internal node voltage and the supply current in real time using a hardware multiplier to obtain the transient power sequence, and extracts feature vectors within the aligned time window, including the average steady-state power consumption, the root mean square error of power consumption fluctuations, and the maximum transient power consumption peak value. These feature vectors are purely derived from the chip's functional activities under the true limit stress steady state and do not contain any physical disturbances from the transition state establishment process. At the same time, the inference cycle of the stability assessment link is also reset, so that its trigger clock is strictly locked at the moment when the power consumption feature extraction window ends.

[0044] After acquiring the power consumption feature vector strictly aligned with the physical state and the effective anomaly capture data area, a hardware stability assessment based on fuzzy logic is performed, and the assessment results are output in a split manner. The processing objects are the feature vector extracted in the previous step and the actual timing violation rate statistically analyzed within the effective anomaly capture window. The fuzzy logic unit first fuzzifies these input variables, using a pre-defined membership function to map clear numerical values ​​to the membership degrees of fuzzy sets. For example, the root mean square error of power consumption fluctuation is mapped to three fuzzy subsets: "low," "medium," and "high"; the actual timing violation rate is mapped to three fuzzy subsets: "very rare," "occasional," and "frequent." Since the input features have been completely isolated from the interference of the transition state, the values ​​of these variables can truly reflect the intrinsic stability of the chip under extreme stress, and the membership calculation will no longer oscillate violently near the boundaries of adjacent sets. Subsequently, the fuzzy inference engine performs logical deduction based on a pre-defined fuzzy rule base. The rule base contains empirical rules such as "if the power consumption fluctuation mean squared error is high and the actual timing violation rate is frequent, then the hardware stability is extremely poor" and "if the power consumption fluctuation mean squared error is medium and the actual timing violation rate is very low, then the hardware stability is good." The inference engine calculates the activation strength of each rule and fuses them to obtain a comprehensive fuzzy output set. Finally, the centroid method is used to defuzzify the fuzzy output set, calculating a clear stability score between 0 and 100. Based on this score, the system classifies the hardware stability of the tested chip under the current extreme stress condition into three categories: "stable," "edge-stable," or "unstable." Regarding output, the testing platform employs a splitting strategy: the first type of output is the corrected, valid anomaly capture data and its corresponding time boundaries. This data is directly pushed to the downstream fault diagnosis server for engineers to perform in-depth circuit-level anomaly localization and logic failure analysis. The second type of output is the stability score and classification conclusion, along with physical state identifiers such as transition state duration and envelope decay rate. This data is recorded in the test batch database for the yield analysis system to filter inputs and interpret results when generating the final conclusion. This state-isolated evaluation and splitting output completely solves the problem of repeated jumps in evaluation results, ensuring that the testing system can complete the physical effect verification under complex operating conditions in real time and accurately.

[0045] It should be noted that the use of the above-mentioned fuzzy logic (including fuzzification processing performed by fuzzy logic units, logical deduction by the fuzzy inference engine based on a preset fuzzy rule base, and defuzzification processing of the fuzzy output set using the centroid method) to test and evaluate the stability of chip hardware functions is existing technology and will not be elaborated here.

[0046] The following example will provide a more detailed explanation of the above technical solution: Suppose a chip is undergoing a limit voltage slope test, and an external test platform applies a dynamic voltage stress with an extremely high rise slope. Traditional methods use the initial edge of the external stress waveform as the sampling trigger point to begin recording voltage and power consumption data at critical nodes within the chip. However, due to parasitic effects in the chip's internal power supply network, the actual internal voltage response exhibits delays and severe ringing. This causes traditional methods to begin sampling before the internal voltage has stabilized, capturing a large number of non-steady-state transition signals, thus generating false anomalies and potentially missing genuine functional anomalies under limit stress.

[0047] The method proposed in this application solves the above problems through the following steps: First, in step S1, the test platform acquires the actual voltage response signals of key nodes in the internal power supply network of the chip under test, ensuring that these signals are consistent with the time reference of the dynamic voltage stress. Specifically, the test platform is configured with a multi-channel high-speed analog-to-digital converter to strictly phase-lock the sampling clock with the reference clock of the stress waveform generator. When an external stress application command is issued, the system uses this command as a global synchronization zero point to initiate continuous high-frequency sampling of the externally applied voltage and the internal key node voltage. This data is written in real time to a deep circular buffer and appended with a high-precision timestamp, forming a triplet data stream consisting of a timestamp, an external voltage value, and an internal voltage value. For example, when the external stress rises from 0V to 1.2V, the internal key node voltage may only begin to rise after the external stress reaches 1.2V, accompanied by ringing. Through synchronous sampling, the timing relationship between external stress and internal response can be accurately recorded.

[0048] Next, in step S2, the system extracts the voltage change rate from the actual voltage response signal. Based on the continuous voltage data stream in the ring buffer, the system calculates the first derivative of the internal voltage signal using a sliding differential window. When the voltage change rate exceeds a preset drift threshold, the system determines that the internal response of the chip under test has entered the ringing transition phase and identifies this determination moment as the response start point. For example, if the internal voltage begins to rise rapidly at a certain moment, its voltage change rate will increase sharply. Once it exceeds the preset threshold, the system can accurately identify the start moment of internal ringing, rather than simply relying on the external stress edge.

[0049] Subsequently, in step S3, the system extracts the fluctuation envelope characteristics of the actual voltage response signal after the response start point. Specifically, the processing logic initiates an envelope extraction algorithm, searching for local maxima and local minima of the internal voltage sequence in real time within a sliding time window, and connecting them to form an upper and lower envelope. By calculating the difference between the upper and lower envelopes, a peak-to-peak sequence of the envelope reflecting the ringing amplitude in real time is obtained. For example, during ringing attenuation, the peak-to-peak sequence gradually decreases, reflecting the attenuation of the ringing amplitude.

[0050] Further, in step S4, the system compares the fluctuation envelope characteristics with the preset steady-state tolerance range in real time. When the fluctuation envelope characteristics remain within the steady-state tolerance range within a continuously set verification time window, the system determines the start time of the verification time window as the transition state end boundary (i.e., the effective ultimate stress reaches the starting point). For example, if the peak-to-peak value of the envelope line remains within ±5% of the target ultimate stress voltage value for a period of time, the system confirms that the internal voltage has stabilized, the ringing process has truly converged, and marks the start time of the verification time window as the effective ultimate stress reaches the starting point.

[0051] Then, in step S5, the system divides the effective stress data range from the actual voltage response signal according to the transition state end boundary, and isolates the transition state data outside the effective stress data range. Specifically, the system divides the data segment from the global synchronization zero point to the "effective ultimate stress reaching the starting point" into the "transition state data area," and divides the portion after the "effective ultimate stress reaching the starting point" and continuing for the preset ultimate stress duration into the "effective anomaly capture data area." For signals within the "transition state data area," the system downweights all captured functional anomaly flags or directly labels them with "physical transition state shielding," so that they are not used as the basis for true ultimate stress functional failure in subsequent anomaly statistics and location, thereby completely eliminating false anomaly components.

[0052] Finally, in step S6, the system extracts feature vectors within the effective stress data range and performs hardware functional stability assessment on the chip under test based on these feature vectors. In the power consumption analysis link, the system uses the "effective limit stress reaching the starting point" as the absolute zero point of the power consumption feature extraction window, and only initiates the integral calculation of transient power consumption within the "effective anomaly capture data area". The system calculates the product of internal node voltage and supply current in real time through a hardware multiplier to obtain the transient power sequence, and extracts feature vectors within the aligned time window, including average steady-state power consumption, the root mean square error of power consumption fluctuations, and the peak value of maximum transient power consumption. These feature vectors are purely derived from the functional activities of the chip under true limit stress steady state and do not contain any physical disturbances in the transition state establishment process.

[0053] As can be seen from the above examples, the chip hardware functional testing method proposed in this application achieves precise separation of transient fluctuations and steady-state data in chip ultimate stress testing by shifting from passively relying on external triggers to actively sensing internal physical responses. Compared with traditional methods that rely solely on external stress edge triggers, this application, by extracting the voltage change rate and setting a drift threshold, can automatically identify the ringing transition phase caused by rapid voltage slopes within the chip and define this moment as the response start point, thereby overcoming the timing deviations caused by traditional methods. By extracting the fluctuation envelope features after the response start point and comparing them with the steady-state tolerance range in real time, this application can accurately lock the moment when the internal voltage tends to stabilize, i.e., the transition state end boundary, thus precisely switching the test sampling window from the non-steady-state ringing phase to the effective ultimate stress phase. This data partitioning and isolation process effectively eliminates the interference of false anomaly signals, ensuring that the data used in subsequent evaluations are all in the steady-state ultimate operating state of the chip. Finally, based on the pure ultimate stress response data, feature vectors are extracted for stability evaluation, eliminating repeated jumps in evaluation results caused by transition state disturbances, and significantly improving the accuracy and reliability of hardware functional stability evaluation. The technical solution of this application provides a more accurate and reliable basis for evaluating the hardware functional stability of chips under extreme stress conditions through precise perception and data processing of internal physical responses, and has made a significant technical contribution.

[0054] In some embodiments, the specific steps in step S3 include: S31. For the voltage data after the response start point in the actual voltage response signal, set a sliding time window, and identify the local extreme points of the actual voltage response signal within the sliding time window; S32. Based on local extreme points, construct the upper and lower envelopes of the actual voltage response signal; S33. Calculate the difference between the upper and lower envelopes to obtain the fluctuation envelope characteristics.

[0055] Setting a sliding time window is a data processing technique that defines a fixed or variable-length time interval that moves continuously across the data sequence, analyzing the data within the window at each movement. Its purpose is to divide a continuous voltage response signal into a series of local data segments, allowing for refined analysis of each segment and thus capturing the signal's transient characteristics. The length of the window can be preset to a fixed value, such as a window with a fixed number of sampling points determined based on experience or the signal sampling rate; alternatively, its length can be dynamically adjusted according to the real-time characteristics of the signal, such as based on the signal's transient frequency or rate of change. Identifying local extrema refers to the local maxima (local maximums) and local minima (local minimums) of the voltage response signal within the sliding time window. Identifying these points is crucial for depicting the signal's oscillation boundaries. Identification methods can include: comparing the magnitude of each data point within the window with its neighboring data points; if a point is greater than all its neighbors, it is a local maximum; if it is less, it is a local minimum. Alternatively, by calculating the first derivative of the signal, finding points where the derivative is zero or the sign changes, and combining this with the second derivative to determine whether they are local maximums or minimums. Constructing upper and lower envelopes are two curves used to depict the signal's oscillation amplitude. The upper envelope connects all local maxima points, and the lower envelope connects all local minimum points. The purpose of constructing the envelopes is to transform discrete local extrema points into continuous curves, thus visually representing the signal's amplitude variation trend. Construction methods can employ interpolation algorithms; for example, linear interpolation can connect adjacent local maxima points to form the upper envelope, and adjacent local minimum points to form the lower envelope. Alternatively, smoother curve fitting methods, such as cubic spline interpolation or B-spline curve fitting, can be used to better reflect the continuous changes in the signal. The difference between the upper and lower envelopes is calculated, i.e., the value of the upper envelope minus the value of the lower envelope at each time point. This difference directly quantifies the instantaneous oscillation amplitude of the signal at that time point, forming a time-varying sequence, i.e., the fluctuation envelope characteristic. This characteristic sequence can accurately reflect the intensity and attenuation process of the ringing of the internal power supply network. The calculation can be performed by subtracting from each sampling point to obtain a difference sequence aligned with the time axis of the original signal; or it can be performed by calculating the maximum or average difference between the upper and lower envelopes within each sliding time window to obtain the representative fluctuation amplitude within that window.

[0056] This application's solution achieves refined capture of local features of the voltage response signal by introducing a sliding time window mechanism. After acquiring the actual voltage response signal of key nodes in the internal power supply network of the chip under test, a sliding time window is first set for the voltage data after the response start point. This window moves along the time axis to analyze local data segments. Within each sliding time window, the system identifies local extreme points of the actual voltage response signal, which represent the peak and valley values ​​of the signal oscillation. Based on these identified local extreme points, the system further constructs upper and lower envelopes of the actual voltage response signal, where the upper envelope connects all local maxima and the lower envelope connects all local minima. These two envelopes together depict the amplitude variation range of the voltage signal during the transition phase. Subsequently, by calculating the difference between the upper and lower envelopes, the fluctuation amplitude of the voltage signal is directly quantified, thus obtaining the fluctuation envelope feature. This series of steps, organically combined, transforms the complex raw voltage signal into an intuitive and quantifiable fluctuation envelope feature, which can accurately characterize the ringing intensity of the internal power supply network under dynamic voltage stress. In this way, this application can accurately and efficiently extract the fluctuation envelope features reflecting the ringing state of the internal power supply network from complex voltage response signals. This provides a precise quantitative basis for determining the transition state end boundary in the subsequent step S4, thereby enhancing the objectivity and accuracy of the entire chip hardware functional testing method in assessing hardware functional stability. This refined feature extraction method makes the subsequent steady-state tolerance comparison and effective stress data interval division more reliable, avoiding false anomaly signals and evaluation result jumps caused by inaccurate feature extraction, thus significantly improving the accuracy and robustness of the entire testing method.

[0057] In one specific implementation, after acquiring the actual voltage response signal, the system can first preprocess the voltage data after the response start point, for example, by performing digital filtering to remove high-frequency noise. Then, a fixed-length sliding time window is set, for example, containing 100 sampling points. This window slides across the voltage data sequence in steps of one sampling point. Within each sliding time window, the system can use a local comparison method to identify local extrema: for each data point within the window, it is compared with N points before and after it (e.g., N=5). If the point is greater than these 2N points, it is marked as a local maximum; if it is less than these 2N points, it is marked as a local minimum. After identifying all local maxima, a cubic spline interpolation algorithm can be used to connect these points, forming a smooth, continuous upper envelope of the actual voltage response signal. Similarly, all local minimum points are connected using cubic spline interpolation to form the lower envelope of the actual voltage response signal. Finally, at each time point, the value of the upper envelope is subtracted from the value of the lower envelope to obtain the fluctuation envelope characteristic value at that time point, thus forming a fluctuation envelope characteristic sequence that reflects the change of ringing amplitude over time.

[0058] Through the above technical solution, this application provides a method for accurately and efficiently extracting the ringing state fluctuation envelope features of the power supply network inside a chip. This method performs local analysis of the voltage response signal by setting a sliding time window, identifies local extreme points within this window, constructs upper and lower envelopes, and calculates their difference, thereby transforming the complex original voltage signal into intuitive and quantifiable fluctuation envelope features. This refined feature extraction method effectively filters out high-frequency noise interference in the signal, focuses on the key fluctuation trends reflecting the ringing characteristics of the power supply network, and avoids subsequent judgment errors caused by inaccurate feature extraction in traditional methods. Therefore, this solution provides a more accurate and reliable input for the subsequent step S4, which compares the fluctuation envelope features with the preset steady-state tolerance range in real time. This significantly improves the accuracy of the transition state end boundary determination, thereby ensuring the accuracy of the effective stress data interval S5 divided from the actual voltage response signal. Ultimately, it enhances the objectivity and reliability of the hardware functional stability assessment S6 based on feature vectors for the chip under test, effectively solving the problem that the fluctuation envelope feature extraction in traditional methods is not accurate enough or lacks specificity, thus affecting the reliability of stability assessment.

[0059] In some of the solutions described above in this application, a sliding time window is proposed to identify the local extreme points of the actual voltage response signal, and then construct an envelope to extract the fluctuation envelope features. However, under different extreme stress conditions, the internal power supply network of the chip may generate ringing with different transient frequencies and decay rates. This makes it impossible to adaptively capture the features of different ringing modes when using a sliding time window of a fixed size to extract the envelope, thus affecting the envelope extraction accuracy.

[0060] In some embodiments, step S31, which involves setting a sliding time window for voltage data after the response start point in the actual voltage response signal, includes the following specific steps: S311. Calculate the transient frequency of the voltage data after the response start point in the actual voltage response signal, and set the length of the sliding time window based on the transient frequency.

[0061] This solution aims to address the problem in chip ultimate voltage slope testing scenarios where the chip's internal power supply network generates ringing with different transient frequencies and decay rates under varying ultimate stress conditions. Existing technologies, using a fixed-size sliding time window to extract fluctuation envelope features, cannot adaptively capture the characteristics of different ringing modes, thus affecting the envelope extraction accuracy and leading to inaccurate transition state termination boundary positioning. This solution improves the accuracy of fluctuation envelope feature extraction by introducing the calculation of the ringing transient frequency and a sliding time window adjustment mechanism based on that frequency.

[0062] Specifically, calculating the transient frequency of the voltage data after the response start point in the actual voltage response signal refers to acquiring the local oscillation frequency of the signal at a certain moment to reflect the frequency change characteristics of the signal over a short period of time. In the ringing scenario of the chip's internal power supply network, the ringing frequency is not constant but dynamically changes with time decay and stress conditions. The purpose of calculating the transient frequency is to accurately capture this dynamic change and provide a basis for subsequent adaptive adjustment of the sliding time window. This transient frequency can be calculated in several ways. For example, the Hilbert transform can be used to process the actual voltage response signal, and the transient frequency can be estimated in real time by analyzing the phase derivative of the analytical signal. Alternatively, zero-crossing detection or peak detection methods can be used to identify the period of the signal within a local time window and then calculate the transient frequency. The processing logic can also calculate the time interval between adjacent maxima and use its reciprocal as the estimated transient frequency of the current ringing.

[0063] Setting the length of the sliding time window based on the transient frequency means dynamically adjusting the size of the sliding time window according to the real-time calculated transient frequency. The length of the sliding time window directly affects the accuracy of local extremum identification and the smoothness of envelope construction. In scenarios where the ringing frequency changes dynamically, a window of fixed length may not be able to effectively capture ringing features at different frequencies. Dynamically setting the window length based on the transient frequency aims to enable the window to adaptively cover at least one or more complete ringing cycles, thereby more accurately identifying local extrema and improving the accuracy of envelope extraction. For example, the length of the sliding time window can be set to an integer multiple of the reciprocal of the transient frequency (i.e., the transient period), such as 1, 1.5, or 2 times the transient period, to ensure that the window contains at least one complete oscillation cycle. Alternatively, the transient frequency can be mapped to a preset frequency range, dividing the transient frequency into multiple intervals, each interval corresponding to a preset sliding time window length.

[0064] In the aforementioned chip hardware functional testing method, after the system determines that the internal response of the chip under test has entered the ringing transition phase and identifies the response start point, the data processing module continuously monitors the actual voltage response signal after the response start point. To calculate the transient frequency of this signal, the data processing module can identify local maxima of the actual voltage response signal in real time. For example, by comparing the current sampling point with the values ​​of several sampling points before and after it, a local peak value is determined. Once two adjacent local maxima are identified, the system records the time interval between these two maxima. The reciprocal of this time interval is estimated as the current transient frequency. For example, if the time interval between two adjacent local maxima is 10 nanoseconds, the current transient frequency is estimated to be 100 MHz. Subsequently, the system dynamically sets the length of the sliding time window used to identify local maxima based on this transient frequency. For example, the length of the sliding time window can be set to 1.5 times the transient period. If the transient frequency is 100 MHz, the transient period is 10 nanoseconds, and the length of the sliding time window will be set to 15 nanoseconds. When the transient frequency changes, for example to 50 MHz (with a period of 20 nanoseconds), the length of the sliding time window will be adjusted accordingly to 30 nanoseconds. In this way, the length of the sliding time window can always be matched with the transient frequency of the actual voltage response signal, ensuring that at least one oscillation cycle can be completely captured within the sliding time window. This allows for more accurate identification of local extrema, the construction of precise upper and lower envelopes, and ultimately, the calculation of more reliable fluctuation envelope characteristics.

[0065] In the process of extracting wave envelope features, since the ringing frequency generated by the internal power supply network of the chip under different stress conditions is not constant, the frequency change characteristics of the signal can be accurately captured by calculating the transient frequency of the voltage data after the response start point in real time. Setting the length of the sliding time window based on the transient frequency ensures that the window can cover the complete signal cycle, avoiding the loss of smooth signal features due to an excessively long window and preventing local extreme point identification deviations due to an excessively short window. This technique of dynamically adjusting the sampling window based on the signal's own frequency characteristics effectively improves the precision of wave envelope feature extraction, providing a reliable data foundation for accurately determining the transition state end boundary, thus solving the problem of insufficient adaptability of fixed windows under complex transient responses. Through the above technical solution, this application can effectively solve the problem that in chip ultimate voltage slope testing scenarios, when the internal power supply network of the chip generates ringing with different transient frequencies and decay rates under different ultimate stress conditions, existing technologies using fixed-size sliding time windows to extract wave envelope features cannot adaptively capture the features of different ringing modes, thus affecting the envelope extraction accuracy and leading to inaccurate positioning of the transition state end boundary. By calculating the transient frequency of the actual voltage response signal and adaptively setting the length of the sliding time window based on this transient frequency, the sliding time window can dynamically match the periodic characteristics of the ringing signal. This significantly improves the accuracy of fluctuation envelope feature extraction under complex transient responses, ensures the accuracy of local extreme point identification, and allows the constructed upper and lower envelopes to more realistically reflect the ringing decay process. Ultimately, this provides a more reliable data foundation for accurately determining the transition state end boundary, avoiding misjudgments caused by inaccurate envelope extraction, and thus improving the overall accuracy and reliability of chip hardware functional testing.

[0066] In some of the solutions described above in this application, the effective stress data range is divided by identifying the transition state end boundary of the voltage response signal, thereby realizing hardware functional stability assessment. However, in the continuous stress cycle test scenario, due to the charge accumulation or physical inertia of the internal power supply network of the chip, the transition state fluctuation of the previous cycle may not have completely dissipated before entering the next cycle. This cross-cycle residual oscillation will interfere with the voltage response signal of the current cycle, causing the determination of the transition state end boundary to be biased, and thus affecting the accuracy of the subsequent effective stress data range division.

[0067] In some embodiments, a further step is included between step S4 and step S5: S71. In continuous stress cycle testing, obtain the duration of the transition state of the previous stress cycle preceding the current stress cycle, and determine whether there is inter-cycle residual oscillation in the current stress cycle based on the duration of the transition state of the previous stress cycle, specifically including step S711: S711. Compare the duration of the transition state of the previous stress cycle with the preset residual oscillation judgment threshold, and determine whether there is cross-cycle residual oscillation in the current stress cycle based on the comparison result. S72. If it is determined that there is a residual oscillation across cycles, the transition state end boundary is corrected by performing a preset residual oscillation elimination operation. The residual oscillation elimination operation includes: pausing the application of dynamic voltage stress and inserting a baseline recovery idle period of preset duration to allow the internal power supply network of the chip under test to be completely discharged and restored to the static operating point, thereby eliminating the residual oscillation.

[0068] The acquisition of the transition state duration of the previous stress cycle preceding the current stress cycle refers to the system recording and storing the time length from the response start point to the transition state end boundary after each stress cycle ends. This can be achieved by recording the time difference using a high-precision timer or by calculating it through analysis of timestamp sequences. Determining whether there is cross-cycle residual oscillation in the current stress cycle based on the transition state duration of the previous stress cycle means that the system needs to assess whether the oscillations of the chip's internal power supply network have completely decayed after the previous stress cycle ended. This can be done by comparing the transition state duration of the previous cycle with a preset threshold or by predicting it through analysis of historical data trends. This determination aims to identify signal interference caused by physical inertia or charge accumulation during continuous testing, providing a basis for subsequent correction. The transition state duration of the previous stress cycle is compared with a preset residual oscillation judgment threshold, which is a pre-set time value representing the maximum time required for the chip's internal power supply network to fully recover to its static operating point under normal conditions after the stress ends. This threshold can be determined based on chip design parameters, simulation results, or previous experimental data. For example, it can be set as the time required for the voltage fluctuation of the chip's internal power supply network to decay to a specific steady-state tolerance range under stress-free conditions. If the duration of the transition state in the previous cycle exceeds this threshold, it indicates that the oscillation duration is too long and residual oscillations may exist; conversely, it is considered that the oscillations have sufficiently decayed. If a cross-cycle residual oscillation is detected, a preset residual oscillation elimination operation is performed to correct the transition state end boundary. The residual oscillation elimination operation aims to actively intervene in the testing process to eliminate the oscillation effect left over from the previous cycle; this is an active baseline recovery mechanism. Correcting the transition state end boundary means that when residual oscillations are detected, the system will not directly use the transition state end boundary determined by S4, but will re-evaluate or adjust the effective stress start point of the current cycle based on the result of the elimination operation to ensure that it is not affected by residual oscillations. The residual oscillation elimination operation includes pausing the application of dynamic voltage stress, that is, stopping the supply of rapidly changing voltage excitation to the chip, allowing the chip to enter a relatively stable state. At the same time, a baseline recovery idle period of preset duration is inserted, that is, after pausing stress, a period of time without applying dynamic stress is introduced. This time period is pre-set and sufficient to allow the charge in the chip's internal power supply network to be completely discharged, and the energy of parasitic inductance and capacitance to dissipate. This duration can be estimated or determined experimentally based on the chip's RC constant, LCR resonant characteristics, etc. The purpose of this operation is to completely discharge and restore the chip's internal power supply network to its quiescent operating point. This is the goal of the elimination operation, ensuring that at the start of the next stress cycle, the chip's internal power supply network is in a known, stable, and residual oscillation-free initial state.

[0069] This solution addresses signal interference caused by physical inertia during continuous testing by introducing a cross-cycle residual oscillation detection and elimination mechanism. After determining the transition state end boundary in step S4 and before dividing the effective stress data interval in step S5, the solution first acquires the transition state duration of the previous stress cycle during continuous stress cycle testing. This duration measures the time required for the chip's internal power supply network to recover from the response start point to ringing decay to the steady-state tolerance range under the stress of the previous cycle. Subsequently, the system determines whether cross-cycle residual oscillation exists in the current stress cycle based on the acquired transition state duration of the previous stress cycle. Specifically, by comparing the transition state duration of the previous stress cycle with a preset residual oscillation judgment threshold, if the duration exceeds the threshold, it indicates that the residual ringing energy from the previous cycle has not been dissipated in time, indicating a cross-cycle physical memory effect. If cross-cycle residual oscillation is detected, the system will proactively intervene and execute a preset residual oscillation elimination operation to correct the transition state end boundary of the current cycle. The core of this elimination operation is to pause the application of dynamic voltage stress and insert a baseline of a preset duration to restore the idle cycle. During this idle period, the internal power supply network of the chip under test is completely discharged and restored to its static operating point, thereby physically eliminating residual oscillations. This ensures that the chip's internal power supply network is in a clean reference state at the start of the next stress cycle, preventing residual oscillations from being misinterpreted as valid stress data for the current cycle. This detection and elimination of cross-cycle residual oscillations, inserted after S4 determines the transition state end boundary and before S5 divides the effective stress data interval, makes the transition state end boundary determined by S4 more reliable because it eliminates interference from historical cycles. When dividing the effective stress data interval in S5, a corrected and more accurate transition state end boundary can be used, ensuring that the divided effective stress data interval truly reflects the chip's behavior under steady-state ultimate stress, rather than data affected by transition states or residual oscillations.

[0070] In one specific implementation, during continuous stress cycling testing, after each stress cycle, the feedback control module can extract the duration of the transition state for the current cycle. For example, this duration can be recorded by a high-precision timer, representing the time difference between the response start point and the transition state end boundary. The feedback control module can compare this duration with a preset residual oscillation judgment threshold. This threshold can be an empirical value, such as 100 nanoseconds, or obtained through pre-characterization experiments on a specific chip type. If the transition state duration for the current cycle, for example, 150 nanoseconds, exceeds the preset 100 nanosecond threshold, the system determines that inter-cycle residual oscillation exists. At this time, the system will trigger an inter-cycle anomaly handling branch. For example, the test platform's main controller will immediately send a command to the dynamic voltage stress application module to pause the currently ongoing dynamic voltage stress application. Subsequently, the system will insert a baseline recovery idle period of a preset duration, such as 500 nanoseconds. During this idle period, the test platform ensures that no dynamic voltage stress is applied to the chip under test, allowing the decoupling capacitors in the chip's internal power supply network to completely discharge and restoring the internal voltage to its static operating point, such as the nominal voltage of 1.0V. This forced baseline recovery completely dissipates the ringing energy left over from the previous cycle, thus eliminating residual oscillations. After the idle cycle ends, the system restarts the test for the next stress cycle. At this time, the transition state termination boundary determined by S4 will be more accurate and unaffected by residual oscillations from the previous cycle.

[0071] The above technical solution addresses the problem in continuous stress cycling tests where charge accumulation or physical inertia within the chip's internal power supply network can cause residual oscillations from the previous cycle to interfere with the voltage response signal of the current cycle, leading to deviations in the determination of the transition state termination boundary and consequently affecting the accuracy of subsequent effective stress data interval division. This solution introduces a cross-cycle residual oscillation detection and elimination mechanism to effectively identify and quantify potential interference caused by incomplete stress release from the previous cycle. Upon detecting residual oscillation, the application of dynamic voltage stress is paused, and a baseline recovery idle cycle is inserted, forcing the chip's internal power supply network to completely discharge and return to its static operating point. This ensures that the initial state of subsequent test cycles is at a pure reference level, thereby accurately correcting the transition state termination boundary and preventing residual oscillations from being misjudged as effective stress data for the current cycle. Therefore, this solution significantly improves the rigor and stability of effective stress data interval division, making hardware functional stability assessments based on this data more accurate and reliable, effectively avoiding the generation of false anomaly signals, and ensuring accurate capture of real anomaly events.

[0072] Traditional chip hardware functional testing methods isolate transient data outside the effective stress data range. Transient data is not just noise, but includes multiple physical processes such as initial overshoot, initial undershoot, and ringing attenuation. Existing isolation methods use a uniform weighting or masking strategy for all transient data, which fails to distinguish the diagnostic value of different types of transients and may lead to the oversimplification or loss of useful physical behavior information.

[0073] In some embodiments, step S5, which involves isolating transition state data outside the effective stress data range, includes the following specific steps: S51. In the transient state data outside the effective stress data range, different types of transient states are identified based on the waveform characteristics of the actual voltage response signal; the different types of transient states include the initial overshoot state, the initial undershoot state, and the ringing decay state; S52. Classify and label the identified transition states, and perform differential isolation processing on the transition state data according to the classification labels to retain the diagnostic value of different types of transition states.

[0074] This data range refers to the segment of data from the global synchronization zero point to the transition state termination boundary in chip hardware functional testing methods, from the application of dynamic voltage stress. This segment includes the non-steady-state response experienced by the chip's internal power supply network during the transition from the static operating point to the target ultimate stress state under external dynamic voltage stress, such as rapid voltage rises, falls, and subsequent oscillations. Processing this data range is crucial to ensuring the accuracy of subsequent stability assessments. The waveform characteristics of the actual voltage response signal refer to its morphological properties in the time domain, including but not limited to the instantaneous voltage value, rate of change, local extrema, duration, frequency components, and waveform envelope. These characteristics reflect the physical behavior of the chip's internal power supply network under dynamic stress. For example, rapid voltage rises or falls may indicate overshoot or undershoot, while periodic fluctuations indicate ringing. Identifying different types of transition states involves analyzing the waveform characteristics of the actual voltage response signal to decompose the complex transition process into sub-stages with specific physical meanings. This can be achieved through various signal processing techniques, such as: threshold and slope detection, which detects rapid rises or falls in the voltage signal by setting voltage amplitude and rate of change thresholds to identify initial overshoot or undershoot; or envelope analysis, which extracts the upper and lower envelopes of the voltage signal and analyzes the attenuation characteristics of the envelope peak-to-peak values ​​to identify the ringing decay process. Different types of transition states include: initial overshoot, which refers to the phenomenon where the voltage of the chip's internal power supply network momentarily exceeds the target steady-state voltage value at the initial stage of dynamic voltage stress application, and then falls back; initial undershoot, which refers to the phenomenon where the voltage of the chip's internal power supply network momentarily falls below the target steady-state voltage value at the initial stage of dynamic voltage stress application, and then rises back; and ringing decay, which refers to the process where, after the initial overshoot or undershoot, the voltage of the chip's internal power supply network fluctuates periodically around the target steady-state voltage value, with the fluctuation amplitude gradually decreasing. Classification labeling refers to assigning a unique identifier or attribute label to each identified transition state. This can be achieved by adding enumeration types, string labels, or binary flags to the data structure. These markings provide a basis for subsequent differentiated processing, enabling the system to adopt different processing strategies based on the type of transition state. Differentiated isolation processing refers to using different strategies to process this data according to the type of transition state, rather than uniformly reducing weight or masking it. For example, for transition states that may contain critical diagnostic information, their original data can be retained or slightly reduced in weight; while for transition states that are purely noise or known to have no diagnostic value, heavy weighting or complete masking can be performed. Preserving diagnostic value means ensuring, through differentiated isolation processing, that the information contained in different types of transition states that reflects the internal physical behavior of the chip or potential failure modes is not lost or excessively weakened.

[0075] In this chip hardware functional testing method, when dynamic voltage stress is applied to the chip under test, its internal power supply network undergoes a transition process from static to steady state. The voltage response signal generated during this process contains rich physical information. This method first identifies different types of transition states, such as initial overshoot, initial undershoot, and ringing decay, by deeply analyzing the waveform characteristics of the actual voltage response signal in the transition state data outside the effective stress data range. This identification process utilizes signal processing techniques, such as detecting the instantaneous amplitude, rate of change, and envelope characteristics of the voltage to distinguish these physical phenomena. After identification, the system classifies and labels these different types of transition states, providing a clear basis for subsequent processing. Based on these classification labels, the system no longer adopts a uniform isolation strategy for all transition state data, but instead performs differentiated isolation processing. For example, signals within the "transition state data area," which contain undershoot, overshoot, and ringing during the internal voltage build-up process, are highly susceptible to causing pseudo-timing violations and pseudo-functional failures at the chip's logic output. Therefore, the system downweights all captured functional anomaly flags within this region or directly labels them with "physical transition state shielding," preventing them from being used as true ultimate stress functional failure criteria in subsequent anomaly statistics and localization, thus completely eliminating pseudo-anomaly components. This refined processing method allows for the maximum retention of diagnostically valuable transition state information while eliminating non-steady-state noise that interferes with stability assessment. Combined with basic chip hardware functional testing methods, in step S5, when isolating transition state data outside the effective stress data range, this approach no longer simply treats all transition state data as useless information and processes them uniformly, but rather delves into their internal structure. By identifying and classifying initial overshoot, initial undershoot, and ringing decay states, this approach can more accurately understand the true physical behavior of the chip's internal power supply network under dynamic stress. This refined management of transition state data not only avoids interference from pseudo-anomaly signals in subsequent hardware functional stability assessments but also provides engineers with richer diagnostic information. For example, if a specific type of overshoot or ringing mode is associated with a specific fault mode of the chip, retaining this information can significantly improve the efficiency and accuracy of fault localization.

[0076] As a specific implementation method, when processing transition state data outside the effective stress data range, the system can adopt the following process: First, for the actual voltage response signal, real-time waveform analysis can be implemented using a digital signal processor (DSP) or a field-programmable gate array (FPGA). For example, by setting multiple voltage thresholds and time windows, when the voltage signal exceeds 10% of the target steady-state voltage for a very short time (e.g., a few nanoseconds) and then falls back, it can be identified as an initial overshoot state; when the voltage signal is below 10% of the target steady-state voltage and then rises back, it can be identified as an initial undershoot state. For ringing decay states, a combination of local extremum detection within a sliding window and an envelope fitting algorithm can be used. When periodic fluctuations in the voltage signal are detected and the peak-to-peak value of its envelope shows an exponential decay trend, it can be identified as a ringing decay state. After identifying these different types of transition states, the system will assign a corresponding classification label to each identified data segment. For example, an enumerated variable can be used to represent the type of transition state. When performing differentiated isolation processing on these data, different strategies can be adopted based on these labels. For example, for initial overshoot and initial undershoot states, since they are highly prone to causing pseudo-timing violations and pseudo-functional failures at the chip logic output, the system can reduce the weight of all captured functional anomaly flags, for example, by setting their weight coefficient to 0.2, or by directly labeling them as "physical transition state shielding," so that they are not used as the basis for true ultimate stress functional failure in subsequent anomaly statistics and localization. For ringing decay states, if their amplitude and frequency are within a specific range, they may contain diagnostic information about the chip's decoupling network characteristics. In this case, they can be slightly reduced in weight (e.g., by setting the weight coefficient to 0.5), or their original waveform data can be stored separately for subsequent spectral analysis or time-domain feature extraction, thus retaining their diagnostic value. In this way, when processing signals in the "transition state data region," the power consumption analysis module can selectively filter or adjust data weights based on these classification labels, avoiding the distortion of power consumption characteristics by reactive current spikes, while retaining useful physical behavior information.

[0077] By employing the aforementioned technical solution, this application effectively addresses the problem that traditional methods, when processing transition state data, fail to distinguish the diagnostic value of different types of transition states, leading to the oversimplification or loss of useful physical behavior information. This solution, through refined analysis of the waveform characteristics of the actual voltage response signal, accurately identifies and classifies various transition states, such as the initial overshoot state, initial undershoot state, and ringing decay state. Based on this, the system can perform differentiated isolation processing of transition state data according to these classification labels, rather than simply uniformly reducing weight or masking it. This processing method allows for the selective retention of diagnostically valuable transition state information while eliminating non-steady-state noise that interferes with stability assessment. For example, by retaining specific types of ringing decay states, engineers can be provided with clues about key parameters such as the impedance of the chip's internal power supply network and the performance of decoupling capacitors, thereby assisting in fault location and performance optimization. Therefore, this solution, while ensuring the accuracy of hardware functional stability assessment, significantly improves the diagnostic depth and fault analysis capabilities of the testing method, providing more comprehensive and reliable data support for chip design and verification.

[0078] Reference Appendix Figure 2 This invention provides a chip hardware functional testing system (the chip hardware functional testing system adopts the chip hardware functional testing method of the above embodiment, and the specific process is described in the corresponding steps above), including: The signal receiving unit 100 is used to acquire the actual voltage response signal of the key node of the internal power supply network of the chip under test under dynamic voltage stress; the actual voltage response signal is consistent with the time reference of the dynamic voltage stress. The determination unit 200 is used to extract the voltage change rate from the actual voltage response signal, and when the voltage change rate exceeds the preset drift threshold, determine that the internal response of the chip under test has entered the ringing transition stage, and at the same time determine the determination time as the response start point. The feature extraction unit 300 is used to extract the fluctuation envelope features of the actual voltage response signal after the response start point; The comparison unit 400 is used to compare the fluctuation envelope feature with the preset steady-state tolerance range in real time, and when the fluctuation envelope feature remains within the steady-state tolerance range within the continuously set verification time window, the start time of the verification time window is determined as the transition state end boundary. The data processing unit 500 is used to divide the effective stress data range from the actual voltage response signal according to the transition state end boundary, and to isolate the transition state data outside the effective stress data range. The evaluation unit 600 is used to extract feature vectors within the effective stress data range and to evaluate the hardware functional stability of the chip under test based on the feature vectors.

[0079] In some embodiments, reference is made to the appendix. Figure 3 It also includes a correction unit 700, used to perform the following steps after the comparison unit 400 has run and before the data processing unit 500 has run: S71. In continuous stress cycle testing, obtain the duration of the transition state of the previous stress cycle before the current stress cycle, and determine whether there is cross-cycle residual oscillation in the current stress cycle based on the duration of the transition state of the previous stress cycle. S72. If it is determined that there is a residual oscillation across the cycle, the transition state end boundary is corrected by performing a preset residual oscillation elimination operation.

[0080] In this context, the units described as separate components may or may not be physically separate. Similarly, the components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0081] Furthermore, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0082] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0083] The above description is merely an embodiment of the present invention and is not intended to limit the scope of protection of the present invention. For those skilled in the art, the present invention can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for testing the hardware functions of a chip, characterized in that, Includes the following steps: S1. Obtain the actual voltage response signal of the key node of the power supply network inside the chip under test under dynamic voltage stress; the actual voltage response signal is consistent with the time reference of the dynamic voltage stress; S2. Extract the voltage change rate from the actual voltage response signal, and when the voltage change rate exceeds a preset drift threshold, determine that the internal response of the chip under test has entered the ringing transition stage, and determine the determination time as the response start point; S3. Extract the fluctuation envelope characteristics of the actual voltage response signal after the response start point; S4. The fluctuation envelope feature is compared with the preset steady-state tolerance range in real time, and when the fluctuation envelope feature remains within the steady-state tolerance range within the continuously set verification time window, the start time of the verification time window is determined as the transition state end boundary. S5. Based on the transition state termination boundary, divide the effective stress data range from the actual voltage response signal, and isolate the transition state data outside the effective stress data range; S6. Extract the feature vector within the effective stress data range, and evaluate the hardware functional stability of the chip under test based on the feature vector.

2. The chip hardware function testing method according to claim 1, characterized in that, The fluctuation envelope feature includes the peak-to-peak sequence of the envelope.

3. The chip hardware function testing method according to claim 2, characterized in that, The specific steps in step S3 include: S31. For the voltage data after the response start point in the actual voltage response signal, a sliding time window is set, and the local extreme points of the actual voltage response signal are identified within the sliding time window; S32. Based on the local extreme points, construct the upper and lower envelopes of the actual voltage response signal; S33. Calculate the difference between the upper and lower envelopes to obtain the fluctuation envelope feature.

4. The chip hardware function testing method according to claim 3, characterized in that, In step S31, the specific steps for setting a sliding time window for the voltage data after the response start point in the actual voltage response signal include: S311. Calculate the transient frequency of the voltage data after the response start point in the actual voltage response signal, and set the length of the sliding time window according to the transient frequency.

5. The chip hardware function testing method according to claim 1, characterized in that, The steps between step S4 and step S5 include: S71. In continuous stress cycle testing, obtain the duration of the transition state of the previous stress cycle before the current stress cycle, and determine whether there is cross-cycle residual oscillation in the current stress cycle based on the duration of the transition state of the previous stress cycle. S72. If it is determined that there is a residual oscillation across cycles, the transition state end boundary is corrected by performing a preset residual oscillation elimination operation.

6. The chip hardware function testing method according to claim 5, characterized in that, In step S71, the specific steps for determining whether there is inter-cycle residual oscillation in the current stress cycle based on the duration of the transition state of the previous stress cycle include: S711. Compare the duration of the transition state of the previous stress cycle with the preset residual oscillation judgment threshold, and determine whether there is cross-cycle residual oscillation in the current stress cycle based on the comparison result.

7. The chip hardware function testing method according to claim 5, characterized in that, The residual oscillation elimination operation includes: pausing the application of the dynamic voltage stress and inserting a baseline recovery idle period of a preset duration to allow the internal power supply network of the chip under test to be completely discharged and restored to the static operating point, thereby eliminating the residual oscillation.

8. The chip hardware function testing method according to claim 1, characterized in that, Step S5, specifically the steps for isolating the transition state data outside the effective stress data range, include: S51. In the transition state data outside the effective stress data range, different types of transition states are identified based on the waveform characteristics of the actual voltage response signal; S52. Classify and label the identified transition states, and perform differential isolation processing on the transition state data according to the classification labels to retain the diagnostic value of different types of transition states.

9. The chip hardware function testing method according to claim 8, characterized in that, The different types of transition states include the initial overshoot state, the initial undershoot state, and the ringing decay state.

10. A chip hardware functional testing system, characterized in that, include: The signal receiving unit is used to acquire the actual voltage response signal of the key node of the power supply network inside the chip under test under dynamic voltage stress. The actual voltage response signal is consistent with the time reference of the dynamic voltage stress; The determination unit is used to extract the voltage change rate from the actual voltage response signal, and when the voltage change rate exceeds a preset drift threshold, determine that the internal response of the chip under test has entered the ringing transition stage, and at the same time determine the determination time as the response start point; The feature extraction unit is used to extract the fluctuation envelope features of the actual voltage response signal after the response start point; The comparison unit is used to compare the fluctuation envelope feature with the preset steady-state tolerance range in real time, and when the fluctuation envelope feature remains within the steady-state tolerance range within a continuously set verification time window, the start time of the verification time window is determined as the transition state end boundary. The data processing unit is used to divide the effective stress data range from the actual voltage response signal according to the transition state end boundary, and to isolate the transition state data outside the effective stress data range. An evaluation unit is used to extract feature vectors within the effective stress data range and to evaluate the hardware functional stability of the chip under test based on the feature vectors.

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