A wiring harness simulator and a wiring harness fault simulation method

Abstract

The application discloses a kind of wire harness analog and wire harness fault simulation method, wire harness analog includes display and operation panel, control mainboard, relay matrix board and interface board.The relay matrix board has M rows × N column relay matrix, and each relay is independently controlled by control mainboard through main single-chip microcomputer.The key is that interface board and control mainboard are pluggable connection, interface single-chip microcomputer and nonvolatile memory are provided on interface board, for storing configuration file including connection relationship mapping and process step sequence.Simulation starts, and interface single-chip microcomputer is as main control engine, and sends instruction to main single-chip microcomputer according to step sequence, and drive relay matrix forms predetermined connection topology between output end point, to simulate wire harness fault.The application realizes hardware binding and plug and play of calibration scheme by the architecture innovation of pluggable intelligent interface board, completely replaces physical fault sample wire harness, eliminates artificial configuration error, significantly reduces calibration cost, improves calibration efficiency and flexibility.

Description

Technical Field

[0001] This invention relates to the field of calibration technology for wire harness production testing equipment, and more specifically to a wire harness simulator and a wire harness fault simulation method for calibrating wire harness testers. Background Technology

[0002] In the production of wire harnesses in the automotive, aerospace, and industrial equipment industries, finished wire harnesses must undergo rigorous electrical continuity and insulation tests. To ensure the accuracy and reliability of test results, the wire harness testers used on the production line must be calibrated before formal testing.

[0003] The traditional calibration process is as follows: technicians manually prepare a batch of sample wire harnesses containing typical faults based on possible fault modes, such as wire harnesses containing single or combined faults such as short circuits, open circuits, and misconnections. Then, these sample wire harnesses are connected one by one to the wire harness tester to verify that the instrument can correctly detect and identify all fault types.

[0004] This traditional method has the following significant problems: First, producing a wide variety of faulty sample wire harnesses is time-consuming and labor-intensive, and each sample is often used only once, resulting in a large waste of materials and manpower. Second, the accumulated faulty sample wire harnesses require storage space and incur management costs. Third, when changing to different wire harness models, a complete set of faulty samples needs to be remade, resulting in slow calibration process switching and low overall efficiency. Summary of the Invention

[0005] To address the problems of high cost, slow switching, and low efficiency caused by existing wire harness tester calibration methods that rely on a large number of customized physical fault sample wire harnesses, the present invention aims to provide a wire harness simulator and wire harness fault simulation method that uses an electronic switch matrix to dynamically simulate arbitrary wire harness fault states and supports rapid program switching. This method can be used to flexibly and quickly simulate various wire harness fault states, replacing the device and method that requires a large number of physical samples, thereby reducing calibration costs and improving calibration efficiency.

[0006] To achieve the above objectives, the technical solution provided by the present invention is as follows: Option 1: A wire harness simulator, comprising a display and operation panel and a control unit, wherein the control unit consists of a control motherboard, a relay matrix board and an interface board; The relay matrix board includes a relay array with M horizontal common nodes and N vertical wire harness endpoints. Each horizontal common node and each vertical wire harness endpoint is connected to a relay, forming an M-row × N-column matrix structure, where M and N are both integers greater than 1. The control motherboard is equipped with a main microcontroller, which is connected to each relay in the relay array through a drive circuit to independently control the activation and deactivation of each relay. The interface board and the control motherboard are connected by a pluggable electrical and communication connection, and the interface board can bring out N longitudinal wire harness endpoints of the relay matrix board for connection to the test port of the wire harness tester being calibrated. The interface board stores at least one configuration file, each configuration file containing M sets of connection relationship mapping data and a process step sequence. The process step sequence specifies the order in which the connection relationship mapping data is called during the simulation. The interface board is configured to load and parse the configuration file, and after the simulation process starts, it acts as the main control process engine, sending the corresponding connection relationship mapping data to the main microcontroller step by step according to the process step sequence. This allows the main microcontroller to drive the corresponding relays to operate based on the received connection relationship mapping data, thereby forming a predetermined connection topology between the N longitudinal wire harness endpoints to simulate the fault state or normal state of the wire harness.

[0007] In the wire harness simulator solution, the interface board is equipped with an interface microcontroller, a non-volatile memory, and an output connector. The output connector is used to bring out N longitudinal wire harness endpoints of the relay matrix board for connection to the test port of the wire harness tester being calibrated. The non-volatile memory is connected to the interface microcontroller and is used to store at least one configuration file. The interface microcontroller is communicatively connected to the main microcontroller through the pluggable connection structure and is used to load and parse the configuration file.

[0008] In the wire harness simulator solution, the interface microcontroller on the interface board is also used to receive a step switching trigger signal, and automatically advance to the next step in the process step sequence after receiving the signal, until the entire calibration process is completed; the step switching trigger signal is a signal received from the wire harness tester being calibrated by the IO interaction interface set on the wire harness simulator, or a user manual trigger command received on the display and operation panel.

[0009] In the wire harness simulator solution, the control motherboard is further equipped with a multiplexer module and a driver module; the multiplexer module includes at least one multiplexed analog switch chip, and the driver module includes at least one Darlington transistor array chip; the address lines of the main microcontroller are connected to the address selection terminal of the multiplexed analog switch chip, the output channel of the multiplexed analog switch chip is electrically connected to the input terminal of the Darlington transistor array chip, and the output terminal of the Darlington transistor array chip is connected to the drive coil of a relay.

[0010] In the wire harness simulator solution, the multiplexer module on the control motherboard is composed of multiple multiplexed analog switch chips arranged in parallel. The address selection lines of each chip are connected in parallel to the same set of address buses of the main microcontroller. The main microcontroller selects each chip through independent chip select signal lines to expand the control channels.

[0011] In the wire harness simulator solution, the output connector is a plurality of FAKRA coaxial cable sockets, each FAKRA socket providing two electrical connection points; the number N of longitudinal wire harness endpoints of the relay matrix board is equal to twice the number of FAKRA sockets.

[0012] In the wire harness simulator solution, the display and operation panel provides a graphical user interface. This interface represents M sets of connection relationships as M independently editable virtual wires and N longitudinal wire harness endpoints as N virtual terminal lines. Users define connectivity relationships by illuminating icons at the intersections of virtual wires and virtual terminal lines. The display and operation panel compiles the user-defined graphical connectivity relationships into connection relationship mapping data and sends it to the interface microcontroller for storage in the non-volatile memory.

[0013] Option 2: A method for simulating wire harness faults, the method being based on the aforementioned wire harness simulator, specifically including the following steps: Step S1: Edit and generate a configuration file on the display and operation panel of the wire harness simulator, and store it in the non-volatile memory by the interface microcontroller; the configuration file contains multiple sets of connection relationship mapping data and process step sequence. Each set of connection relationship mapping data defines the on / off state between any two ends of multiple wire harness endpoints, and the process step sequence specifies which set of connection relationship mapping data to use in sequence. Step S2: After selecting and starting a configuration file, the interface microcontroller acts as the main control engine, reads the configuration file from the non-volatile memory, and executes the sequence of process steps. Step S3: The interface microcontroller obtains the connection relationship mapping data pointed to in the current step, and encapsulates it into a control command and sends it to the control motherboard. Step S4: The control motherboard controls the corresponding relays in its internal relay matrix to operate according to the control command, so that each terminal on the output connector of the wire harness simulator presents a predetermined connection topology to simulate a wire harness fault state or normal state. In step S5, after receiving the preset step switching trigger signal, the interface microcontroller automatically advances to the next step in the process step sequence and returns to step S3 until all steps are completed.

[0014] In the wire harness simulation method, the step switching trigger signal is a signal received from the calibrated wire harness tester via the IO interaction interface, or a user-manually triggered command received from the display and operation panel.

[0015] In the wire harness simulation method, before step S1, there is a step of replacing the interface board; the non-volatile memory of the replaced interface board is pre-stored with a configuration file for another wire harness model, so that the wire harness simulator can quickly switch to the corresponding calibration scheme.

[0016] The solution provided by this invention achieves hardware binding and plug-and-play functionality for the calibration scheme through the innovative architecture of a "pluggable smart interface board," completely replacing physically faulty sample harnesses, eliminating human configuration errors, significantly reducing calibration costs, and improving calibration efficiency and flexibility.

[0017] Compared with existing technologies, it has the following advantages: 1. By placing the configuration file containing the complete calibration scheme on a pluggable interface board, and using the microcontroller on the interface board as the execution body of the scheme, the hardware binding between the calibration scheme and the interface board is realized; when users change the model of the wire harness product, they only need to replace the corresponding pre-programmed interface board to complete the complete and error-free switching of the calibration scheme, realizing "plug and play".

[0018] 2. It replaces a wide variety of physical fault sample wire harnesses and uses an electronically programmable relay matrix to achieve dynamic simulation of arbitrary wire connection states, significantly reducing the labor, material, and storage costs of sample preparation.

[0019] 3. It supports linkage with wire harness testers through IO interaction function to form a fully automatic closed-loop calibration, which further reduces manual intervention and improves the consistency and reliability of calibration. Attached Figure Description

[0020] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0021] Figure 1 This is a block diagram of the wire harness simulator system in an example of the present invention.

[0022] Figure 2 This is a schematic diagram of the circuit principle of the control motherboard and relay matrix board in an example of the present invention.

[0023] Figure 3 This is a schematic diagram showing the relationship between the display and the operation panel in an example of the present invention.

[0024] Figure 4 This is a schematic diagram of the process setting interface displayed on the operation panel in an example of the present invention.

[0025] Figure 5 This is a schematic diagram of the circuit principle of the interface board in an example of the present invention.

[0026] Figure 6 This is an example diagram illustrating the interaction between the wire harness simulator and the wire harness test bench in an embodiment of the present invention. Detailed Implementation

[0027] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below with reference to specific illustrations.

[0028] like Figure 1 As shown, the wire harness simulator provided by the present invention includes four main components: a display and operation panel 100, a control main board 200, a relay matrix board 300, and an interface board 400. These components work together through electrical connections and communication lines to form a complete programmable fault simulation system.

[0029] In the wire harness simulator provided by the present invention, the display and operation panel 100 is the human-machine interaction front end of the entire system. It can convert the user's intention to operate on the fault connection relationship and test process into digital configuration data and visualize the current working status of the system.

[0030] The control motherboard 200 serves as the decision-making and driving core of the system. Its function is to receive commands from the display and operation panel 100 or the interface board 400, parse them into switching control signals for each relay on the relay matrix board, and achieve sufficient driving capability through the driving circuit.

[0031] The relay matrix board 300 is the actuator for fault simulation. It has an M-row × N-column relay matrix consisting of M horizontal common nodes and N vertical wire harness endpoints. Its function is to reproduce fault states such as short circuit, open circuit, and misconnection in the wire harness by controlling the closing of these relays in a planned manner to form an arbitrary preset connection topology between the N vertical endpoints.

[0032] The interface board 400 is used for external connection and configuration. The interface board 400 can be connected with the relay matrix board 300 to standardize the N longitudinal wire harness endpoints of the relay matrix for docking with the wire harness tester being calibrated. At the same time, the interface board 400 has a pre-stored test process configuration file or can obtain the configuration file from the display and operation panel 100, and can generate test process control commands based on the configuration file and feed them back to the control motherboard 200.

[0033] In this wiring harness simulator, the display and operation panel 100 is connected to the control motherboard 200 via a serial communication bus. All connection relationships and process settings that the user can edit on the panel are compiled into instruction data and sent to the control motherboard 200. After receiving the instruction, the control motherboard 200 parses the position of the relay that needs to be closed, generates the corresponding drive signal, and controls the specified relay on the relay matrix board 300 to operate through the drive circuit.

[0034] When the system configuration interface board 400 realizes online storage and automatic process functions, the interface board 400 can replace the display and operation panel and directly serve as the command source of the control motherboard 200. It reads the pre-stored configuration file and sends the relay control command sequence to the control motherboard 200 according to the process steps, so that the entire simulation process can be carried out automatically.

[0035] At the same time, the control motherboard 200 transmits information such as the current matrix status and step number back to the display and operation panel 100 or the interface board 400 for status indication and step synchronization.

[0036] Based on this, the interface board 400 in this wire harness simulator is constructed as an independently replaceable intelligent module, and the control of the calibration process is configured on this interface board. Specifically, the interface board 400 and the control motherboard 200 are electrically and communicatively connected via a pluggable connector. This physical separability is the basis for its plug-and-play functionality. In traditional automated testing equipment, replaceable interface modules typically serve only as passive signal transfer and adaptation units, with the host still controlling the testing process. In this invention, the interface board 400 is not only a passive interface and storage carrier but also an active executor of the simulation process. After the user completes the graphical configuration, the generated configuration file is sent to the interface board 400, thereby binding the solution with the hardware. After the test starts, the interface board 400, as the main control process engine, retrieves the configuration file and actively and step-by-step sends instructions to the control motherboard 200 according to the process step sequence. The control motherboard 200 then becomes a controlled actuator, responsible only for parsing the instructions and converting them into drive signals for the specific relays on the relay matrix board 300.

[0037] Accordingly, when calibrating different wire harness models, the wire harness simulator provided by this invention only needs to unplug the current interface board 400 and replace it with another interface board 400 that has been pre-programmed with the corresponding calibration scheme. After the system is powered on, the new interface board 400 can take over the control and execute the new scheme. No on-site software configuration is required throughout the process, which completely eliminates the risk of calibration failure caused by manual configuration errors. It replaces a wide variety of physically faulty sample wire harnesses and realizes dynamic simulation of arbitrary wire connection states through an electronically programmable relay matrix, which greatly reduces the labor, material and storage costs of sample preparation.

[0038] The following section provides a further explanation of the specific configuration of each major component in the wire harness simulator.

[0039] The display and operation panel 100 in this wire harness simulator preferably adopts an embedded industrial control all-in-one computer with a touch screen and runs a graphical operating system.

[0040] See Figure 3 and Figure 4 The graphical interface provided by this display and operation panel 100 transforms the abstract relationship of wire harness connections into an intuitive two-dimensional matrix graphic.

[0041] As an example, the display and operation panel 100 is configured as follows: M independently editable virtual wires are arranged on the left side of the interface, and N virtual terminal lines are arranged below. Each virtual terminal line corresponds to a specific physical endpoint on the output connector 403. Accordingly, the user defines the connection relationship by lighting up icons at the intersections, and this operation is compiled into binary matrix data in real time.

[0042] Unlike the traditional text list-based configuration method, this display and operation panel 100 adopts a graphical two-dimensional matrix interface for configuration, which greatly reduces the complexity of operation. This allows production line engineers who are not familiar with programming to quickly and accurately complete complex fault simulation configurations, avoiding the error-prone problems of traditional text configuration.

[0043] See Figure 2 In this wiring harness simulator, the control motherboard 200 is equipped with a main microcontroller 201, whose firmware is configured with a matrix refresh algorithm. The control motherboard 200 also includes a multiplexer module 202 and a driver module 203, thus forming a control signal link from the main microcontroller to the multiplexer and then to the driver module.

[0044] The multiplexer module 202 is configured to expand the limited I / O lines of the main microcontroller 201 into more control channels through address decoding and channel selection, so as to cover the control requirements of M×N relays.

[0045] The drive module 203 is configured to convert the logic level signal output by the multiplexer module 202 into a power signal with sufficient current driving capability to reliably drive the corresponding relay coil in the relay matrix board 300 to engage.

[0046] When the control motherboard 200 is in operation, the main microcontroller 201 encodes the position of the relays that need to be closed into address data and outputs it to the multiplexer module 202 through the address bus. The multiplexer module 202 selects the corresponding channel according to the address signal and transmits a high-level signal to the corresponding input terminal of the driver module 203. The Darlington transistor in the driver module 203 is saturated and turned on, so that the corresponding relay coil in the relay matrix board 300 is energized and attracted. For relays that need to be held released, the main microcontroller 201 does not select its corresponding channel, the corresponding input terminal of the driver module 203 is at a low level, the Darlington transistor is cut off, and no current flows through the relay coil.

[0047] As a further explanation, for applications with a small number of relays and sufficient I / O port resources of the main microcontroller 201, the multiplexer module 202 can be omitted, and the driver module 203 can be directly constructed from discrete transistors or general-purpose Darlington array chips (such as ULN2003A). The main microcontroller 201 directly drives the relays in a static level manner to achieve independent control of each relay.

[0048] For the large-scale wiring harness (e.g., N≥16, M≥5) simulation scenarios addressed by this invention, I / O port resources become a bottleneck. Therefore, this invention provides an optimized circuit implementation scheme, such as... Figure 2 As shown in the diagram. In this optimized scheme, the multiplexer module 202 is composed of multiple multiplexed analog switch chips (such as CD4051) in a parallel expansion structure. The address selection lines (A, B, C) of each chip are connected in parallel to the same address bus of the main microcontroller 201, and the inhibit terminal (INH) of each chip is controlled by the independent chip select signal line of the main microcontroller 201. The driver module 203 is composed of multiple Darlington transistor array chips (such as ULN2003A). The input pins of each ULN2003A are connected one-to-one with the output channels (X0~X7) of the corresponding CD4051 chip, and the output terminal of each ULN2003A is connected to the coil terminal of the corresponding relay in the relay matrix board 300. In the resulting parallel expansion structure, the main microcontroller 201 requires only 3 address buses and N chip select lines (where N is the number of CD4051 chips) to obtain 8×N independent control channels, effectively solving the problem of insufficient microcontroller I / O resources. Simultaneously, since each CD4051 chip shares the same set of address buses, address signals are transmitted synchronously among the parallel chips, avoiding the response delay accumulation problem common in serial expansion schemes and ensuring the synchronization of channel switching during large-scale matrix refreshes.

[0049] Regarding the drive logic for the main microcontroller 201 to control the multiplexer module 202, the main microcontroller 201 employs a dynamic scanning and refreshing mechanism to drive a large number of relays. The specific scanning strategy configuration is as follows: After the main microcontroller 201 parses all the relay positions that need to be closed in the current step, it generates an address scan list. At the start of the scan cycle, the main microcontroller 201 enables the first CD4051 through the chip select signal and sequentially outputs the addresses of each channel belonging to that chip and needing to be closed on the address bus; then it switches the chip select signal to enable the next CD4051, and repeats this operation until all chips have been polled. After one scan cycle is completed, the next cycle begins immediately, and so on at a fixed frequency (approximately 1kHz).

[0050] To ensure stable contact closure during dynamic scanning, this invention further utilizes the inductive energy storage characteristics of the relay coil and the mechanical inertia of the armature. During the brief intervals between drive pulses, the current in the coil continues to flow through the reverse-parallel freewheeling diode, preventing abrupt changes. Simultaneously, the mechanical inertia of the armature ensures that the contacts do not have time to release before entering the next drive pulse cycle, thus maintaining a stable closed state. Furthermore, the configured scanning frequency is much higher than the mechanical response time of the relay contacts (typically a few milliseconds to tens of milliseconds), ensuring that contact bounce caused by scanning does not occur.

[0051] The relay matrix board 300 in this wiring harness simulator has a relay array designed as an M-row × N-column physical matrix. In the preferred structure of this invention, the M lateral common nodes in each row are independently isolated from each other. A freewheeling diode is connected in reverse parallel across each relay coil to suppress the reverse induced electromotive force generated by the relay coil when the drive transistor is off, protecting the drive chip from high-voltage breakdown.

[0052] As further explanation, this relay matrix board 300 is configured such that any two or more longitudinal wire harness endpoints within a row can achieve an electrical short circuit through the row's lateral common node simply by simultaneously engaging their corresponding relays, thus simulating a short-circuit fault between wires within the wire harness. If all relays corresponding to an endpoint are disconnected, that endpoint is in a floating state, simulating an open-circuit fault. Defining M rows as M independent connection relationships means that this instrument can pre-store and quickly switch between up to M different fault connection topologies without any mechanical plugging or unplugging. This represents a significant improvement in both functional flexibility and switching speed compared to physical sample wire harnesses that can only present a single fault state at a time.

[0053] In this wire harness simulator, the interface board 400 and the control motherboard 200 are electrically and communicatively connected via a pluggable connector (such as a dual-row pin header or other standard inter-board connector), allowing the interface board 400 to be easily replaced from outside or inside the chassis.

[0054] For details, see Figure 1 and Figure 5The interface board 400 is equipped with an interface microcontroller 401 and a non-volatile memory 402. The non-volatile memory 402 (such as EEPROM or Flash) is connected to the interface microcontroller 401 and is internally divided into multiple storage areas. Each storage area stores a complete configuration file, which contains M sets of connection relationship mapping data and a process step table. In the process step table, each step specifies which set of connection relationship mapping data should be called, and the conditions for step switching can be set, such as I / O triggering or timer triggering.

[0055] Furthermore, the interface microcontroller 401 communicates with the master microcontroller 201 via a UART or IIC communication bus carried on a pluggable connector. Simultaneously, the interface microcontroller 401 is configured to default as a slave device upon power-up, waiting for instructions. Upon receiving a start instruction, it parses the current active configuration file and begins a loop execution from step 1—packing the corresponding connection mapping data into instruction frames and sending them to the master microcontroller 201, waiting for the master microcontroller's response or status feedback. Upon receiving a switching trigger signal, it automatically loads the data for the next step until all steps are completed and returns to standby mode.

[0056] This allows for a complete calibration process defined and implemented entirely by the interface board 400. The main microcontroller 201 is simplified to a purely hardware-dependent matrix driver, while the product-specific calibration process logic is fully encapsulated within the replaceable interface board 400. When operators insert the interface board corresponding to different wire harness product models into the wire harness simulator, a complete hardware-level replacement of the calibration scheme is achieved without requiring any on-site software configuration editing, fundamentally eliminating the risk of calibration failure due to manual configuration errors.

[0057] Furthermore, the specific configuration of the output connector 403 on the interface board 400 is as follows: the output connector 403 uses multiple FAKRA coaxial cable sockets. Using this standard automotive connector allows the instrument to seamlessly connect directly to the test cable of the automotive wiring harness tester. Each FAKRA socket provides two electrical connection points: the core and the shield. For example, this configuration preferably uses 8 sockets to provide exactly 16 wiring harness endpoints, suitable for applications where N=16. It is understood that the number of FAKRA sockets can be flexibly chosen to other values ​​based on actual application requirements, as long as the number of endpoints N equals the number of sockets multiplied by 2.

[0058] In addition, both the control motherboard 200 and the interface board 400 have reserved I / O interfaces. These I / O interfaces include optocoupler-isolated input and output lines, and their function is to exchange hardware handshake signals with the wire harness tester. After the instrument completes a step of matrix setup, it sends a "ready" signal to the tester through its output line. After the tester performs the test, it returns a "test complete" pulse to the instrument's input line through its output port. The instrument uses this pulse as a step switching trigger signal and automatically proceeds to the next step. This design makes the wire harness simulator no longer an independent static simulator, but rather an integral part of the automated calibration closed loop, becoming a cohesive component of the intelligent calibration system.

[0059] Based on the system architecture and specific components of the wire harness simulator described above, this invention further provides a method for simulating wire harness faults using a wire harness simulator. Its technical principles and working process can be understood through… Figures 1-5 The data flow and control logic are fully explained.

[0060] This method runs on the aforementioned hardware platform and encapsulates all the fault simulation requirements of a wiring harness product into a configuration file. The method consists of two main phases: an editing phase and a runtime phase.

[0061] During the editing phase, the user accesses the display and operation panel 100, such as... Figure 3 , Figure 4 As shown, M sets of connection relationships and a sequence of process steps composed of these relationships are defined. Each set of connection relationships is encoded as an M×N binary matrix, where an element "1" represents that the relay at the corresponding intersection should be driven to engage, and "0" represents that the relay should remain released. The sequence of process steps is a sequential list of length K (K≤M), containing the group number of the connection relationship corresponding to each step. After these data are compiled by the display and operation panel 100, they are forwarded by the main microcontroller 201 and stored in the non-volatile memory 402 of the interface board 400, or directly written to the non-volatile memory 402 by the interface microcontroller 401 in programming mode. This editing stage binds the complete calibration scheme to a physical hardware (interface board).

[0062] During the operation phase, after the system enters the simulation working state, the interface microcontroller 401 is selected as the engine of the main control flow. The specific working process is as follows: The interface microcontroller 401 reads the flow step table of the currently active file from the non-volatile memory 402 and sets the step pointer to the first step. For the current step, the interface microcontroller 401 retrieves the corresponding connection relationship mapping data, frames it according to the specified communication protocol, and sends it to the main microcontroller 201. After receiving the instruction frame, the main microcontroller 201 parses it, converts the binary matrix in it into a list of relay addresses that need to be activated, and starts a matrix refresh cycle.

[0063] When employing a large-scale matrix dynamic scanning scheme, the main microcontroller 201 dynamically generates an address scan sequence and polls each target channel of the multiplexer module 202 via the address bus and chip select signal line, sequentially distributing high-level signals to the Darlington drive channel corresponding to each relay that needs to be activated. The main microcontroller 201 continuously and cyclically executes the above polling operation at a fixed scanning frequency (e.g., 1kHz). Based on the inductive energy storage characteristics of the relay coil, the freewheeling diode's freewheeling effect, and the mechanical inertia of the armature, it achieves macroscopically synchronized and stable activation of all target relays. Afterward, the main microcontroller 201 returns a setting completion response to the interface microcontroller 401.

[0064] The interface microcontroller 401 then determines the switching trigger mode for the current step. If configured for I / O interactive triggering, the interface microcontroller 401 monitors the input signal lines of the I / O interactive interface and waits for the "test complete" pulse from the wire harness tester; if configured for manual triggering, it waits for the trigger command issued by the display and operation panel 100. Once the trigger condition is met, the interface microcontroller 401 increments the step pointer by 1 and repeats the above sending and setting process until all steps in the process step sequence are executed.

[0065] During each step of the process, the connection topology between the N longitudinal wire harness endpoints is reconstructed in real time to a preset fault state without the need for manual plugging or unplugging of any connectors or replacement of samples. After each step stabilizes, the wire harness tester tests each endpoint and records the identification results, thereby verifying whether its fault detection capability meets the standards.

[0066] Throughout the process, the display and operation panel 100 can obtain the current step number, the executed connection group number, and the cumulative number of tests from the main microcontroller 201 in real time and display them graphically.

[0067] As can be seen from the above, the wire harness simulator provided by the present invention can completely digitize and program the traditional fault simulation process that relies on physical connections. The entire process of storage, parsing and execution control can be completed through the replaceable interface board 400, so that a complex automated calibration process can be physically transmitted and replicated.

[0068] The following example, calibrating an automotive wiring harness tester, details the structure and deployment of the wiring harness simulator of this invention, the detailed process of implementing the wiring harness fault simulation method, and the technical features and effects of the entire solution.

[0069] The wire harness simulator in this example uses a relay matrix configuration of M=5 and N=16, which means it has 5 independent connection relationships, corresponding to 16 wire harness endpoints.

[0070] The multiplexer module 202 on the control motherboard 200 consists of five CD4051 eight-to-one analog switch chips in a parallel expansion structure. The address selection lines A, B, and C of each chip are connected in parallel to the same address bus of the main microcontroller 201. The main microcontroller 201 is connected to the INHIBIT terminal (pin 6) of each CD4051 chip through five independent chip select signal lines to independently select the working state of each chip, thereby obtaining a total of 5×8=40 independent output channels, which is sufficient to cover and independently control all 80 relays.

[0071] The driver module 203 uses five ULN2003A Darlington array chips. The eight input pins of each ULN2003A chip are respectively connected to the eight output channels X0 to X7 of a CD4051 chip. The eight open-collector outputs of each ULN2003A chip are each connected to the driving terminal of a relay coil.

[0072] The main microcontroller 201 refreshes its firmware by polling each CD4051 chip at a fixed scanning frequency of 1kHz. In each scanning cycle, the main microcontroller 201 sequentially enables each chip select signal and sequentially outputs the channel address corresponding to each relay that needs to be activated on the address bus, thereby completing the rapid scanning and refreshing of all target relays.

[0073] The relay matrix board 300 is equipped with 80 signal relays with a rated drive voltage of 5V, arranged in 5 rows and 16 columns. Each relay coil has a freewheeling diode connected in reverse parallel across its two ends.

[0074] The interface board 400 is equipped with eight FAKRA coaxial sockets as output connectors 403. These eight sockets are numbered P1 to P8. The core wire and shielding layer of each socket are connected to a longitudinal wiring harness endpoint of the relay matrix, for a total of 16 endpoints corresponding one-to-one with N=16. The interface microcontroller 401 on the interface board 400 is an STC15W series microcontroller, and the non-volatile memory 402 is an AT24C512 EEPROM, capable of storing multiple configuration files.

[0075] The interface board 400 and the control motherboard 200 are connected by a dual-row pin header and female header connector, which carries power, UART communication bus and IO interaction signal lines.

[0076] The display and operation panel 100 is a 7-inch embedded touch screen industrial computer that runs a Linux system and is equipped with dedicated graphical interface software.

[0077] See Figure 6Before performing the calibration, the engineer first completed the physical deployment of the wire harness simulator 10: placing the instrument 10 in a suitable position on the test bench 20, connecting the display and operation panel 100 and the control motherboard 200 with a DB9 communication cable, and connecting the interface board 400 with the pre-programmed target calibration scheme to the corresponding interface on the control motherboard 200 via a dual-row pin header and female connector. A standard FAKRA test cable was then used to connect the P1-P8 sockets of the interface board 400 to the corresponding test ports of the wire harness tester being calibrated. Additionally, an IO interaction line was selected to connect the instrument's "Test Complete Input" port to the tester's "Detection End Output" port, and the instrument's "Ready Output" port to the tester's "Start Test Input" port.

[0078] After deployment, the configuration file is edited first. The operator clicks "New File" on the main interface of the display and operation panel 100, and enters the file name "SUV Main Harness Calibration". The system creates a blank configuration file, which by default contains 5 sets of blank connection relationships and empty process step sequences. The operator then enters the relationship settings interface (e.g., ...). Figure 3 The interface displays 5 horizontally oriented virtual conductors (connection relationships 1-5) and 16 vertically oriented virtual terminal lines (labeled as P1 core, P1 shield...P8 shield, respectively). Based on the possible fault modes of the SUV's main wiring harness, the operator edits connection relationship 1, illuminating the intersection of all corresponding shielded wires to set a fault of "interconnection short circuit of all shielding layers"; edits connection relationship 2, illuminating the intersection of P1 core and P3 core to set a fault of "short circuit between terminal 1 and terminal 3 core wires"; edits connection relationship 3, illuminating the intersection of P2 core with P4 and P6 cores to set a multi-point short circuit fault; connection relationships 4 and 5 are also configured with different short circuit or open circuit combinations as needed. After editing each group of relationships, the operator can switch to the next group to continue editing.

[0079] After all connections have been edited, the operator enters the process settings interface (e.g., Figure 4 In the drop-down menus for STEP1 to STEP5, select Connection Relationship 2, Connection Relationship 1, Connection Relationship 3, Connection Relationship 4, and Connection Relationship 5 respectively. Also, check the "IO Interaction" option to enable the hardware handshake function. Finally, click "Save".

[0080] After compiling the five binary matrices and process step table, the display and operation panel 100 sends them to the interface board 400 via the main microcontroller 201. The interface microcontroller 401 writes them, along with file information, into the non-volatile memory 402. The calibration scheme for the SUV main wiring harness is thus finalized and hardware-bound to the interface board 400. If calibration for another vehicle model (such as a sedan) is required in the future, the engineer only needs to replace the current interface board with another interface board pre-programmed according to the sedan wiring harness fault modes, without any on-site software configuration.

[0081] When calibration is required, the operator ensures the current active file is "SUV Main Wiring Harness Calibration" and then clicks the "Start Test" button. The display and operation panel 100 sends a start command to the interface microcontroller 401. The interface microcontroller 401 loads the flow table of the file from the EEPROM, sets the step pointer to STEP1, retrieves the matrix data of connection relationship 2 (short circuit between wires 1 and 3), packages it, and sends it to the main microcontroller 201 via the IIC bus.

[0082] The main microcontroller 201 parses the list of coordinates of all relays that need to be closed and immediately initiates a dynamic scanning and refreshing process: the main microcontroller 201 polls five CD4051 chips at a fixed frequency of 1kHz. In each scan, the main microcontroller 201 sequentially pulls down the chip select signal lines of each chip to enable the corresponding CD4051 chip. At the same time, it sequentially outputs the channel address of each relay that needs to be activated on the address bus. The high-level signal is sent to the input pin of the corresponding ULN2003A through the output channel of the corresponding CD4051, driving the corresponding Darlington transistor to saturate and conduct, thereby energizing and activating the corresponding relay coil. Since the scanning frequency (1kHz) is much higher than the mechanical response time of the relay contacts, coupled with the freewheeling effect of the coil inductance and the freewheeling diode, as well as the mechanical inertia of the armature, all relay contacts that should be activated remain stably closed throughout the entire scan cycle, without any jitter or accidental release. In less than 20 milliseconds, all target relays have been stably closed. At this point, the P1 and P3 pins of the interface board 400 have been short-circuited inside the instrument, while the remaining unspecified endpoints remain suspended.

[0083] After the main microcontroller 201 responds to the interface microcontroller 401, the interface microcontroller 401 controls the IO output port to send a "ready" signal to the wire harness tester. After the tester detects this signal, it starts a continuity scan of the 16 endpoints of the instrument. The tester should be able to identify the fault of "short circuit between P1 and P3" and record the result.

[0084] After the tester completes the test, it returns a "test complete" pulse through its output port. The I / O input port of the interface microcontroller 401 captures this pulse and uses it as a step switching trigger signal, immediately incrementing the step pointer to STEP2. The interface microcontroller 401 reads the matrix data of connection relationship 1 (all shielding layers are short-circuited) from the EEPROM and repeats the above process of sending, setting, scanning and refreshing, responding, and triggering, so that the wire harness simulator switches to the second fault state in a very short time, allowing the tester to continue testing.

[0085] The entire process runs automatically. After five steps, the interface microcontroller 401 sends a reset command to the main microcontroller 201 to release all relays and returns "process completed" information to the display and operation panel 100. The test count on the panel is incremented by 1.

[0086] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A wire harness simulator, comprising a display and operation panel (100) and a control unit, characterized in that: The control unit consists of a control motherboard (200), a relay matrix board (300), and an interface board (400); The relay matrix board (300) includes a relay array, which has M horizontal common nodes and N vertical wire harness endpoints. Each horizontal common node and each vertical wire harness endpoint is connected to a relay, forming an M-row × N-column matrix structure, where M and N are both integers greater than 1. The control motherboard (200) is equipped with a main microcontroller (201). The main microcontroller (201) is connected to each relay in the relay array through a drive circuit to independently control the activation and deactivation of each relay. The interface board (400) and the control motherboard (200) are connected by a pluggable electrical and communication connection, and the N longitudinal wire harness endpoints of the relay matrix board (300) can be brought out to connect to the test port of the wire harness tester being calibrated. The interface board (400) stores at least one configuration file, each configuration file containing M sets of connection relationship mapping data and process step sequence, the process step sequence specifying the order in which each set of connection relationship mapping data is called during the simulation process. The interface board (400) is configured to load and parse the configuration file, and after the simulation process starts, as the main control process engine, it sends the corresponding connection relationship mapping data to the main microcontroller (201) step by step according to the process step sequence, so that the main microcontroller (201) drives the corresponding relay to act according to the received connection relationship mapping data, thereby forming a predetermined connection topology between the N longitudinal wire harness endpoints to simulate the fault state or normal state of the wire harness.

2. The wire harness simulator according to claim 1, characterized in that: The interface board (400) is provided with an interface microcontroller (401), a non-volatile memory (402) and an output connector (403). The output connector (403) is used to bring out N longitudinal wire harness endpoints of the relay matrix board (300) for connection to the test port of the wire harness tester being calibrated. The non-volatile memory (402) is connected to the interface microcontroller (401) and is used to store at least one configuration file. The interface microcontroller (401) is communicatively connected to the main microcontroller (201) through the pluggable connection structure and is used to load and parse the configuration file.

3. The wire harness simulator according to claim 2, characterized in that: The interface microcontroller (401) on the interface board (400) is also used to receive the step switching trigger signal, and automatically advance to the next step of the process step sequence after receiving the signal, until the entire calibration process is completed; the step switching trigger signal is a signal received from the calibrated wire harness tester by the IO interaction interface set on the wire harness simulator, or a user manual trigger command received on the display and operation panel (100).

4. The wire harness simulator according to claim 1, characterized in that: The control motherboard (200) is also provided with a multiplexer module (202) and a driver module (203); the multiplexer module (202) includes at least one multiplexed analog switch chip, and the driver module (203) includes at least one Darlington transistor array chip; the address lines of the main microcontroller (201) are connected to the address selection terminal of the multiplexed analog switch chip, the output channel of the multiplexed analog switch chip is electrically connected to the input terminal of the Darlington transistor array chip, and the output terminal of the Darlington transistor array chip is connected to the drive coil of the relay.

5. The wire harness simulator according to claim 4, characterized in that: The multiplexer module (202) on the control motherboard (200) is composed of multiple multiplexed analog switch chips in a parallel expansion structure. The address selection lines of each chip are connected in parallel to the same set of address buses of the main microcontroller (201). The main microcontroller (201) selects each chip through independent chip select signal lines to expand the control channels.

6. The wire harness simulator according to claim 2, characterized in that: The output connector (403) is a plurality of FAKRA coaxial cable sockets, each FAKRA socket providing two electrical connection points; the number N of the longitudinal harness endpoints of the relay matrix board is equal to twice the number of the FAKRA sockets.

7. The wire harness simulator according to claim 1 or 3, characterized in that: The display and operation panel (100) provides a graphical interactive interface, which represents M sets of connection relationships as M independently editable virtual wires and N vertical wire bundle endpoints as N virtual terminal lines. Users define the connection relationship by lighting up the icons at the intersection of the virtual wires and virtual terminal lines. The display and operation panel (100) compiles the user-defined graphical connection relationship into the connection relationship mapping data and sends it to the interface microcontroller (401) to be stored in the non-volatile memory (402).

8. A method for simulating wire harness faults, characterized in that, The method, based on the wire harness simulator according to any one of claims 1-7, specifically includes the following steps: Step S1: Edit and generate a configuration file on the display and operation panel of the wire harness simulator, and store it in the non-volatile memory by the interface microcontroller; the configuration file contains multiple sets of connection relationship mapping data and process step sequence. Each set of connection relationship mapping data defines the on / off state between any two ends of multiple wire harness endpoints, and the process step sequence specifies which set of connection relationship mapping data to use in sequence. Step S2: After selecting and starting a configuration file, the interface microcontroller acts as the main control engine, reads the configuration file from the non-volatile memory, and executes the sequence of process steps. Step S3: The interface microcontroller obtains the connection relationship mapping data pointed to in the current step, and encapsulates it into a control command and sends it to the control motherboard. Step S4: The control motherboard controls the corresponding relays in its internal relay matrix to operate according to the control command, so that each terminal on the output connector of the wire harness simulator presents a predetermined connection topology to simulate a wire harness fault state or normal state. In step S5, after receiving the preset step switching trigger signal, the interface microcontroller automatically advances to the next step in the process step sequence and returns to step S3 until all steps are completed.

9. The wiring harness fault simulation method according to claim 8, characterized in that: The step switching trigger signal is a signal received from the calibrated wire harness tester via the IO interaction interface, or a user-manual trigger command received from the display and operation panel.

10. The wiring harness fault simulation method according to claim 8, characterized in that: Before step S1, the method further includes replacing the interface board; the non-volatile memory of the replaced interface board is pre-stored with a configuration file for another wire harness model, so that the wire harness simulator can quickly switch to the corresponding calibration scheme.

Images