Risc-v based full link configurable radar target detection circuit microsystem

Abstract

The application discloses a RISC-V-based full-link configurable radar target detection circuit microsystem, and aims to solve the problem that edge-end radar processing is difficult to consider full-link acceleration and parameter flexible configuration. The microsystem comprises a RISC-V processor and a configurable accelerator. The accelerator comprises a data distribution module, a multi-path parallel processing channel, a channel merging module and a configurable two-dimensional constant false alarm rate detection module, and constitutes a full-pipe detection link. Each channel is integrated with a configurable windowing module, an FFT module and a transpose module. The FFT module adopts a maximum point number common rotation factor storage and a multi-stage gating structure, so that the register level dynamic configuration of the FFT point number, the window function and the CFAR neighborhood size is realized with a small hardware overhead. The application has the advantages of low delay, low power consumption and multi-scene adaptation.

Description

Technical Field

[0001] This invention relates to the field of millimeter-wave radar target detection circuits, and in particular to a RISC-V-based fully configurable radar target detection circuit microsystem. Background Technology

[0002] In the field of millimeter-wave radar target detection, the echo of the transmitted frequency-modulated continuous wave signal is typically deskewed. Then, windowing and a two-dimensional fast Fourier transform are used to obtain the range-Doppler matrix. A constant false alarm rate (CFAR) detection algorithm is then applied to this matrix using a sliding window to distinguish noise from the target, ultimately outputting the detection result. This processing flow involves a large amount of real-time data computation, posing significant challenges to the real-time performance, low power consumption, and computing power of the processing unit, especially when applied to edge computing scenarios such as autonomous driving obstacle avoidance and gesture recognition.

[0003] Existing hardware solutions for radar target detection mainly fall into three categories. First, dedicated accelerators are designed for single algorithms such as Fast Fourier Transform (FFT) or Constant False Alarm Rate (CFR) detection. These solutions only accelerate local components and cannot form a complete link from echo input to detection result output. Frequent data transfer in the middle leads to high latency and poor real-time performance. Second, echo data is processed in software by powerful personal computers or high-computing platforms. While flexible, this approach suffers from high power consumption, large size, and significant processing latency, making it difficult to meet deployment requirements under resource-constrained edge environments. Third, fixed-function system-on-a-chip (SoC) accelerators are used, where parameters such as windowing type, Fourier transform points, chirp count, and detection threshold are fixed in hardware. Once the application scenario or radar parameters change, the hardware needs to be redesigned or significantly modified, resulting in poor reusability and high adaptation costs.

[0004] It is evident that existing technologies cannot simultaneously achieve end-to-end acceleration, low-power real-time processing, and flexible configurability of key parameters. Especially in edge intelligent perception scenarios that require adaptation to different numbers of sampling points, chirps, sliding window sizes, and threshold factors, there is an urgent need for a highly configurable radar target detection end-to-end acceleration circuit microsystem to simultaneously meet the requirements of low latency, low power consumption, and adaptability to diverse scenarios. Summary of the Invention

[0005] The technical problem to be solved by this invention is that edge radar processing is difficult to balance full-link acceleration and flexible parameter configuration.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is: a RISC-V-based full-link configurable radar target detection circuit microsystem, comprising: a RISC-V-based detection processor and a configurable radar baseband signal processing accelerator; The detection processor is used to configure the parameters of the configurable radar baseband signal processing accelerator and control the transmission of radar echo data. The configurable radar baseband signal processing accelerator includes a data distribution module, multiple single-channel baseband signal processing modules, a channel merging module, and a configurable two-dimensional constant false alarm rate detection module; the data distribution module is used to cyclically distribute the serially input radar echo data to multiple parallel channels so that they are respectively input to the corresponding single-channel baseband signal processing modules. Each of the single-channel baseband signal processing modules includes at least a configurable range-dimensional fast Fourier transform module and a configurable Doppler-dimensional fast Fourier transform module, used to generate a range-Doppler matrix according to the parameters configured; Both the configurable distance-dimensional fast Fourier transform module and the configurable Doppler-dimensional fast Fourier transform module adopt a rotation factor storage unit based on the maximum number of shared points and a multi-stage pipeline gating structure to dynamically adjust the effective number of Fourier transform operations and the rotation factor index mapping according to the parameter configuration. The channel merging module is used to merge the range-Doppler matrices output by multiple single-channel baseband signal processing modules to generate a single range-Doppler energy matrix. The configurable two-dimensional constant false alarm rate (CFAR) detection module is used to perform two-dimensional CFAR target detection on the range-Doppler energy matrix according to the parameter configuration, and output structured target detection information. The parameter configuration supports dynamic setting of at least the number of distance-dimensional Fourier transform points, the number of Doppler-dimensional Fourier transform points, the window function type, and the neighborhood size for two-dimensional constant false alarm rate detection.

[0007] Furthermore, each of the single-channel baseband signal processing modules includes, in sequence according to the data flow direction: a configurable range Viga window module, a configurable range fast Fourier transform module, a configurable Doppler Viga window and zero-frequency shift module, a matrix transpose module, and a configurable Doppler fast Fourier transform module. The configurable range-dimensional windowing module is used to window the radar echo data according to the windowing function type and the number of range-dimensional Fourier transform points in the parameter configuration. The configurable Doppler Viga window and zero-frequency shifting module is used to perform Doppler Viga windowing and shift the zero frequency to the center of the spectrum. The matrix transpose module is used to convert the data stream from continuous according to the distance dimension to sequential output according to the continuous Doppler dimension index under the same distance unit, so as to adapt to the subsequent Doppler dimension fast Fourier transform processing.

[0008] Furthermore, both the configurable distance-dimensional fast Fourier transform module and the configurable Doppler-dimensional fast Fourier transform module contain a rotation factor address decoding unit. This rotation factor address decoding unit is used to dynamically map the rotation factor index of Fourier transforms with different point counts to the rotation factor index space corresponding to the maximum number of points by left shifting operations, based on the current operation level and the number of Fourier transform points configured. This enables the sharing of the same set of basic rotation factor parameters under different configured point counts.

[0009] Furthermore, the rotation factor storage unit based on the maximum number of shared points only stores the basic rotation factor for a quarter period of the maximum Fourier transform points; and, through quadrant index gating, real-virtual swapping, and sign flipping, a complete rotation factor is generated from the basic rotation factor.

[0010] Furthermore, both the configurable distance Vega window module and the configurable Doppler Vega window and zero-frequency shift module support the configuration of multiple window function types, including at least rectangular window, Hanning window, Hamming window and Kaiser window.

[0011] Furthermore, the configurable Doppler windowing and zero-frequency shifting module is specifically used for: for the same Doppler index, different distance cells share the same Doppler window coefficients; and, according to the parity of the Doppler index, the windowed data is alternately multiplied by a positive one or a negative one to shift the Doppler zero-frequency component to the center position of the Doppler fast Fourier transform output spectrum.

[0012] Furthermore, the matrix transpose module includes two alternately operating buffers, used to convert two-dimensional data blocks that are continuously input according to distance units into sequential output according to Doppler dimensions by address remapping within the same frame; and the address control logic of the matrix transpose module automatically adjusts the read and write addresses according to the distance dimension and Doppler dimension size in the parameter configuration.

[0013] Furthermore, the channel merging module is specifically used to calculate the power spectrum of the complex distance-Doppler matrix output by each single-channel baseband signal processing module in parallel, and to sum the power spectra of all channels point by point to achieve incoherent accumulation.

[0014] Furthermore, the configurable two-dimensional constant false alarm rate (CFAR) detection module is configured to: when constructing the sliding detection window, set the size of the protection unit to zero, and directly sum the data within the reference unit range determined by the reference unit distance dimension and reference unit Doppler dimension in the parameter configuration to estimate the background noise energy; wherein, during the summation, if the reference unit range exceeds the boundary of the distance-Doppler energy matrix, the index is subjected to modulo loopback or zero-padding according to the boundary processing mode set in the parameter configuration; and, the adaptive decision threshold is calculated by replacing the divider with a shifter and multiplier.

[0015] Furthermore, the detection processor, through the configuration of a direct memory access module, enables the transfer of radar echo data between the external memory and the configurable radar baseband signal processing accelerator, as well as the backhaul of the structured target detection information; the structured target detection information includes target decision results, range index, Doppler index, background noise energy estimate, energy value of the target unit, and frame target statistics.

[0016] The beneficial effects of this invention are as follows: By heterogeneously collaborating a RISC-V-based detection processor with a full-link baseband signal processing accelerator containing configurable range-dimensional and Doppler-dimensional fast Fourier transform modules, and employing a shared rotation factor storage unit with a maximum number of points and a multi-stage pipelined gating structure in the Fourier transform module, a complete pipelined hardware acceleration for radar echo data from the time domain to the detection result output is achieved. This scheme enables the system to dynamically configure key parameters such as the number of Fourier transform points, the type of windowing function, and the size of the two-dimensional constant false alarm rate detection neighborhood with extremely low storage overhead and logic resources. This ensures that real-time throughput and deterministic processing latency are maintained while adapting to different radar frame structures and operating modes, while also achieving a comprehensive technical effect of low power consumption, lightweight hardware overhead, and flexible adaptation to multiple scenarios. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a configurable multi-channel radar baseband signal processing accelerator architecture according to an embodiment of the present invention; Figure 2 This is a flowchart of the radar target detection pipeline processing according to an embodiment of the present invention; Figure 3This is a configurable distance Vega window architecture diagram according to an embodiment of the present invention; Figure 4 This is a configurable FFT architecture diagram according to an embodiment of the present invention; Figure 5 This is a diagram of a configurable Doppler window and zero-frequency shifting module according to an embodiment of the present invention; Figure 6 This is a matrix transpose architecture diagram according to an embodiment of the present invention; Figure 7 This is a configurable two-dimensional CFAR detection architecture diagram according to an embodiment of the present invention; Figure 8 This is a diagram of a configurable radar baseband signal processing SoC architecture based on RISC-V, according to an embodiment of the present invention. Figure 9 This is a system operation flowchart of an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be noted that the descriptions involving "first," "second," etc., in this invention are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Furthermore, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0021] An embodiment of the present invention is: a RISC-V-based full-link configurable radar target detection circuit microsystem, comprising: a RISC-V-based detection processor and a configurable radar baseband signal processing accelerator; The detection processor is used to configure the parameters of the configurable radar baseband signal processing accelerator and control the transmission of radar echo data. The configurable radar baseband signal processing accelerator includes a data distribution module, multiple single-channel baseband signal processing modules, a channel merging module, and a configurable two-dimensional constant false alarm rate detection module; the data distribution module is used to cyclically distribute the serially input radar echo data to multiple parallel channels so that they are respectively input to the corresponding single-channel baseband signal processing modules. Each of the single-channel baseband signal processing modules includes at least a configurable range-dimensional fast Fourier transform module and a configurable Doppler-dimensional fast Fourier transform module, used to generate a range-Doppler matrix according to the parameters configured; Both the configurable distance-dimensional fast Fourier transform module and the configurable Doppler-dimensional fast Fourier transform module adopt a rotation factor storage unit based on the maximum number of shared points and a multi-stage pipeline gating structure to dynamically adjust the effective number of Fourier transform operations and the rotation factor index mapping according to the parameter configuration. The channel merging module is used to merge the range-Doppler matrices output by multiple single-channel baseband signal processing modules to generate a single range-Doppler energy matrix. The configurable two-dimensional constant false alarm rate (CFAR) detection module is used to perform two-dimensional CFAR target detection on the range-Doppler energy matrix according to the parameter configuration, and output structured target detection information. The parameter configuration supports dynamic setting of at least the number of distance-dimensional Fourier transform points, the number of Doppler-dimensional Fourier transform points, the window function type, and the neighborhood size for two-dimensional constant false alarm rate detection.

[0022] In a specific embodiment, the detection processor is configured with a direct memory access module to realize the transfer of radar echo data between the external memory and the configurable radar baseband signal processing accelerator, as well as the back transmission of the structured target detection information; the structured target detection information includes target decision results, range index, Doppler index, background noise energy estimate, energy value of the target unit, and frame target statistics.

[0023] In this embodiment, as Figure 8As shown, the RISC-V-based detection processor and the configurable radar baseband signal processing accelerator are interconnected via a bus, forming a heterogeneous accelerated SoC architecture. Parameter configuration is achieved through a set of configurable registers, including range dimension configuration registers, Doppler dimension configuration registers, and mean-like filter configuration registers. Specifically, the range dimension configuration registers include data input type configuration registers, window function type configuration registers, and chirp length configuration registers; the Doppler dimension configuration registers include chirp group number configuration registers, Doppler dimension window function type configuration registers, and Doppler dimension FFT configuration registers; the mean-like filter configuration registers include mean-like filter boundary mode configuration registers, threshold factor configuration registers, reference cell range dimension size configuration registers, and reference cell Doppler dimension size configuration registers. Table 1 details each configuration parameter. By configuring register parameters covering the entire link, the system can flexibly adapt key parameters such as chirp length, chirp number, window function type, detection neighborhood size, and boundary mode under different radar frame structures, providing higher scenario adaptability compared to traditional fixed single-parameter solutions.

[0024] Table 1: Introduction to configurable table parameters. like Figure 1 As shown, the configurable radar baseband signal processing accelerator also includes an AXI interface module. The AXI interface module includes an AXI-Lite interface and an AXI-Stream interface. The AXI-Lite interface is used to receive address offset and register configuration information transmitted by the processor module, while the AXI-Stream interface is used to complete high-speed streaming transmission of radar echo data and target detection result data. Both interfaces are designed entirely according to the AMBA bus standard protocol, enabling the accelerator to be easily mounted into a SoC as an IP core. The data allocation module cyclically distributes the continuously serially input radar echo data to four parallel single-channel baseband signal processing modules according to channel order. A single chirp data is transmitted one data point per cycle in the order {RX0, RX1, RX2, RX3}. The data allocation module allocates data to the corresponding processing module cycle by cycle and channel by channel, realizing parallel processing of multi-channel data and effectively improving system throughput.

[0025] In a specific embodiment, each of the single-channel baseband signal processing modules includes, in sequence according to the data flow direction: a configurable range Viga window module, a configurable range fast Fourier transform module, a configurable Doppler Viga window and zero-frequency shift module, a matrix transpose module, and a configurable Doppler fast Fourier transform module. The configurable range-dimensional windowing module is used to window the radar echo data according to the windowing function type and the number of range-dimensional Fourier transform points in the parameter configuration. The configurable Doppler Viga window and zero-frequency shifting module is used to perform Doppler Viga windowing and shift the zero frequency to the center of the spectrum. The matrix transpose module is used to convert the data stream from continuous according to the distance dimension to sequential output according to the continuous Doppler dimension index under the same distance unit, so as to adapt to the subsequent Doppler dimension fast Fourier transform processing.

[0026] In this embodiment, as Figure 2 As shown, the overall pipeline processing flow is as follows: the echo data sequentially passes through a configurable range-dimensional windowing module, a configurable range-dimensional fast Fourier transform module, a configurable Doppler-dimensional windowing and zero-frequency shifting module, a matrix transpose module, and a configurable Doppler-dimensional fast Fourier transform module, outputting a range-Doppler matrix. The configurable range-dimensional windowing module is used to window the radar echo data to suppress spectral leakage; the configurable range-dimensional fast Fourier transform module is used to convert single chirp data from the time domain to the frequency domain to evaluate target range; the configurable Doppler-dimensional windowing and zero-frequency shifting module is used to window each group of chirp frequency domain data and shift the center frequency of the chirp signal to facilitate subsequent differentiation of velocity direction information; the matrix transpose module is used to convert single chirp stream data into multi-chirp stream data to facilitate subsequent Doppler-dimensional FFT processing; and the configurable Doppler-dimensional fast Fourier transform module is used to extract phase information from multiple groups of radar chirp frequency domain data to evaluate target velocity. The entire radar baseband processing link adopts a hybrid pipelined architecture combining streaming front-end processing, frame-level transposition buffering, and sliding window detection. Preprocessing, range-dimensional windowing, range-dimensional FFT, and Doppler-dimensional windowing with the zero-frequency shift module can be started continuously with a single chirp data stream. However, the Doppler-dimensional FFT requires complete chirp data within the same range bin before forming a slow-time dimension input sequence and performing the FFT operation. Once the Doppler-dimensional FFT calculation begins, the results of each calculation are directly transmitted to the detection module for processing, achieving pipelined processing. This significantly reduces memory read / write operations and latency, ensuring real-time throughput.

[0027] In a specific embodiment, both the configurable distance-dimensional fast Fourier transform module and the configurable Doppler-dimensional fast Fourier transform module contain a rotation factor address decoding unit. This rotation factor address decoding unit is used to dynamically map the rotation factor index of Fourier transforms with different point counts to the rotation factor index space corresponding to the maximum number of points by left shifting operations, based on the current operation level and the number of Fourier transform points configured by the parameter configuration. This enables the sharing of the same set of basic rotation factor parameters under different configuration point counts.

[0028] Specifically, the rotation factor storage unit based on the maximum number of shared points only stores the basic rotation factor for a quarter period of the maximum Fourier transform points; and, through quadrant index gating, real-virtual swapping, and sign flipping, a complete rotation factor is generated from the basic rotation factor.

[0029] In this embodiment, as Figure 4 As shown, the configurable range-dimensional Fast Fourier Transform (FFT) module employs a step-by-step butterfly operation structure to perform FFT processing. The configurable range-dimensional FFT module converts the input single-chirp windowed time-domain data into frequency-domain data to obtain the target range-dimensional spectrum information, thereby achieving frequency decomposition of the radar echo in the range dimension. Its expression is as follows: Where k is the frequency index of the distance FFT output, N is the number of distance-dimensional FFT points, and the rotation factor is... The module supports The configurable length is a power of 2, therefore, the configurable number of levels includes... In actual hardware execution, the input is first passed through a FIFO module to facilitate handshaking between upstream and downstream modules. Then, the input data is encoded according to its address index, and butterfly operations are performed at each stage. The configurable distance-dimensional Fast Fourier Transform module uses a step-by-step butterfly operation structure to complete the FFT processing. Let the current FFT operation level be... , and have Where P is the total number of levels corresponding to the currently configured FFT points. Each butterfly operation is generated by the address decoding unit, which produces the data read address, data write address, and twiddle factor index required for the current level. The butterfly operation unit then performs complex number addition and subtraction and twiddle factor multiplication. In the... In a butterfly operation, let the two input complex data of the butterfly operation unit be: in, and Given two input complex data channels or two output complex data channels from the previous stage, this module's hardware implementation uses a butterfly output structure with one channel for summation (through-through) and one channel for difference (through-rotation). The corresponding butterfly operation is as follows: in, This refers to the rotation factor for the specific index of the corresponding level. Furthermore, these rotation factors are not stored separately for different FFT point counts; instead, they share a single set of rotation factor parameters based on the maximum supported FFT point count. Let the maximum supported point count be: in, To maximize the supported configuration parameter length, the corresponding address decoding unit generates the rotation factor address based on the current level number, the current FFT point configuration, and the low-order bits of the butterfly index. The address adjustment method is as follows: in, This represents the corresponding stage number in the calculation process. This is a local index of the twiddle factor within the current operation level, used to indicate the position of the current butterfly unit within the twiddle factor repetition cycle of this level. It can be expressed as: in, Used to count the butterfly units within the current level, This indicates the number of low-order bits required for current-level truncation factor addressing. It will be performed within the current computing level according to The periodic changes are used to generate the twitch factor phase required for this level of butterfly unit. Based on the address bits corresponding to the current operation level, the address decoding unit uses a left shift operation to uniformly map the twitch factor indices for different FFT point counts and levels to the index space of the maximum FFT point count, allowing FFTs with different point counts to share the same set of twitch factor parameters. Because the twitch factor has periodicity and quadrant symmetry, the twitch factor storage unit does not need to store the twitch factor for the entire period, but only the basic twitch factor corresponding to one-quarter of the period for the maximum FFT point count. Let the length of the one-quarter table be: Let the base rotation factor read from the quarter rotation factor table be: The complete rotation factor is generated from the quadrant index q through MUX gating, real-imaginary swapping, and sign reversal: Based on the configured parameter length, when completed After the butterfly operation, the configurable distance-dimensional fast Fourier transform module outputs distance-dimensional frequency domain data as follows: The output of the final stage is then selected via the MUX, and the module uses two banks to alternate outputs to ensure data continuity. Specifically, it has the following advantages: 1. With configurable length gating output, it can support the length of a single radar echo and the scenario requirements of multiple chirp configurations.

[0030] 2. By using the FFT twiddle factor index with the maximum number of points and the four-quadrant sign conversion method, the twiddle factor parameters required for caching can be reduced to the extreme, thereby reducing caching requirements.

[0031] 3. Reducing the amount of computation and storage will effectively reduce system energy consumption, finding a better balance between hardware performance and power consumption.

[0032] In a specific embodiment, the configurable distance Vega window module and the configurable Doppler Vega window and zero-frequency shift module both support the configurability of multiple window function types, including at least rectangular window, Hanning window, Hamming window and Kaiser window.

[0033] In this embodiment, as Figure 3 The configurable range Vega window architecture shown has radar echo data composed of signed real and imaginary data, and its data format is as follows: Where n is the index of the fast-time sampling point in the distance dimension, and m is the chirp index in the slow-time dimension of the Doppler dimension. The configurable distance-dimensional windowing process is as follows: in, The output is processed using a distance Vega window. This is window function data. The configurable distance dimension windowing module determines the current distance dimension processing length based on the distance dimension point count configuration parameter. Let the configuration parameter be... ,Right now: Then the current distance dimension number for: At the same time, each length corresponds to four window function types, namely: in, For the first kind of zeroth order modified Bessel function, In the hardware implementation, the window coefficient is represented using Q15 fixed-point, and its conversion relationship is as follows: At the same time, the corresponding windowing calculation also requires saturation truncation, therefore, the corresponding real part output is: The imaginary part output is: The windowed output is: Specifically, it has the following advantages: 1. Supports multiple window function lengths to adapt to different distance dimension sampling point requirements.

[0034] 2. Supports multiple window function types, which can adapt to the configuration requirements of different signal-to-noise ratio scenarios.

[0035] In a specific embodiment, the configurable Doppler windowing and zero-frequency shifting module is specifically used to: for the same Doppler index, different distance cells share the same Doppler window coefficients; and, according to the parity of the Doppler index, alternately multiply the windowed data by a positive one or a negative one to shift the Doppler zero-frequency component to the center position of the Doppler fast Fourier transform output spectrum.

[0036] In this embodiment, the configurable Doppler Vickers window and zero-frequency shifting module is used to perform Doppler Vickers windowing on the complex frequency domain data after the range-dimensional FFT output, and to perform a slow-time-dimensional zero-frequency shifting operation after windowing to suppress Doppler spectral leakage and shift the Doppler zero-frequency component to the center frequency position in the subsequent Doppler FFT output. The structural diagram is shown below. Figure 5 As shown. The module receives a complex data stream from the distance-dimensional FFT module, and its input data consists of signed real part data. With imaginary data Composition, data format is: Similarly, the corresponding window function type and window length can be selected by configuring parameters, i.e., let the configuration parameters be... ,Right now: Then the current Dopplerweis points for: At the same time, each length corresponds to four window function types, namely: in, For the first kind of zeroth order modified Bessel function, That is, in the hardware implementation, the window coefficient is represented using Q15 fixed-point, and its conversion relationship is as follows: Since Doppler processing is performed along the chirp direction, the windowing coefficients remain consistent across all distance bins within the same chirp. After the range-dimensional FFT data for a set of chirps is output, the chirp index is updated, and the next set of Doppler window coefficients is read; that is, all distance bins within the same chirp share the same Doppler window coefficients. Simultaneously, the corresponding windowing calculation also requires saturation truncation, thus obtaining the real part... The output is: virtual part The output is: The Doppler Viga window output is: in, The output data after the Doppler Viga window. Let be the coefficients of the Doppler window function corresponding to the m-th chirp. After completing the Doppler windowing, the module further performs zero-frequency shifting based on the parity of the chirp index, so that the subsequent output can be directly determined as positive or negative according to the intermediate index of the Doppler dimension. This is expressed as: .

[0037] In a specific embodiment, the matrix transpose module includes two alternately operating buffers, which are used to convert two-dimensional data blocks that are continuously input according to distance units into sequential output according to Doppler dimensions by address remapping within the same frame; and the address control logic of the matrix transpose module automatically adjusts the read and write addresses according to the distance dimension and Doppler dimension size in the parameter configuration.

[0038] In this embodiment, as Figure 6 As shown, the matrix transpose module caches and transposes the two-dimensional radar data after the configurable Doppler windowing and zero-frequency shifting module, so that the data input in the order of the range dimension bin within a single chirp is rearranged into the data output in the order of the chirp dimension under the same range bin, thereby meeting the input requirements of the subsequent configurable Doppler fast Fourier transform module for slow-time dimension continuous data. The two-dimensional radar matrix after the configurable Doppler windowing and zero-frequency shifting module... The input order is: The output data stream is output in ascending order of chirp dimensions within the same distance bin, and the output order is as follows: Therefore, the address decoding module will write the address based on the distance bin index k and chirp index m. The update, namely: The determination of whether the current frame has been fully buffered is based on the configured input data type, distance dimension size configuration parameters, and Doppler dimension size configuration. The corresponding relationships are as follows: After the entire frame of data F is buffered, the address decoding module will read the address based on the distance bin index k and chirp index m. The update, namely: Therefore, the matrix transpose module outputs: Right now, .

[0039] In a specific embodiment, the channel merging module is specifically used to calculate the power spectrum of the complex distance-Doppler matrix output by each single-channel baseband signal processing module in parallel, and to sum the power spectra of all channels point by point to achieve incoherent accumulation.

[0040] In this embodiment, the channel merging module performs power spectrum merging processing on the outputs of four single-channel configurable Doppler Fast Fourier Transform (FFT) modules to achieve incoherent accumulation of multi-channel radar data, thereby improving the target detection signal-to-noise ratio and suppressing random noise. The module receives Doppler FFT output data from multiple channels and performs point-by-point power calculation and accumulation operations on it, finally outputting the merged multi-channel Doppler power spectrum. The Doppler FFT output for the c-th channel is: The channel merging module performs power calculations on the complex frequency domain data of each channel in parallel, which is expressed as follows: After solving the power spectrum, point-by-point accumulation is performed to achieve incoherent accumulation, which can be expressed as: Where C represents the total number of channels, i.e., 4 channels. This is the power spectrum output after multi-channel merging.

[0041] Through incoherent accumulation, the power of the target signal in multiple channels is superimposed in phase, while the power of uncorrelated random noise between channels is partially canceled out, which effectively improves the signal-to-noise ratio of the input two-dimensional constant false alarm rate detector and increases the detection probability of weak targets.

[0042] In a specific embodiment, the configurable two-dimensional constant false alarm rate (CFAR) detection module is configured to: when constructing the sliding detection window, set the size of the protection unit to zero, and directly sum the data within the reference unit range determined by the reference unit distance dimension and reference unit Doppler dimension in the parameter configuration to estimate the background noise energy; wherein, during the summation, if the reference unit range exceeds the boundary of the distance-Doppler energy matrix, the index is subjected to modulo loopback or zero-padding according to the boundary processing mode set in the parameter configuration; and, the adaptive decision threshold is calculated by replacing the divider with a shifter and multiplier.

[0043] In this embodiment, the configurable two-dimensional constant false alarm rate (CFAR) detection module is used to perform adaptive target detection processing on the range-Doppler energy matrix output by the channel merging module, so as to achieve robust detection of target signals under complex noise backgrounds. The configurable two-dimensional CFAR detection module constructs sliding detection windows in the range and Doppler dimensions, respectively, including: a target cell (CUT), a guard cell, and a reference cell. The configurable two-dimensional CFAR detection module is configured according to the neighborhood size in the range dimension. Doppler neighbor size configuration Each reference cell size is set, with configuration values ​​ranging from 3 to 5. A two-dimensional neighborhood sliding window is constructed centered on the current cell to be detected. At this point, the corresponding neighborhood range in the distance dimension is: Similarly, the neighborhood range in the Doppler direction is: Therefore, the corresponding neighborhood range is: Therefore, for the unit under test The power within the reference cell is statistically analyzed to estimate the background noise level. In actual hardware design, the sliding window directly sums the data within the neighborhood, which also includes the actual value of the cell under test. This approach is more pipeline-friendly for hardware design. This can be expressed as: in, It is important to emphasize that, considering hardware complexity, the protection unit design of this invention is zero. Although this results in some loss of precision, it significantly reduces hardware complexity, thereby reducing hardware area and power consumption. Simultaneously, converting the division logic into multiplication logic also reduces computational complexity. In the actual module design, the structure diagram is as follows... Figure 7As shown, the configurable two-dimensional constant false alarm rate (CFAR) detection module first performs address encoding and data buffering on the output of the channel merging module. Then, it sums the data within the surrounding neighborhood to obtain the background noise result. The neighborhood range varies depending on the boundary configuration method. In the boundary loopback method, the index is moduloed to obtain a new index value, and the corresponding data is selected as the neighborhood data. In the boundary zero-padding method, the neighborhood range exceeding the index is directly set to 0. This is based on a configurable threshold factor. The threshold value is obtained by multiplying it with the background noise and comparing it with the energy of the cell under test. This can be expressed as: Finally, the judgment result and related information are structured and encapsulated for output, including a 1-bit target flag, 8 bits of all zeros, an 11-bit target row index, a 1-bit 0, an 11-bit target column index, a 32-bit frame target statistics, a 32-bit noise energy value, a 9-bit 0, and a 23-bit CUT energy value. The bits are concatenated in the field order to represent the judgment result, row and column coordinates, noise statistics, CUT energy value, and frame target number, forming a fixed-format structured output data.

[0044] This invention is based on a 28nm process, operates at a clock speed of 500MHz, and uses a supply voltage of 0.81V. Performance, power consumption, and area analyses were performed on the proposed configurable baseband signal processing accelerator, as shown in Table 2. (Where, latency is...) As can be seen from the configuration, the configurable baseband signal processing accelerator of the present invention has the characteristics of low latency, low power consumption, and lightweight.

[0045] Table 2: PPA data for configurable baseband signal processing accelerators. The delay mentioned here is the pure algorithm delay, excluding the intermediate delay caused by the actual radar pulse repetition period.

[0046] By mounting a configurable baseband signal processing accelerator on a RISC-V architecture, the configurable baseband signal processing proposed in this invention is combined with RISC-V to realize a RISC-V-based end-to-end configurable radar target detection circuit SoC. The overall SoC architecture diagram is shown below. Figure 8 As shown, this method enables heterogeneous acceleration of radar target detection, thereby reducing the data processing pressure on the RISC-V core and improving the system's response speed.

[0047] Then, based on Xilinx's Artix-7 200T series FPGA chip (specifically, chip model: xc7a200tsbg484-1), the full-link configurable radar target detection circuit microsystem proposed in this invention was implemented in hardware. The main clock frequency was 50MHz, and the amount of resources consumed is shown in Table 3. Since the full-link configurable radar target detection circuit SoC proposed in this invention is a lightweight, low-power module, the overall SoC consumes fewer resources after being implemented on an FPGA, and it is also easy to integrate with downstream application modules such as clustering, tracking, autonomous driving obstacle avoidance, and gesture recognition.

[0048] Table 3: Resource consumption of configurable baseband signal processing SoC based on FPGA. It should be noted that this invention includes four single-channel baseband signal processing accelerators, which are divided into two output paths at output. One path buffers the single-frame distance-Doppler matrix of the channel (to facilitate subsequent angle measurement algorithm processing), and the other path is transmitted to the channel merging module. Therefore, the actual BRAM usage is relatively large.

[0049] After implementation using FPGA, the workflow of the entire target detection system is as follows: Figure 9 As shown, each box indicates the module that executes that part of the process. For example, processes such as system initialization, parameter configuration, DMA scheduling, DDR3 memory access, and result reading are completed by the RISC-V processor in conjunction with the DMA module, MIG controller, and DDR3 memory; processes such as radar baseband signal processing and two-dimensional CFAR target detection are executed by a configurable baseband signal accelerator. A detailed description of the system workflow is as follows: 1. The FPGA system and peripherals are powered on and start up, completing hardware initialization; including the generation of basic clocks on the RISC-V processor side and the FPGA logic side, reset release, on-chip interconnect, TileLink to AXI protocol bridge, AXI Interconnect, MIG controller, DDR3 memory, DMA module and single-channel baseband signal accelerator are brought into an accessible or configurable state.

[0050] 2. The RISC-V processor configures basic peripherals and the operating environment; this includes configuring the operating modes of peripherals or interfaces such as the UART / JTA debug interface, GPIO, timers, interrupt controller, DMA control interface, and MIG controller status interface, for subsequent data transmission, DDR3 memory access, status interaction, and debug output. The task completion status can be obtained via interrupts or by polling the status register.

[0051] 3. Configure the parameters of the single-channel baseband signal accelerator of the RISC-V processor; send the parameter configuration information required for the current frame processing through the register or memory mapping control interface. The parameter configuration information includes one or more of the following: frame size, distance dimension FFT points, Doppler dimension FFT points, window function parameters, two-dimensional CFAR detection window parameters, threshold parameters, boundary processing mode and output format parameters, and enable the accelerator to enter the waiting state.

[0052] 4. The RISC-V processor completes DMA transfer initialization, including DMA read / write channel configuration, DDR3 input and output buffer address / length settings, transfer control register configuration, and data bit width and burst transfer strategy configuration aligned with the accelerator data interface. The MIG controller is used to perform memory access control between the AXI Interconnect and the DDR3 memory; the DMA module accesses the DDR3 memory through the AXI Interconnect. In embodiments supporting descriptor mode, DMA transfer may also include descriptor configuration.

[0053] 5. The RISC-V processor initiates the DMA return channel, making the DDR3 output buffer receptive; subsequently, it starts the single-channel baseband signal accelerator and the DMA packet transmission channel, sending the frame data to be detected stored in the DDR3 input buffer to the single-channel baseband signal accelerator. The frame data is the radar baseband data to be processed or the radar frame data before range-Doppler processing, and is continuously input to the accelerator input port via the DMA MM2S read channel according to a preset data format.

[0054] 6. The single-channel baseband signal accelerator performs radar baseband signal processing on the received frame data; the processing flow includes, in sequence: range window function processing, range FFT, Doppler window function processing, transpose buffer, Doppler FFT and power calculation.

[0055] 7. After the accelerator completes the power calculation, it enters the two-dimensional CFAR sliding window target detection stage; this stage includes: row / column data caching, construction of training unit and guard unit windows, background noise solution, threshold calculation, target decision and detection result integration.

[0056] 8. The accelerator outputs the detection results to the DMA return channel; the output data may include the target decision result, the target distance index and Doppler index, the corresponding energy value, noise statistics, threshold value, and frame-level statistics, and is packaged and output according to a predetermined data format. The DMA's S2MM write channel writes the accelerator output results to the DDR3 output buffer via AXI Interconnect and the MIG controller.

[0057] 9. The RISC-V processor determines "Frame processing complete?" based on the DMA status register, accelerator status register, or interrupt signal. If the current frame has not yet been processed, it continues to wait for the current transmission and acceleration processing to complete, or continues to execute the subsequent data transfer of the current frame according to the segmented transmission strategy. If the current frame has been processed, the RISC-V processor reads the detection result through the DDR3 output buffer and enters the subsequent result processing, caching, reporting, or display process.

[0058] 10. The RISC-V processor sends the final detection results to external devices via UART and JTAG for display on the host computer, data recording, and subsequent clustering or target tracking processing.

[0059] In summary, the RISC-V-based end-to-end configurable radar target detection circuit microsystem provided by this invention achieves end-to-end heterogeneous acceleration of radar target detection by mounting the end-to-end parameter configurable acceleration module on the RISC-V processor and employing a pipelined architecture and register-level parameter configuration mechanism to reduce memory read-and-write operations. The system possesses high configurability in key dimensions such as chirp length, chirp number, windowing function type, detection size, and boundary mode. It can maintain real-time throughput and deterministic latency under different radar frame structures and output structured data containing information such as decision results, range index, velocity index, target quantity, noise energy, and target energy. Specifically, the system achieves variable-point Fourier transform with minimal hardware overhead by using a shared rotation factor storage unit and a multi-stage pipelined gating structure in the configurable range-dimensional and Doppler-dimensional fast Fourier transform modules. By setting the protection unit size to zero and replacing division with shift and multiplication, the hardware complexity of two-dimensional constant false alarm rate (CFAR) detection is simplified. The matrix transpose module's dual-buffer alternation mechanism and automatic address adjustment adapt to the processing requirements of different frame structures. The incoherent accumulation of the channel merging module improves the target detection signal-to-noise ratio. The synergistic application of these technologies gives the system a comprehensive advantage of low latency, low power consumption, small footprint, and flexible adaptability to various scenarios. This facilitates integration with downstream clustering, target tracking, and trajectory fusion algorithms, providing high-efficiency and portable target detection capabilities for various radar edge intelligence applications such as autonomous driving obstacle avoidance, pedestrian / vehicle detection, and gesture and posture recognition.

[0060] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A RISC-V-based fully configurable radar target detection circuit microsystem, characterized in that, include: RISC-V based detection processor and configurable radar baseband signal processing accelerator; The detection processor is used to configure the parameters of the configurable radar baseband signal processing accelerator and control the transmission of radar echo data. The configurable radar baseband signal processing accelerator includes a data distribution module, multiple single-channel baseband signal processing modules, a channel merging module, and a configurable two-dimensional constant false alarm rate detection module; the data distribution module is used to cyclically distribute the serially input radar echo data to multiple parallel channels so that they are respectively input to the corresponding single-channel baseband signal processing modules. Each of the single-channel baseband signal processing modules includes at least a configurable range-dimensional fast Fourier transform module and a configurable Doppler-dimensional fast Fourier transform module, used to generate a range-Doppler matrix according to the parameters configured; Both the configurable distance-dimensional fast Fourier transform module and the configurable Doppler-dimensional fast Fourier transform module adopt a rotation factor storage unit based on the maximum number of shared points and a multi-stage pipeline gating structure to dynamically adjust the effective number of Fourier transform operations and the rotation factor index mapping according to the parameter configuration. The channel merging module is used to merge the range-Doppler matrices output by multiple single-channel baseband signal processing modules to generate a single range-Doppler energy matrix. The configurable two-dimensional constant false alarm rate (CFAR) detection module is used to perform two-dimensional CFAR target detection on the range-Doppler energy matrix according to the parameter configuration, and output structured target detection information. The parameter configuration supports dynamic setting of at least the number of distance-dimensional Fourier transform points, the number of Doppler-dimensional Fourier transform points, the window function type, and the neighborhood size for two-dimensional constant false alarm rate detection.

2. The RISC-V-based fully configurable radar target detection circuit microsystem according to claim 1, characterized in that, Each of the single-channel baseband signal processing modules includes, in sequence according to the data flow direction: a configurable range Viga window module, a configurable range fast Fourier transform module, a configurable Doppler Viga window and zero-frequency shift module, a matrix transpose module, and a configurable Doppler fast Fourier transform module. The configurable range-dimensional windowing module is used to window the radar echo data according to the windowing function type and the number of range-dimensional Fourier transform points in the parameter configuration. The configurable Doppler Viga window and zero-frequency shifting module is used to perform Doppler Viga windowing and shift the zero frequency to the center of the spectrum. The matrix transpose module is used to convert the data stream from continuous according to the distance dimension to sequential output according to the continuous Doppler dimension index under the same distance unit, so as to adapt to the subsequent Doppler dimension fast Fourier transform processing.

3. The RISC-V-based fully configurable radar target detection circuit microsystem according to claim 2, characterized in that, Both the configurable distance-dimensional fast Fourier transform module and the configurable Doppler-dimensional fast Fourier transform module contain a rotation factor address decoding unit. This rotation factor address decoding unit is used to dynamically map the rotation factor index of Fourier transforms with different point counts to the rotation factor index space corresponding to the maximum number of points by left shifting operations, based on the current operation level and the number of Fourier transform points configured by the parameter configuration. This enables the sharing of the same set of basic rotation factor parameters under different configured point counts.

4. The RISC-V-based fully configurable radar target detection circuit microsystem according to claim 3, characterized in that, The rotation factor storage unit based on the maximum number of shared points only stores the basic rotation factor for a quarter period of the maximum Fourier transform points; Furthermore, a complete rotation factor is generated from the basic rotation factor by using quadrant index gating, real-to-virtual swapping, and sign reversal.

5. The RISC-V-based fully configurable radar target detection circuit microsystem according to claim 2, characterized in that, The configurable distance Vega window module and the configurable Doppler Vega window and zero-frequency shift module both support the configuration of multiple window function types, including at least rectangular window, Hanning window, Hamming window and Kaiser window.

6. The RISC-V-based fully configurable radar target detection circuit microsystem according to claim 2, characterized in that, The configurable Doppler windowing and zero-frequency shifting module is specifically used for: for the same Doppler index, different distance cells share the same Doppler window coefficients; and, according to the parity of the Doppler index, the windowed data is alternately multiplied by a positive or negative one to shift the Doppler zero-frequency component to the center position of the Doppler fast Fourier transform output spectrum.

7. The RISC-V-based fully configurable radar target detection circuit microsystem according to claim 2, characterized in that, The matrix transpose module includes two alternately operating buffers, which are used to convert two-dimensional data blocks that are continuously input according to distance units into sequential output according to Doppler dimensions by address remapping within the same frame; and the address control logic of the matrix transpose module automatically adjusts the read and write addresses according to the distance dimension and Doppler dimension size in the parameter configuration.

8. The RISC-V-based fully configurable radar target detection circuit microsystem according to claim 1, characterized in that, The channel merging module is specifically used to calculate the power spectrum of the complex distance-Doppler matrix output by each single-channel baseband signal processing module in parallel, and to sum the power spectra of all channels point by point to achieve incoherent accumulation.

9. The RISC-V-based fully configurable radar target detection circuit microsystem according to claim 1, characterized in that, The configurable two-dimensional constant false alarm rate (CFAR) detection module is configured to: when constructing the sliding detection window, set the size of the protection unit to zero, and directly sum the data within the reference unit range determined by the reference unit distance dimension and reference unit Doppler dimension in the parameter configuration to estimate the background noise energy; wherein, during the summation, if the reference unit range exceeds the boundary of the distance-Doppler energy matrix, the index is subjected to modulo loopback or zero-padding according to the boundary processing mode set in the parameter configuration; and, the adaptive decision threshold is calculated by replacing the divider with a shifter and multiplier.

10. The RISC-V-based fully configurable radar target detection circuit microsystem according to claim 1, characterized in that, The detection processor, by configuring a direct memory access module, enables the transfer of radar echo data between the external memory and the configurable radar baseband signal processing accelerator, as well as the back transmission of the structured target detection information. The structured target detection information includes target decision results, distance index, Doppler index, background noise energy estimate, energy value of the target cell, and frame target statistics.

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