An APD array chip applied to laser ranging

Abstract

The application provides an APD array chip applied to laser ranging, which comprises an APD array and a readout circuit, wherein the APD array is connected with the readout circuit through flip-chip bonding of indium columns; the APD array is composed of multiple APD groups side by side, and each APD group comprises APDs in a reverse bias state, a bias resistor R and a blocking capacitor C; the anode of the APD device is connected with a negative high-voltage power supply, the cathode is connected with the blocking capacitor C after being connected with the ground through the bias resistor R; the circuit structures of the APD groups are the same; the other end of the blocking capacitor C is connected with the indium column; the readout circuit is composed of the same number of operational amplifier circuits as the APD groups, wherein the input end of the operational amplifier circuit is electrically connected with the corresponding APD group through the indium column, and the output end outputs a signal; the application takes into account the sensitive detection of weak signals and the anti-saturation robustness in a strong light environment, and significantly expands the application range of the APD array chip in laser ranging.

Description

Technical Field

[0001] This invention relates to laser ranging technology, and more specifically to an APD array chip used in laser ranging. Background Technology

[0002] Laser ranging technology is primarily based on the characteristics of lasers, such as high monochromaticity, strong directionality, and high brightness. It indirectly calculates the distance by measuring the time of flight (ToF) of the laser pulse between the target and the detector. This technology is widely used in autonomous driving, remote sensing mapping, and robot navigation. At the receiving end, avalanche photodiode (APD) array chips are commonly used as the core detection element. APD devices operate in the avalanche region under reverse bias. When a weak light signal is received, photogenerated carriers undergo collisional ionization under a strong electric field, generating an avalanche multiplication effect, thus amplifying the original photocurrent by tens to hundreds of times. Subsequent circuits then amplify these multiplied current signals stage by stage and convert them into voltage signals that can be recognized by the system, enabling the effective detection of even extremely weak light echoes.

[0003] However, in practical applications, laser ranging systems face a prominent problem: when external natural light (such as sunlight) is too strong, the intense background light causes the APD array chip to continuously generate a large number of photogenerated carriers, leading to the device entering an oversaturated state, resulting in distorted output signals or even saturation cutoff, making it unable to respond properly to subsequent laser echo signals. This phenomenon is commonly referred to as the APD chip being "blinded" by strong light. Blinding not only causes ranging failure but can also damage the chip in severe cases. Therefore, how to suppress strong light interference and improve the dynamic range of the APD in complex lighting environments has become a key challenge that laser ranging technology urgently needs to solve. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention proposes an APD array chip for laser ranging. The chip includes an APD array and a readout circuit, wherein the APD array is connected to the readout circuit via indium pillar flip-chip bonding. The APD array consists of multiple APD groups arranged side-by-side. Each APD group includes an APD in reverse bias, a bias resistor R, and a DC blocking capacitor C. The anode of each APD device is connected to a negative high-voltage power supply, and the cathode is grounded through the bias resistor R and connected to the DC blocking capacitor C. Each APD group has the same circuit structure. The other end of the DC blocking capacitor C is connected to an indium pillar. The readout circuit consists of operational amplifier circuits of the same number as the APD groups, wherein the input terminals of the operational amplifier circuits are electrically connected to the corresponding APD group via indium pillars, and the output terminals output signals.

[0005] The beneficial effects of this invention are:

[0006] This invention can efficiently amplify extremely weak laser echo signals and significantly improve the signal-to-noise ratio through the avalanche multiplication effect, enabling the system to achieve accurate ranging even at long distances or with low reflectivity targets. Furthermore, the chip possesses stable operating capabilities in strong background light environments, effectively suppressing or resisting saturation and blinding effects caused by external natural light (such as sunlight), avoiding output signal distortion or interruption, thereby ensuring the reliability and measurement accuracy of the laser ranging system under all-weather and complex lighting conditions. In short, this invention balances sensitive detection of weak signals with robust anti-saturation performance in strong light environments, significantly expanding the application range of APD array chips in laser ranging. Attached Figure Description

[0007] Figure 1 This is a circuit diagram of an APD array chip for laser ranging according to the present invention;

[0008] Figure 2 This is a schematic diagram of the readout circuit of the APD array chip of the present invention;

[0009] Figure 3 This is a schematic diagram of the pre-amplifier TIA circuit for the readout circuit of the present invention. Detailed Implementation

[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0011] An APD array chip for laser ranging comprises an APD array and a readout circuit. The anode of the APD is connected to a negative high-voltage power supply, while the cathode is grounded through a bias resistor R, ensuring the APD is in reverse bias and linear operating mode. The input signal to the readout circuit is transmitted from the APD through a DC blocking capacitor. A TIA circuit and an intermediate amplifier circuit amplify the input signal step by step, and an output buffer circuit outputs the final analog signal to the backend for processing. The APD array and readout circuit are interconnected by flip-chip bonding using indium pillars.

[0012] When a pulsed laser is incident, the APD receives the optical signal and generates a multiplied photocurrent, which has a preliminary amplification effect. The DC blocking capacitor filters out low-frequency signals, and the TIA circuit further amplifies the remaining dynamic information. After being finally amplified by the intermediate amplifier circuit, it is transmitted from the output buffer circuit to the external backend for processing.

[0013] Furthermore, the APD array includes an APD in reverse bias, a bias resistor R, and a DC blocking capacitor C.

[0014] Furthermore, the readout circuit adopts a monolithic integrated approach to achieve full array asynchronous output, mainly including a transimpedance amplifier (TIA), a central amplifier, and an output buffer circuit.

[0015] Furthermore, the transTIA circuit includes an amplifier circuit, an output circuit, and resistors R and capacitors C for feedback and frequency compensation.

[0016] In this embodiment, an APD array chip for laser ranging is disclosed, such as... Figure 1 As shown, the chip includes an APD array and a readout circuit, wherein the APD array is connected to the readout circuit via indium pillar flip-chip bonding; the APD array is composed of multiple APD groups arranged side by side, each APD group containing an APD in reverse bias, a bias resistor R, and a DC blocking capacitor C; the anode of the APD device is connected to a negative high-voltage power supply, and the cathode is grounded through the bias resistor R and then connected to the DC blocking capacitor C; the circuit structure of each APD group is the same; the other end of the DC blocking capacitor C is connected to an indium pillar; the readout circuit consists of operational amplifier circuits of the same number as the APD groups, wherein the input terminal of the operational amplifier circuit is electrically connected to the corresponding APD group through an indium pillar, and the output terminal outputs a signal.

[0017] In this embodiment, the operational amplifier circuit includes 64 readout units, which are evenly arranged.

[0018] like Figure 2 As shown, each readout unit includes a bias circuit and four amplifier circuits, all of which are connected to the bias circuit. The amplifier circuits include a pre-amplifier (TIA) circuit and a mid-amplifier circuit, wherein the pre-amplifier (TIA) circuit and the mid-amplifier circuit are connected in series.

[0019] The preamplifier TIA circuit includes an amplifier circuit, an output circuit, two resistors, and two capacitors; the amplifier circuit is connected to the output current; the resistors and capacitors are connected in parallel to form a filter and then connected between the amplifier circuit and the output circuit.

[0020] like Figure 3As shown, the amplifier circuit includes four identical MPOS transistors MP1~MP4, four identical NMOS transistors MN1~MN4, and an NMOS bias transistor MN7. The source of MP1, the source of MP2, the substrate of MP1, and the substrate of MP2 are all connected to the VDD signal. The gates of MP1 and MP2 are both connected to the vb3 signal. The drain of MP1 is connected to the source of MP3. The gate of MP3 is connected to the vb2 signal, the substrate of MP3 is connected to the VDD signal, and the drain of MP3 is connected to the drain of MN3 and the output circuit. After the gate of MN3 is connected to the vb1 signal, the substrate of MN3 is grounded, and the source of MN3 is connected to MN4. The drain of MN1 is connected to the source of MN2 and the drain of MN7. The gate of MN7 is connected to the VIN1 signal, the substrate of MN1 is grounded, and the source of MN1 is connected to the source of MN2 and the drain of MN7. The gate of MN7 is connected to the output circuit after being connected to the vb4 signal, and the source and substrate of MN7 are grounded. The drain of MP2 is connected to the source of MP4, the substrate of MP4 is connected to the VDD signal, the gate of MP4 is connected to the vb2 signal, and the drain of MP4 is connected to the output circuit and the drain of MN4. The gate of MN4 is connected to the vb1 signal, the substrate of MN4 is grounded, and the source of MN4 is connected to the drain of MN2. The substrate of MN2 is grounded, and the gate of MN2 is connected to the VIN2 signal.

[0021] Vb1, vb2, vb3, and vb4 are four sets of bias voltages generated by the bias circuit, where vb1 > VIN1 + V. sat1 vb4=V thn +V sat2 vb3 > vb2 + V sat3 vb3=V DD -V thp -V sat4 Among them, V thn V thp It is the threshold voltage of devices MN7 and MP1, V sat1 V sat2 V sat3 and V sat4 These are the overdrive voltages of MN1, MN7, MP3, and MP1, respectively.

[0022] VIN1 passed Figure 1 The indium pillar is connected to the DC blocking capacitor, and VIN2 is left floating; the output small signal VO=Rf*I, where I is the small signal photocurrent generated by the APD.

[0023] Technical principle: A single-pixel APD device receives light signals and generates photocurrent, which then passes through... Figure 1 The DC blocking capacitor C filters out the DC component, retaining only the high-frequency part, and then... Figure 3 The TIA circuit shown converts the signal into a voltage signal VO with only dynamic information, VO = Rf*I. Figure 3The TIA circuit amplifier module requires high gain characteristics to ensure that the TIA transimpedance gain depends only on the resistor Rf value. Therefore, the amplifier circuit adopts a cascade structure to ensure a sufficiently large open-loop gain.

[0024] The output circuit includes four NMOS transistors: MN5, MN6, MN8, and MN9. The drains of MN5 and MN6 are connected to the VDD signal. The gate of MN5 is connected to the drain of MN3 in the amplifier circuit. The source of MN5 is connected to the substrate of MN5 and then to the drain of MN8, serving as the first output terminal to output the VO1 signal. The gate of MN8 is connected to the gate of MN9 and then to the gate of MN7 in the amplifier circuit. The source and substrate of MN8 are grounded. The gate of MN6 is connected to the drain of MP4 in the amplifier circuit. The source of MN6 is connected to the substrate of MN6 and the drain of MN9, serving as the second output terminal to output the VO2 signal. The substrate and source of MN9 are grounded.

[0025] The filter, which combines resistors and capacitors in parallel, is connected between the amplifier circuit and the output circuit. The filter consists of: a first resistor and a first capacitor connected in parallel, with one end of the first resistor connected to the gate of MN1 in the amplifier circuit and the other end connected to the source of MN5 in the output circuit; and a second resistor and a second capacitor connected in parallel, with one end of the second resistor connected to the gate of MN2 in the amplifier circuit and the other end connected to the source of MN6 in the output current.

[0026] Figure 1 This diagram illustrates an APD array chip used in laser ranging. The chip comprises an APD array and a readout circuit. The anode of the APD device is connected to a negative high-voltage power supply, while the cathode is grounded through a bias resistor R, ensuring the APD device is in reverse bias and linear operating mode. The APD output current is proportional to the input light intensity. Since the APD device operates under high bias, while the readout circuit operates at 3.3V, AC coupling is required to ensure both the APD and the readout circuit function correctly. Furthermore, when the background light intensity is too high, the avalanche current generated by the APD can easily reach the mA level. Without isolation between the APD device and the readout circuit, the operating point of the readout circuit may change, leading to abnormal operation. Therefore, a DC blocking capacitor needs to be integrated between the APD device and the readout circuit. If the integrated DC blocking capacitor is C=100 pF and the transimpedance of the downstream readout circuit is Rf=100 kΩ, the minimum response frequency is approximately 1 / RC=1.6 MHz. The APD array and readout circuit are interconnected by flip-chip bonding using indium pillars. The chip has a simple structure, high overall gain, low dark current and noise, and can resist strong external light interference.

[0027] Figure 2This is a schematic diagram of the readout circuit for an APD array chip used in laser ranging. The designed readout circuit has a unit size of 16×16 and uses a monolithic integration method to achieve asynchronous output across the entire array. Due to the fixed size of the readout unit and limited layout space, a structure is adopted where four adjacent readout units share a single bias circuit. This approach optimizes the bias circuit layout, ensures consistent bias voltage, and reduces the number of bias circuits from 16×16 to 8×8, thus lowering the overall chip power consumption. The pre-amplifier (TIA) circuit and mid-amplifier circuit amplify the input signal progressively, while the output buffer circuit outputs the final analog signal to the back-end processing. This readout circuit can simultaneously output 256 analog signals.

[0028] Figure 3 This is the schematic diagram of the pre-amplifier TIA circuit in the readout circuit of an APD array chip used in laser ranging. It is mainly divided into two parts: an amplifier circuit and an output circuit. The amplifier circuit adopts a sleeve-type common-source common-gate amplifier circuit structure, which has a high small-signal gain. The output circuit adopts a source follower structure to increase the output load-driving capability. Resistors Rf and capacitors C form a feedback structure between the inputs VIN1 and VIN2 and the outputs VO1 and VO2, which can cancel out a pole, stabilize the output frequency, and avoid oscillation.

[0029] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An APD array chip for laser ranging, characterized in that, It includes an APD array and a readout circuit, wherein the APD array is connected to the readout circuit via indium pillar flip-chip bonding; the APD array is composed of multiple APD groups arranged side by side, and each APD group includes an APD in reverse bias, a bias resistor R, and a DC blocking capacitor C. The anode of the APD device is connected to a negative high-voltage power supply, and the cathode is grounded through a bias resistor R and then connected to a DC blocking capacitor C. The circuit structure of each APD group is the same. The other end of the DC blocking capacitor C is connected to an indium pillar. The readout circuit consists of the same number of operational amplifier circuits as the APD groups. The input terminal of the operational amplifier circuit is electrically connected to the corresponding APD group through an indium pillar, and the output terminal outputs a signal.

2. The APD array chip for laser ranging according to claim 1, characterized in that, The bias resistor R has a resistance of 1kΩ.

3. The APD array chip for laser ranging according to claim 1, characterized in that, The capacitance of the DC blocking capacitor C is 100 pF.

4. An APD array chip for laser ranging according to claim 1, characterized in that, The operational amplifier circuit contains 64 readout units, which are evenly arranged.

5. An APD array chip for laser ranging according to claim 4, characterized in that, Each readout unit contains a bias circuit and four amplifier circuits, all of which are connected to the bias circuit. The amplifier circuits include a pre-amplifier (TIA) circuit and a mid-amplifier circuit, wherein the pre-amplifier (TIA) circuit and the mid-amplifier circuit are connected in series.

6. An APD array chip for laser ranging according to claim 5, characterized in that, The preamplifier TIA circuit includes an amplifier circuit, an output circuit, two resistors, and two capacitors; the amplifier circuit is connected to the output current; the resistors and capacitors are connected in parallel to form a filter and then connected between the amplifier circuit and the output circuit.

7. An APD array chip for laser ranging according to claim 6, characterized in that, The amplifier circuit includes four MPOS transistors (MP1-MP4) and five NMOS transistors (MN1-MN4, MN7). The sources of MP1 and MP2, the substrates of MP1 and MP2 are all connected to the VDD signal. The gates of MP1 and MP2 are both connected to the vb3 signal. The drain of MP1 is connected to the source of MP3. The gate of MP3 is connected to the vb2 signal, the substrate of MP3 is connected to the VDD signal, and the drain of MP3 is connected to the drain of MN3 and the output circuit. After the gate of MN3 is connected to the vb1 signal, the substrate of MN3 is grounded, and the source of MN3 is connected to the drain of MN1. The gate of MN1... The source of MN1 is connected to the source of MN2 and the drain of MN7, respectively. The gate of MN7 is connected to the output circuit after the vb4 signal is connected to it. The source and the substrate of MN7 are grounded. The drain of MP2 is connected to the source of MP4. The substrate of MP4 is connected to the VDD signal. The gate of MP4 is connected to the vb2 signal. The drain of MP4 is connected to the output circuit and the drain of MN4, respectively. The gate of MN4 is connected to the vb1 signal. The substrate of MN4 is grounded. The source of MN4 is connected to the drain of MN2. The substrate of MN2 is grounded. The gate of MN2 is connected to the VIN2 signal.

8. An APD array chip for laser ranging according to claim 7, characterized in that, The output circuit includes four NMOS transistors: MN5, MN6, MN8, and MN9. The drains of MN5 and MN6 are connected to the VDD signal. The gate of MN5 is connected to the drain of MN3 in the amplifier circuit. The source of MN5 is connected to the substrate of MN5 and then to the drain of MN8, serving as the first output terminal to output the VO1 signal. The gate of MN8 is connected to the gate of MN9 and then to the gate of MN7 in the amplifier circuit. The source and substrate of MN8 are grounded. The gate of MN6 is connected to the drain of MP4 in the amplifier circuit. The source of MN6 is connected to the substrate of MN6 and the drain of MN9, serving as the second output terminal to output the VO2 signal. The substrate and source of MN9 are grounded.

9. An APD array chip for laser ranging according to claim 8, characterized in that, The filter, which combines resistors and capacitors in parallel, is connected between the amplifier circuit and the output circuit. The filter consists of: a first resistor and a first capacitor connected in parallel, with one end of the first resistor connected to the gate of MN1 in the amplifier circuit and the other end connected to the source of MN5 in the output circuit; and a second resistor and a second capacitor connected in parallel, with one end of the second resistor connected to the gate of MN2 in the amplifier circuit and the other end connected to the source of MN6 in the output current.

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