Liquid detection circuit and electronic device

Abstract

The application provides a liquid detection circuit and electronic equipment. The liquid detection circuit comprises a reference capacitor, a digital logic circuit master control chip, a first resistor, a second resistor and a pull-up resistor. The digital logic circuit master control chip comprises a comparison unit and a counting unit. The comparison unit is used for comparing the voltage across the reference capacitor with a standard voltage value and comparing the voltage at the to-be-detected end with the standard voltage value. The comparison unit comprises a reference voltage input end, a sampling signal input end, a first comparison signal output end, a second comparison signal output end, a third comparison signal output end and a fourth comparison signal output end. The counting unit is used for counting the first level signal collected by the first signal collection end and the second signal collection end respectively. When the counting unit outputs a second level signal, it is confirmed that there is liquid at the to-be-detected end. The application effectively judges the liquid at the interface and reduces the probability of short circuit of the equipment.

Description

Technical Field

[0001] This application relates to the field of liquid detection technology for device interfaces, specifically to a liquid detection circuit and electronic device. Background Technology

[0002] In daily use of electronic products, humid environments are frequently encountered, such as rain or sweat. Users often use power cords with Type-C, Micro USB, and USB-C interfaces to charge or discharge electronic products in humid environments. Since liquid may be present on the interface, inserting the electronic product in such conditions can easily cause a short circuit, compromising charging safety and potentially damaging the product. Furthermore, the liquid detection circuitry in related technologies requires calculation and detection via a system-on-a-chip (SoC). Therefore, for electronic products without an SoC, such as power banks, Bluetooth earphone cases, smartwatches, and AR glasses, liquid detection at the interface is not possible. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this application provides a liquid detection circuit and electronic device to solve the problem that electronic devices cannot detect liquid at the interface during charging, which can easily lead to short circuits.

[0004] The technical solution of this application is as follows:

[0005] This application provides a liquid detection circuit for use in electronic devices. The liquid detection circuit includes: a reference capacitor, a digital logic circuit main control chip, a first resistor, a second resistor, and a pull-up resistor. The digital logic circuit main control chip includes a comparison unit and a counting unit. The comparison unit includes a reference voltage input terminal, a sampling signal input terminal, a first comparison signal output terminal, a second comparison signal output terminal, a third comparison signal output terminal, and a fourth comparison signal output terminal. The reference voltage input terminal is connected to the reference capacitor, and the sampling signal input terminal is connected to the device under test in the electronic device. The counting unit includes a first signal acquisition terminal, a second signal acquisition terminal, and a detection signal output terminal. The first signal acquisition terminal is connected to the first comparison signal output terminal, the second signal acquisition terminal is connected to the second comparison signal output terminal, the detection signal output terminal is connected to a power supply via a pull-up resistor, the third comparison signal output terminal is connected to the reference voltage input terminal via the first resistor, and the fourth comparison signal output terminal is connected to the sampling signal input terminal via the second resistor. The comparison unit compares the voltage across the reference capacitor with a standard voltage value, and compares the voltage at the test terminal with a standard voltage value. When the voltage across the reference capacitor is greater than the standard voltage value, the first comparison signal output terminal outputs a first-level signal, and the third comparison signal output terminal outputs a second-level signal. When the voltage at the test terminal is greater than the standard voltage value, the second comparison signal output terminal outputs a first-level signal, and the fourth comparison signal output terminal outputs a second-level signal. The counting unit counts the first-level signals acquired by the first signal acquisition terminal and the first-level signals acquired by the second signal acquisition terminal. When the rate at which the number of first-level signals acquired by the first signal acquisition terminal reaches a first threshold is less than or equal to the rate at which the number of first-level signals acquired by the second signal acquisition terminal reaches a second threshold, the detection signal output terminal outputs a first-level signal to indicate that there is no liquid at the test terminal. When the rate at which the number of first-level signals acquired by the first signal acquisition terminal reaches the first threshold is greater than the rate at which the number of first-level signals acquired by the second signal acquisition terminal reaches the second threshold, the detection signal output terminal outputs a second-level signal to indicate that liquid is present at the test terminal.

[0006] In one embodiment, the comparison unit includes a first comparison unit for comparing the voltage across a reference capacitor with a standard voltage value. The first comparison unit includes: a first comparator, whose first input terminal is a reference voltage input terminal, electrically connected to one end of the reference capacitor, with the other end of the reference capacitor grounded; a second input terminal of the first comparator is electrically connected to a standard voltage unit; and an output terminal of the first comparator is a first comparison signal output terminal. A first inverter, whose first input terminal is electrically connected to the output terminal of the first comparator; its output terminal is a third comparison signal output terminal; and its output terminal is electrically connected to one end of a first resistor, with the other end of the first resistor electrically connected to the first input terminal of the first comparator.

[0007] In one embodiment, the comparison unit includes a second comparison unit for comparing the voltage at the test terminal with a standard voltage value. The second comparison unit includes: a second comparator, whose first input terminal is a sampling signal input terminal, electrically connected to the test terminal, and whose second input terminal is electrically connected to a standard voltage unit; and whose output terminal is a second comparison signal output terminal. A second inverter, whose first input terminal is electrically connected to the output terminal of the second comparator, whose output terminal is a fourth comparison signal output terminal, and whose output terminal is electrically connected to one end of a second resistor, and whose other end is electrically connected to the first input terminal of the second comparator.

[0008] In one embodiment, the counting unit includes a first counting unit and a logic gate circuit. The first counting unit is used to count the first level signal acquired by the first signal acquisition terminal. The first counting unit includes a first counter, which includes a first input port and a first output port. The first input port is the first signal acquisition terminal, which is electrically connected to the first comparison signal output terminal, and the first output port is electrically connected to the logic gate circuit.

[0009] In one embodiment, the counting unit further includes a second counting unit, which is used to count the first level signal acquired by the second signal acquisition terminal. The second counting unit includes a second counter, which includes a second input port and a second output port. The second input port is the second signal acquisition terminal. The second input port is electrically connected to a second comparison signal output terminal, and the second output port is electrically connected to a logic gate circuit.

[0010] In one embodiment, the first input terminal of the logic gate is electrically connected to the first output port, the second input terminal of the logic gate is electrically connected to the second output port, and the output terminal of the logic gate is a detection signal output terminal. The logic gate outputs a detection signal based on the output results of the first counting unit and the second counting unit. Specifically, when the signal output from the first output port is at a rising edge and the signal output from the second output port is a first-level signal, the output terminal of the logic gate outputs a first-level signal; when the signal output from the first output port is at a rising edge and the signal output from the second output port is a second-level signal, the output terminal of the logic gate outputs a second-level signal.

[0011] In one embodiment, the digital logic circuit main control chip further includes a clock module, which provides a clock signal to the digital logic circuit main control chip. The clock module includes an oscillator, a first clock component, and a second clock component. The first output terminal of the oscillator is electrically connected to the first input terminal of the first clock component, the second output terminal of the oscillator is electrically connected to the first input terminal of the second clock component, the output terminal of the first clock component is electrically connected to the second input terminal of the second clock component, the output terminal of the first clock component is electrically connected to a comparison unit, and the output terminal of the second clock component is electrically connected to both the comparison unit and the counting unit.

[0012] In one embodiment, the digital logic circuit main control chip further includes a power supply module for providing power to the digital logic circuit main control chip. The power supply module includes: a first power supply unit, one end of which is electrically connected to a first power supply pin of the digital logic circuit main control chip, and the other end of which is grounded; and a second power supply unit, one end of which is electrically connected to a second power supply pin of the digital logic circuit main control chip, and the other end of which is grounded.

[0013] In one embodiment, the digital logic circuit main control chip further includes a serial bus, which is used to realize the communication connection between the digital logic circuit main control chip and the electronic device. The serial bus includes a serial data line and a serial clock line, whereby the serial data line is used to realize data transmission and the serial clock line is used to realize data transmission and reception synchronization.

[0014] A second aspect of this application provides an electronic device that includes the liquid detection circuit described in any of the above embodiments.

[0015] The technical solution of this application has at least the following technical effects or advantages:

[0016] The liquid detection circuit provided in this application compares the voltage across a reference capacitor with a standard voltage value using a comparison unit in the digital logic circuit main control chip, and also compares the voltage at the test terminal with the standard voltage value. A counting unit counts the first-level signals acquired by the first signal acquisition terminal and the first-level signals acquired by the second signal acquisition terminal. When the rate at which the number of first-level signals acquired by the first signal acquisition terminal reaches a first threshold is greater than the rate at which the number of first-level signals acquired by the second signal acquisition terminal reaches a second threshold, the detection signal output terminal outputs a second-level signal to indicate the presence of liquid at the test terminal. Thus, this application, on the one hand, utilizes the principle of capacitance change when the test interface encounters liquid to effectively determine the presence of liquid at the test interface, reducing the probability of short circuits caused by liquid and ensuring user safety when charging electronic products. On the other hand, liquid detection can be achieved with a small number of components, adapting to various circuits, reducing usage costs, and improving the efficiency and dynamism of conductive liquid detection. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a liquid detection circuit provided in one embodiment of this application.

[0018] Figure 2 This is a module composition diagram of a liquid detection circuit provided in an embodiment of this application.

[0019] Figure 3 This is a circuit diagram of a liquid detection circuit provided in one embodiment of this application.

[0020] Figure 4 This is the output waveform diagram of the liquid detection circuit when the interface under test is dry, provided in one embodiment of this application.

[0021] Figure 5 This is an output waveform diagram of the liquid detection circuit when liquid is present at the interface under test, according to another embodiment of this application.

[0022] Figure 6 This is a schematic diagram of a clock module provided in one embodiment of this application.

[0023] Figure 7 This is a schematic diagram of a power supply module provided in one embodiment of this application.

[0024] Figure 8 yes Figure 7 A schematic diagram of the circuit connection of the first power supply.

[0025] Figure 9 yes Figure 7 A schematic diagram of the circuit connection for the second power supply.

[0026] Figure 10This is a functional block diagram of a digital logic circuit main control chip provided in an embodiment of this application.

[0027] Figure 11 This is an embodiment provided by this application. Figure 10 The diagram shows the pin connections of the serial bus.

[0028] Figure 12 This is a schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0030] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0031] It should be noted that when one component is referred to as "electrically connected" to another component, it can be directly on the other component or there can be an intervening component. When one component is considered to be "electrically connected" to another component, it can be a contact connection, such as a wire connection, or a non-contact connection, such as a non-contact coupling.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0033] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0034] In daily use of electronic products, humid environments are frequently encountered, such as rain or sweat. Users often charge electronic products in humid environments using power cords with interfaces such as Type-C, Micro USB, and USB-C. Since liquid may be present on the power cord connector, inserting an electronic product in this condition can easily cause a short circuit, compromising charging safety and potentially damaging the product. Furthermore, the liquid detection circuitry in related technologies requires calculation and detection via a system-on-a-chip (SoC). Therefore, for electronic products without an SoC, such as power banks, Bluetooth earphone cases, smartwatches, and AR glasses, liquid detection at the connector is not possible.

[0035] Based on this, this application provides a liquid detection circuit and electronic device that can effectively detect liquids at the interface of electronic devices, ensuring user safety when charging electronic products, and improving the efficiency and dynamism of conductive liquid detection.

[0036] The following is a further description of a liquid detection circuit and electronic device provided in the embodiments of this application.

[0037] Please see Figure 1 , Figure 1 A schematic diagram of a liquid detection circuit according to an embodiment of this application is shown. Figure 1 As shown, the liquid detection circuit 100 includes a reference capacitor 101, a digital logic circuit main control chip 20, a first resistor 103, a second resistor 104, and a pull-up resistor 105. The input terminal of the digital logic circuit main control chip 20 is electrically connected to the reference capacitor 101, the output terminal of the digital logic circuit main control chip 20 is electrically connected to the pull-up resistor 105, and the first resistor 103 and the second resistor 104 are respectively electrically connected to the digital logic circuit main control chip 20.

[0038] In this embodiment, the digital logic circuit main control chip 20 has the function of monitoring the level changes during capacitor charging and discharging, thereby detecting whether liquid is present at the test terminal 102 of the electronic device. The digital logic circuit main control chip 20 can be an SLG46826V chip, which is a chip with in-system programmability. Of course, in other embodiments, the digital logic circuit main control chip 20 can also be other chips, circuits, or modules with in-system programmability. This application does not limit the specific style of the digital logic circuit main control chip 20. By pre-configuring the internal circuit of the digital logic circuit main control chip 20 and then building the external circuit, the liquid detection circuit 100 can realize the function of detecting the presence of liquid at the interface. The circuit construction method is relatively simple, small in size, low in cost, and low in power consumption. At the same time, the liquid detection circuit 100 does not need to perform data calculation and analysis. Therefore, the liquid detection circuit 100 is not only suitable for electronic devices with system-on-a-chip (SoC) but also for electronic devices without SoC, which improves the wide applicability of the liquid detection circuit 100 and reduces the probability of errors in liquid detection.

[0039] Reference capacitor 101 provides a stable capacitance value that remains constant under various environmental conditions, serving as a reference standard for the test terminal 102 of the electronic device. One end of reference capacitor 101 is electrically connected to the main control chip 20 of the digital logic circuit, and the other end is grounded. Reference capacitor 101 can be a preset capacitor; this application does not limit the specific size or signal of reference capacitor 101. One end of the test terminal 102 is electrically connected to the main control chip 20 of the digital logic circuit, and the other end is grounded. When the test terminal 102 of the electronic device is connected to other devices, the corresponding capacitance of the test terminal 102 at that time is obtained as the input capacitance.

[0040] In one embodiment of this application, such as Figure 1 As shown, the digital logic circuit main control chip 20 includes a comparison unit 201 and a counting unit 202. The comparison unit 201 includes a reference voltage input terminal A, a sampling signal input terminal B, a first comparison signal output terminal C, a second comparison signal output terminal D, a third comparison signal output terminal E, and a fourth comparison signal output terminal F. The reference voltage input terminal A is connected to a reference capacitor 101, and the sampling signal input terminal B is connected to the test terminal 102 of the electronic device. The counting unit 202 includes a first signal acquisition terminal X, a second signal acquisition terminal Y, and a detection signal output terminal Z. The first signal acquisition terminal X is connected to the first comparison signal output terminal C, the second signal acquisition terminal Y is connected to the second comparison signal output terminal D, the detection signal output terminal Z is connected to a power supply 106 through a pull-up resistor 105, the third comparison signal output terminal E is connected to the reference voltage input terminal A through a first resistor 103, and the fourth comparison signal output terminal F is connected to the sampling signal input terminal B through a second resistor 104.

[0041] Understandably, the pull-up resistor 105 has the function of keeping the pin at a high level when the circuit is not in use. The pull-up resistor 105 keeps the PIN3 pin of the digital logic circuit main control chip 20 at a high level when the circuit is not in use, improving circuit stability and reducing the probability of errors occurring at power-on. The power supply 106 can be a preset value; this application does not limit the specific size of the power supply 106. The first resistor 103 and the second resistor 104 are used to adjust the detection accuracy of the liquid detection circuit 100. The detection accuracy of the liquid detection circuit 100 is adjusted by adjusting the coefficients of the first resistor 103 and / or the second resistor 104, such as the resistance value or resistivity. In one embodiment, the preset coefficient is the ratio of the second resistor 104 to the first resistor 103; the larger the ratio, the higher the accuracy. Different detection accuracies can be adjusted for different environments. For example, in frequently humid environments, the coefficient can be increased, thus improving detection accuracy and making the detection results for liquids at the interface more precise. This application does not limit the specific method for adjusting the detection accuracy of the liquid detection circuit 100.

[0042] Please refer to the following: Figure 2 and Figure 3 The digital logic circuit main control chip 20 also includes a standard voltage unit 2024. The standard voltage unit 2024 can be a preset rated voltage, for example, the preset standard voltage unit 2024 is 64mV. This application does not limit the specific setting size of the standard voltage unit 2024. By comparing the voltage value across the reference capacitor 101 with the standard voltage value output by the standard voltage unit 2024, and by comparing the voltage value across the terminal under test 102 with the standard voltage value output by the standard voltage unit 2024, the comparison standard can be unified, which helps to ensure the accuracy and objectivity of the comparison.

[0043] Comparison unit 201 is used to compare the voltage across reference capacitor 101 with a standard voltage value, and to compare the voltage at the test terminal 102 with a standard voltage value. Comparison unit 201 includes a first comparison unit 2011, which is used to compare the voltage across reference capacitor 101 with a standard voltage value. The first comparison unit 2011 includes a first comparator 2011a, whose first input terminal is a reference voltage input terminal A. The first input terminal of the first comparator 2011a is electrically connected to one end of reference capacitor 101 via pin PIN17, and the other end of reference capacitor 101 is grounded. The second input terminal of the first comparator 2011a is electrically connected to a standard voltage unit 2024. The output terminal of the first comparator 2011a is a first comparison signal output terminal C. The first comparison unit 2011 further includes: a first inverter 2011b, the first input terminal of the first inverter 2011b is electrically connected to the output terminal of the first comparator 2011a, the output terminal of the first inverter 2011b is the third comparison signal output terminal E, the output terminal of the first inverter 2011b is electrically connected to one end of the first resistor 103 through pin PIN4, and the other end of the first resistor 103 is electrically connected to the first input terminal of the first comparator 2011a.

[0044] Understandably, the first comparison unit 2011 is used to compare the voltage across the reference capacitor 101 with a standard voltage value. The first comparator 2011a compares the voltage across the reference capacitor 101 with the standard voltage value. The first comparator 2011a can be an analog comparator, such as the low-power analog comparator ACMP3L in the SLG46826V chip, or other components with voltage comparison functions. This application does not limit the specific implementation of the first comparator 2011a. The first inverter 2011b is used to invert the phase of the level signal output by the first comparator 2011a by 180 degrees. For example, if the first comparator 2011a outputs a high-level signal, it will output a low-level signal after passing through the first inverter 2011b; conversely, if the first comparator 2011a outputs a low-level signal, it will output a high-level signal after passing through the first inverter 2011b. The first inverter 2011b can also be a logic NOT gate circuit or other components that invert signals. This application does not limit the specific implementation of the first inverter 2011b. When the voltage across the reference capacitor 101 is greater than the standard voltage value, the first comparison signal output terminal C outputs a first level signal, and the third comparison signal output terminal E outputs a second level signal. The second level signal is the signal obtained by inverting the first level signal.

[0045] Comparison unit 201 includes a second comparison unit 2012, which compares the voltage of the test terminal 102 with a standard voltage value. The second comparison unit 2012 includes a second comparator 2012a, whose first input terminal is a sampling signal input terminal B, and is electrically connected to one end of the test terminal 102 via pin PIN18. The second input terminal of the second comparator 2012a is electrically connected to the standard voltage unit 2024. The output terminal of the second comparator 2012a is a second comparison signal output terminal D. The second comparison unit 2012 further includes: a second inverter 2012b, the first input terminal of the second inverter 2012b is electrically connected to the output terminal of the second comparator 2012a, the output terminal of the second inverter 2012b is the fourth comparison signal output terminal F, the output terminal of the second inverter 2012b is electrically connected to one end of the second resistor 104 through pin PIN5, and the other end of the second resistor 104 is electrically connected to the first input terminal of the second comparator 2012a.

[0046] Understandably, the second comparison unit 2012 is used to compare the voltage of the test terminal 102 with a standard voltage value. The second comparator 2012a compares the voltage of the test terminal 102 with the standard voltage value. The second comparator 2012a can be an analog comparator, such as the low-power analog comparator ACMP2L in the SLG46826V chip, or other components with voltage comparison functions. This application does not limit the specific implementation of the second comparator 2012a. The second inverter 2012b is used to invert the phase of the level signal output by the second comparator 2012a by 180 degrees. The second inverter 2012b can also be a logic NOT gate circuit or other components that invert signals. This application does not limit the specific implementation of the second inverter 2012b. When the voltage of the test terminal 102 is greater than the standard voltage value, the second comparison signal output terminal D outputs a first level signal, and the fourth comparison signal output terminal F outputs a second level signal.

[0047] In one embodiment of this application, a counting unit 202 is used to count a first level signal acquired by a first signal acquisition terminal X, and to count a first level signal acquired by a second signal acquisition terminal Y. The counting unit 202 includes a first counting unit 2021 and a logic gate circuit 2023. The first counting unit 2021 is used to count the first level signal acquired by the first signal acquisition terminal X. The first counting unit 2021 includes a first counter 2021a, which includes a first input port and a first output port. The first input port is the first signal acquisition terminal X, and is electrically connected to a first comparison signal output terminal C. The first output port is electrically connected to the logic gate circuit 2023.

[0048] The counting unit 202 further includes a second counting unit 2022, which is used to count the first level signal acquired by the second signal acquisition terminal Y. The second counting unit 2022 includes a second counter 2022a, which has a second input port and a second output port. The second input port is the second signal acquisition terminal Y. The second input port is electrically connected to the second comparison signal output terminal D. The second output port is electrically connected to the logic gate circuit 2023.

[0049] Understandably, the first input port of the first counter 2021a is electrically connected to the output of the first comparator 2011a, and the second input port of the second counter 2022a is electrically connected to the output of the second comparator 2012a. The first counter 2021a counts the number of times the first level signal output by the first comparator 2011a is received, and outputs the first level signal when the count reaches a first threshold. The second counter 2022a counts the number of times the first level signal output by the second comparator 2012a is received, and outputs the first level signal when the count reaches a second threshold. The first threshold is less than the second threshold, and the difference between the first and second thresholds is less than or equal to a preset value, such as 2. This allows the output times of the first level signals by the first counter 2021a and the second counter 2022a to be relatively close. For example, the first threshold could be 55, and the second threshold could be 56. The first counter 2021a and the second counter 2022a can be frequency counters, counting relays, or other components that can identify and count input signals. This application does not limit the specific implementation of the first counter 2021a and the second counter 2022a.

[0050] Logic gate 2023 outputs a detection signal based on the outputs of the first counting unit 2021 and the second counting unit 2022 to achieve timing synchronization and control. The first input terminal of logic gate 2023 is electrically connected to the first output port, and the second input terminal is electrically connected to the second output port. The output terminal of logic gate 2023 is the detection signal output terminal Z. Specifically, when the signal output from the first output port is at a rising edge and the signal output from the second output port is a first-level signal, the output terminal of logic gate 2023 outputs a first-level signal; when the signal output from the first output port is at a rising edge and the signal output from the second output port is a second-level signal, the output terminal of logic gate 2023 outputs a second-level signal. In other words, when the rate at which the number of times the first level signal acquired by the first signal acquisition terminal X reaches the first threshold is less than or equal to the rate at which the number of times the first level signal acquired by the second signal acquisition terminal Y reaches the second threshold, the detection signal output terminal Z outputs a first level signal to indicate that there is no liquid in the test terminal 102. When the rate at which the number of times the first level signal acquired by the first signal acquisition terminal X reaches the first threshold is greater than the rate at which the number of times the first level signal acquired by the second signal acquisition terminal Y reaches the second threshold, the detection signal output terminal Z outputs a second level signal to indicate that there is liquid in the test terminal 102.

[0051] Understandably, within the same time period, when the count of the first counter 2021a is less than or equal to the count of the second counter 2022a, the output of logic gate 2023 outputs a first-level signal; when the count of the first counter 2021a is greater than the count of the second counter 2022a, the output of logic gate 2023 outputs a second-level signal. Logic gate 2023 can be a rising-edge triggered logic gate. When the counts of the first counter 2021a and / or the second counter 2022a reach the first threshold and / or the second threshold, a high-level signal is output to logic gate 2023. Logic gate 2023 outputs a high-level signal or a low-level signal through pin PIN3 according to a preset logic function. Pin PIN3 is an open-drain output pin. Open-drain output is a circuit output method in which the output terminal is open, that is, it does not directly output voltage. When the control output is low, the pin is grounded; when the control output is high, the pin neither outputs a high nor a low level, but remains in a high-impedance state. Since an external pull-up resistor 105 is connected, the voltage is pulled up to the power supply voltage of the pull-up resistor 105 when the output is high. Thus, when the count of the first counter 2021a reaches the first threshold first, the first counter 2021a outputs a first-level signal to the logic gate circuit 2023. The output signal of the logic gate circuit 2023 is pulled down internally by the digital logic circuit main control chip 20 and outputs a second-level signal through the PIN3 pin to indicate the presence of liquid at the test terminal 102. When the count of the second counter 2022a reaches the second threshold first, the second counter 2022a outputs a first-level signal to the logic gate circuit 2023. The logic gate circuit 2023 outputs a high-impedance state. Due to the presence of the pull-up resistor 105, the logic gate circuit 2023 outputs a first-level signal through the PIN3 pin to indicate the absence of liquid at the test terminal 102. The logic gate circuit 2023 can be an integrated logic gate circuit that integrates multiple AND gates, OR gates and / or NOT gates, or it can be a flip-flop with pre-set trigger events or other chips, circuits or modules with logic operation capabilities. This application does not limit the specific components used in the logic gate circuit 2023.

[0052] In one embodiment of this application, those skilled in the art can preset the first level signal to a high level signal and the second level signal to a low level signal. When the liquid detection circuit 100 starts running, the first input terminal of the first comparator 2011a is set to a default low level at pin PIN17 of the reference capacitor 101, which is lower than the standard voltage value. Therefore, the output terminal of the first comparator 2011a outputs the second level signal, i.e., a low level signal, and the output terminal of the first inverter 2011b outputs the first level signal to pin PIN4, i.e., a high level signal. This high level signal passes through the first resistor 103 and the reference capacitor 101 to reach pin PIN17, charging the reference capacitor 101. Therefore, the rising edge of the voltage waveform corresponding to the reference capacitor 101 becomes slower. When the rising edge of the voltage is higher than the standard voltage value, the output terminal of the first comparator 2011a outputs the first level signal, i.e., a high level signal, and the output terminal of the first inverter 2011b outputs the second level signal to pin PIN4, i.e., a low level signal. The low-level signal passes through the first resistor 103 and the reference capacitor 101 to reach pin PIN17. At this time, the reference capacitor 101 discharges until the first input terminal of the first comparator 2011a inputs a low level, and so on.

[0053] In one embodiment of this application, the reference voltage input terminal A is connected to a reference capacitor 101 with a capacitance of 3.3 nF. When there is no liquid at the test terminal 102, the sampling signal input terminal B can be considered as having a connected capacitor of 0 nF. The voltage levels of the reference voltage input terminal A and the sampling signal input terminal B are constantly changing between high and low levels, thus continuously charging and discharging the capacitors connected thereto. Since the capacitance value of the reference voltage input terminal A is greater than the capacitance value of the sampling signal input terminal B, the rise and fall times of the waveform at the reference voltage input terminal A are greater than the rise and fall times of the waveform at the sampling signal input terminal B, and the waveform period at the reference voltage input terminal A is greater than the waveform period at the sampling signal input terminal B. Therefore, the waveform period output by the first comparator 2011a is greater than the waveform period output by the second comparator 2012a, and the counting speed of the first counter 2021a is less than the counting speed of the second counter 2022a. Thus, the second counter 2022a reaches the second threshold before the first counter 2021a reaches the first threshold. When the second counter 2022a reaches the second threshold, it outputs a first-level signal as the second input signal of logic gate 2023. That is, when the first counter 2021a reaches the first threshold, it outputs a first-level signal as the first input signal of logic gate 2023, at which point the second counter 2022a has already output a first-level signal. Logic gate 2023 is a rising-edge triggered logic gate. When both the second and first input signals of logic gate 2023 are at the first level, logic gate 2023 outputs a first-level signal. The detection signal output terminal Z outputs a first-level signal to indicate that there is no liquid at the test terminal 102. When liquid is present at the test terminal 102, the capacitance value connected to the sampling signal input terminal B can be considered to increase significantly, reaching tens to hundreds of nF, and the capacitance value increases with the turbidity of the liquid. If the capacitance value at the sampling signal input terminal B is greater than the capacitance value at the reference voltage input terminal A, then the rise and fall times of the waveform at the sampling signal input terminal B are greater than those at the reference voltage input terminal A. Therefore, the waveform period output by the first comparator 2011a is less than the waveform period output by the second comparator 2012a, resulting in a higher counting speed for the first counter 2021a compared to the second counter 2022a. Consequently, when the first counter 2021a reaches the first threshold but the second counter 2022a has not yet reached the second threshold, the second counter 2022a outputs a second-level signal as the second input signal to the logic gate 2023, while the first counter 2021a outputs a first-level signal as the first input signal to the logic gate 2023.When the second input signal of logic gate circuit 2023 is a second level signal and the first input signal of logic gate circuit 2023 is a first level signal, logic gate circuit 2023 outputs a second level signal, and the detection signal output terminal Z outputs a second level signal to indicate that there is liquid at the test terminal 102.

[0054] When there is no liquid on the test end 102, the result is as follows: Figure 4 The waveform diagram is shown. The first counter 2021a counts the high-level signal output by the first comparator 2011a, and the second counter 2022a counts the high-level signal output by the second comparator 2012a. When the count of the first counter 2021a is less than or equal to the count of the second counter 2022a, the logic gate 2023 outputs a high-level signal. Since there is no liquid on the test terminal 102, the capacitance value at the test terminal 102 is very small. The charging and discharging time of the test terminal 102 is faster than the charging and discharging time of the reference capacitor 101. When the count of the second counter 2022a reaches the second threshold, the count of the first counter 2021a also simultaneously reaches the first threshold or does not reach the first threshold. For example, when the first counter 2021a records 55 high-level signals output by the first comparator 2011a, the second counter 2022a records 56 high-level signals output by the second comparator 2012a. The logic gate circuit 2023 detects that the second counter 2022a is a high-level signal when the first counter 2021a outputs a rising edge. At this time, the logic gate circuit 2023 outputs a high-level signal to confirm that there is no liquid on the test terminal 102.

[0055] When liquid is present on the test terminal 102, the following result is obtained: Figure 5The waveform diagram is shown. When the count of the first counter 2021a is greater than the count of the second counter 2022a, the output of logic gate 2023 is a low-level signal. Liquid is present on the test terminal 102. Due to the conductivity of the liquid, a short circuit occurs between the interface of the test terminal 102 and the liquid, causing the capacitance at the test terminal 102 to increase. This slows down the rising edge of the high-level signal at pin PIN18. Through the above charging process, the time it takes for the voltage value input to the first input terminal of the second comparator 2012a to reach the standard voltage value becomes longer. At this time, the signal output by the second comparator 2012a lags behind the signal output by the first comparator 2011a. Therefore, the frequency of the high-level signal output at pin PIN5 will be significantly less than the frequency of the high-level signal output at pin PIN4. That is, when the count of the first counter 2021a reaches the first threshold, the count of the second counter 2022a has not reached the second threshold. At this time, when the first counter 2021a records 12 high-level signals output by the first comparator 2011a, and the second counter 2022a records less than 10 high-level signals output by the second comparator 2012a, the logic gate circuit 2023 outputs a low-level signal to confirm the presence of liquid on the test terminal 102.

[0056] In other embodiments of this application, those skilled in the art may also pre-set other signal forms to indicate whether there is liquid on the test terminal 102. This application does not limit the specific style of the output signal of the liquid detection circuit 100 after detection.

[0057] Please refer to the following: Figure 3 and Figure 6 The digital logic circuit main control chip 20 also includes a clock module 107, which provides a clock signal to the digital logic circuit main control chip 20. The clock module 107 includes an oscillator 1071, a first clock component 1072, and a second clock component 1073. The first output terminal of the oscillator 1071 is electrically connected to the first input terminal of the first clock component 1072, the second output terminal of the oscillator 1071 is electrically connected to the first input terminal of the second clock component 1073, the output terminal of the first clock component 1072 is electrically connected to the second input terminal of the second clock component 1073, the output terminal of the first clock component 1072 is electrically connected to the comparison unit 201, and the output terminal of the second clock component 1073 is electrically connected to both the comparison unit 201 and the counting unit 202.

[0058] Understandably, clock signals are the foundation of sequential logic, used to determine when the state in a logic unit is updated. They are signals with a fixed period and independent of operation. By using periodic clock signals, the charging and discharging processes of the reference capacitor 101 and the input capacitor at the test terminal 102 are detected, providing a unified time reference. This ensures that data transmission and processing proceed in the correct order and timing, laying the foundation for the stable operation of the liquid detection circuit 100.

[0059] In one embodiment of this application, oscillator 1071 provides a stable clock signal to other components, enabling data transmission and processing to proceed in the correct order and timing. Oscillator 1071 can use the built-in oscillator (OSC) of the SLG46826V chip, such as an OSC0 oscillator capable of providing 2.048kHz, or an external oscillator. This application does not limit the specific design of oscillator 1071. An oscillator is an electronic device capable of generating AC signals of a specific frequency. It can generate and maintain a periodic signal output using internal circuitry or external input signals. This signal can be a sine wave, square wave, or other waveform, depending on the design and application requirements of the oscillator. The output of the first clock component 1072 is electrically connected to the third input of the first comparator 2011a and the third input of the second comparator 2012a, respectively. By inputting clock signals through the third inputs of the first comparator 2011a and the second comparator 2012a, the timing consistency of the first comparator 2011a and the second comparator 2012a during operation can be ensured. The output of the second clock component 1073 is electrically connected to the second inputs of the first inverter 2011b, the second inverter 2012b, the first counter 2021a, and the second counter 2022a. The second clock component 1073 provides a unified and stable clock signal to the first inverter 2011b, the second inverter 2012b, the first counter 2021a, and the second counter 2022a. The first clock component 1072 and the second clock component 1073 are used in conjunction with the oscillator 1071 to provide a stable clock signal. For example, the first clock component 1072 and the second clock component 1073 can be frequency selectors. The first clock component 1072 selects a specific frequency from the signal provided by the oscillator 1071 and inputs it to the first comparator 2011a and the second comparator 2012a, so that the first comparator 2011a and the second comparator 2012a operate at the same frequency. The second clock component 1073 selects a specific frequency from the signals provided by the oscillator 1071 and the first clock component 1072 and inputs it to the first inverter 2011b, the second inverter 2012b, the first counter 2021a, and the second counter 2022a, so that the first inverter 2011b, the second inverter 2012b, the first counter 2021a, and the second counter 2022a operate at the same frequency. Meanwhile, the first clock component 1072 and the second clock component 1073 can also send feedback signals to the oscillator 1071. The feedback signals include the clock frequency selected by the first clock component 1072 and the second clock component 1073. By adjusting the oscillation frequency of the oscillator 1071, it is stabilized within the frequency range selected by the first clock component 1072 and the second clock component 1073, thus generating a stable clock pulse.This helps ensure the detection accuracy and document operation of the liquid detection circuit 100, and improves the versatility of the liquid detection circuit 100 in different environments. In other embodiments, the first clock component 1072 and the second clock component 1073 can also be other components, and this application does not limit the specific style of the first clock component 1072 and the second clock component 1073.

[0060] For the first inverter 2011b, initially, the first comparator 2011a outputs a low-level signal. When the clock signal is high, the first inverter 2011b outputs a high-level signal. Due to the presence of the first resistor 103, the reference capacitor 101 is charged until the voltage across the reference capacitor 101 is greater than the standard voltage value. At this point, the first comparator 2011a outputs a high-level signal. Similarly, when the clock signal is high, the first inverter 2011b outputs a low-level signal, and the reference capacitor 101 discharges through the first resistor 103. When the voltage across the reference capacitor 101 is less than the standard voltage value, the first comparator 2011a outputs a low-level signal. If the clock signal is high, the first inverter 2011b outputs a high-level signal and charges the reference capacitor 101 again. This charging and discharging cycle continues. When the clock signal is low, the first inverter 2011b maintains a low-level output signal. The working principle of the second inverter 2012b is similar to that of the first inverter 2011b, and will not be described in detail here.

[0061] Please refer to the following: Figures 7 to 9The digital logic circuit main control chip 20 also includes a power supply module 108, which provides power to the digital logic circuit main control chip 20. The power supply module 108 includes: a first power supply unit 1081, one end of which is electrically connected to the first power supply pin VDD of the digital logic circuit main control chip 20, and the other end of which is grounded; and a second power supply unit 1082, one end of which is electrically connected to the second power supply pin VDD2 of the digital logic circuit main control chip 20, and the other end of which is grounded. This application does not limit the specific amount of power provided by the power supply module 108; those skilled in the art can select the appropriate power supply based on the actual electronic equipment being used. The power supply module 108 effectively ensures the operation of the digital logic circuit main control chip 20, enabling the liquid detection circuit 100 to function normally. By providing different power supply voltages through the first power supply unit 1081 and the second power supply unit 1082, it is beneficial to meet the power requirements of different components. Understandably, the first power supply unit 1081 and the second power supply unit 1082 can be power supplies that can directly provide different voltages, or power supplies with boost or buck components. The boost or buck components can be circuits, chips or modules with boost or buck capabilities. This application does not limit the specific internal configuration of the first power supply unit 1081 and the second power supply unit 1082.

[0062] In one embodiment of this application, such as Figure 10 and Figure 11 As shown, the digital logic circuit main control chip 20 also includes a serial bus 205, which is used to realize the communication connection between the digital logic circuit main control chip 20 and external devices. The serial bus 205 includes a serial data line 2051 and a serial clock line 2052. The serial data line 2051 is used to realize data transmission, and the serial clock line 2052 is used to realize data transmission and reception synchronization. The serial bus 205 can be the two-wire serial bus (Inter-Integrated Circuit, I2C) built into the SLG46826V chip. 2C) This interface enables communication between the chip and other devices. The two-wire serial bus interface has two bidirectional lines: a serial data line 2051 (SDA) and a serial clock line 2052 (SCL), used for sending and receiving data to achieve data transmission. The serial clock line 2052 is electrically connected to the external device via pin PIN8 of the digital logic circuit main control chip 20, and is used to generate synchronous clock pulses to synchronize data transmission. The serial data line 2051 is electrically connected to the external device via pin PIN9 of the digital logic circuit main control chip 20 to transmit data between components. In other embodiments, the digital logic circuit main control chip 20 can also transmit data through other communication methods, such as a serial peripheral interface (SPI) or a controller area network (CAN) bus. This application does not limit the specific data transmission method of the digital logic circuit main control chip 20.

[0063] Please see Figure 12 This application also provides an electronic device 10, which includes the liquid detection circuit 100 described in any of the above embodiments. Understandably, the electronic device 10 can be an electronic device with a system-on-a-chip (SoC), such as a mobile phone or tablet computer, or an electronic device without a SoC, such as a power bank or Bluetooth headset. Liquid detection at the interface of the electronic device 10 can be performed using only a few components, reducing the probability of short circuits caused by liquids and effectively ensuring the charging safety of the electronic device 10.

[0064] It should be noted that, for the sake of simplicity, the aforementioned method embodiments are described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps may be performed in other orders or simultaneously.

[0065] The above embodiments are preferred embodiments of this application and are not intended to limit the scope of this application. Any modifications and improvements made by those skilled in the art to the technical solutions of this application without departing from the spirit of this application shall fall within the protection scope defined by the claims of this application.

Claims

1. A liquid detection circuit, applied in electronic equipment, characterized in that, The liquid detection circuit includes: a reference capacitor, a digital logic circuit main control chip, a first resistor, a second resistor, and a pull-up resistor; The main control chip of the digital logic circuit includes a comparison unit and a counting unit; The comparison unit includes a reference voltage input terminal, a sampling signal input terminal, a first comparison signal output terminal, a second comparison signal output terminal, a third comparison signal output terminal, and a fourth comparison signal output terminal. The reference voltage input terminal is connected to the reference capacitor, and the sampling signal input terminal is connected to the test terminal of the electronic device. The counting unit includes a first signal acquisition terminal, a second signal acquisition terminal, and a detection signal output terminal. The first signal acquisition terminal is connected to the first comparison signal output terminal, the second signal acquisition terminal is connected to the second comparison signal output terminal, the detection signal output terminal is connected to the power supply through the pull-up resistor, the third comparison signal output terminal is connected to the reference voltage input terminal through the first resistor, and the fourth comparison signal output terminal is connected to the sampling signal input terminal through the second resistor. The comparison unit is used to compare the voltage across the reference capacitor with a standard voltage value, and to compare the voltage at the test terminal with the standard voltage value. When the voltage across the reference capacitor is greater than the standard voltage value, the first comparison signal output terminal outputs a first level signal, and the third comparison signal output terminal outputs a second level signal. When the voltage at the test terminal is greater than the standard voltage value, the second comparison signal output terminal outputs the first level signal, and the fourth comparison signal output terminal outputs the second level signal. The counting unit is used to count the first level signal acquired by the first signal acquisition terminal and to count the first level signal acquired by the second signal acquisition terminal. When the rate at which the number of times the first level signal acquired by the first signal acquisition terminal reaches a first threshold is less than or equal to the rate at which the number of times the first level signal acquired by the second signal acquisition terminal reaches a second threshold, the detection signal output terminal outputs the first level signal to indicate that there is no liquid at the test end. When the rate at which the number of times the first level signal acquired by the first signal acquisition terminal reaches the first threshold is greater than the rate at which the number of times the first level signal acquired by the second signal acquisition terminal reaches the second threshold, the detection signal output terminal outputs the second level signal to indicate that there is liquid at the test end.

2. The liquid detection circuit as described in claim 1, characterized in that, The comparison unit includes a first comparison unit, which is used to compare the voltage across the reference capacitor with the standard voltage value. The first comparison unit includes: A first comparator, wherein the first input terminal of the first comparator is the reference voltage input terminal, the first input terminal of the first comparator is electrically connected to one end of the reference capacitor, the other end of the reference capacitor is grounded, the second input terminal of the first comparator is electrically connected to the standard voltage unit, and the output terminal of the first comparator is the first comparison signal output terminal; The first inverter has its first input terminal electrically connected to the output terminal of the first comparator. The output terminal of the first inverter is the third comparison signal output terminal. The output terminal of the first inverter is electrically connected to one end of the first resistor, and the other end of the first resistor is electrically connected to the first input terminal of the first comparator.

3. The liquid detection circuit as described in claim 2, characterized in that, The comparison unit includes a second comparison unit, which is used to compare the voltage of the terminal under test with the standard voltage value. The second comparison unit includes: The second comparator has a first input terminal that is the sampling signal input terminal, a first input terminal that is electrically connected to the terminal under test, a second input terminal that is electrically connected to the standard voltage unit, and an output terminal that is the second comparison signal output terminal. The second inverter has its first input terminal electrically connected to the output terminal of the second comparator, and its output terminal is the fourth comparison signal output terminal. The output terminal of the second inverter is electrically connected to one end of the second resistor, and the other end of the second resistor is electrically connected to the first input terminal of the second comparator.

4. The liquid detection circuit as described in claim 1, characterized in that, The counting unit includes a first counting unit and a logic gate circuit. The first counting unit is used to count the first level signal acquired by the first signal acquisition terminal. The first counting unit includes a first counter, which includes a first input port and a first output port. The first input port is the first signal acquisition terminal. The first input port is electrically connected to the first comparison signal output terminal, and the first output port is electrically connected to the logic gate circuit.

5. The liquid detection circuit as described in claim 4, characterized in that, The counting unit further includes a second counting unit, which is used to count the first level signal acquired by the second signal acquisition terminal; the second counting unit includes a second counter, which includes a second input port and a second output port, the second input port being the second signal acquisition terminal, the second input port being electrically connected to the second comparison signal output terminal, and the second output port being electrically connected to the logic gate circuit.

6. The liquid detection circuit as described in claim 5, characterized in that, The first input terminal of the logic gate circuit is electrically connected to the first output port, the second input terminal of the logic gate circuit is electrically connected to the second output port, the output terminal of the logic gate circuit is the detection signal output terminal, and the logic gate circuit outputs the detection signal according to the output results of the first counting unit and the second counting unit; Specifically, when the signal output from the first output port is at a rising edge and the signal output from the second output port is the first level signal, the output terminal of the logic gate circuit outputs the first level signal; when the signal output from the first output port is at a rising edge and the signal output from the second output port is the second level signal, the output terminal of the logic gate circuit outputs the second level signal.

7. The liquid detection circuit as described in claim 1, characterized in that, The digital logic circuit main control chip also includes a clock module, which is used to provide a clock signal to the digital logic circuit main control chip. The clock module includes an oscillator, a first clock component, and a second clock component; The first output terminal of the oscillator is electrically connected to the first input terminal of the first clock component, the second output terminal of the oscillator is electrically connected to the first input terminal of the second clock component, the output terminal of the first clock component is electrically connected to the second input terminal of the second clock component, the output terminal of the first clock component is electrically connected to the comparison unit, and the output terminal of the second clock component is electrically connected to both the comparison unit and the counting unit.

8. The liquid detection circuit as described in claim 1, characterized in that, The digital logic circuit main control chip also includes a power supply module, which provides power to the digital logic circuit main control chip; the power supply module includes: The first power supply unit has one end electrically connected to the first power supply pin of the main control chip of the digital logic circuit, and the other end of the first power supply unit is grounded. The second power supply unit has one end electrically connected to the second power supply pin of the main control chip of the digital logic circuit, and the other end grounded.

9. The liquid detection circuit as described in claim 1, characterized in that, The digital logic circuit main control chip also includes a serial bus, which is used to realize the communication connection between the digital logic circuit main control chip and the electronic device. The serial bus includes a serial data line and a serial clock line. The serial data line is used to realize data transmission, and the serial clock line is used to realize data transmission and reception synchronization.

10. An electronic device, characterized in that, The electronic device includes a liquid detection circuit as described in any one of claims 1 to 9.

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