Orthogonal dithering phase-locked detection optical iq modulator bias control method and system

Abstract

The application discloses a bias control method and system of an optical IQ modulator based on quadrature dithering phase-locked detection, and belongs to the technical field of optical communication and integrated photonics. The system comprises a laser for providing a continuous optical carrier; an optical IQ modulator comprising an I-path sub-MZM, a Q-path sub-MZM and a Ph phase shifter; a bias voltage source for providing adjustable DC bias for I, Q and Ph, and superimposing a perturbation signal from a dithering generator; and a dithering signal generator for generating cosine and sine signals with a frequency of f and an amplitude of A. The application realizes independent control of three paths of bias by using only one dithering frequency, greatly reduces the system complexity and power consumption, and avoids multi-frequency crosstalk. By setting a target value of a frequency doubling component through software, the I path or the Q path can be flexibly locked to an arbitrary working point, so that different modulation formats and power control requirements can be adapted.

Description

Technical Field

[0001] This invention relates to the fields of optical communication and integrated photonics technology, specifically to a signal processing method and system for automatic control of the bias point of an optical IQ modulator, which is particularly suitable for transmitter bias stabilization control of high-order modulation formats. Background Technology

[0002] Optical IQ modulators are the core components for implementing high-order modulation formats. They typically consist of two parallel Mach-Zehnder modulators (MZMs, corresponding to the I and Q paths respectively) and a parent phase modulator (Ph path). To ensure the quality of the modulated signal, these three bias points must be precisely controlled at specific positions: usually, the I and Q paths need to be locked at the Null point (minimum transmission point), and the Ph path needs to be locked at the Quad point (90° phase shift point). However, in some applications, it is desirable to lock the I or Q path bias to any preset operating point to achieve flexible signal pre-distortion or power control.

[0003] The existing automatic bias control (ABC) scheme has the following main shortcomings:

[0004] 1. The need for multiple jitter signals of different frequencies or the use of time-division multiplexed jitter increases system complexity and the risk of crosstalk. For example, Chinese patent CN103873152A uses jitter at two different frequencies for I / Q channels, which needs to be filtered and extracted separately, thus limiting frequency planning;

[0005] 2. Most of them can only lock to a fixed Null / Peak point and cannot achieve stable control at any offset point. For example, although Huawei CN109314576B uses orthogonal jitter, it is only for a fixed offset point.

[0006] 3. The coupling between the multiple control loops is strong, the locking process is cumbersome, and the convergence speed is slow. Traditional solutions often require each bias to be calibrated in turn, which cannot be done synchronously.

[0007] 4. Traditional methods rely on analog mixers or narrowband filters, whose accuracy is greatly affected by temperature drift and device aging, and analog circuits are difficult to debug and integrate.

[0008] To address the aforementioned issues, we propose a bias control method and system for optical IQ modulators using quadrature jitter phase-locked loop detection. Summary of the Invention

[0009] The purpose of this invention is to solve the problems in the prior art by proposing a bias control method and system for optical IQ modulators with quadrature jitter phase-locked loop detection.

[0010] To achieve the above objectives, the present invention adopts the following technical solution:

[0011] A bias control method for an optical IQ modulator with quadrature jitter phase-locked detection includes the following steps:

[0012] S1: The frequency superimposed at the I-path bias terminal of the optical IQ modulator is... cosine jitter signal A sinusoidal jitter signal of the same frequency is superimposed at the Q-path bias terminal. This forms a pair of orthogonal perturbation signals;

[0013] S2: Monitor the output optical power of the IQ modulator using a photodetector to obtain the photocurrent signal. ;

[0014] S3: Based on sampling rate Synchronous acquisition and three reference signals ;

[0015] S4: Perform digital phase-locked loop detection on the acquired signal and calculate the first harmonic cosine component. First harmonic sine component Second harmonic sine component ;

[0016] S5: Construct three error signals:

[0017] ;

[0018] in To preset the target value, The polarity coefficient, This is the gain adjustment coefficient for the I-channel;

[0019] S6: Send the three error signals to the digital PI controller respectively, according to the formula: Update all bias voltages;

[0020] S7: Repeat steps S2 to S6 until the error converges, thus completing the bias point locking.

[0021] Preferably, the preset target value Desired mentioned in step S5 is obtained through pre-calibration: scanning the I-channel bias voltage under jitter-free conditions and recording... Maximum amplitude When it is necessary to lock to any work point At that time, set When locked to a null point, set .

[0022] Preferably, the jitter amplitude Much smaller than the half-wave voltage of each arm ,and The range of values ​​is The jitter frequency Much smaller than the bandwidth of the modulation signal, and for .

[0023] Preferably, the integral term of the PI controller is set with integral saturation limit and proportional gain. and integral gain All are chosen to be negative powers of 2 to facilitate hardware shifting.

[0024] Preferably, an optical IQ modulator bias control system with quadrature jitter phase-locked detection is also provided, comprising:

[0025] Lasers are used to provide continuous optical carriers;

[0026] An optical IQ modulator, comprising an I-channel MZM, a Q-channel MZM, and a Ph phase shifter;

[0027] Bias voltage source, used to provide adjustable DC bias for I, Q, Ph And superimposed with the perturbation signal from the jitter generator;

[0028] A jitter signal generator is used to generate a frequency of The cosine and sine signals have amplitudes of ;

[0029] A photodetector is used to monitor the output optical power of the IQ modulator and convert it into a current signal. ;

[0030] Analog-to-digital converter for synchronous acquisition and reference signals;

[0031] A digital signal processor is used to execute steps S3 to S6 of the method according to any one of claims 1 to 4 and output an updated bias voltage.

[0032] Preferably, the digital signal processor is a DSP or FPGA, which integrates a digital phase-locked loop (PLL) detection unit and a PI control unit. The PLL detection unit is used for calculation. The PI control unit is used to generate the bias voltage update value.

[0033] Preferably, the bias voltage source has an adder function, which can superimpose the DC bias and the jitter signal and apply them to each arm of the modulator.

[0034] Preferably, the sampling rate of the analog-to-digital converter jitter frequency It is 50 to 100 times faster, and all acquisition and processing are synchronized with the jitter signal.

[0035] Preferably, it also includes a host computer communication interface for receiving the user-defined target operating point parameter Desired and polarity configuration, and for reading the system status in real time.

[0036] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0037] 1. Single-frequency jitter decoupling: Three-way bias independent control is achieved using only one jitter frequency, which greatly reduces system complexity and power consumption and avoids multi-frequency crosstalk.

[0038] 2. Arbitrary point locking capability: By setting the target value of the first harmonic component through software, the I or Q path can be flexibly locked to any operating point to adapt to different modulation formats and power control requirements.

[0039] 3. Orthogonal decoupling mechanism: Utilizing sine / cosine quadrature dithering signals, the control of the I and Q paths is naturally decoupled; the Ph path error signal is extracted by frequency doubling, resulting in extremely low crosstalk and fast convergence speed.

[0040] 4. High precision and high signal-to-noise ratio: It adopts digital phase-locked loop detection technology to effectively suppress noise and DC drift. The PI controller parameters can be flexibly adjusted and the dynamic response is excellent.

[0041] 5. Fully digital implementation: All processing is completed in the digital domain, which is easy to integrate and adjust parameters, has good temperature stability, and is suitable for large-scale production. Attached Figure Description

[0042] Figure 1 This is a block diagram of the optical IQ modulator bias control system of the present invention;

[0043] Figure 2 A 3D surface plot of the hybrid correlation signal obtained from simulation as a function of I / Q bias;

[0044] Figure 3 The curve shows the variation of the first harmonic cosine component of the I-path with the I-bias.

[0045] Figure 4 The curve shows the variation of the second harmonic sinusoidal component of the Phase path with the Ph bias.

[0046] Figure 5 The closed-loop convergence curves for the three bias voltages are shown. Detailed Implementation

[0047] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0048] Example 1: System Initialization and Parameter Settings

[0049] This embodiment first constructs a simulation model of the optical IQ modulator bias control system in the MATLAB / Simulink environment to verify the decoupling performance and convergence characteristics of the core algorithm under ideal conditions. System parameters are set according to the typical technical specifications of commercial lithium niobate (LiNbO3) IQ modulators:

[0050] Half-wave voltage of each arm: This is used to simulate the inter-arm asymmetry of actual devices caused by manufacturing processes;

[0051] Initial offset This represents the random bias state before calibration after power-on.

[0052] The jitter amplitude A is taken as This value is much smaller than This ensures that the additional modulation depth introduced by jitter is less than 5%, and does not cause perceptible distortion to the main modulation signal. Generally, A can... Within the range, the value is selected by compromise between the phase-locked detection signal-to-noise ratio and the allowable degree of modulation impairment. The value in this embodiment takes into account both the amplitude of the error signal and the suppression of output optical power fluctuations.

[0053] jitter frequency This bandwidth is much lower than that of typical modulation signals (such as above 10GHz), avoiding overlap with the data spectrum and facilitating subsequent digital low-pass filtering.

[0054] Sampling rate This is 50 times the jitter frequency, satisfying the Nyquist sampling theorem with a margin. The number of sampling points per control cycle... That is, the integration interval includes 10 complete jitter cycles to ensure that the coherent accumulation gain of the phase-locked detection is sufficient to suppress white noise and quantization noise. More generally, It can be an integer between 8 and 20. The larger the value, the higher the detection signal-to-noise ratio, but the control cycle will also be correspondingly longer. In practical applications, a balance needs to be struck between response speed and measurement accuracy.

[0055] During the initialization phase, the digital signal processor (DSP or FPGA) also needs to complete the following preparatory work:

[0056] (1) Use an internal clock generator or a direct digital frequency synthesizer (DDS) to generate a cosine and sine sequence that is strictly synchronized with the reference signal. The initial phase value can be set arbitrarily, but once determined, it remains unchanged in all subsequent control cycles to ensure orthogonality.

[0057] (2) Clear the integral accumulator of the three-way PI controller to prevent integral saturation at the moment of power-on;

[0058] (3) If the system has a host computer communication interface, the user-defined target working point parameter Desired and polarity coefficient are read in via serial port or Ethernet. If no external command is given, the default value will be used, which corresponds to locking I / Q to the Null point and Ph to the Quad point.

[0059] Example 2: Digital phase-locked loop detection and error signal extraction:

[0060] Within each control cycle, the system synchronously performs the following data acquisition and processing steps:

[0061] First, the analog-to-digital converter (ADC) operates at a fixed sampling rate. The photocurrent signal output by the synchronous sampling photodetector Simultaneously, three local reference sequences are generated:

[0062] ,

[0063] Where n = 0, 1, ..., N-1;

[0064] Then, three coherent accumulation operations are performed within each control cycle:

[0065] ;

[0066] The above accumulation process is essentially equivalent to a narrowband digital phase-locked amplification centered on the jitter frequency and its second harmonic, with an equivalent noise bandwidth of approximately The bandwidth is much smaller than that of traditional analog bandpass filters, thus effectively suppressing broadband noise and out-of-band interference from the modulated signal. To further improve computational efficiency, the accumulation operation can be performed in parallel within the FPGA using a pipelined multiplier and accumulator structure, or it can be implemented in the DSP using a multiply-accumulate instruction (MAC) loop. In particular, when When taking integer powers of 2, division can be simplified to a shift operation, which helps save hardware resources.

[0067] In this embodiment, the following settings are provided: The measured values ​​were obtained after adding Gaussian white noise with a root mean square amplitude of 5% of the photocurrent. The fluctuation variance is reduced by about 20dB compared to direct sampling, effectively verifying the noise resistance advantage of digital phase-locked loop detection.

[0068] Example 3: Arbitrary point locking setup and error signal construction:

[0069] This example illustrates how to achieve arbitrary operating point locking of the I-channel bias through software configuration. First, a calibration process needs to be performed (this can be done automatically during factory testing or system startup):

[0070] Under conditions of no jitter (or with minimal jitter amplitude, used only for measurement), lock the Q-path bias at the Null point and the Ph-path bias at the Quad point, then scan the I-path DC bias with step voltages. from arrive ;

[0071] Apply standard jitter at each scan point and calculate Value, record The complete curve of the bias variation yields its peak amplitude. (Usually corresponds to the point of maximum positive slope of the I-channel MZM transmission curve) and zero crossing point (corresponding to the Null point).

[0072] Will It is stored in non-volatile memory and serves as the normalization reference for subsequent arbitrary point locking.

[0073] When the user wants to lock the I-path to the corresponding modulation phase When the working point is reached, a preset target value is set: ;

[0074] For the Q-path, its error signal utilizes Construction. Mathematical derivation shows that when the I-path bias is fixed, The error signal is approximately proportional to the Q-path bias error and crosses zero at the Null point. Therefore, the error signal for the Q-path locking to the Null point is: ;

[0075] in This indicates the direction of negative feedback. To lock onto the Peak point, you can... Set it to -1 so that the error signal crosses zero at Peak and has the opposite sign.

[0076] The error signal of the Ph circuit utilizes the second harmonic component. This component takes a zero value when Ph is biased at the Quad point, and the sign of the zero-crossing slope depends on the modulator phase offset direction, therefore: ;

[0077] Under normal circumstances If the user requires inverting control due to differences in modulator structure (such as different initial phase offsets between arms), this polarity coefficient can also be adjusted.

[0078] Furthermore, for the I-channel error signal, considering The amplitude may drift with device aging or temperature changes. This invention introduces an adjustable gain coefficient. (Value range 0.5~2.0), used for online adjustment of the error amplification factor to ensure consistent loop gain under different amplitude jitter. The final three error signals are unified as follows:

[0079]

[0080] In this embodiment, the I-path target is set as The Q-path and Ph-path are locked to Null and Quad respectively. After closed-loop control, the steady-state error at the I-path bias point is less than 0.5° (corresponding to a voltage error of approximately 0.05). This verifies the feasibility of arbitrary point locking.

[0081] Example 4: PI Controller Design and Convergence Performance:

[0082] This invention employs a digital position PI control algorithm, the discrete domain expression of which is:

[0083] ;

[0084] in To control the cycle number. To prevent the integral term from accumulating too large and causing the bias voltage to exceed the driver output range, the integral term is limited after each cycle update:

[0085] ;

[0086] Conversely, the same applies. Points cap. Based on the maximum output voltage of the bias source and the proportional gain, this embodiment is set to... (Equivalent voltage limit is ±5V).

[0087] To facilitate the use of shift operations instead of floating-point multiplication in FPGAs, all scaling gains... and integral gain All are chosen to be negative powers of 2. For example, in this embodiment, we take:

[0088] ;

[0089] These values ​​were obtained through simulation optimization, balancing convergence speed and overshoot. Specifically, the time constant of the I / Q path is approximately... ,in This represents the slope of the modulator's transmission curve at the lock point, approximately 0.2 V. -1 Therefore One control cycle; Ph path due to The amplitude is relatively small, the gain is slightly large, and the corresponding time constant is about 40 cycles.

[0090] In practical control, we use an incremental PI controller (equivalent to a positional controller, but to avoid integral overflow), and the update formula is:

[0091] ;

[0092] In this embodiment, a step disturbance (simulating a bias drift of +0.5V caused by a sudden temperature change) is applied in the simulation, and the convergence curves of the three bias voltages are recorded as follows. Figure 5 As shown. After approximately 256 control cycles (i.e., 256 × 10 ms = 2.56 s, because...) With a control period of 10ms, all three errors converged to zero, and the absolute value of the steady-state error was less than 0.01V. When the frequency is increased to 10kHz, the convergence time can be shortened to less than 300ms, but a higher ADC sampling rate (at least 500kHz) and processing speed are required. In practical engineering, a compromise can be made based on the system throughput and power consumption requirements.

[0093] Example 5: Simulation verification of decoupling performance and anti-crosstalk capability:

[0094] To quantitatively verify the natural decoupling effect of the orthogonal jitter signal, we fixed the Ph bias at the Quad point in the simulation, and simultaneously scanned the I-path bias (range -5V to +5V) and Q-path bias (range -6V to +6V) independently, calculating at each grid point. , and The value. Draw. 3D surface plot (see) Figure 2 As can be seen, the surface exhibits a standard sine wave along the I-axis, while it is almost flat along the Q-axis. The maximum crosstalk fluctuation is less than 3% of the main signal amplitude, proving that the I-path error signal is essentially independent of the Q-path bias. Similarly, Sensitive only to the Q-path, not to the I-path; It is only sensitive to the Ph path and crosses zero precisely at the Quad point. Figure 4 The zero-crossing slope is approximately 0.15V. -1 This meets the sensitivity requirements for error detection.

[0095] Furthermore, under the condition that the I, Q, and Ph biases simultaneously deviate from their optimal points, three closed loops are started simultaneously, and the transient response of each bias voltage is recorded. The results show that the three controls do not interfere with each other and converge independently. The maximum instantaneous coupling deviation during the convergence process is less than 5% of the final steady-state value, which fully demonstrates the superiority of the orthogonal decoupling mechanism of this invention over the traditional sequential calibration method.

[0096] Example 6: Hardware Implementation Case and Temperature Stability Test

[0097] This embodiment verifies the feasibility of the invention in a real-world environment based on an actual hardware platform. The hardware configuration is as follows:

[0098] Laser: 1550nm DFB laser, output power 10dBm;

[0099] Optical IQ modulator: Fujitsu FTM7960, with integrated optical power monitoring PD;

[0100] Bias voltage source: Four-channel 16-bit DAC (AD5781), output range ±12V, built-in adder can superimpose external analog jitter signals;

[0101] Jitter signal generator: The FPGA internal DDS generates a 5kHz quadrature sine / cosine signal, which is output to the jitter input terminal of the bias source via a 16-bit DAC;

[0102] Analog-to-digital converter: 16-bit parallel SARADC (AD7606), sampling rate set to 500kHz (100 times the jitter frequency), simultaneously acquiring... Synchronization clock with three reference signals;

[0103] Digital processor: Xilinx Zynq-7000SoC, with ARM Cortex-A9 as the main controller and FPGA logic to implement phase-locked loop detection and PI controller;

[0104] The FPGA uses the CORDIC algorithm to iteratively generate sine and cosine reference values, saving lookup table resources; the multiplier uses a DSP48E hard core, and the accumulator uses a 48-bit width to avoid overflow.

[0105] The host computer sends the target operating point and polarity parameters through the UART interface, and can read back the bias voltage and error signal in real time.

[0106] The experimental environment temperature was cyclically varied within ±5℃ using a temperature-controlled chamber based on 25℃, and the drift of the bias point was measured. Results showed that within 12 hours, the angle drift of the I-path bias lock point was <±0.4°, the Q-path <±0.5°, and the Ph-path <±0.3°, all superior to the traditional analog ABC scheme (typically above ±2°). The lock time (from startup to a steady state with an error less than 1%) was measured at 48ms (corresponding to approximately 240 control cycles with a period of 0.2ms), meeting the startup requirements of the high-speed optical transmitter. Furthermore, we tested the error vector amplitude (EVM) when the main modulation signal was 32GBaudQPSK. Under bias lock, the EVM was 6.2%, very close to the theoretical value of 5.8%, demonstrating that the additional damage introduced by jitter is negligible.

[0107] Example 7: Anti-interference and fault protection mechanism:

[0108] To further enhance the robustness of the system, this embodiment adds the following auxiliary functions to the basic control method:

[0109] (1) Reference signal phase calibration: Each time the system is powered on, the overall delay of the jitter signal from the DAC output to the ADC sampling is measured using a square wave or pulse signal, and compensation is performed when the reference sequence is generated to ensure that and The jitter components in the signal are in phase, avoiding a decrease in phase-locked detection gain caused by phase mismatch.

[0110] (2) Error signal validity check: Calculated simultaneously in each control cycle , , If the sum of the absolute values ​​of the amplitudes is lower than a preset threshold (e.g., 10% of the normal amplitude), it is determined that the optical path is interrupted or the PD is faulty. At this time, the integral term is immediately frozen, the output maintains the bias voltage of the previous cycle, and an alarm is sent to the host computer.

[0111] (3) Jitter amplitude adaptive: The jitter amplitude is automatically adjusted according to the measured amplitude of the phase-locked loop detection signal. When detected or Reduce when amplitude exceeds preset upper limit To avoid nonlinear distortion, and conversely, to appropriately increase the value when the signal is weak. To maintain a sufficient signal-to-noise ratio. The adaptive range is limited to Inside.

[0112] The aforementioned extended functions can be implemented by modifying the internal state machine of the FPGA without the need for additional hardware, further enhancing the practicality and versatility of the present invention.

[0113] Example 8: Comparison experiment with other schemes:

[0114] To objectively evaluate the effectiveness of this invention, we conducted comparative experiments with two existing schemes: (a) an analog mixing scheme based on two-frequency jitter; and (b) a time-division multiplexing single-frequency jitter alternating calibration scheme. Under the same IQ modulator and environmental conditions, the test results are shown in the table below:

[0115]

[0116] It is evident that the present invention has significant advantages in terms of convergence speed, accuracy, and resource consumption, and does not require complex frequency planning.

[0117] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A bias control method for an optical IQ modulator using quadrature jitter phase-locked loop detection, characterized in that, Includes the following steps: S1: The frequency superimposed at the I-path bias terminal of the optical IQ modulator is... cosine jitter signal A sinusoidal jitter signal of the same frequency is superimposed at the Q-path bias terminal. This forms a pair of orthogonal perturbation signals; the cosine and sine jitter signals are generated from the same clock source to ensure a strict orthogonal phase relationship. S2: Monitor the output optical power of the IQ modulator using a photodetector to obtain the photocurrent signal. ; S3: Based on sampling rate Synchronous acquisition and three reference signals Number of sampling points per control cycle ,in It is an integer, and This ensures that the integration period of the phase-locked loop detection includes an integer number of jitter periods; S4: Perform digital phase-locked loop detection on the acquired signal and calculate the first harmonic cosine component. First harmonic sine component Second harmonic sine component ; The above accumulation within one control cycle Completed on each sampling point, equivalent to coherent detection of a digital lock-in amplifier, which can effectively suppress noise components that are not at the same frequency as the jitter frequency; S5: Construct three error signals: in To preset the target value, The polarity coefficient, The gain adjustment coefficient for the I-path is used; the error signal is constructed using the mathematical properties of the quadrature jitter signal in the IQ modulator transfer function: It is only sensitive to the I-path bias and is independent of the Q-path bias. It is only sensitive to the Q-path bias and is independent of the I-path bias. It is only sensitive to the Ph path bias, thus achieving natural decoupling of the three error signals; S6: Send the three error signals to the digital PI controller respectively, according to the formula: Update all bias voltages; S7: Repeat steps S2 to S6 until the error converges, completing the bias point locking.

2. The control method according to claim 1, characterized in that, The preset target value Desired mentioned in step S5 is obtained through pre-calibration: scanning the I-channel bias voltage under jitter-free conditions and recording... Maximum amplitude When it is necessary to lock to any work point At that time, set When locked to a null point, set .

3. The control method according to claim 1, characterized in that, The amplitude of the jitter Much smaller than the half-wave voltage of each arm ,and The range of values ​​is The jitter frequency Much smaller than the bandwidth of the modulation signal, and for .

4. The control method according to claim 1, characterized in that, The integral term of the PI controller is set with integral saturation limit and proportional gain. and integral gain All are chosen to be negative powers of 2 to facilitate hardware shifting.

5. A bias control system for an optical IQ modulator with quadrature jitter phase-locked loop detection, characterized in that, include: Lasers are used to provide continuous optical carriers; An optical IQ modulator, comprising an I-channel MZM, a Q-channel MZM, and a Ph phase shifter; Bias voltage source, used to provide adjustable DC bias for I, Q, Ph And superimposed with the perturbation signal from the jitter generator; A jitter signal generator is used to generate a frequency of The cosine and sine signals have amplitudes of ; A photodetector is used to monitor the output optical power of the IQ modulator and convert it into a current signal. ; Analog-to-digital converter for synchronous acquisition and reference signals; A digital signal processor is used to execute steps S3 to S6 of the method according to any one of claims 1 to 4 and output an updated bias voltage.

6. The system according to claim 5, characterized in that, The digital signal processor is a DSP or FPGA, which integrates a digital phase-locked loop (PLL) detection unit and a PI control unit. The PLL detection unit is used for calculation. The PI control unit is used to generate the bias voltage update value.

7. The system according to claim 5, characterized in that, The bias voltage source has an adder function, which can superimpose the DC bias and the jitter signal and apply them to each arm of the modulator.

8. The system according to claim 5, characterized in that, The sampling rate of the analog-to-digital converter jitter frequency It is 50 to 100 times faster, and all acquisition and processing are synchronized with the jitter signal.

9. The system according to claim 5, characterized in that, It also includes a host computer communication interface, which is used to receive the user-defined target operating point parameter Desired and polarity configuration, and to read the system status in real time.

Images