Thin film electro-optic modulator based on substrate transfer and method of making the same

Abstract

The application provides a substrate transfer-based thin film electro-optic modulator and a preparation method thereof, and relates to the technical field of optoelectronics. The preparation method comprises the following steps: forming a device layer on an initial substrate, bonding and connecting an intermediate substrate to a side of the device layer away from the initial substrate, removing the initial substrate, bonding and connecting a first substrate to a side of the device layer away from the intermediate substrate, and removing the intermediate substrate and forming an electro-optic modulator. The device layer comprises a waveguide layer and an electrode, and the electrode is arranged on a side surface of the waveguide layer; the initial substrate is arranged in a stack with the device layer. The scheme adopts a substrate transfer-based preparation method, the device is transferred to an optimized permanent substrate as a whole, the suspended thin film structure caused by direct etching and hollowing-out on a high dielectric constant substrate is avoided, and therefore, the mechanical strength is improved, the processing precision and yield are guaranteed by relying on a silicon-based platform, and the difficulty of direct processing of a non-standard substrate is avoided while good high-frequency performance is obtained.

Description

Technical Field

[0001] This application relates to the field of optoelectronic technology, and in particular to a thin-film electro-optic modulator based on substrate transfer and its fabrication method. Background Technology

[0002] Electro-optic materials, such as lithium niobate, lithium tantalate, barium titanate, and organic electro-optic polymers, have become the core platform for realizing ultra-wideband electro-optic modulators due to their excellent electro-optic effects, wide transparency windows, and low optical losses. The current mainstream approach is to bond these materials in thin films onto silicon substrates; however, the high dielectric constant of silicon severely limits the design of high-frequency electrodes. Existing technologies often employ back-side etching to remove the silicon substrate, distributing microwaves in a low-dielectric-constant medium. However, this approach significantly weakens the device's mechanical strength, increases manufacturing complexity, and deteriorates heat dissipation performance. Furthermore, using substrates such as quartz and sapphire also presents problems such as large differences in thermal expansion coefficients or excessively high dielectric constants. Summary of the Invention

[0003] This application provides a thin-film electro-optic modulator based on substrate transfer and its fabrication method. By transferring the entire device onto an optimized permanent substrate, the suspended thin-film structure caused by directly etching and hollowing out the substrate with a high dielectric constant is avoided. This not only achieves better high-frequency performance, but also significantly improves the mechanical strength of the electro-optic modulator and ensures processing accuracy and yield by relying on a silicon-based platform, thus avoiding the difficulties of directly processing non-standard substrates.

[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solutions: In a first aspect, a method for fabricating a thin-film electro-optic modulator based on substrate transfer is provided, comprising: forming a device layer on an initial substrate, bonding an intermediate substrate to the side of the device layer away from the initial substrate, removing the initial substrate, bonding a first substrate to the side of the device layer away from the intermediate substrate, and removing the intermediate substrate and forming an electro-optic modulator.

[0005] The device layer includes a waveguide layer and electrodes, with the electrodes disposed on one side surface of the waveguide layer; the initial substrate is stacked with the device layer.

[0006] The substrate-transfer-based thin-film electro-optic modulator fabrication method provided in this application avoids suspended thin-film structures by completely transferring the device to a permanent substrate (i.e., the first substrate), significantly improving mechanical strength. Simultaneously, the permanent substrate material can be flexibly selected according to application requirements, achieving comprehensive optimization of bandwidth, thermal matching, heat dissipation, and cost. Compared to methods that directly use heterogeneous substrates to fabricate devices, this method fully utilizes a mature silicon-based processing platform to complete high-precision front-side fabrication of the waveguide layer and electrodes on the initial substrate, and then obtains the final device by transferring the substrate to the first substrate. This ensures both processing accuracy and yield, while avoiding the difficulties of direct processing on non-standard substrates (such as quartz, sapphire with cavities, etc.).

[0007] In some embodiments, the waveguide layer is made of one or more of lithium niobate, lithium tantalate, barium titanate, or organic electro-optic polymers.

[0008] In some embodiments, the material of the first substrate includes at least one of quartz and diamond.

[0009] In some embodiments, the material of the first substrate includes at least one of silicon or sapphire; before bonding the first substrate to the side of the device layer away from the intermediate substrate, the method further includes: forming a groove on one side surface of the first substrate. The groove extends from one side surface of the first substrate into the interior of the first substrate. After bonding the first substrate to the side of the device layer away from the intermediate substrate, the device layer and the groove form a receiving cavity.

[0010] In some embodiments, forming a groove on one side surface of the first substrate includes: using deep reactive ion etching; the etching depth is 5 micrometers to 30 micrometers, and the width of the groove is 2 micrometers to 10 micrometers larger than the width of the electrode; the etching is performed using a Bosch process.

[0011] In some embodiments, bonding an intermediate substrate to the side of the device layer away from the initial substrate includes: forming an adhesive layer on the side of the device layer away from the initial substrate, and bonding the intermediate substrate to the adhesive layer.

[0012] The adhesive layer is made of temporary bonding adhesive; the intermediate substrate is made of at least one of silicon wafer, glass wafer or sapphire wafer.

[0013] In some embodiments, removing the initial substrate includes: mechanical polishing, and removing the remaining initial substrate after mechanical polishing by wet etching or reactive ion etching.

[0014] Mechanical grinding includes coarse grinding, medium grinding, and fine grinding. Coarse grinding uses grinding wheels with a particle size of 10 to 50 micrometers to thin the initial substrate to 100 micrometers. Medium grinding uses grinding wheels with a particle size of 5 to 20 micrometers. Fine grinding uses grinding wheels with a particle size of 1 to 10 micrometers. Wet etching uses tetramethylammonium hydroxide solution.

[0015] In some embodiments, bonding the first substrate to the side of the device layer away from the intermediate substrate includes: directly bonding the first substrate to the side of the device layer away from the intermediate substrate; or, using a bonding layer to bond the first substrate to the side of the device layer away from the intermediate substrate. The material of the bonding layer includes resin, and the dielectric constant of the bonding layer is less than 3.5.

[0016] Before direct bonding, the bonding surface is activated by oxygen plasma; after direct bonding, it is annealed for 1 to 4 hours.

[0017] In some embodiments, removing the intermediate substrate includes removing the intermediate substrate by at least one of thermal slip debonding, laser debonding, or chemical dissolution debonding.

[0018] In a second aspect, an electro-optic modulator is provided, which is prepared using the preparation method provided in any embodiment of the first aspect.

[0019] The technical effects brought about by the structural design of the electro-optic modulator in the second aspect can be referred to the technical effects brought about by the substrate transfer-based thin-film electro-optic modulator fabrication method in any embodiment of the first aspect, and will not be repeated here. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not actual dimensions of the products or actual processes of the methods involved in the embodiments of this application.

[0021] Figure 1 A flowchart illustrating the fabrication method of the electro-optic modulator provided in this application embodiment; Figures 2-4 This is a cross-sectional schematic diagram of the fabrication process of the electro-optic modulator provided in the embodiments of this application; Figures 5-7 A cross-sectional view of an electro-optic modulator provided in an embodiment of this application; Figure 8 Another cross-sectional view of the electro-optic modulator provided in the embodiments of this application. Detailed Implementation

[0022] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0023] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0024] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the aforementioned particular features, structures, materials, or characteristics may be included in any suitable manner in any one or more embodiments or examples.

[0025] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0026] Connection or link: can refer to a mechanical or physical connection relationship, that is, A and B are connected or linked. It can mean that there are fastened components (such as screws, bolts, rivets, etc.) between A and B, or that A and B are in contact with each other and are difficult to separate. A and B can be fixed, detachable, or integrated; they can be directly connected or indirectly connected through an intermediate medium.

[0027] Coupling can be understood as direct coupling and / or indirect coupling. "Coupled connection" can be understood as a direct coupling connection and / or indirect coupling connection. Direct coupling, also known as "electrical connection," refers to components being in direct or indirect physical contact and electrically conductive. For example, in circuit construction, different components are connected through physical lines that can transmit electrical signals, such as copper foil or wires on a printed circuit board (PCB). "Indirect coupling" can be understood as two conductors conducting electricity through a gap or without contact. In one embodiment, indirect coupling can also be called capacitive coupling, for example, using the coupling between two conductive parts to form an equivalent capacitance to achieve signal transmission.

[0028] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0029] This document describes exemplary embodiments with reference to sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0030] Furthermore, the scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0031] Figure 1 A flowchart illustrating the fabrication method of the electro-optic modulator 100 provided in this embodiment of the application.

[0032] Figures 2-4 This is a cross-sectional schematic diagram of the fabrication process of the electro-optic modulator 100 provided in the embodiments of this application.

[0033] This application also provides a method for fabricating an electro-optic modulator 100, such as... Figure 1 As shown, the preparation method includes the following steps S1 to S5: S1: See Figure 2 A device layer is formed on the initial substrate 7.

[0034] The device layer includes a waveguide layer 1 and an electrode 2; the electrode 2 is disposed on one side surface of the waveguide layer 1, and the initial substrate 7 is stacked with the device layer.

[0035] S2: See also Figure 2 The intermediate substrate 8 is bonded to the side of the device layer away from the initial substrate 7.

[0036] S3: See also Figure 2 Remove the initial substrate 7.

[0037] S4: See also Figure 2 The first substrate 3 is bonded to the side of the waveguide layer 1 away from the intermediate substrate 8.

[0038] S5: See Figure 2 Remove the intermediate substrate 8 to form an electro-optic modulator 100.

[0039] For example, see Figure 2 The device layer may further include a buried oxide layer 4, which is located between the first substrate 3 and the waveguide layer 1. The buried oxide layer 4 serves to provide electrical isolation, optical confinement, and stress buffering, preventing light field leakage from the waveguide layer 1 to the first substrate 3 and reducing the impact of interface defects on electro-optical performance. For example, the buried oxide layer 4 can be thermally oxidized silicon dioxide with a thickness of 1 μm to 5 μm.

[0040] For example, a thin-film electro-optic modulator wafer has been fabricated with front-side device layers such as an optical waveguide (waveguide layer 1) and a traveling-wave electrode (electrode 2). This wafer is a standard wafer of electro-optic material on insulator (such as LNOI, LTOI, BaTiO3-on-insulator, or organic electro-optic polymer-on-insulator). Its structure, from bottom to top, includes: a silicon substrate (i.e., initial substrate 7, with a thickness of 300 μm to 1000 μm, preferably high-resistivity silicon to reduce substrate loss), a buried oxide layer 4 (thermally oxidized silicon dioxide, with a thickness of 1 μm to 5 μm), and an electro-optic material thin film layer (including waveguide layer 1 and electrode 2, with a thickness of 0.2 μm to 5 μm). The optical waveguide is fabricated on the electro-optic material layer (e.g., lithium niobate) using standard micro-nano fabrication processes. The waveguide type can be a ridge waveguide, a strip waveguide, or a loaded waveguide. The waveguide sidewall tilt angle is approximately 70 degrees to 80 degrees, and the sidewall roughness is less than 5 nanometers. The traveling wave electrode (i.e., electrode 2) adopts a ground-signal-ground structure. The material of electrode 2 is a titanium / gold composite layer, copper or aluminum, with a thickness of 0.1μm~3μm, a signal line width of 5μm~50μm, a gap of 5μm~15μm between electrodes, and a total length of 2mm~10mm.

[0041] For example, the specific implementation process of step S1 is as follows: A 6-inch (150 mm diameter) X-cut lithium niobate-on-insulator (LNOI) wafer was selected. This wafer was fabricated using a smart-cut ion-cutting technique. Its structure, from bottom to top, consists of: a 625 μm thick high-resistivity silicon substrate (resistivity greater than 10 kΩ·cm), a 2 μm thick thermally oxidized silicon dioxide buried oxide layer, and a 400 nm thick X-cut thin-film lithium niobate layer. The wafer is polished on both sides, achieving a surface roughness of less than 0.5 nm. If barium titanate or organic electro-optic polymers are used, the corresponding electro-optic material wafer on insulator is selected, and the thickness can be adjusted according to the material properties.

[0042] Optical waveguides were fabricated on thin-film lithium niobate layers using standard micro / nano fabrication processes. First, an electron beam photoresist (AR-P 6200) of approximately 300 nm thickness was spin-coated onto the wafer surface and pre-baked at 90°C for 90 seconds. Then, an electron beam exposure apparatus (accelerating voltage 100 kV, dose 300 μcoulombs per square centimeter) was used to define a ridge waveguide pattern with a designed width of 1.5 μm. After exposure, the waveguide was developed in AR 600-546 developer for 60 seconds, rinsed with deionized water, and dried with nitrogen. Subsequently, lithium niobate was etched using inductively coupled plasma etching (ICP-RIE) with a mixture of argon and trifluoromethane (flow rate ratio 10:15), a chamber pressure of 5 mTorr, ICP power of 800 W, RF bias power of 150 W, an etching time of 120 seconds, and an etching depth of 200 nm, forming a ridge waveguide with a ridge height of 200 nm and a planar region thickness of 200 nm. For barium titanate materials, the etching gas can be adjusted to a chlorine-based gas; for organic electro-optic polymers, reactive ion etching or ultraviolet lithography can be used for direct patterning. After etching, the photoresist is removed, and the waveguide sidewall roughness is less than 5 nm as measured by atomic force microscopy. The transmission loss in the communication band (1550 nm) is less than 0.2 dB per centimeter.

[0043] Further, a traveling wave electrode (i.e., electrode 2) was fabricated. A double-layer photoresist was spin-coated (lower layer: LOR 10B, 500 nm thick, baked at 190°C for 5 minutes; upper layer: AZ 5214E, 1 μm thick, pre-baked at 95°C for 90 seconds). Mask alignment and exposure were performed using an i-line UV lithography machine (365 nm) at an exposure dose of 120 mJ / cm², defining a ground-signal-ground electrode pattern, where the signal line width was 10 μm, the gap between the signal and ground lines was 8 μm, and the total length of electrode 2 was 5 mm. Development was performed in AZ 400K developer (diluted 1:3 with water) for 45 seconds, followed by rinsing with deionized water. Then, metal deposition was performed using an electron beam evaporation apparatus: first, a 20 nm titanium layer was deposited at a rate of 0.5 Å / s as an adhesion layer, followed by a 500 nm gold layer at a rate of 2 Å / s, with a vacuum level better than 5 × 10⁻⁶. -7 The wafer is then immersed in N-methylpyrrolidone (NMP) at 80°C for 30 minutes after deposition, followed by ultrasonic lift-off, and then sequentially cleaned with acetone, isopropanol, and deionized water, and dried with nitrogen. This yields a titanium / gold traveling wave electrode with steep edges and a thickness of approximately 520 nm. Optionally, a thin film of silicon oxide is deposited below or above electrode 2 for protection.

[0044] For example, the specific implementation process of step S2 is as follows: A temporary bonding adhesive (i.e., adhesive layer 9) is spin-coated onto the surface of the device layer (i.e., the side of the waveguide layer 1 away from the initial substrate 7). The temporary bonding adhesive can be selected from thermoplastic resin, photosensitive adhesive, or thermally decomposable adhesive, and the spin-coating thickness is 5μm~30μm. The side of the device with adhesive layer 9 is temporarily bonded to the intermediate substrate 8 at the wafer level. The intermediate substrate 8 can be selected from silicon wafer, glass wafer, or sapphire wafer, and its diameter matches that of the device wafer (3 inches, 4 inches, 6 inches, 8 inches, or 12 inches), and its thickness is 300μm~1000μm. The temporary bonding is performed in a vacuum bonding device, with the bonding temperature controlled at 50 to 250 degrees Celsius, the pressure at 0.1 to 1 MPa, and the time at 5 to 30 minutes. The temporary bonding adhesive softens and fills the tiny gaps at the interface under heating and pressure. After cooling, it solidifies to form a strong temporary bonding layer (i.e., the adhesive layer 9 mentioned later), which provides sufficient mechanical support for the complete removal of the original silicon substrate in the subsequent step S3 (removal of the initial substrate 7).

[0045] For example, step S3: Completely remove the initial substrate 7 by mechanical polishing combined with wet etching or reactive ion etching. Mechanical polishing is divided into three stages: coarse polishing, medium polishing and fine polishing. Coarse polishing uses a grinding wheel with a particle size of 10μm to 50μm to thin the silicon substrate to 100μm. Medium polishing uses a grinding wheel with a particle size of 5μm to 20μm. Fine polishing uses a grinding wheel with a particle size of 1μm to 10μm. Then, wet etching is performed using tetramethylammonium hydroxide solution until the initial substrate 7 is completely removed and stops on the surface of the buried oxide layer 4.

[0046] For example, the first substrate 3 is selected from quartz wafers, sapphire wafers, silicon wafers, or diamond wafers, with a thickness of 200μm to 1000μm, a surface roughness of less than 0.5nm, and a diameter matching that of the device wafer. The bonding method can be direct bonding or resin adhesive bonding.

[0047] For example, when the first substrate 3 is quartz, its extremely low dielectric constant directly achieves excellent microwave loss and extremely high bandwidth; when the first substrate 3 is sapphire, its thermal expansion coefficient, which matches that of electro-optic materials, achieves excellent temperature stability. At the same time, by pre-etching hollow grooves (i.e., grooves K, without deep etching) on ​​the surface of sapphire, its equivalent dielectric constant can be effectively reduced, taking into account both thermal matching and high-frequency performance.

[0048] Alternatively, for example, when silicon is used as the first substrate 3, its mature process and low cost can be utilized to form an air cavity with surface hollowing grooves (i.e., grooves K), achieving perfect speed matching and low high-frequency microwave loss while retaining the excellent heat dissipation capabilities of the silicon substrate; when diamond is used as the first substrate 3, its ultra-high thermal conductivity (>1800 W·m) can be utilized. -1 ·K -1With a moderate dielectric constant (approximately 5.7), it solves the thermal management problem under high power density.

[0049] For example, if the first substrate 3 is made of quartz or diamond, then step S4 can be performed by directly performing permanent bonding. If the first substrate 3 is made of silicon or sapphire, then a hollow structure (i.e., groove K) needs to be made on the surface of the first substrate 3 before permanent bonding in step S4 to reduce its equivalent dielectric constant.

[0050] Specifically, a silicon substrate is used as the initial substrate 7. Due to the mature and high-precision silicon-based processing platform, this embodiment prefabricates the required electro-optic structure (including the optical waveguide pattern on the waveguide layer 1 and the electrode 2) on the silicon substrate, achieving high-resolution photolithography alignment and low-damage etching quality. This fully utilizes the mature silicon-based processing platform to complete the fabrication of the front-side device, thereby ensuring processing accuracy and yield. Subsequently, through the bonding and transfer processes in steps S2 to S5, the waveguide layer 1 and the electrode 2 are transferred as a whole to the optimized first substrate 3, while the high-dielectric-constant initial silicon substrate is removed.

[0051] In the fabrication method of the optoelectronic modulator 100 provided in this application, the suspended thin film structure is avoided by transferring the device completely to a permanent substrate (i.e., the first substrate 3), thus significantly improving mechanical strength. Simultaneously, the permanent substrate material can be flexibly selected according to application requirements, achieving comprehensive optimization of bandwidth, thermal matching, heat dissipation, and cost. Compared with the scheme of directly using a heterogeneous substrate to fabricate the device, this scheme fully utilizes a mature silicon-based processing platform to complete the high-precision front-side fabrication of the waveguide layer 1 and electrode 2 on the initial substrate 7, and then transfers the device to the first substrate 3 to obtain the final device. This ensures both processing accuracy and yield, while avoiding the difficulties of direct processing on non-standard substrates (such as quartz, sapphire with cavities, etc.).

[0052] In some embodiments, the waveguide layer 1 is made of one or more of lithium niobate, lithium tantalate, barium titanate, or organic electro-optic polymers.

[0053] For example, an optical waveguide can be fabricated on the electro-optic material layer mentioned above using standard micro-nano fabrication processes. The waveguide type can be a ridge waveguide, a strip waveguide, or a loaded waveguide, thereby forming waveguide layer 1. The waveguide sidewall tilt angle is about 70 to 80 degrees, the sidewall roughness is less than 5 nm, and the thickness of waveguide layer 1 is 0.2 μm to 5 μm.

[0054] In some embodiments, the material of the first substrate 3 includes at least one of quartz and diamond.

[0055] For example, the dielectric constant of quartz is about 3.8; the dielectric constant of diamond is about 5.0 to 5.7.

[0056] That is, by directly fabricating the first substrate 3 using a material with a relatively small dielectric constant, this embodiment can effectively reduce the equivalent dielectric environment experienced by microwave transmission without increasing additional structural deformation or introducing complex processes, thereby achieving a good match between the microwave equivalent refractive index and the optical wavegroup refractive index, improving the modulation bandwidth, and maintaining the integrity and good mechanical strength of the substrate.

[0057] For example, the specific implementation process of using quartz as the first substrate 3 and performing direct bonding is as follows: The silicon-based thin-film electro-optic modulator wafer that has undergone front-side processing using the method described in step S1 above will not be elaborated here.

[0058] Temporary bonding. Laser-debonded temporary bonding is performed on the surface of the device layer after front-side processing. In this embodiment, the LTHC (Light-to-Heat Conversion) laser debonding system from 3M is used. First, an LTHC photothermal conversion layer is spin-coated onto the device surface at 1500 rpm for 30 seconds, resulting in a uniform coating approximately 1 μm thick. This coating is then baked on a hot plate at 120°C for 2 minutes. Next, temporary bonding adhesive (3M LC-3200 series) is spin-coated onto the LTHC layer at 1000 rpm for 30 seconds, resulting in a uniform adhesive layer approximately 20 micrometers thick. This adhesive is then soft-baked on a hot plate at 150°C for 5 minutes.

[0059] Prepare a 6-inch glass wafer (such as BF33 or quartz glass) as the intermediate substrate 8, with a thickness of 500 micrometers, double-sided polished, and a transmittance greater than 90% at a wavelength of 365 nm. Align and bond the device wafer (adhesive side down) to the glass intermediate substrate 8 in a vacuum bonding apparatus. The bonding parameters are: cavity pressure less than 10... -3 The bonding temperature is 150°C, the bonding pressure is 0.3 MPa, and the holding time is 5 minutes. This temporary bonding adhesive is temperature-insensitive after curing and maintains stable adhesion in subsequent processes at 200 to 300°C.

[0060] The original silicon substrate (initial substrate 7) was completely removed. Mechanical grinding was performed first to thin it. A fully automated double-sided grinding machine (Disco DGP8761) was used, divided into three stages: In the coarse grinding stage, a 20-micron (approximately 800 mesh) diamond wheel was used, with a grinding pressure of 0.5 MPa, a working disc speed of 60 rpm, a deionized water flow rate of 500 ml / min, and a temperature controlled at 22±1 degrees Celsius. The silicon substrate was thinned from 625 microns to 150 microns, removing approximately 475 microns of thickness, taking about 30 minutes. In the medium grinding stage, a 9-micron (approximately 1800 mesh) diamond wheel was used, with a grinding pressure... The grinding pressure was reduced to 0.3 MPa, and the rotation speed was 50 rpm. The silicon substrate was thinned from 150 μm to 50 μm, removing 100 μm, which took approximately 35 minutes. In the fine grinding stage, a diamond wheel with a grit size of 3 μm (approximately 4000 mesh) was used. The grinding pressure was reduced to 0.2 MPa, the rotation speed was 40 rpm, and 0.5% surfactant was added to the grinding slurry to reduce frictional heat. The silicon substrate was then thinned from 50 μm to 25 μm, with the feed rate controlled at 1 μm per minute, which took approximately 25 minutes. During the grinding process, the thickness was monitored in real time using a laser displacement sensor to ensure uniform thinning. After fine grinding, the surface roughness was less than 0.1 μm, and the thickness uniformity was better than ±1 μm.

[0061] Chemical mechanical polishing (CMP) was then performed to remove the abrasion damage layer and further thin the substrate. The polishing slurry used was Cabot's Semi-Sperse 25 silicon-based CMP slurry, primarily composed of colloidal silica abrasive particles with a particle size of 50 to 100 nanometers and a pH of approximately 10.5. The polishing pad was an IC1000 soft polyurethane polishing pad. The polishing parameters were: polishing pressure 0.15 MPa, polishing head speed 70 rpm, polishing pad speed 60 rpm, polishing slurry flow rate 200 ml / min, and polishing time 8 minutes. During the polishing process, the thickness was monitored online using infrared interferometry, precisely reducing the silicon substrate thickness from 25 micrometers to approximately 20 micrometers. After polishing, the surface roughness of the silicon substrate was less than 0.5 nanometers, the thickness uniformity (TTV) was better than ±1 micrometer, and there were no scratches, microcracks, or residual stress layers.

[0062] Finally, wet etching was used to completely remove the remaining silicon. The thinned wafer was immersed in a 25% (w / w) tetramethylammonium hydroxide (TMAH) solution at 80°C, with magnetic stirring at 300 rpm to ensure uniform etching. TMAH has high selectivity for silicon, with an etching rate of less than 0.1 nm per minute for silicon dioxide. The etching rate was approximately 1.2 μm per minute, and the silicon substrate was completely removed after about 17 minutes, precisely stopping at the buried oxide layer surface. When the silicon was completely removed, the wafer surface color changed from gray to transparent, a noticeable change visible to the naked eye. Immediately after etching, the wafer was rinsed three times in deionized water for 5 minutes each time, then rinsed for 10 seconds in a 1% (v / v) dilute hydrofluoric acid solution to remove the native oxide layer, rinsed again with deionized water, and finally dried with high-purity nitrogen. The surface roughness of the exposed buried oxide layer was measured using atomic force microscopy and was less than 0.5 nm; the thickness of the buried oxide layer was measured using an ellipsometry and was 2 μm ± 5 nm.

[0063] Permanent bonding to a quartz substrate (first substrate 8). A 6-inch fused silica wafer, 500 micrometers thick, is prepared as the permanent substrate, polished on both sides, with a surface roughness of less than 0.5 nanometers. The coefficient of thermal expansion of quartz material is 0.5 × 10⁻⁶. -6 Per Kelvin, dielectric constant is approximately 3.8 (at 10 GHz), refractive index is 1.46, and thermal conductivity is 1.4 W / m / Kelvin.

[0064] The device wafers with exposed buried oxide layers and the quartz substrate underwent standard RCA cleaning: First, they were cleaned for 10 minutes at 80°C in an SC1 solution with a volume ratio of ammonia:hydrogen peroxide:deionized water of 1:1:5 to remove particulates and organic contaminants; then, they were cleaned for 10 minutes at 80°C in an SC2 solution with a volume ratio of hydrochloric acid:hydrogen peroxide:deionized water of 1:1:6 to remove metal ions; finally, they were rinsed 5 times with deionized water for 2 minutes each time, followed by spin drying (2000 rpm, 60 seconds). Immediately after cleaning, both wafers were placed in an oxygen plasma chamber for activation treatment at an oxygen flow rate of 100 standard cubic centimeters per minute, a chamber pressure of 200 millitriles, an RF power of 100 watts, and a treatment time of 60 seconds. After activation, silanol groups (Si-OH) were generated on the wafer surface, the water contact angle decreased to below 5 degrees, and the surface energy was significantly improved.

[0065] Two activated wafers were aligned and bonded in a clean environment at room temperature, using the flat edges of the wafers as alignment marks. Bonding began from the center of the wafers, allowing the bonding interface to expand naturally due to surface tension. After pre-bonding, the wafers were allowed to stand for 30 minutes. The bonded pair was then placed in an annealing furnace and heated to 200°C at a rate of 5°C per minute in a high-purity nitrogen atmosphere (99.999% purity, flow rate 1000 standard cubic centimeters per minute). This temperature was maintained for 2 hours, followed by natural cooling to room temperature. During annealing, adjacent silanol groups underwent a condensation reaction to form silicon-oxygen-silicon covalent bonds, achieving a bond strength of over 1 joule per square meter. The bonding interface was examined using an infrared microscope, showing a bonding rate greater than 99.9%, with no bubbles or cracks.

[0066] Debonding and removal of the intermediate substrate 8. The glass intermediate substrate 8 is removed using laser debonding. An excimer laser with a wavelength of 308 nm and a laser energy density of approximately 300 to 400 millijoules per square centimeter is used to scan and irradiate the back side (device-free side) of the glass intermediate substrate 8. The laser light is absorbed by the LTHC layer after passing through the glass, generating instantaneous high temperatures that decompose and vaporize the LTHC layer, while the temporary bonding adhesive loses its adhesion. After irradiation, the glass intermediate substrate 8 automatically separates under gravity or with slight mechanical assistance. After debonding, the device wafer is immersed in a special cleaning agent (3M LTHC Remover) at 60 degrees Celsius for 10 minutes, then rinsed with isopropanol and deionized water, and dried with nitrogen. No adhesive residue remains on the surface after cleaning.

[0067] In some embodiments, step S3: removing the initial substrate 7 includes the following steps S31~S32: S31: Mechanical grinding is employed.

[0068] S32: The initial substrate 7 remaining after mechanical polishing is removed by wet etching or reactive ion etching.

[0069] The mechanical polishing process is divided into three stages: coarse polishing, medium polishing, and fine polishing. Coarse polishing uses a grinding wheel with a particle size of 10μm to 50μm to thin the silicon substrate to 100μm. Medium polishing uses a grinding wheel with a particle size of 5μm to 20μm. Fine polishing uses a grinding wheel with a particle size of 1μm to 10μm. Then, a tetramethylammonium hydroxide solution is used for wet etching until the initial substrate 7 is completely removed and the process stops at the surface of the buried oxide layer 4.

[0070] For example, the specific implementation process of steps S31 to S32 is the same as the process of removing the initial substrate 7 when using quartz as the first substrate 3, and will not be repeated here.

[0071] In some embodiments, step S5: removing the intermediate substrate 8 includes removing the intermediate substrate 8 by at least one of thermal slip debonding, laser debonding, or chemical dissolution debonding.

[0072] Exemplary methods include thermal slip debonding, which involves heating the bonded pairs to the softening temperature of the temporary bonding adhesive (typically 200 to 280 degrees Celsius) while applying a shear force of 50 to 200 Newtons to cause the intermediate substrate 8 to slip and separate. Laser debonding involves irradiating the temporary bonding adhesive layer with a laser of a specific wavelength (e.g., 308 nm) through the intermediate substrate 8 (e.g., glass), causing the adhesive layer to vaporize and decompose instantaneously. Chemical dissolution debonding involves immersing the bonded pairs in a specialized solvent (e.g., N-methylpyrrolidone, dimethyl sulfoxide, etc.) at 60 to 80 degrees Celsius for 30 to 60 minutes to completely dissolve the temporary bonding adhesive. After debonding, residual temporary bonding adhesive is removed with a cleaning agent, and the pair is rinsed with deionized water and dried with nitrogen to obtain the thin-film electro-optic modulator 100 transferred onto the final substrate.

[0073] Furthermore, after bonding is completed in step S5, as Figure 8 As shown, through-silicon vias (TSVs) or through-glass vias (TGVs) or vias can be selectively fabricated on the back side of the first substrate 3 to create contact structures 6 that connect to the electrode 2, facilitating subsequent flip-chip packaging and integration with the driver chip. The specific implementation process is as follows: First, the first substrate 3 was mechanically thinned to 200 μm (using the same polishing process as S3) to reduce the via aspect ratio. Then, AZ 4620 thick photoresist, 5 μm thick, was spin-coated onto the back of the first substrate 3 and pre-baked at 95 degrees Celsius for 90 seconds. The via pattern was defined using mask alignment exposure (dose 150 mJ / cm²) with a via diameter of 50 μm, aligned with the pad area of ​​the front metal electrode 2. Development was performed in AZ 400K developer (diluted 1:3 with water) for 60 seconds, followed by rinsing with deionized water. ICP-RIE etching was then performed on the quartz using a mixture of carbon tetrafluoride and trifluoromethane (volume ratio 4:1), a total flow rate of 50 standard cubic centimeters per minute, a chamber pressure of 10 mTorr, an ICP power of 800 W, an RF bias power of 200 W, an etching rate of approximately 0.5 μm per minute, and etching for approximately 400 minutes until the metal electrode 2 was exposed. Following etching, a 0.5 μm thick silicon dioxide insulating layer was deposited on the inner wall of the via using plasma-enhanced chemical vapor deposition (PECVD) at a deposition temperature of 200 degrees Celsius. Then, 30 nm titanium and 200 nm copper were sequentially deposited as seed layers via magnetron sputtering, with a sputtering vacuum level better than 5 × 10⁻⁶. -6The setup was as follows: argon pressure 5 mTorr, titanium target DC power 100 W, copper target DC power 150 W. The wafer was immersed in a copper sulfate plating solution (containing 80 g / L copper sulfate, 200 g / L sulfuric acid, 50 mg / L chloride ions, and appropriate additives), with the seed layer as the cathode, a current density of 0.5 amperes per square decimeter, and a temperature of 25°C for 90 minutes, allowing copper to completely fill the vias and form a capping layer of approximately 10 μm on the surface. Finally, excess copper on the back side was removed by CMP, making the copper pillars in the vias flush with the quartz surface. Titanium / copper (20 nm / 500 nm) was then sputtered onto the back side, patterned by photolithography, and electroplated to a thickness of 2 μm to form a redistribution layer and pads.

[0074] For example, the difference in the coefficient of thermal expansion between the initial substrate 7 and the device layer is smaller than the difference in the coefficient of thermal expansion between the first substrate 3 and the device layer.

[0075] Specifically, the difference in the coefficient of thermal expansion between the initial substrate 7 and the device layer, that is, the difference in the coefficient of thermal expansion between the electro-optic materials (such as lithium niobate, lithium tantalate, barium titanate, or organic electro-optic polymers) used in the waveguide layer 1.

[0076] For example, taking the lithium niobate waveguide layer 1 as an example, the coefficient of thermal expansion of silicon (initial substrate 7) is approximately 2.6 × 10⁻⁶. -6 / K, and the coefficient of thermal expansion of lithium niobate (approximately 5.0 × 10⁻⁶). -6 The difference in thermal expansion coefficient ( / K) is small; while the coefficient of thermal expansion of quartz (which can be used as the first substrate 3) is approximately 0.55 × 10⁻⁶. -6 / K differs significantly from lithium niobate.

[0077] Since the steps of fabricating the device layer (including waveguide layer 1 and electrode 2) are all completed on the initial substrate 7, and the difference in thermal expansion coefficient between the initial substrate 7 and the device layer is small, excessive thermal stress can be avoided in high-temperature processes (such as electrode annealing and bonding curing), thereby reducing the risk of device cracking or performance degradation. This results in more stable processing accuracy and device performance compared to fabricating the device layer directly on the first substrate 3, effectively ensuring the quality and yield of the electro-optic modulator 100.

[0078] In some embodiments, see Figure 7 The material of the first substrate 3 includes at least one of silicon or sapphire; before step S4: bonding the first substrate 3 to the side of the device layer away from the intermediate substrate 8, the method further includes step S301: S301: A groove K is formed on one side surface of the first substrate 3.

[0079] The groove K extends from one side surface of the first substrate 3 into the interior of the first substrate 3. After the first substrate 3 is bonded to the side of the device layer away from the intermediate substrate 8, the device layer and the groove K form a receiving cavity Q.

[0080] For example, silicon has a dielectric constant of about 11.7, sapphire has a dielectric constant of about 9.4 to 11.5, and the cavity Q of the first substrate 3 can be filled with air or other low dielectric constant materials, thereby significantly reducing the effective dielectric constant of the first substrate 3 compared to the original silicon or sapphire.

[0081] For example, after the device layer is bonded to the first substrate 3, the groove K is sealed to form a closed air cavity (i.e., the cavity Q is filled with closed air). The microwaves are mainly transmitted in the air (with a dielectric constant of about 1). Through this structure, the effective dielectric constant can be reduced to 2.0~2.2, which is well matched with the group refractive index (about 2.2) of the electro-optic material waveguide.

[0082] Furthermore, compared to the approach that requires deep etching of a large area of ​​the substrate to form a suspended thin film, this embodiment has two advantages: First, the sealed cavity Q and the complete waveguide layer 1 form an integral composite substrate with no suspended areas, resulting in higher mechanical strength and avoiding problems such as film rupture and stress concentration caused by deep etching, thereby improving device reliability and process yield. Second, the groove K is pre-processed before the first substrate 3 is bonded to the waveguide layer 1, rather than being etched or drilled on the completed device, so that the key device layers (waveguide layer 1 and electrode 2) are completely free from mechanical impact and damage during the grooving process, while the first substrate 3 still maintains sufficient strength to support subsequent processes after grooving.

[0083] In practical applications, the selection can be made based on the comprehensive requirements for bandwidth, heat dissipation, thermal stress, and process cost.

[0084] For example, the receiving cavity Q can be as follows: Figure 3 The diagram shows a single, continuous, large-sized groove, but it can also consist of multiple independent, small grooves located directly below electrode 2 and isolated from each other. Regardless of whether the cavity Q is a single integral structure or multiple discrete structures, as long as it enables microwave transmission within a region dominated by a low-dielectric-constant medium (such as air), thereby effectively reducing the overall effective dielectric constant, the technical effect of extending the modulation bandwidth can be achieved. All the above-described different implementations alter the equivalent dielectric environment of the microwaves by introducing the cavity Q structure; therefore, any specific implementation using such a structure to achieve a low effective dielectric constant falls within the protection scope of this application.

[0085] For example, when silicon is used as the first substrate 3, the specific implementation process of step S301 is as follows: A 6-inch high-resistivity silicon wafer is selected as the first substrate 3, with a thickness of 500 μm and a resistivity greater than 10 kΩ·cm, and double-sided polished. AZ 5214E ​​photoresist is spin-coated onto the silicon substrate surface, with a thickness of 1.5 μm, and pre-baked at 95 degrees Celsius for 90 seconds. A stepper lithography machine (i-line, 365 nm) is used for mask alignment and exposure to define the hollowed-out pattern. The hollowed-out groove (i.e., the groove K) is located directly below the front electrode 2 and the waveguide. For example, the groove K can be 20 μm wide (10 μm larger than the signal line), 5 mm long, and rectangular in shape. The exposure dose is 120 mJ / cm². 2 Develop in AZ 400K developer (diluted with water 1:3) for 45 seconds, then rinse with deionized water.

[0086] Furthermore, a deep reactive ion etching (DRIE) apparatus was used, with an etching depth of 5μm~30μm. The trench width was 2μm~10μm larger than the width of electrode 2, and silicon was etched using Bosch technology. Each etching cycle consisted of: an etching step with sulfur hexafluoride introduced at 200 standard cubic centimeters per minute, a pressure of 20 millitor, an ICP power of 2000 watts, a bias power of 50 watts, and a time of 5 seconds; and a passivation step with octafluorocyclobutane introduced at 150 standard cubic centimeters per minute, a pressure of 20 millitor, an ICP power of 1500 watts, a bias power of 30 watts, and a time of 3 seconds. The cycle was repeated 300 times, with a total etching depth of approximately 30 micrometers. The sidewall angle after etching was approximately 88 degrees, nearly vertical. The photoresist was then removed using oxygen plasma. The grooved silicon substrate was cleaned in an RCA solution and then thermally oxidized in an oxygen atmosphere at 1000 degrees Celsius for 2 hours to generate a silicon dioxide layer of about 100 nanometers thickness on the silicon surface (including the inner wall of the groove K) as an electrical insulating layer.

[0087] Alternatively, exemplarily, when sapphire is used as the first substrate 3, the specific implementation process of step S301 is as follows: A 4-inch sapphire wafer is selected as the first substrate 3. The steps of photoresist spin coating, exposure and development, groove K size, and cleaning have been described in the silicon substrate example above and will not be repeated here. The difference lies in the etching process: After exposure and development, inductively coupled plasma reactive ion etching (ICP-RIE) is used to etch the sapphire. The etching gas is a mixture of boron trichloride and argon (volume ratio 3:1), with a total flow rate of 50 standard cubic centimeters per minute, a chamber pressure of 5 millitor, an ICP power of 1000 watts, an RF bias power of 300 watts, an etching rate of approximately 0.3 μm per minute, and an etching depth of approximately 30 micrometers achieved in approximately 100 minutes. The sidewall angle after etching is approximately 85 degrees. The photoresist is removed using oxygen plasma, and the grooved sapphire substrate is cleaned in an RCA solution.

[0088] In some embodiments, the aforementioned step S301: forming a groove K on one side surface of the first substrate 3 includes: using deep reactive ion etching; the etching depth is 5 micrometers to 30 micrometers, and the width of the groove K is 2 micrometers to 10 micrometers larger than the width of the electrode; the etching is performed using the Bosch process.

[0089] The specific implementation process of deep reactive ion etching has been described in the aforementioned step S301, and will not be repeated here.

[0090] In this embodiment, the width of the groove K is set to be 2 to 10 micrometers larger than the width of the electrode 2. This can effectively avoid unnecessary electrical contact or short circuit between the electrode 2 and the first substrate 3, reduce parasitic capacitance, and help improve the high-frequency modulation bandwidth. Furthermore, this range provides sufficient tolerance space for photolithography alignment and substrate bonding processes, and will not significantly weaken the mechanical support strength of the first substrate 3 or increase the overall size of the device due to an excessively wide groove K, thus achieving a good balance between electrical performance and process feasibility.

[0091] In some embodiments, after the first substrate 3 with the groove K is fabricated, step S4 is further performed. Step S4: bonding the first substrate 3 to the side of the device layer away from the intermediate substrate 8 includes: like Figure 3 As shown, the first substrate 3 is directly bonded to the side of the device layer away from the intermediate substrate 8; or, as... Figure 4 As shown, the first substrate 3 is bonded to the side of the device layer away from the intermediate substrate 8 using a bonding layer 5. The material of the bonding layer 5 includes resin, and the dielectric constant of the bonding layer 5 is less than 3.5.

[0092] Before direct bonding, the bonding surface is activated by oxygen plasma; after direct bonding, it is annealed for 1 to 4 hours.

[0093] For example, such as Figure 3 As shown, the specific implementation process of permanent bonding in step S4 when silicon is used as the first substrate 3 is as follows: The buried oxide layer 4 wafer (device wafer) exposed in step 301 is activated with oxygen plasma on the first substrate 3 with groove K. The activation parameters are the same as those used in the preparation of the quartz substrate. A high-precision wafer bonding machine (EVG540) is used, which is equipped with an infrared alignment system that allows the alignment marks to be observed through the silicon. The groove K is precisely aligned with the front electrode 2, with an alignment accuracy better than ±2μm. This is done at room temperature and a chamber pressure below 10. -3 Pre-bonding was performed for 5 minutes under millibar and a bonding pressure of 0.5 MPa. The bonded pairs were then annealed for 2 hours in a nitrogen atmosphere at 200°C to enhance bond strength. The groove K was sealed by the bonding interface, forming a closed receiving cavity Q.

[0094] Or, for example, such as Figure 4 As shown, when sapphire is used as the first substrate 3, direct bonding between sapphire and silicon dioxide (i.e., buried oxide layer 4) is difficult (although the difference in thermal expansion coefficients is small, the surface activity is low). Therefore, this embodiment uses a bonding layer 5 made of a low dielectric constant resin material (such as BCB, photosensitive polyimide, etc.) for bonding. This bonding layer 5 can achieve low-temperature bonding of heterogeneous materials, effectively avoiding high-temperature thermal stress; its flexible properties can buffer thermal expansion mismatch and improve device reliability; at the same time, the bonding layer 5 helps to seal the cavity Q and maintain a low dielectric constant environment inside the cavity; in addition, combined with its own low dielectric constant, it will not have an adverse effect on high-frequency performance.

[0095] Exemplarily, the specific implementation process of step S4 using sapphire as the first substrate 3 is as follows: BCB resin (Cyclotene 3022-35) is sprayed onto the surface of the sapphire substrate (first substrate 3) with grooves K to obtain a uniform resin layer with a thickness of approximately 5 μm. The solvent is removed by soft baking on a hot plate at 120 degrees Celsius for 2 minutes, and then pre-cured in a vacuum oven at 150 degrees Celsius for 30 minutes. The buried oxide layer 4 wafer exposed in step S3 is aligned and bonded to the BCB-coated sapphire substrate in a vacuum bonding device, using the wafer edge flatness and the groove K pattern for alignment, with an alignment accuracy better than ±2 μm. The bonding parameters are: cavity pressure less than 10... -3 The bonding was performed at a pressure of 0.3 MPa, a bonding temperature of 200 degrees Celsius, and a holding time of 10 minutes. The bonded pairs were then cured in a nitrogen atmosphere at 250 degrees Celsius for 1 hour to fully crosslink the BCB.

[0096] It is worth noting that the steps of S1~S3 and S5 mentioned above, as well as the specific implementation process of using quartz as the first substrate 3, can be referred to to complete the steps of silicon-based thin film electro-optic modulator wafer processing on the front side of silicon or sapphire, temporary bonding, complete removal of the initial substrate 7, and debonding and removal of the intermediate substrate 8. These steps will not be repeated here.

[0097] In some embodiments, see 5~ Figure 7 Step S2: Bonding the intermediate substrate 8 to the side of the device layer away from the initial substrate 7 includes the following steps S21~S22: S21: An adhesive layer 9 is formed on the side of the device layer away from the initial substrate 7.

[0098] S22: Bond the intermediate substrate 8 to the adhesive layer 9.

[0099] The adhesive layer 9 is made of temporary bonding adhesive; the intermediate substrate 8 includes at least one of silicon wafer, glass wafer or sapphire wafer.

[0100] For example, since there are protruding electrodes 2 (typically 0.1μm to 3μm thick) on the surface of the device layer, direct bonding with the intermediate substrate 8 will lead to bonding failure due to surface unevenness. In this embodiment, a thicker adhesive layer 9 is spin-coated to effectively cover the morphology of the electrode 2 and the waveguide layer 1 surface, providing a flat bonding interface.

[0101] Furthermore, by using adhesive layer 9 to temporarily bond the intermediate substrate 8 to the device, selective dissolution or thermal decomposition of adhesive layer 9 can be applied only during the subsequent removal of the intermediate substrate 8, without requiring destructive treatments such as mechanical polishing or chemical etching of the intermediate substrate 8 or waveguide layer 1, thereby reducing the risk of process damage. The specific steps for removing the adhesive layer 9 have been described in the aforementioned step S5 (removal of intermediate substrate 8) and will not be repeated here.

[0102] It is worth noting that the temporary bonding adhesive used in the adhesive layer 9 is not sensitive to temperature and can withstand the curing process of the subsequent curing layer 5 (i.e., BCB resin) at 250 degrees Celsius without softening or decomposing. This allows the high-temperature curing step to still be carried out after the adhesive layer 9 is bonded to the intermediate substrate 8 without affecting the stability of the temporary bonding interface, ensuring that the wafer does not warp or slip during subsequent processes.

[0103] The selection of the adhesive layer 9 material and its process adaptability can be optimized according to the type of intermediate substrate 8 actually used and the subsequent thermal budget. All technical solutions that connect the waveguide layer 1 and the intermediate substrate 8 through a temporary bonding layer fall within the protection scope of this application.

[0104] Figures 5-7 A cross-sectional view of the electro-optic modulator 100 provided in an embodiment of this application; Figure 8 Another cross-sectional view of the electro-optic modulator 100 provided in the embodiments of this application.

[0105] This application also provides an optoelectronic modulator 100, which is prepared using the preparation method provided in any of the foregoing embodiments.

[0106] See Figures 5-7 The electro-optic modulator 100 includes a waveguide layer 1, an electrode 2, and a first substrate 3. The electrode 2 is disposed on one side surface of the waveguide layer 1; the first substrate 3 is stacked with the waveguide layer 1 and is located on the same side as the waveguide layer 1 and the electrode 2.

[0107] For example, Figure 2 As an example of using quartz or diamond as the first substrate 3 of the electro-optic modulator 100, no hollowing is required and direct bonding is used; Figure 3In an example of using silicon as the first substrate 3 of the electro-optic modulator 100, a hollowed-out trench needs to be pre-etched and direct bonding is employed. Figure 4 As an example of using sapphire as the first substrate 3 of the electro-optic modulator 100, it is necessary to pre-etch a hollowed-out groove and use resin bonding to bond it, having a bonding layer 5.

[0108] For example, see Figure 8 The electro-optic modulator 100 may further include a contact structure 6 located on the side of the first substrate 3 away from the waveguide layer 1, and the contact structure 6 penetrates the first substrate 3 and is electrically connected to the electrode 2. That is, the contact structure 6 is used to extract the microwave signal of the electrode 2 from the front or back of the device for subsequent packaging and integration.

[0109] For example, through-silicon vias (TSVs) or through-glass vias (TGVs) can be fabricated on the back side of the first substrate 3. The vias are filled with conductive material (such as copper, gold, or tungsten) to form a contact structure 6. One end of the contact structure 6 is electrically connected to the electrode 2, and the other end forms a pad or bump, thereby enabling the electrode signal to be led out from the back side, facilitating subsequent flip-chip packaging and integration with the driver chip. The TSV / TGV vias and the receiving cavity Q below the electrode 2 can be spatially located in different areas, without affecting each other's process and performance. The specific fabrication process of the aforementioned back-side vias can be referred to the fabrication process exemplified after completing step S5, and will not be repeated here.

[0110] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for fabricating a thin-film electro-optic modulator based on substrate transfer, characterized in that, include: A device layer is formed on the initial substrate; The device layer includes a waveguide layer and electrodes; The electrode is disposed on one side surface of the waveguide layer; The initial substrate and the device layer are stacked together; The intermediate substrate is bonded to the side of the device layer away from the initial substrate; Remove the initial substrate; The first substrate is bonded to the side of the device layer away from the intermediate substrate; The intermediate substrate is removed to form an electro-optic modulator.

2. The preparation method according to claim 1, characterized in that, The waveguide layer is made of one or more of lithium niobate, lithium tantalate, barium titanate, or organic electro-optic polymers.

3. The preparation method according to claim 1, characterized in that, The material of the first substrate includes at least one of quartz or diamond.

4. The preparation method according to claim 1, characterized in that, The material of the first substrate includes at least one of silicon or sapphire; Before bonding the first substrate to the side of the device layer away from the intermediate substrate, the method further includes: A groove is formed on one side surface of the first substrate; the groove extends from one side surface of the first substrate into the interior of the first substrate; Wherein, after the first substrate is bonded to the side of the device layer away from the intermediate substrate, the device layer and the groove form a receiving cavity.

5. The preparation method according to claim 4, characterized in that, The method of creating a groove on one side surface of the first substrate includes: Deep reactive ion etching is employed; the etching depth is 5 micrometers to 30 micrometers, and the width of the groove is 2 micrometers to 10 micrometers larger than the width of the electrode; the etching is performed using the Bosch process.

6. The preparation method according to claim 1, characterized in that, The step of bonding the intermediate substrate to the side of the device layer away from the initial substrate includes: An adhesive layer is formed on the side of the device layer away from the initial substrate; The intermediate substrate is bonded to the adhesive layer; The adhesive layer is made of temporary bonding adhesive; the intermediate substrate is made of at least one of silicon wafer, glass wafer or sapphire wafer.

7. The preparation method according to claim 1, characterized in that, The removal of the initial substrate includes: Mechanical grinding is employed; the mechanical grinding includes: coarse grinding, medium grinding and fine grinding, wherein the coarse grinding uses a grinding wheel with a particle size of 10 micrometers to 50 micrometers to thin the initial substrate to 100 micrometers, the medium grinding uses a grinding wheel with a particle size of 5 micrometers to 20 micrometers, and the fine grinding uses a grinding wheel with a particle size of 1 micrometer to 10 micrometers; The initial substrate remaining after mechanical polishing is removed by wet etching or reactive ion etching; the wet etching uses a tetramethylammonium hydroxide solution.

8. The preparation method according to claim 1, characterized in that, The step of bonding the first substrate to the side of the device layer away from the intermediate substrate includes: The first substrate is directly bonded to the side of the device layer away from the intermediate substrate; or, The first substrate is bonded to the side of the device layer away from the intermediate substrate using a bonding layer; the bonding layer is made of resin and has a dielectric constant of less than 3.

5. Prior to the direct bonding, the bonding surface is activated by oxygen plasma; after the direct bonding, it is annealed for 1 to 4 hours.

9. The preparation method according to claim 1, characterized in that, The removal of the intermediate substrate includes: The intermediate substrate is removed by at least one of thermal sliding debonding, laser debonding, or chemical dissolution debonding.

10. An electro-optic modulator, characterized in that, It is prepared by any one of the preparation methods described in claims 1 to 9.

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