A controller and an adaptive control method thereof

Abstract

The application provides a controller and an adaptive control method thereof, the controller comprising: a control board, a self-defined standard connector and a signal conversion board; the control board is configured as a core board to run a parameter adaptive unit, a structure adaptive unit and a pulse width modulation module, and has a multi-core DSP or ARM architecture; the signal conversion board dynamically routes a signal path by using a programmable logic device to realize flexible configuration of an interface; the adaptive control method is realized by using the controller, a physical constraint relationship is defined by establishing a control model, a composite algorithm is constructed by the structure adaptive unit through a general interface of a standardized data channel, and a neural network forward propagation calculation is executed by the parameter adaptive unit to realize online setting of control parameters. Through cooperation of hardware architecture standardization and algorithm logic adaptation, the application solves the defects of poor adaptability and dependence on manual parameter adjustment of a traditional controller, and significantly improves the universality, steady-state accuracy and dynamic response speed of a system.

Description

Technical Field

[0001] This invention relates to the field of standardized and modular power electronic device control technology, and in particular to a controller and its adaptive control method. Background Technology

[0002] With the development of science and technology, various power electronic devices, such as converters, inverters, active power filters (APF), static var compensators (SVG), solid-state transformers (SST), power quality management equipment, AC-DC modules, DC-DC modules, DC-AC modules, AC-AC modules, current modules, voltage modules, resonant modules, energy dissipation modules, energy storage modules, power amplifier modules, linear power modules, nonlinear power modules, linear power supplies, nonlinear power supplies, rectifiers, inverters, UPS, AC / DC power supplies, scanning power supplies, constant current power supplies, constant voltage power supplies, superconducting power supplies, high voltage power supplies, magnetic power supplies, pulse power supplies, fast pulse power supplies, resonant power supplies, power sources, high-frequency power supplies, energy storage power supplies, and charging power supplies, are widely used in industrial power supply and distribution, new energy grid connection, data centers, computing centers, nuclear physics experiments, accelerator devices, isotope devices, and nuclear energy and similar applications. As the application scenarios of these power electronic devices continue to expand, their power levels become more diverse, their topologies more complex, and their control functions more frequently iterated. Traditional integrated and customized controller design models suffer from long R&D cycles, low design reusability, high maintenance difficulty, and poor compatibility, making them insufficient to meet the engineering requirements of standardization, modularization, mass production, rapid delivery, and flexible expansion. Therefore, in similar devices such as accelerators, isotopes, and nuclear energy systems, standardized and modular technologies based on hot-swappable magnet power supplies and power sources have gradually emerged to address issues such as high reliability, high availability, and uninterrupted maintenance. In these standardized power electronic devices, the design, production, testing, and upgrading processes of standard modules are becoming increasingly standardized, automated, and intelligent. Simultaneously, there is an urgent need to achieve plug-and-play functionality for standard modules to quickly adapt to special requirements such as wide variations in load parameters, fast response, high precision, and high stability.

[0003] In standardized and modular power electronic devices such as magnet power supplies, there are many types of standard modules, typically including: current modules, voltage modules, resonant modules, energy dissipation modules, energy storage modules, H-bridge modules, scanning modules, and so on. To implement these standard modules, the internal controller hardware and interface designs of standard modules from different manufacturers vary widely, lacking a unified standard. The diverse and specific requirements of standard modules often necessitate redesigning and adjusting the controller hardware and its interfaces, severely impacting the efficiency of standard module design, development, production, debugging, testing, and maintenance. Furthermore, these standard modules typically employ high-efficiency, high-power-density circuit technology. Due to limitations in size, space, and cost, the output accuracy, stability, flexibility, scalability, and adaptability of standard modules are limited, often requiring modifications to hardware design and interfaces for adaptation. Moreover, voltage / current sampling is susceptible to temperature, device aging, and electromagnetic interference, resulting in zero-point drift, gain drift, and switching noise crosstalk. Regarding standard module control strategies, fixed-parameter proportional-integral (PI) control is currently widely used. Its control parameters are typically designed and tuned based on an ideal mathematical model established for specific operating points and conditions, such as rated voltage and rated load. When circuit component parameters are perturbed, temperature drifts occur, or load parameters change, the system often lacks sufficient self-regulation capability, making it difficult to maintain optimal control performance under complex and variable operating conditions. Consequently, it struggles to maintain high accuracy, stability, and repeatability of output current or voltage over long periods. In applications where load inductance and other parameters vary widely, and where high requirements are placed on output accuracy, stability, speed, and repeatability, adaptive control strategies are even more necessary to ensure the high reliability, availability, stability, and accuracy of standard modules.

[0004] Finally, with continuous technological iteration and upgrades, the daily output of standard modules in standardized and modular power electronic devices is constantly increasing, and the demand for plug-and-play and rapid deployment is becoming increasingly urgent. However, the fixed parameter control strategies within existing standard modules heavily rely on manual on-site debugging. Technicians need to perform tedious manual on-site debugging for each standard module to correct the control parameters. This approach cannot automatically adapt to changes in the environment and load, and it is difficult to meet the testing, acceptance, upgrade, installation, debugging, and engineering application requirements of standardized power electronic devices for plug-and-play and rapid turnaround. This greatly limits the efficiency advantages brought by standardized and modular power electronic devices. Summary of the Invention

[0005] This invention provides a controller and its adaptive control method to solve the problems of long R&D cycle, low design reuse rate, high operation and maintenance difficulty, poor compatibility, rigid control strategy, extreme reliance on manual debugging and difficulty in quickly adapting to diverse topologies and large-scale changes in load parameters in the existing standard module embedded controller. It realizes plug-and-play of standard modules of power electronic devices and automatic tuning of control parameters.

[0006] This invention provides a controller, including a control board, a custom standard connector, and a signal conversion board; The control board, as a replaceable core board, includes interconnected microprocessors and programmable logic chips, and is configured as an operating parameter adaptive unit, a structure adaptive unit, and a pulse width modulation module. The signal conversion board is connected to the control board via the custom standard connector. The signal conversion board includes a programmable logic device and multiple signal interfaces. The programmable logic device is used to execute the routing logic determined by the structure adaptive unit to dynamically route the physical connection path of digital signals, thereby realizing the flexible configuration function of each signal interface on the signal conversion board. The signal conversion board also includes a PWM port, which is used to output the pulse width modulation signal of the pulse width modulation module under the drive of the control board; The control board has a multi-core DSP architecture or a multi-core ARM architecture based on the microprocessor; wherein, the multi-core DSP architecture is used for computationally intensive control, and the multi-core ARM architecture is used for communication-intensive control; The signal conversion board integrates at least two CAN controllers, which are used for system cascading, upgrades, and local area network communication, respectively.

[0007] According to the controller provided by the present invention, the custom standard connector includes 180-pin and 400-pin connectors; wherein, for the scenario where the control board is arranged perpendicular to the signal conversion board, the custom standard connector is selected as a 180-pin connector; for the scenario where the control board is arranged parallel to the signal conversion board, the custom standard connector is selected as four 100-pin connectors.

[0008] According to the controller provided by the present invention, the signal interface integrated in the signal conversion board includes: at least 24 ADC sampling interfaces, at least 12 DAC output interfaces, at least 8 serial digital communication signal interfaces, at least 16 digital control input interfaces, and at least 4 relay interfaces for controlling the switching state of the main circuit.

[0009] According to the controller provided by the present invention, the control board is further provided with a BOOTSET start selection DIP switch and JTAG connectors for debugging the microprocessor and the programmable logic chip respectively; and the microprocessor and the programmable logic chip are interconnected through a parallel bus and a serial bus.

[0010] The present invention also provides a controller adaptive control method, implemented using any of the controllers described above, the method comprising: Establish a control model to describe the dynamic characteristics of power electronic devices; Using the structural adaptive unit, based on the control model, the control algorithm modules are combined through a custom standard data interface to construct a composite algorithm for the device topology; wherein, the custom standard data interface adopts a general data type with a preset bit width that is independent of specific data types, and the basic data unit of the standard data interface contains multiple standardized data channels; Using the parameter adaptive unit, the system status is monitored in real time through the standard data interface, the control parameters of each module in the composite algorithm are predicted and output, and the internal weights are updated online. The pulse width modulation module generates a pulse width modulation signal based on the adjustment result calculated by the composite algorithm; the programmable logic device dynamically routes the pulse width modulation signal to the PWM port output to drive the power converter circuit.

[0011] According to the adaptive control method for controllers provided by the present invention, the control model is used to define the dynamic physical constraint relationship between circuit inputs and outputs; The establishment of a control model describing the dynamic characteristics of power electronic devices specifically includes: The switching state of the power electronic device is continuously processed using the switching cycle averaging method to construct an average model. Based on the average model, a differential equation describing the energy conversion relationship between input and output is derived; The differential equations are transformed into a unified form differential equation model in a synchronously rotating coordinate system through coordinate transformation, which serves as the control model.

[0012] According to the adaptive control method for controllers provided by the present invention, the construction of a composite algorithm for the device topology includes: Identify the topology type of the power electronic device and call at least one control algorithm block from the preset algorithm library; The standard data interface is used to establish a data mapping relationship between the called control algorithm blocks in order to construct a composite algorithm chain with a cascaded or decoupled structure. The composite algorithm is used to perform voltage and current loop control and feedforward decoupling operations based on the coupling characteristics defined in the control model.

[0013] According to the adaptive control method for controllers provided by the present invention, the prediction and output of control parameters for each module in the composite algorithm specifically includes: The error signal of the output of the power electronic device is collected in real time and input to the parameter adaptive unit. The parameter adaptive unit is used to perform forward propagation calculation of the neural network, and the error signal is mapped to the proportional, integral, and derivative coefficients of the regulator in the corresponding control algorithm. The parameter adaptive unit updates its internal weights through a loss function feedback based on the ideal trajectory or ideal index determined by the control model, thereby achieving adaptive online tuning of the control parameters.

[0014] According to the adaptive control method of the controller provided by the present invention, the general data type is U32bit data type, the basic unit of the standardized data interface contains 4 standardized data channels, and the control algorithm module includes at least one of PI, PR, PID, hysteresis control and decoupling control algorithm blocks.

[0015] According to the adaptive control method of the controller provided by the present invention, the pulse width modulation module includes at least one of an SPWM module, an SVPWM module, a chopper module, and an H-bridge cascade module; wherein, the SPWM module adds optimal zero-sequence injection or third harmonic injection when generating the duty cycle time.

[0016] According to the adaptive control method of the present invention, the parameter adaptive unit adopts a three-layer fully connected feedforward neural network architecture, the hidden layer adopts the hyperbolic tangent function as the activation function, and the gradient descent method with momentum term is used for backpropagation learning, and the Jacobian information of the controlled object is approximated by the sign function.

[0017] According to the adaptive control method of the present invention, the parameter adaptive unit adopts a multi-layer neural network, and based on the Lyapunov stability theory, it constructs Lyapunov candidate functions and analyzes their forward difference characteristics to determine the weight update formula that makes the system asymptotically stable.

[0018] According to the controller adaptive control method provided by the present invention, the parameter adaptive unit adopts a loss function that includes time window, ripple evaluation and concept drift detection when performing performance evaluation; and the parameter adaptive unit has multiple working modes including performance evaluation selection mode, start-up replacement mode, periodic replacement mode and instruction replacement mode.

[0019] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the adaptive control method of the controller as described above.

[0020] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the adaptive control method of the controller as described above.

[0021] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the controller adaptive control method as described above.

[0022] The controller and its adaptive control method provided by this invention combine the standardized design of the core control board with the dynamic routing logic of the signal conversion board to achieve modularity of the hardware structure and reconfigurability of the signal interface. By utilizing the programmable logic devices on the signal conversion board to dynamically adjust the physical connection paths of digital signals, the controller's adaptability to diverse power topologies and signal configuration requirements is improved. Combined with a replaceable core board DSP and ARM architecture and targeted computational division of labor, resources can be flexibly allocated according to different operating conditions. Furthermore, the diverse arrangement of custom connectors and the design of multi-channel communication buses enhance the flexibility of physical installation compatibility and system expansion. Standardized data interfaces increase the reusability and flexibility of algorithm modules, facilitating automated software updates and upgrades. At the control logic level, by defining a universal interface with standardized data channels, decoupling and flexible combination between control algorithm modules are achieved, facilitating online upgrades and functional expansion of functional modules. The use of a parameter adaptive unit to optimize control parameters online reduces the system's reliance on manual on-site debugging and mitigates the impact of component aging and environmental drift on control performance. This invention helps to shorten the research and development and debugging cycle of standardized power modules and improves the steady-state accuracy and dynamic response of the system under different operating conditions. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the hardware structure of the controller provided by the present invention.

[0025] Figure 2This is a hardware architecture and interface block diagram of the controller provided by the present invention.

[0026] Figure 3 This is a flowchart illustrating the adaptive control method for controllers provided by the present invention.

[0027] Figure 4 This is an architecture diagram of the adaptive control strategy of the controller provided by the present invention.

[0028] Figure 5 This is a flowchart of the adaptive control strategy design provided by the present invention.

[0029] Figure 6 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0031] The present invention will now be described in detail with reference to the accompanying drawings. The specific operation methods in the method embodiments can also be applied to the device embodiments or system embodiments. In the description of the present invention, unless otherwise stated, "at least one" includes one or more. "Multiple" refers to two or more. For example, at least one of A, B, and C includes: A existing alone, B existing alone, A and B existing simultaneously, A and C existing simultaneously, B and C existing simultaneously, and A, B, and C existing simultaneously. In the present invention, " / " means "or". For example, A / B can mean A or B. "And / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone.

[0032] The present invention will now be described in detail with reference to specific embodiments.

[0033] In existing power electronic controller designs, the hardware architecture typically employs fixed PCB routing, where the physical connection paths between the control core (such as a microprocessor) and peripheral sampling and drive circuits are determined at the factory. Under this design paradigm, it's difficult for the same controller to adapt to various topologies without altering the hardware layout, such as switching from an H-bridge cascade to a full-bridge or resonant circuit. Furthermore, the lack of a unified communication standard between control algorithm modules (such as PI regulators and PWM generators) in traditional controllers leads to significant data isolation in data types, interface definitions, and calling logic among algorithm blocks written by different developers, severely limiting the reconfiguration and reuse of control logic. In the field of adaptive control, existing solutions often suffer from high computational resource consumption or model complexity, making real-time operation on resource-constrained embedded platforms (such as low-power DSPs or MCUs) difficult, and they lack specific evaluation mechanisms for power electronic operating conditions (such as ripple interference and parameter drift).

[0034] To address the aforementioned industry pain points, this application proposes a controller and its adaptive control method. This solution achieves dual adaptation of the controller's physical structure and algorithm logic through reconfigurable signal routing at the hardware level and standardized interface definition at the software level. Simultaneously, it introduces an efficient neural network model to achieve online automatic optimization of control parameters while ensuring embedded real-time performance.

[0035] Specifically, for the controller hardware platform, this embodiment provides two optional core architectures: ARM+FPGA and DSP+FPGA. For scenarios requiring advanced network communication and an embedded operating system, the core board uses Allwinner Technology's quad-core ARM Cortex-A7 architecture chip as the task scheduling center, with a main frequency of 1.2GHz, in conjunction with a high-performance FPGA from Unisoc's Logos series for PWM acquisition and neural network deployment. For devices with extremely high real-time control response requirements, TI's TMS320F2837xD dual-core DSP works in collaboration with the FPGA. The control core connects to the signal conversion board via custom 180-pin and 400-pin standard connectors (such as a 180-pin vertical connector or four 100-pin B2B connectors), ensuring hot-swapping and flexible replacement of the core board, adapting to different application scenarios from high-power magnetic power supplies to precision industrial converters.

[0036] In terms of signal processing and logic reconstruction, the signal conversion board incorporates a digital signal routing matrix centered on a CPLD (such as the EPM570T100C5N). This device uses programmable logic to connect digital signals (such as PWM and IO) output from the microprocessor and FPGA with external main circuits and sensors in real time, thus supporting software configuration to change the physical connection path of the signals. The accompanying software framework introduces a structure-adaptive unit, the core of which is the definition of a set of universal standard data interfaces. This interface is decoupled from specific physical quantities, uses the U32bit data type as the basic transmission unit, and specifies that each standard interface contains 4 parallel data channels. Through this interface, voltage control modules, current control modules, decoupling operations, and various PWM modulation modules (such as SPWM, SVPWM, and H-bridge cascade modules) can be combined in series and parallel cascades to form composite algorithm chains for specific topologies.

[0037] In practical implementation, the adjustment signal (U32 type data) output by the front-end voltage control module through the standard data interface is directly used as the reference input for the subsequent current control module. Because the interface standard is unified, multi-stage closed-loop control can be achieved without complex data conversion.

[0038] In the adaptive optimization stage, this embodiment embeds a parameter adaptive unit into the algorithm chain. This unit supports deployment on ARM cores, high-performance FPGAs, or remote servers, and utilizes a BP neural network or a multi-layer neural network, i.e., an RBF neural network, to perform real-time tuning of the PID parameters of the control system. To address the switching noise and nonlinear disturbances commonly found in power electronic devices, the loss function of the neural network specifically incorporates time window evaluation and ripple evaluation mechanisms, and possesses concept drift monitoring capabilities, automatically resetting the integral term and adjusting the learning rate when there are sudden load changes or parameter fluctuations. Through this deep adaptive mechanism combining hardware and software, this invention achieves plug-and-play and highly reliable operation of the power electronic module under all operating conditions.

[0039] In some specific embodiments of the present invention, this solution provides a controller, such as... Figure 1 As shown, Figure 1 This is a schematic diagram of the hardware structure of the controller. The main hardware components of this embodiment include a control board, a custom standard connector, and a signal conversion board.

[0040] The control board, as a replaceable core board, includes interconnected microprocessors and programmable logic chips, and is configured as an operating parameter adaptive unit, a structure adaptive unit, and a pulse width modulation module. The signal conversion board is connected to the control board via the custom standard connector. The signal conversion board includes a programmable logic device and multiple signal interfaces. The programmable logic device is used to execute the routing logic determined by the structure adaptive unit to dynamically route the physical connection path of digital signals, thereby realizing the flexible configuration function of each signal interface on the signal conversion board. The signal conversion board also includes a PWM port, which is used to output the pulse width modulation signal of the pulse width modulation module under the drive of the control board; The control board has a multi-core DSP architecture or a multi-core ARM architecture based on the microprocessor; wherein, the multi-core DSP architecture is used for computationally intensive control, and the multi-core ARM architecture is used for communication-intensive control; The signal conversion board integrates at least two CAN controllers, which are used for system cascading upgrades and local area network communication, respectively.

[0041] In a specific embodiment, the control board, as the core of the controller, adopts a dual-core architecture of microprocessor + FPGA. For example, such as... Figure 2 As shown, Figure 2 The controller hardware architecture and interface block diagram show that the microprocessor used is an Allwinner Technology quad-core ARM Cortex-A7 architecture chip with a main frequency of 1.2GHz, and the FPGA used is a Unisoc Logos series chip with integrated digital signal processing (DSP) unit. The control board connects to the signal conversion board via a custom standard connector. For physical connections, see [link to documentation]. Figure 1 The dotted lines indicate that the connection interface supports either soldering or gold finger insertion. The microprocessor is responsible for complex task scheduling and adaptive parameter prediction, while the FPGA utilizes its parallelism to support PWM signal generation and accelerate neural network calculations, achieving core board replaceability and efficient allocation of computing resources, and supporting the real-time operation of complex adaptive algorithms.

[0042] The control board can use the same high-speed PCB board, with completely identical shape, size and electrical interfaces.

[0043] The control board is also equipped with a BOOTSET boot selection DIP switch and JTAG connectors for debugging the microprocessor and the programmable logic chip, respectively; and the microprocessor and the programmable logic chip are interconnected via a parallel bus and a serial bus.

[0044] For example, the control board includes a BOOTSET DIP switch, a USB-UART debug interface, and 14-pin simple horn-shaped JTAG connectors for the DSP and FPGA, respectively.

[0045] In some specific embodiments of the present invention, the custom standard connector includes 180-pin and 400-pin connectors; wherein, for the scenario where the control board is arranged perpendicular to the signal conversion board, the custom standard connector uses a single 180-pin header; for the scenario where the control board is arranged parallel to the signal conversion board, the custom standard connector uses four 100-pin B2B connectors.

[0046] The signal conversion board integrates multiple interface resources and is mainly used to isolate high-power signals from low-power signals and to perform signal routing functions.

[0047] The signal interfaces integrated in the signal conversion board include: at least 24 ADC sampling interfaces, at least 12 DAC output interfaces, at least 8 serial digital communication signal interfaces, at least 16 digital control input interfaces, and at least 4 relay interfaces for controlling the switching state of the main circuit.

[0048] like Figure 2 As shown, the signal conversion board integrates two CAN controllers. CAN1 is used for system cascading / upgrading, while CAN2 is used for local area network communication, at least one RS485 port, at least one RS232 port, one Ethernet port, 24 ADC sampling circuits, 12 DACs, 8 serial digital communication signals, 16 digital control input signals, 24 PWM control signal ports, and 200 custom digital interface signals.

[0049] In the signal output path, digital signals can be output directly from the microprocessor or via an FPGA. A rich set of physical interfaces adapts to the installation and communication needs of various high-power power electronic devices, enhancing the controller's versatility and meeting the hardware requirements for ppm-level high-precision sampling.

[0050] For different installation scenarios, such as Figure 2 As shown, the custom connectors have a specific arrangement. The control board connects to the signal conversion board via custom standard connectors, which are 180-pin and 400-pin connectors.

[0051] Specifically, to adapt to the installation requirements of different physical spaces, for vertical installation, a 180-pin header can be selected to arrange the control board and signal conversion board vertically; for horizontal installation, four 100-pin B2B connectors can be selected to arrange the control board and signal conversion board in parallel.

[0052] The controller provided by this invention uses a control board as its core, which connects to a signal conversion board via a custom standard connector. The signal conversion board has multiple digital, analog, and control interfaces, facilitating integration and connection with the main circuit, sensors, and external communication networks. The control board is a unified high-speed PCB board containing interconnected microprocessor chips and programmable logic device chips. Microprocessors include ARM and DSP, and programmable logic devices include FPGAs. Control boards can be broadly categorized into two types based on the microprocessor used: ARM+FPGA and DSP+FPGA.

[0053] In possible embodiments, the custom standard connector electrical interface signal definitions are uniform and redundant, facilitating expansion and flexible configuration adjustments. The connector can be pin-headed for soldering applications or multiple B2B connectors for screw-tightening applications. Different control boards share the same shape, size, and electrical interface, supporting plug-and-play functionality and soldering through the custom standard connectors. Therefore, it can be flexibly applied to various standardized and modular power electronic devices as needed. The ARM+FPGA control board is designed for power electronic devices requiring network communication and embedded operating systems, while the DSP+FPGA control board is primarily used for power electronic devices with fast response and complex algorithms. The control board is configured to run the parameter adaptive unit and the composite algorithm in the adaptive control strategy; the electrical interface signal definitions mainly fall into three categories: communication signals, digital I / O signals, and analog signals.

[0054] In a possible embodiment, the signal conversion board includes a programmable logic device, an isolation chip, a signal conversion chip, etc. The programmable logic device dynamically routes the physical connection path of digital signals through programming logic; the signal conversion board is responsible for the routing, conversion and isolation of signals, including the conversion and isolation of digital I / O signals, the routing of digital signals, and the conversion of digital to analog signals.

[0055] In a possible embodiment, the signal conversion board's PWM port is used to output signals from the pulse width modulation module under the drive of the control board. The signal conversion board integrates multiple Ethernet and LAN communication signals, and at least two CAN controllers, used for system cascading upgrades and LAN communication respectively. It includes relay circuitry for controlling switch states. It also includes ADC and DAC conditioning circuitry for acquiring or outputting the high-precision analog signals required by the system.

[0056] In possible embodiments, see still Figure 2The control board primarily contains a microprocessor (ARM or DSP) chip, a programmable logic device (FPGA), read-only memory (ROM) (FLASH), random access memory (RAM) (SDRM / DDR / DDR3), and a USB-UART chip. Depending on the microprocessor, the board has two main implementations: an ARM microprocessor + FPGA board and a DSP microprocessor + FPGA board. They have the same shape, size, and electrical interfaces. Additionally, the control board includes a BOOTSET DIP switch, multiple LED indicators, and a 14-pin simple horn-shaped JTAG connector for both the DSP and FPGA.

[0057] For control boards composed of ARM and FPGA, the ARM and FPGA processor resources form a dual-architecture hardware core for control and computing, which can be adapted to task requirements of different complexities.

[0058] The ARM processor can be an Allwinner Technology chip, which adopts a quad-core ARM Cortex-A7 architecture with a maximum clock speed of 1.2GHz. It has built-in 32-bit third-generation double data rate synchronous dynamic random access memory (DDR3) and eMMC 5.0 high-speed storage module, and has strong task scheduling and complex algorithm driving capabilities, which can meet the control tasks such as data interaction, parameter configuration, status detection and communication in adaptive systems. The FPGA can be a Unisoc Logos series FPGA (PGL25 / 50) chip, which is equipped with 51,360 lookup tables (LUT4) and 64,200 flip-flops (FF) resources, and integrates rich digital signal processing (DSP) units to match the requirements of high-performance floating-point computing and high-speed signal processing, and can support the efficient operation of real-time computing tasks such as PWM signal acquisition and neural network model deployment.

[0059] For control boards composed of DSP and FPGA, the DSP can be a dual-core TI TMS320F2837xD chip. Such control boards also include off-chip memory chips, including ROM (FLASH, model W25Q32JV) and RAM (DDR, model IS61LV25616AL), for temporary storage of operational data. USB-UART is used for debugging the microprocessor ARM / DSP. For each microprocessor, the FPGA is configured with corresponding FLASH chips for convenient data storage.

[0060] The microprocessor and FPGA are interconnected via bus signals. This bus is divided into parallel buses and serial digital communication buses. Parallel buses include: GPMC, EBI, FMC, AXI, EMIF / XINTF, and FSMC (Flexible Static Memory Controller), which maps the FPGA to external SRAM for access. Serial digital communication buses include: SPI, UART, IIC, SCI, etc.

[0061] The signal conversion board consists of at least one programmable CPLD (EPM570T100C5N), at least two CAN controllers, at least one RS485 port, at least one RS232 port, at least one Ethernet port, multiple isolation circuits, at least four relays, at least 24 ADCs, at least 12 DACs, at least eight serial digital communication / synchronous bitstream signals, at least 24 PWM control signals, at least 16 digital control input signals, and custom digital interface signals. The CPLD (EPM570T100C5N) connects all digital signals, facilitating flexible configuration and increasing the controller's flexibility and expandability. CAN control is used for system cascading, RS485 for connecting to the LCD screen and external status board, RS232 for system debugging, and Ethernet for connecting to the Ethernet network. Four relays and 16 digital input signals control the main circuit's fault status and relay switches. The 24 ADCs acquire low-precision analog signals, the 12 DACs output the required analog signals, and the eight serial digital communication ports connect to high-precision ADC chips.

[0062] 24 PWM signals are used to control the power components of the main circuit. All digital signals are isolated. The board is powered by 12V, and 3.3V and 5V power are provided by 12V to 3.3V and 12V to 5V power chips on the signal conversion board to power all chips on the control board and signal conversion board.

[0063] The controller provided by this invention increases control flexibility and scalability by flexibly allocating interface signals through the addition of custom standard interface signals, redundant signals, and programmable logic units. By establishing a control model and utilizing a structural adaptive unit to flexibly combine algorithm modules through standard data interfaces based on this model, a composite algorithm tailored to a specific device topology is constructed. This overcomes the technical limitations of traditional controllers with fixed software architectures and difficulties in cross-topology reuse. Simultaneously, the parameter adaptive unit predicts and outputs optimal control parameters in real time based on the ideal trajectory or index determined by the control model, achieving online automatic optimization and dynamic weight updates of control parameters. This effectively addresses the technical pain points of existing fixed-parameter control strategies, which struggle to cope with component aging, temperature drift, and sudden load changes, and require manual on-site debugging. It significantly shortens the debugging cycle and maintenance costs of standardized, modular power electronic devices, ensuring high-precision steady-state operation and rapid dynamic response under all operating conditions, truly realizing plug-and-play functionality of power electronic standard modules in complex systems.

[0064] In some specific embodiments of the present invention, such as Figure 3 As shown, this solution also provides a controller adaptive control method, implemented using the controller described in any of the above embodiments, the method comprising: Step S100: Establish a control model describing the dynamic characteristics of the power electronic device; Step S200: Using the structural adaptive unit, the control algorithm modules are combined through a custom standard data interface according to the control model to construct a composite algorithm for the device topology; wherein, the custom standard data interface adopts a general data type with a preset bit width that is independent of specific data types, and the basic data unit of the standard data interface contains multiple standardized data channels. In possible embodiments, a composite control algorithm is constructed for different device topologies. Due to the addition of a standard data interface, the flexibility, scalability, and adaptability of the control algorithm are increased.

[0065] Furthermore, in possible embodiments, the control algorithm block may include: a proportional-integral (PI) module, a proportional-integral-derivative (PID) module, a hysteresis control module, a current decoupling control module, a voltage control module, a PWM module, etc., wherein the PWM module is further divided into: a multi-H-bridge series-parallel PWM module, a multi-channel chopper module, an SVPWM module, a third harmonic injection SPWM module, etc., as well as composite modules composed of these modules in series and parallel. Step S300: Using the parameter adaptive unit, the system status is monitored in real time through the standard data interface, the control parameters of each module in the composite algorithm are predicted and output, and the internal weights are updated online. In a possible embodiment, each control algorithm module corresponds to a parameter adaptation unit. The parameter adaptation unit monitors the state of the corresponding control algorithm module in real time through the standard data interface, predicts and outputs the control parameters of each module in the composite algorithm, so that the system achieves optimal performance. The parameter adaptation unit has online learning capabilities, can set fixed output parameters, update the internal network structure, and update the internal weights online.

[0066] Step S400: A pulse width modulation (PWM) signal is generated using the PWM module based on the adjustment result calculated by the composite algorithm. The PWM signal is then dynamically routed to the PWM port output using a programmable logic device to drive the power converter circuit. In a possible embodiment, the PWM module converts the signal output by the composite algorithm into a switching signal to control the power converter circuit. The PWM module can be further categorized into: multi-H-bridge series-parallel PWM modules, multi-channel chopper modules, SVPWM modules, third harmonic injection SPWM modules, and composite modules composed of these modules in series and parallel configurations.

[0067] Based on the hardware platform, this embodiment uses... Figure 4 The software framework shown implements adaptive control logic, which is carried out in the following steps: Step 1: Establish a control model: This step corresponds to Figure 3 Step S100: Establish a control model that describes the dynamic characteristics of the power electronic device.

[0068] In some possible embodiments of the present invention, the control model is used to define the dynamic physical constraint relationship between the circuit input and output; The establishment of a control model describing the dynamic characteristics of power electronic devices specifically includes: The switching state of the power electronic device is continuously processed using the switching cycle averaging method to construct an average model. Based on the average model, a differential equation describing the energy conversion relationship between input and output is derived; The differential equations are transformed into a unified form differential equation model in a synchronously rotating coordinate system through coordinate transformation, which serves as the control model.

[0069] Specifically, see Figure 5 In the modeling layer, for typical topologies, an average model of the voltage regulation unit of the power electronic device is established. Through Clark transformation and Park transformation, its unified form differential equation model in the dq synchronous rotating coordinate system is derived to describe the dynamics of the AC side d / q axis current and the DC side voltage. This control model is used to define the physical constraint relationship between the input and output.

[0070] Step 2: Adaptive structural combination: This step corresponds to Figure 3 In step S200, the control algorithm modules are combined using the structure adaptive unit according to the control model through a standard data interface to construct a composite algorithm for the device topology. The standard data interface uses a general data type with a preset bit width and is independent of specific data types. The basic data unit of the standard data interface contains multiple standardized data channels.

[0071] In a possible embodiment, the general data type is a U32bit data type, the basic unit of the standardized data interface contains 4 standardized data channels, and the control algorithm module includes at least one of PI, PR, PID, hysteresis control and decoupling control algorithm blocks. The control algorithm modules are cascaded through the standard data interface to form the composite algorithm.

[0072] In some possible embodiments of the present invention, the construction of the composite algorithm for device topology includes: Identify the topology type of the power electronic device and call at least one control algorithm block from the preset algorithm library; The standard data interface is used to establish a data mapping relationship between the called control algorithm blocks in order to construct a composite algorithm chain with a cascaded or decoupled structure. The composite algorithm is used to perform voltage and current loop control and feedforward decoupling operations based on the coupling characteristics defined in the control model.

[0073] For example, see Figure 4 and Figure 5 Control layer in the middle: By utilizing the structure adaptive unit configured on the FPGA or microprocessor, preset algorithm blocks, such as PI algorithm blocks, PID algorithm blocks, and hysteresis control algorithm blocks, are cascaded and combined through a standard data interface to form a composite algorithm.

[0074] The standard data interface adopts a universal data type with a preset bit width, such as the U32bit data type, and is independent of the specific data type. Its basic unit contains four standardized data channels. By setting up a standard interface, the data isolation problem between different developers' algorithm modules is solved, realizing plug-and-play control logic. This enables the controller to perform voltage and current loop control and feedforward decoupling operations according to the coupling characteristics defined by the control model.

[0075] Step 3: Adaptive parameter optimization This step corresponds to Figure 3In step S300, the configuration parameter adaptive unit monitors the system status in real time through the standard data interface, predicts and outputs the control parameters of each module in the composite algorithm, and updates the internal weights online. In some possible embodiments of the present invention, the prediction and output of control parameters for each module in the composite algorithm specifically includes: The error signal or other performance indicators of the output of the power electronic device are collected in real time and input to the parameter adaptive unit. The parameter adaptive unit is used to perform neural network forward propagation calculations, and the performance indicators such as error are mapped to control parameters such as proportional, integral, and derivative coefficients of the regulator in the corresponding control algorithm. The parameter adaptive unit updates its internal weights through a loss function feedback based on the ideal trajectory or ideal index determined by the control model, thereby achieving adaptive online tuning of the control parameters.

[0076] In some possible embodiments of the present invention, the parameter adaptive unit employs a loss function that includes time window, ripple evaluation, and concept drift detection when performing performance evaluation; and the parameter adaptive unit has multiple operating modes, including a performance evaluation selection mode, a start-up replacement mode, a periodic replacement mode, and an instruction replacement mode. See also Figure 4 Parameter adaptive unit and Figure 5 Adaptive layer: The parameter adaptive unit can be configured in a remote server, ARM microprocessor, or FPGA. When the parameter adaptive unit is configured on a remote server or ARM, the configuration parameters can be managed through a database to achieve historical traceability of parameters and synchronization across multiple devices.

[0077] Depending on the application scenario requirements, the microprocessor can be flexibly selected as either the ARM architecture for complex task scheduling or the DSP architecture for extremely fast response speed.

[0078] In a possible embodiment, the parameter adaptive unit adopts a three-layer fully connected feedforward neural network architecture, the hidden layer uses the hyperbolic tangent function as the activation function, and the gradient descent method with momentum term is used for backpropagation learning, and the Jacobian information of the controlled object is approximated by the sign function.

[0079] The parameter adaptive unit adopts a multilayer neural network, namely the RBF neural network. Based on the Lyapunov stability theory, it constructs Lyapunov candidate functions and analyzes their forward difference characteristics to determine the weight update formula that makes the system asymptotically stable.

[0080] The parameter adaptive unit operation process is as follows: By utilizing a three-layer fully connected feedforward neural network architecture, such as a BP neural network or an RBF neural network, the system status, such as voltage and current, can be monitored in real time through a standard data interface.

[0081] In the BP neural network model, the hidden layer uses the hyperbolic tangent function as the activation function, the gradient descent method with the momentum term is used for backpropagation learning, and the Jacobian information of the controlled object is approximated by the sign function to update the weights.

[0082] In the RBF neural network model, Lyapunov candidate functions are constructed based on Lyapunov stability theory, their forward difference characteristics are analyzed, and the weight update formula that makes the system asymptotically stable is determined.

[0083] During training, a loss function that includes time window, ripple evaluation, and concept drift detection is used.

[0084] Specifically, when performing parameter prediction, the parameter adaptive unit uses the established control model, i.e., the unified form differential equation model, as a reference. The neural network identifies the perturbation trends of physical parameters (such as inductance and load resistance) by comparing the output of the control model under ideal operating conditions with the real-time monitored actual system state. Based on this, the parameter adaptive unit calculates the compensation amount and corrects the control gain of the PI or PID algorithm block in the composite algorithm in real time, thereby ensuring that the closed-loop characteristics of the power converter always closely approximate the optimal dynamic response trajectory defined by the control model.

[0085] Neural networks can predict and output the optimal parameters (KP, KI) of the control algorithm module online, solving the problem of parameter failure caused by environmental fluctuations or component aging.

[0086] Step 4: PWM Generation and Output This step corresponds to Figure 3 In step S400, the signal output by the composite algorithm is converted into a switching signal using the pulse width modulation module (PWM module) to control the operation of the power converter circuit.

[0087] In some possible embodiments of the present invention, the pulse width modulation module includes at least one of an SPWM module, an SVPWM module, a chopper module, and an H-bridge cascade module; wherein the SPWM module adds optimal zero-sequence injection or third harmonic injection when generating the duty cycle time.

[0088] Specifically, see Figure 2 and Figure 4 : The continuous signal output from the composite algorithm is converted into a switching signal using a pulse width modulation (PWM) module. The PWM module supports multiple modes, including SPWM (with optimal zero-sequence injection or third harmonic injection), SVPWM (directly converting voltage to switching states and time), a chopper module, and an H-bridge cascade module. The physical connection paths of these digital signals are dynamically routed using a programmable logic device (CPLDEPM570T100C5N) to drive the main circuit.

[0089] The CPLD's internal logic dynamically switches the mapping relationship between the FPGA's output PWM logic pins and physical ports based on the currently selected composite algorithm topology (e.g., switching from a single-phase full-bridge to a three-phase six-arm topology). This implements software-defined hardware, enabling the same control board to adapt to completely different power loop topologies. The controller and adaptive control method provided in this embodiment are primarily used for plug-and-play and performance optimization of standardized power electronic converters (such as magnet power supplies and grid-connected inverters).

[0090] In this embodiment of the invention, the executing entity for the adaptive control method is a power electronic controller with a dual control-computation architecture. This controller, through the logical reconfiguration of hardware circuitry and the parallel processing of software instructions, jointly completes the establishment of the control model, the construction of the composite algorithm, and the adaptive online tuning of parameters.

[0091] Figure 6 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 6 As shown, the electronic device may include: a processor 810, a communications interface 820, a memory 830, and a communications bus 840, wherein the processor 810, the communications interface 820, and the memory 830 communicate with each other through the communications bus 840. The processor 810 can call logic instructions in the memory 830 to execute a controller adaptive control method. This method includes: establishing a control model describing the dynamic characteristics of the power electronic device; using a structure adaptive unit to combine control algorithm modules according to the control model through a custom standard data interface to construct a composite algorithm for the device topology; wherein the custom standard data interface uses a general data type with a preset bit width and is independent of specific data types, and the basic data unit of the standard data interface contains multiple standardized data channels; using a parameter adaptive unit to monitor the system state in real time through the standard data interface, predict and output the control parameters of each module in the composite algorithm, and update the internal weights online; using a pulse width modulation module to generate a pulse width modulation signal based on the adjustment result calculated by the composite algorithm; and using a programmable logic device to dynamically route the pulse width modulation signal to the PWM port output to drive the power converter circuit.

[0092] Furthermore, the logical instructions in the aforementioned memory 830 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0093] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the controller adaptive control method provided by the above methods. The method includes: establishing a control model describing the dynamic characteristics of a power electronic device; using a structure adaptive unit to combine control algorithm modules according to the control model through a custom standard data interface to construct a composite algorithm for the device topology; wherein the custom standard data interface adopts a general data type with a preset bit width that is independent of specific data types, and the basic data unit of the standard data interface includes multiple standardized data channels; using a parameter adaptive unit to monitor the system status in real time through the standard data interface, predict and output the control parameters of each module in the composite algorithm, and update the internal weights online; using a pulse width modulation module to generate a pulse width modulation signal according to the adjustment result calculated by the composite algorithm; and using a programmable logic device to dynamically route the pulse width modulation signal to the PWM port output to drive the power converter circuit.

[0094] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements the controller adaptive control method provided by the above methods. The method includes: establishing a control model describing the dynamic characteristics of a power electronic device; using a structure adaptive unit to combine control algorithm modules according to the control model through a custom standard data interface to construct a composite algorithm for the device topology; wherein the custom standard data interface adopts a general data type with a preset bit width that is independent of specific data types, and the basic data unit of the standard data interface includes multiple standardized data channels; using a parameter adaptive unit to monitor the system state in real time through the standard data interface, predict and output the control parameters of each module in the composite algorithm, and update the internal weights online; using a pulse width modulation module to generate a pulse width modulation signal according to the adjustment result calculated by the composite algorithm; and using a programmable logic device to dynamically route the pulse width modulation signal to the PWM port output to drive the power converter circuit.

[0095] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0096] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0097] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A controller, characterized in that, Includes control board, custom standard connectors, and signal conversion board; The control board, as a replaceable core board, includes interconnected microprocessors and programmable logic chips, and is configured as an operating parameter adaptive unit, a structure adaptive unit, and a pulse width modulation module. The signal conversion board is connected to the control board via the custom standard connector. The signal conversion board includes a programmable logic device and multiple signal interfaces. The programmable logic device is used to execute the routing logic determined by the structure adaptive unit to dynamically route the physical connection path of digital signals, thereby realizing the flexible configuration function of each signal interface on the signal conversion board. The signal conversion board also includes a PWM port, which is used to output the pulse width modulation signal of the pulse width modulation module under the drive of the control board; The control board has a multi-core DSP architecture or a multi-core ARM architecture based on the microprocessor; wherein, the multi-core DSP architecture is used for computationally intensive control, and the multi-core ARM architecture is used for communication-intensive control; The signal conversion board integrates at least two CAN controllers, which are used for system cascading, upgrades, and local area network communication, respectively.

2. The controller according to claim 1, characterized in that, The custom standard connector includes 180-pin and 400-pin connectors; wherein, for the scenario where the control board is arranged perpendicular to the signal conversion board, the custom standard connector uses a single 180-pin connector; for the scenario where the control board is arranged parallel to the signal conversion board, the custom standard connector uses four 100-pin connectors.

3. The controller according to claim 1, characterized in that, The signal interfaces integrated in the signal conversion board include: at least 24 ADC sampling interfaces, at least 12 DAC output interfaces, at least 8 serial digital communication signal interfaces, at least 16 digital control input interfaces, and at least 4 relay interfaces for controlling the switching state of the main circuit.

4. The controller according to claim 1, characterized in that, The control board is also equipped with a BOOTSET boot selection DIP switch and JTAG connectors for debugging the microprocessor and the programmable logic chip, respectively; and the microprocessor and the programmable logic chip are interconnected via a parallel bus and a serial bus.

5. An adaptive control method for a controller, characterized in that, Implemented using the controller described in claims 1-4, the method includes: Establish a control model to describe the dynamic characteristics of power electronic devices; Using the structural adaptive unit, based on the control model, the control algorithm modules are combined through a custom standard data interface to construct a composite algorithm for the device topology; wherein, the custom standard data interface adopts a general data type with a preset bit width that is independent of specific data types, and the basic data unit of the standard data interface contains multiple standardized data channels; Using the parameter adaptive unit, the system status is monitored in real time through the standard data interface, the control parameters of each module in the composite algorithm are predicted and output, and the internal weights can be updated online. The pulse width modulation module generates a pulse width modulation signal based on the adjustment result calculated by the composite algorithm; the programmable logic device dynamically routes the pulse width modulation signal to the PWM port output to drive the power converter circuit.

6. The adaptive control method for a controller according to claim 5, characterized in that, The control model is used to define the dynamic physical constraint relationships between the circuit inputs and outputs; The establishment of a control model describing the dynamic characteristics of power electronic devices specifically includes: The switching state of the power electronic device is continuously processed using the switching cycle averaging method to construct an average model. Based on the average model, a differential equation describing the energy conversion relationship between input and output is derived; The differential equations are transformed into a unified form differential equation model in a synchronously rotating coordinate system through coordinate transformation, which serves as the control model.

7. The adaptive control method for a controller according to claim 5, characterized in that, The construction of the composite algorithm for device topology includes: Identify the topology type of the power electronic device and call at least one control algorithm block from the preset algorithm library; The standard data interface is used to establish a data mapping relationship between the called control algorithm blocks in order to construct a composite algorithm chain with a cascaded or decoupled structure. The composite algorithm is used to perform voltage and current loop control and feedforward decoupling operations based on the coupling characteristics defined in the control model.

8. The adaptive control method for a controller according to claim 5, characterized in that, The prediction and output of control parameters for each module in the composite algorithm specifically includes: The error signal of the output of the power electronic device is collected in real time and input to the parameter adaptive unit. The parameter adaptive unit is used to perform neural network forward propagation calculations to map the error signal into the proportional, integral, and derivative coefficients of the regulator in the corresponding control algorithm. The parameter adaptive unit updates its internal weights through a loss function feedback based on the ideal trajectory or ideal index determined by the control model, thereby achieving adaptive online tuning of the control parameters.

9. The adaptive control method for a controller according to claim 5, characterized in that, The general data type is U32bit data type, the basic unit of the standardized data interface contains 4 standardized data channels; and the control algorithm module includes at least one of PI, PR, PID, hysteresis control and decoupling control algorithm blocks.

10. The adaptive control method for a controller according to claim 5, characterized in that, The pulse width modulation module includes at least one of an SPWM module, an SVPWM module, a chopper module, and an H-bridge cascade module; wherein, the SPWM module adds optimal zero-sequence injection or third harmonic injection when generating the duty cycle time.

11. The adaptive control method for a controller according to claim 8, characterized in that, The parameter adaptive unit adopts a three-layer fully connected feedforward neural network architecture. The hidden layer uses the hyperbolic tangent function as the activation function and uses the gradient descent method with momentum term to perform backpropagation learning. It also uses the sign function to approximate the Jacobian information of the controlled object.

12. The adaptive control method for a controller according to claim 8, characterized in that, The parameter adaptive unit employs a multi-layer neural network. Based on Lyapunov stability theory, it constructs Lyapunov candidate functions and analyzes their forward difference characteristics to determine the weight update formula that makes the system asymptotically stable.

13. The adaptive control method for a controller according to claim 8, characterized in that, When performing performance evaluation, the parameter adaptive unit adopts a loss function that includes time window, ripple evaluation, and concept drift detection; and the parameter adaptive unit has multiple working modes, including performance evaluation selection mode, start-up replacement mode, periodic replacement mode, and instruction replacement mode.

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