Data-aware instruction closed-loop method, device and storage medium for fire storage collaborative control

Abstract

The application discloses a fire storage collaborative control data sensing instruction closed loop method, equipment and a storage medium, comprising: performing millimeter level online diagnosis on each collection channel; switching an abnormal collection channel to a same type backup collection channel; issuing a power instruction to a storage energy converter; acquiring actual power of the storage energy converter executing the power instruction feedback in a preset period, and calculating a difference value between the actual power and a power target value carried by the power instruction; calculating a power compensation value according to the difference value and an adaptive correction coefficient, and superimposing the power compensation value on the power target value carried by the power instruction to be issued to the storage energy converter in a next control period, and executing the acquisition of the difference value between the actual power and the power target value in each subsequent control period to form a continuously running closed loop control. The application combines the hardware level online diagnosis of the collection channel with the Kalman interpolation application to continuously correct the power deviation through the closed loop compensation, and significantly improves the response speed, the adjustment accuracy and the long-term operation reliability.

Description

Technical Field

[0001] This application relates to the field of fire-storage coordinated control technology, and in particular to a data sensing command closed-loop method, device and storage medium for fire-storage coordinated control. Background Technology

[0002] In a coal-fired power plant and energy storage co-control system, the reliability of data sensing directly determines the accuracy of frequency regulation control. When coal-fired power plants and energy storage systems jointly regulate frequency, they rely on numerous acquisition channels to obtain real-time status information such as cell voltage, current, and temperature. However, these acquisition channels are susceptible to signal loss, environmental noise interference, range abnormalities, and clock drift during long-term operation, leading to distorted uploaded data. If channel faults are not identified and recovered in a timely manner, control decisions will be based on erroneous data, potentially reducing frequency regulation response accuracy or even causing safety issues such as cell overcharging and over-discharging, resulting in system control interruption or equipment damage.

[0003] To ensure data quality, some systems employ software-level data verification or regular manual inspections to detect channel anomalies. However, software verification relies on upper-level algorithms, resulting in slow response times and an inability to eliminate interference at the data source. Manual inspections are time-consuming and struggle to detect transient faults promptly. Hardware-level channel diagnostic technology has been applied in some areas, but it is mostly limited to detecting single fault types. It lacks comprehensive diagnostic capabilities for multi-dimensional anomalies such as signal loss, exceeding measurement range, excessive noise, and timestamp offsets. Furthermore, it lacks seamless data completion and automatic recovery mechanisms during channel anomalies, making it difficult to meet the stringent requirements for high availability of collected data in fire-storage collaborative systems.

[0004] During the command execution phase, when the energy storage converter outputs actual power according to the upper-level power command, factors such as cell aging, temperature changes, and system impedance drift cause a continuous or time-varying deviation between the actual output and the command target value. Traditional open-loop control methods cannot detect this deviation, resulting in a significant decrease in regulation accuracy after long-term operation. Even when some systems introduce a power feedback loop, it is only a single correction and does not form a continuous tracking compensation mechanism. Furthermore, it does not consider the adaptive adjustment requirements of the compensation coefficient based on the cell health status, leading to persistently high steady-state deviations in power control.

[0005] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0006] The main purpose of this application is to provide a data sensing command closed-loop method, device and storage medium for thermal power and energy storage coordinated control, which aims to solve the technical problems of existing thermal power and energy storage coordinated control systems, which suffer from unreliable data sensing, low command execution accuracy and chaotic coordination of multiple time-series tasks, resulting in the overall control performance failing to meet the high dynamic frequency regulation requirements of the power grid.

[0007] To achieve the above objectives, this application proposes a data sensing command closed-loop method for coordinated control of fire and energy storage facilities, the method comprising: Millimeter-level online diagnostics are performed on each acquisition channel within the FPGA acquisition hardware. The diagnostic indicators for the online diagnostics include signal loss, over-range measurement, excessive noise, and timestamp offset. When any acquisition channel is diagnosed as abnormal based on the diagnostic indicators, the abnormal acquisition channel is switched to a backup acquisition channel of the same type. During the switching, short-term disconnection data is supplemented by Kalman interpolation. The acquired data after diagnosis and recovery is used as a valid input to participate in the control decision. The control decision generates a power command for controlling the operation of the energy storage converter based on the acquired data. The power command is sent to each sending channel, and the power command is output to the energy storage converter based on each sending channel. The sending channel includes a microsecond-level sending channel, a millisecond-level sending channel, and a second-level sending channel. The microsecond-level sending channel is configured with a first refresh frequency, the millisecond-level sending channel is configured with a second refresh frequency, and the second-level sending channel is configured with a third refresh frequency. The second refresh frequency is less than the first refresh frequency and greater than the third refresh frequency. Each sending channel shares a unified PTP clock reference for timing synchronization. The actual power fed back by the energy storage converter when executing the power command is obtained at a preset period, and the difference between the actual power and the power target value carried by the power command is calculated. The power compensation value is calculated based on the difference and the preset adaptive correction coefficient. The power compensation value is then added to the power target value carried in the power command to be sent to the energy storage converter in the next control cycle. In each subsequent control cycle, the steps of obtaining the difference between the actual power and the power target value, calculating the power compensation value based on the difference and the adaptive correction coefficient, and adding the power compensation value are performed until a shutdown command is received or the preset shutdown condition of the system is met, so as to form a continuously operating closed-loop control.

[0008] In one embodiment, the step of performing millimeter-level online diagnostics on each acquisition channel within the FPGA acquisition hardware includes: Signal loss detection is performed on the data stream of each acquisition channel with a millimeter-level diagnostic cycle. The number of consecutively lost sampling points is counted. When the number of consecutively lost points exceeds the preset loss threshold, a signal loss diagnostic flag is triggered. The upper and lower limits of the current sampled value of each acquisition channel are judged. When the sampled value exceeds the upper limit of the channel range or falls below the lower limit of the channel range, the over-range diagnostic flag is triggered. The high-frequency noise power of the sampling sequence of each acquisition channel is calculated, and the calculated high-frequency noise power is compared with a preset noise threshold. When the high-frequency noise power exceeds the preset noise threshold, the noise exceedance diagnostic flag is triggered. The timestamps of the sampled data frames from each acquisition channel are extracted and compared with the PTP clock reference inside the FPGA acquisition hardware. When the timestamp deviation exceeds the preset deviation threshold, the timestamp offset diagnostic flag is triggered.

[0009] In one embodiment, after the step of switching the abnormal acquisition channel to a backup acquisition channel of the same type, the method further includes: The abnormal acquisition channels are classified into different types. Abnormal acquisition channels that trigger signal loss diagnostic flags or timestamp offset diagnostic flags are classified into the first type of abnormality, and abnormal acquisition channels that trigger over-range diagnostic flags or noise exceeding standard diagnostic flags are classified into the second type of abnormality. Mark invalid data segments in the data stream of the abnormal acquisition channel of the first type of abnormality, and use the marked invalid data segments as the data range to be interpolated and completed; The sampled values ​​of the abnormal acquisition channel of the second type of abnormality are subjected to amplitude limiting and digital filtering. The sampled values ​​after amplitude limiting and filtering are used as alternative data of the acquisition channel during the period of abnormality to participate in control decision-making.

[0010] In one embodiment, the step of using Kalman interpolation to complete short-term disconnection data includes: Using the latest valid sampled value and the latest rate of change of the abnormal acquisition channel before the disconnection, as the initial state values, a state estimation model of the abnormal acquisition channel signal is constructed. The state estimation model is used to recursively estimate the signal state during the disconnection period, and interpolation sampling points are generated to fill the short-term disconnection data interval. After the short-term disconnection data interval is filled, the interpolated sampling points are smoothly connected with the measured sampling values ​​after the disconnection is restored, so that the rate of change of the sampling values ​​before and after the connection is continuous.

[0011] In one embodiment, after the step of using the diagnosed and recovered collected data as valid input to participate in control decision-making, the method further includes: The acquired data after diagnosis and recovery is sent to the data alignment buffer inside the FPGA acquisition hardware. The data acquired by each acquisition channel is aligned with nanosecond-level timestamps using the PTP clock reference inside the FPGA acquisition hardware as the time axis. After aligning the nanosecond-level timestamps, the collected data from each channel are normalized according to the channel type. The collected data of different dimensions are uniformly converted into per-unit values, and the converted per-unit value data is sent to the control decision unit.

[0012] In one embodiment, the step of outputting the power command to the energy storage converter based on each sending channel includes: The power commands are classified according to time response requirements. Power commands that require instantaneous power response within one control cycle are allocated to the microsecond-level transmission channel. The power commands output through the microsecond-level transmission channel are directly mapped to the power drive interface of the energy storage converter via FPGA hard logic and output as hard-wired signals. Power commands that require continuous power regulation to be completed within multiple control cycles are allocated to the millisecond-level sending channel and output to the energy storage converter via bus communication through the hard real-time controller. The power commands used for operating condition switching and start-stop control are allocated to the second-level sending channel and output to the energy storage converter via the ARM main core in the form of network packets; Before each channel outputs a power command, the output time of the command is synchronized with the PTP clock reference to ensure that each channel outputs under the same timing reference.

[0013] In one embodiment, after the step of calculating the difference between the actual power and the power target value carried by the power command, the method further includes: Determine whether the difference exceeds a preset deviation tolerance value; If not, maintain the current adaptive correction coefficient unchanged, and use the difference as the compensation calculation input for the next control cycle; If so, initiate the adaptive correction coefficient update process, recalculate the adaptive correction coefficient based on the difference and the cumulative historical deviation, and use the updated adaptive correction coefficient for subsequent compensation calculations.

[0014] In one embodiment, the step of performing the following in each subsequent control cycle: obtaining the difference between the actual power and the target power value, and calculating the power compensation value and the superimposed power compensation value based on the difference and the adaptive correction coefficient, includes: The power compensation amount calculated in the current control cycle is temporarily stored in the compensation amount buffer. When the power command is issued in the next control cycle, the currently effective power compensation amount is read from the compensation amount buffer and the power compensation amount is added to the power target value carried by the power command to be issued. After the power compensation is superimposed, the current compensation in the compensation buffer is marked as effective, and the difference between the actual power feedback value obtained this time and the value calculated this time is stored as historical data for use in the update calculation of the adaptive correction coefficient in subsequent control cycles.

[0015] Furthermore, to achieve the above objectives, this application also proposes a data sensing command closed-loop device for fire-storage coordinated control. The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor. The computer program is configured to implement the steps of the data sensing command closed-loop method for fire-storage coordinated control as described above.

[0016] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the steps of the data sensing instruction closed-loop method for fire and energy storage coordinated control as described above.

[0017] One or more technical solutions proposed in this application have at least the following technical effects: The technical solution of this application performs millimeter-level online diagnostics on each acquisition channel within the FPGA acquisition hardware. The diagnostic indicators for this online diagnostics include signal loss, over-range measurement, excessive noise, and timestamp offset. When any acquisition channel is diagnosed as abnormal based on these indicators, the abnormal acquisition channel is switched to a backup acquisition channel of the same type. During the switching process, short-term disconnected data is supplemented using Kalman interpolation. The recovered acquisition data is used as valid input for control decision-making. The control decision-making generates a power command for controlling the operation of the energy storage converter based on the acquisition data. The power command is then sent to each sending channel, and the power command is output to the energy storage converter based on each sending channel. The sending channels include microsecond-level, millisecond-level, and second-level sending channels. The microsecond-level sending channel is configured with a first refresh frequency, and the millisecond-level sending channel is configured with a second refresh frequency. The new frequency, the second-level transmission channel is configured with a third refresh frequency, the second refresh frequency is less than the first refresh frequency but greater than the third refresh frequency, and each transmission channel shares a unified PTP clock reference for timing synchronization; the actual power fed back by the energy storage converter when executing the current power command is obtained at a preset period, and the difference between the actual power and the power target value carried by the power command is calculated; the power compensation value is calculated based on the difference and a preset adaptive correction coefficient, and the power compensation value is added to the power target value carried by the power command to be sent to the energy storage converter in the next control cycle, and the steps of obtaining the difference between the actual power and the power target value, calculating the power compensation value based on the difference and the adaptive correction coefficient, and adding the power compensation value are executed in each subsequent control cycle until a shutdown command is received or the preset shutdown condition of the system is reached, so as to form a continuously operating closed-loop control.

[0018] The technical solution of this application, while ensuring the high availability of the collected data, realizes the continuous correction of instruction execution deviation and the coordinated output of multiple time-series tasks. It solves the technical problems of unreliable data quality, uncorrected power deviation, chaotic multi-task coordination and lack of adaptive compensation capability under the open-loop control paradigm. It realizes the technical leap of fire-storage coordinated control from open-loop feedforward to closed-loop feedback, from single-channel unified distribution to multi-channel hierarchical synchronization, and from passively accepting deviation to actively and continuously compensating. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart illustrating the first embodiment of the data sensing command closed-loop method for fire and energy storage coordinated control in this application. Figure 2 This is a detailed step diagram of step S30 in one embodiment; Figure 3 This is a detailed step diagram of step S50 in one embodiment; Figure 4 This is a schematic diagram of the online self-diagnosis and self-recovery logic flow for the data acquisition channel; Figure 5 This is a flowchart of the logic processing based on power command issuance; Figure 6 This is a schematic diagram of the closed-loop control process; Figure 7 Hardware channel architecture diagram for power command output control; Figure 8 This is a schematic diagram of the equipment structure of the hardware operating environment involved in the data perception command closed-loop method for fire and energy storage coordinated control in the embodiments of this application.

[0022] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0023] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0024] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0025] In the field of fire-storage coordinated control, the time alignment of data perception and command execution mainly follows the technical path of software-timed acquisition and open-loop command issuance, but it has inherent defects and is difficult to meet the dual requirements of ensuring the quality of acquired data and the closed-loop accuracy of command execution.

[0026] This type of solution typically involves the energy management system issuing a power target value, the energy storage converter executing the power output according to the command, and the acquisition channel transmitting cell status data back. However, software-based timed acquisition is limited by the non-real-time scheduling of the operating system, resulting in random jitter during acquisition. Furthermore, it cannot perform hardware-level real-time diagnosis of data quality issues such as signal loss, noise interference, range anomalies, and timestamp drift. After the command is issued, the system cannot detect the deviation between the actual output of the converter and the target value, and it lacks continuous tracking and adaptive compensation capabilities. Multiple time-scale tasks such as primary frequency regulation, AGC scheduling, and operating condition switching share a single channel, causing mutual interference and lacking a unified clock reference.

[0027] The core dilemma faced by the above-mentioned technical approach lies in the fact that the control paradigm of using software to time data acquisition and executing instructions in an open-loop manner has the characteristics of lacking data quality assurance, being unaware of instruction execution deviations, and having chaotic coordination of multiple time-series tasks. This is fundamentally contradictory to the inherent requirements of thermal power storage coordinated control for high-precision power tracking and high-reliability long-term operation.

[0028] To address the aforementioned shortcomings, this application proposes a data-sensing command closed-loop method for coordinated control of thermal power generation and energy storage. This method utilizes FPGA acquisition hardware to perform hardware-level online diagnostics on each acquisition channel for four categories of indicators: signal loss, over-range detection, excessive noise, and timestamp offset. In case of anomalies, it automatically switches to a backup channel and uses Kalman interpolation to complete the missing data. By acquiring the actual power feedback from the converter, it calculates the difference based on the power target value, and combines this with an adaptive correction coefficient dynamically adjusted according to the cell health status to generate a power compensation amount, which is then superimposed on the next cycle command, constructing a continuously operating closed-loop compensation mechanism. Furthermore, by setting up three-level distribution channels at the microsecond, millihertz, and second levels and sharing a unified PTP clock reference for timing synchronization, it enables tasks at different time scales to be executed in a hierarchical parallel manner with fully coordinated timing. This application achieves a technological leap in coordinated control of thermal power generation and energy storage from open-loop feedforward to closed-loop feedback, from single-channel unified distribution to multi-channel hierarchical synchronization, and from passively accepting deviations to actively and continuously compensating.

[0029] Based on this, embodiments of this application provide a data sensing command closed-loop method for coordinated fire and energy storage control, referring to... Figure 1 , Figure 1This is a flowchart illustrating the first embodiment of the data sensing command closed-loop method for fire-storage coordinated control according to this application. In this embodiment, the data sensing command closed-loop method for fire-storage coordinated control includes steps S10-S50: Step S10: Perform millimeter-level online diagnostics on each acquisition channel within the FPGA acquisition hardware. The diagnostic indicators for the online diagnostics include signal loss, over-range measurement, excessive noise, and timestamp offset. In this embodiment, millimeter-level online diagnostics are performed on each acquisition channel within the FPGA acquisition hardware. The thermal power and energy storage coordinated control system typically includes dozens or even hundreds of acquisition channels. These channels are used to acquire analog signals and switching signals such as cell voltage, current, temperature, and insulation resistance of battery clusters. Each acquisition channel physically corresponds to an input interface of the FPGA acquisition hardware, which integrates a multi-channel parallel acquisition unit and a diagnostic logic unit. The diagnostic logic unit cyclically scans each acquisition channel with a millimeter-level diagnostic cycle. This scanning behavior is not affected by the upper-level operating system scheduling and is executed entirely within the FPGA hardware using parallel logic. Therefore, the diagnostic latency is strictly controlled within the millimeter level, preventing the introduction of random jitter at the software level.

[0030] For signal loss diagnosis, the FPGA acquisition hardware has an internal continuous loss counter register that performs real-time statistics on the data stream of each acquisition channel. When the sampled value of a channel remains invalid within a preset diagnostic period window, the continuous loss counter register begins to accumulate until it exceeds a preset loss threshold. At this point, the diagnostic logic unit triggers the signal loss diagnosis flag. For example, in the cell voltage acquisition channel, if the analog-to-digital converter continuously outputs invalid code values ​​due to a fault in the front-end analog circuit, the continuous loss counter register will mark the channel as a signal loss state after several millimeter-level diagnostic cycles. This diagnostic mechanism does not rely on upper-level software intervention; the counting and comparison operations are completed entirely at the hardware level, resulting in extremely fast response speed and the ability to capture anomalies in the shortest possible time after a fault occurs.

[0031] For over-range diagnostics, the FPGA acquisition hardware internally stores an upper and lower limit register for each channel, containing the upper and lower limits for that channel, respectively. When a new sampled value enters the FPGA acquisition hardware, the comparison logic unit synchronously compares the sampled value with the upper and lower limits. If the sampled value exceeds the upper limit or falls below the lower limit, an over-range diagnostic flag is immediately triggered. The upper and lower limits differ significantly for different types of acquisition channels; for example, the upper limit of the voltage channel is much higher than that of the temperature channel. Therefore, the upper and lower limit registers for each channel can be configured independently. The diagnostic logic unit does not involve floating-point operations when performing upper and lower limit judgments; instead, it uses fixed-point comparisons to minimize hardware logic latency.

[0032] For noise exceedance diagnosis, the FPGA acquisition hardware internally includes a sliding window buffer and a noise power calculation unit. The noise power calculation unit extracts high-frequency components from the sampling sequence of each acquisition channel and calculates the high-frequency noise power value, which reflects the intensity of superimposed high-frequency interference components in the channel signal. The noise power calculation unit compares the calculated high-frequency noise power value with a preset noise threshold. When the high-frequency noise power exceeds the preset threshold, a noise exceedance diagnostic flag is triggered. This high-frequency noise power-based calculation method effectively distinguishes between rapid changes in the signal itself and abnormal noise superimposed on the signal, avoiding misjudging normal signal fluctuations as noise exceedance.

[0033] For timestamp offset diagnosis, the FPGA acquisition hardware maintains a global PTP clock reference internally. Each frame of acquired data is stamped with a hardware timestamp referenced to the PTP clock when it enters the FPGA acquisition hardware. The timestamp diagnosis unit extracts this hardware timestamp from the sampled data frame and compares it with the current PTP clock value inside the FPGA acquisition hardware to calculate the timestamp offset value. When the timestamp offset exceeds a preset offset threshold, the diagnosis logic unit triggers the timestamp offset diagnosis flag. This diagnosis mechanism ensures that the data from all acquisition channels have a consistent reference reference on the timeline, avoiding timeline misalignment of multi-source data caused by clock drift.

[0034] Specifically, the step of performing millimeter-level online diagnostics on each acquisition channel within the FPGA acquisition hardware includes: Signal loss detection is performed on the data stream of each acquisition channel with a millimeter-level diagnostic cycle. The number of consecutively lost sampling points is counted. When the number of consecutively lost points exceeds the preset loss threshold, a signal loss diagnostic flag is triggered. The upper and lower limits of the current sampled value of each acquisition channel are judged. When the sampled value exceeds the upper limit of the channel range or falls below the lower limit of the channel range, the over-range diagnostic flag is triggered. The high-frequency noise power of the sampling sequence of each acquisition channel is calculated, and the calculated high-frequency noise power is compared with a preset noise threshold. When the high-frequency noise power exceeds the preset noise threshold, the noise exceedance diagnostic flag is triggered. The timestamps of the sampled data frames from each acquisition channel are extracted and compared with the PTP clock reference inside the FPGA acquisition hardware. When the timestamp deviation exceeds the preset deviation threshold, the timestamp offset diagnostic flag is triggered.

[0035] In this embodiment, when performing millimeter-level online diagnostics on each acquisition channel within the FPGA acquisition hardware, four types of diagnostic logic units are deployed in parallel within the FPGA acquisition hardware. These four types of diagnostic logic units correspond to signal loss diagnosis, over-range diagnosis, noise exceeding limits diagnosis, and timestamp offset diagnosis, respectively. Each type of diagnostic logic unit works independently without interference, performing diagnostic operations on all acquisition channels simultaneously, and completing a full diagnostic cycle within a millimeter-level diagnostic period. Because the diagnostic logic is entirely deployed within the FPGA hardware, its execution is not affected by operating system scheduling or software interrupts, and the diagnostic latency is strictly controlled within the millimeter level.

[0036] During the specific execution of signal loss diagnosis, the continuous loss counter register inside the FPGA acquisition hardware monitors the data stream of each acquisition channel in real time with millimeter-level diagnostic cycles. The continuous loss counter register records the number of consecutive invalid samples for each channel; the counter increments by one for each invalid sample and resets to zero for each valid sample. When the value recorded by the continuous loss counter register exceeds a preset loss threshold, the diagnostic logic unit determines that the channel is in a signal loss state and triggers the signal loss diagnosis flag. The preset loss threshold represents the tolerable number of consecutive lost sampling points, and this value can be configured according to the data refresh rate of different acquisition channels. In typical scenarios of fire and energy storage coordinated control, signal loss is usually caused by front-end sensor disconnection, analog-to-digital converter failure, or communication link interruption. The continuous loss counter register can capture this fault state within several diagnostic cycles and immediately trigger the signal loss diagnosis flag, providing an accurate time starting point for subsequent channel switching and data completion.

[0037] In the specific execution of over-range diagnostics, the FPGA acquisition hardware internally configures independent upper and lower limit registers for each acquisition channel. The upper limit register stores the maximum value that the channel can sample, and the lower limit register stores the minimum value that the channel can sample. These two values ​​together define the effective sampling range of the channel. When a new sampled value enters the FPGA acquisition hardware, the comparison logic unit simultaneously performs two comparison operations: the first comparison compares the sampled value with the upper limit value in the upper limit register, and the second comparison compares the sampled value with the lower limit value in the lower limit register. If the sampled value is greater than the upper limit or less than the lower limit, the comparison logic unit immediately determines that the sampled value exceeds the effective sampling range and triggers the over-range diagnostic flag. Over-range phenomena are usually caused by overdrive of the front-end circuit, abnormal sensor output, or power fluctuations. Such abnormalities may suddenly appear at a single sampling point or may persist. The upper and lower limit discrimination of the FPGA acquisition hardware is performed at every sampling point, without relying on any historical data or statistical information, thus enabling the capture of every over-range event with minimal latency.

[0038] In the specific execution process of noise over-limit diagnosis, the sliding window buffer inside the FPGA acquisition hardware caches the numerical sequence of the most recent sampling points for each acquisition channel. The noise power calculation unit reads this numerical sequence from the sliding window buffer and performs high-frequency noise power calculation. The calculation method for high-frequency noise power is as follows: first, the numerical sequence is mean-filtered to obtain its low-frequency component; then, the low-frequency component is subtracted from the original numerical sequence to obtain the high-frequency component sequence; finally, the squares of each element in the high-frequency component sequence are summed and averaged to obtain the high-frequency noise power value. This calculation process is entirely implemented in hardware logic and does not involve floating-point operations, but uses fixed-point arithmetic to maintain calculation speed. The high-frequency noise power value reflects the strength of high-frequency interference components in the sampled signal of that channel. The noise power calculation unit compares the calculated high-frequency noise power with a preset noise threshold, which is stored in the threshold register inside the FPGA acquisition hardware. When the high-frequency noise power exceeds the preset noise threshold, the diagnostic logic unit determines that the channel is in a noise over-limit state and triggers the noise over-limit diagnostic flag. Excessive noise levels are typically caused by electromagnetic interference, poor grounding, or shielding failure, and are characterized by high-amplitude, high-frequency components superimposed on the normal signal. FPGA acquisition hardware can effectively identify this abnormal interference state through high-frequency noise power calculation.

[0039] In the specific execution of timestamp offset diagnosis, the FPGA acquisition hardware internally maintains a PTP clock module. This module synchronizes with an external PTP clock source via Ethernet, ensuring clock consistency across all hardware within the system. Each frame of acquired data is timestamped upon entering the FPGA acquisition hardware, with the PTP clock as the reference. The timestamp diagnosis unit extracts this hardware timestamp from the header of the sampled data frame and simultaneously reads the current PTP clock value from the PTP clock module, comparing the two values. The comparison result characterizes the degree of deviation between the actual acquisition time of the sampled data and the system time reference. If the difference exceeds a preset deviation threshold, the diagnosis logic unit determines that the channel has a timestamp offset and triggers the timestamp offset diagnosis flag. The preset deviation threshold is expressed in absolute time units, matching the precision of the PTP clock within the FPGA acquisition hardware. In the fire-storage coordinated control system, timestamp offset is usually caused by fluctuations in data buffering and forwarding delays in the acquisition link. If not diagnosed, this will lead to misalignment of multi-source data on the time axis, thereby affecting the timing accuracy of control decisions.

[0040] The diagnostic results of the four types of diagnostic logic units are output in the form of diagnostic flags. Each channel corresponds to four independent diagnostic flag bits. A valid flag bit indicates that the channel has a corresponding anomaly, while an invalid flag bit indicates that the channel is healthy in that dimension. Subsequent steps perform differentiated channel switching and data recovery operations based on the combined states of these diagnostic flag bits.

[0041] Step S20: When any acquisition channel is diagnosed as abnormal based on the diagnostic indicators, the abnormal acquisition channel is switched to a backup acquisition channel of the same type. During the switching, short-term disconnection data is supplemented by Kalman interpolation. The acquired data after diagnosis and recovery is used as a valid input to participate in the control decision. The control decision generates a power command for controlling the operation of the energy storage converter based on the acquired data. In this embodiment, when any acquisition channel is diagnosed as abnormal based on diagnostic indicators, the abnormal acquisition channel is switched to a backup acquisition channel of the same type. During the switching process, Kalman interpolation is used to complete the short-term disconnection data. The recovered acquisition data is used as valid input for control decision-making. The control decision generates a power command for controlling the operation of the energy storage converter based on the acquisition data. In the thermal energy storage coordinated control system, key acquisition channels are all configured with backup acquisition channels of the same type. For example, the main acquisition channel and the backup acquisition channel for cell voltage are connected in parallel to the voltage sampling point of the same cell. The two are completely independent in hardware, including independent analog-to-digital conversion channels and independent signal conditioning circuits. When the diagnostic logic unit determines that a certain acquisition channel has triggered a diagnostic flag, the channel selection logic inside the FPGA acquisition hardware immediately performs a switching operation, switching the data path from the abnormal acquisition channel to a backup acquisition channel of the same type. The switching operation is completed at the hardware level, and the delay from diagnostic triggering to switching effectiveness is extremely short, which will not cause data interruption to subsequent control decisions.

[0042] Simultaneously with the channel switching, the Kalman interpolation logic begins operation. Kalman interpolation is a recursive estimation algorithm based on a state-space model, capable of optimally estimating data during the disconnection period using historical state information of the signal prior to the disconnection. Specifically, the Kalman interpolation logic uses the latest valid sampled value and the latest rate of change of the abnormal acquisition channel before the disconnection as the initial state values. The latest valid sampled value reflects the signal amplitude level at the moment of disconnection, and the latest rate of change reflects the signal's trend before the disconnection; together, they constitute the two dimensions of the initial state value. Based on these two dimensions, the Kalman interpolation logic constructs a state estimation model that describes the evolution of the signal amplitude and rate of change over time.

[0043] After the state estimation model is constructed, the Kalman interpolation logic recursively estimates the signal state during the disconnection period. The recursive process proceeds step by step according to the sampling period of the FPGA acquisition hardware, and each step includes two stages: state prediction and observation update. The state prediction stage uses the state transition matrix to deduce the predicted state at the next moment from the current state; the observation update stage uses the observation matrix to correct the predicted state and obtain the optimal estimate at the current moment. Since there are no measured sample values ​​as observation inputs during the disconnection period, the observation values ​​in the observation update stage are replaced by the state prediction values. At this time, the Kalman interpolation degenerates into a pure prediction mode, but it can still generate reasonable interpolation sampling points based on the initial state value and the state transition matrix. The interpolation sampling points are generated point by point according to the FPGA sampling period, filling each missing position in the short-term disconnection data interval in turn, so that the data stream maintains continuous output during the disconnection period.

[0044] After the short-term data gap is filled, the Kalman interpolation logic smoothly connects the interpolated sampling points with the measured sampling values ​​after the data gap is restored. The purpose of this smooth connection is to ensure that the rate of change of the sampling values ​​before and after the connection point is continuous, avoiding data jumps caused by abrupt changes between the interpolation point and the measured point. The smooth connection adopts a weighted fusion method, gradually increasing the weight of the measured values ​​and decreasing the weight of the interpolation points near the connection point, so that the values ​​in the transition region transition smoothly. The acquired data after diagnosis and recovery, that is, the complete data stream including normal channel data and interpolated data, serves as a valid input to participate in control decisions.

[0045] The control decision unit generates power commands for controlling the energy storage converter based on the recovered data. Running within the upper-level controller, the control decision unit receives data from all recovered acquisition channels and outputs a power command containing the set power target value and a timestamp. Because the acquired data undergoes hardware-level diagnostic recovery, the data source upon which the control decision is based has high availability and continuity. Even in the event of a short-term failure in some channels, the decision algorithm can still obtain complete data input and will not interrupt the control logic or output abnormal commands due to data loss. For more details on the aforementioned data processing logic, please refer to [link to relevant documentation]. Figure 4 , Figure 4 This is a schematic diagram of the online self-diagnosis and self-recovery logic flow for the data acquisition channel.

[0046] Furthermore, after the step of switching the abnormal acquisition channel to a backup acquisition channel of the same type, the method further includes: The abnormal acquisition channels are classified into different types. Abnormal acquisition channels that trigger signal loss diagnostic flags or timestamp offset diagnostic flags are classified into the first type of abnormality, and abnormal acquisition channels that trigger over-range diagnostic flags or noise exceeding standard diagnostic flags are classified into the second type of abnormality. Mark invalid data segments in the data stream of the abnormal acquisition channel of the first type of abnormality, and use the marked invalid data segments as the data range to be interpolated and completed; The sampled values ​​of the abnormal acquisition channel of the second type of abnormality are subjected to amplitude limiting and digital filtering. The sampled values ​​after amplitude limiting and filtering are used as alternative data of the acquisition channel during the period of abnormality to participate in control decision-making.

[0047] After switching the abnormal acquisition channel to a backup acquisition channel of the same type, the abnormal acquisition channel no longer undertakes real-time data output tasks because its data stream has been replaced by the backup acquisition channel. However, its historical data range and sampled values ​​still have value for diagnostic processing. Therefore, the subsequent step is to classify the abnormal acquisition channel according to its anomaly type. The basis for anomaly type classification is the type of diagnostic flag triggered by the abnormal acquisition channel. Different diagnostic flag types reflect different fault mechanisms, and the data processing strategies corresponding to different fault mechanisms are also quite different.

[0048] Specifically, when an abnormal acquisition channel triggers either the signal loss diagnostic flag or the timestamp offset diagnostic flag, the abnormal acquisition channel is classified as a Type I anomaly. The signal loss diagnostic flag means that the channel outputs invalid sample values ​​for several consecutive diagnostic cycles. This usually indicates an interruption in the data stream itself—perhaps the front-end sensor output disappears, the analog-to-digital converter stops working, or the communication link is broken. The timestamp offset diagnostic flag means that the deviation between the timestamp carried by the sampled data frame output by the channel and the system PTP clock reference exceeds a preset threshold. This usually indicates that although the data stream is still transmitting, its time reference coordinates have become misaligned with the system time axis. Whether it's signal loss or timestamp offset, the essential characteristic is that the sequence of sampling points in the data stream has lost its validity in the time dimension; that is, the sampling points themselves may still have values, but these values ​​are unusable in the time dimension. For this type of anomaly, the goal of subsequent processing is to identify which time periods in the data stream belong to invalid intervals, thereby determining the accurate filling range for interpolation completion.

[0049] When an abnormal acquisition channel triggers either the over-range diagnostic flag or the noise exceeding the limit diagnostic flag, the abnormal acquisition channel is classified as a Type II anomaly. The over-range diagnostic flag means that the sampled value of the channel exceeds its upper limit or falls below its lower limit. This usually indicates that the amplitude of the sampled value itself has exceeded the normal range, but the data stream still remains continuous in the time dimension. The noise exceeding the limit diagnostic flag means that there are excessively high-frequency noise components in the sampling sequence of the channel. This usually indicates that the numerical accuracy of the sampled value itself has been severely contaminated by noise, but the data stream also remains continuous in the time dimension. The common essential characteristic of both over-range and noise exceeding the limit is that the sampling point sequence has lost accuracy in the numerical dimension; that is, the time axis of the data stream is correct, but the value represented by each sampling point is no longer reliable. For this type of anomaly, the goal of subsequent processing is to correct the sampled values, rather than filling in the gaps in the time axis.

[0050] For abnormal acquisition channels classified as Category I anomalies, invalid data segments are marked in their data streams. The marking process for invalid data segments begins at the trigger time of the diagnostic flag and ends at the recovery time of the diagnostic flag. In the case of signal loss, the starting point is the moment when the continuous loss count first exceeds a preset loss threshold, and the ending point is the moment when the continuous loss count returns to zero. In the case of timestamp offset, the starting point is the moment when the timestamp offset first exceeds a preset offset threshold, and the ending point is the moment when the timestamp offset returns to within the preset offset threshold. After the invalid data segments are marked, the marked invalid data segments are used as data intervals to be interpolated and completed. This interval is used to indicate in which time ranges the subsequent Kalman interpolation logic needs to generate interpolation sampling points. An invalid data segment may be a continuous time interval or multiple dispersed short time intervals. Each invalid data segment is marked and processed independently.

[0051] For abnormal acquisition channels classified as Category II anomalies, amplitude limiting and digital filtering are applied to the sampled values. Amplitude limiting compresses values ​​exceeding the upper limit of the range to that value and raises values ​​below the lower limit to that value, preventing extreme values ​​from impacting subsequent control decisions. Digital filtering smooths the amplitude-limited sampled sequence using a sliding window averaging or low-pass filtering algorithm to attenuate high-frequency noise components. The output of digital filtering is a sequence of sampled values ​​with attenuated noise. While this sequence may not be completely equivalent to normal sampled values ​​in terms of numerical accuracy, its amplitude range and fluctuation have been suppressed to an acceptable level. The amplitude-limited and filtered sampled values ​​serve as alternative data for the acquisition channel during the period of anomaly in control decisions. That is, although the channel is marked as an abnormal channel and has been switched to a backup channel, its amplitude-limited and filtered sampled values ​​can still be used for redundancy comparison or quality assessment with the backup channel's data, or to verify the data consistency of the backup channel after the channel recovers. The two types of anomalies described above form different recovery strategies: the first type of anomaly focuses on data filling on the time axis, while the second type of anomaly focuses on data correction on the numerical axis. Each type of anomaly uses the most suitable processing method for its different fault mechanisms.

[0052] In addition, the step of using Kalman interpolation to complete short-term disconnection data includes: Using the latest valid sampled value and the latest rate of change of the abnormal acquisition channel before the disconnection, as the initial state values, a state estimation model of the abnormal acquisition channel signal is constructed. The state estimation model is used to recursively estimate the signal state during the disconnection period, and interpolation sampling points are generated to fill the short-term disconnection data interval. After the short-term disconnection data interval is filled, the interpolated sampling points are smoothly connected with the measured sampling values ​​after the disconnection is restored, so that the rate of change of the sampling values ​​before and after the connection is continuous.

[0053] In this embodiment, after the short-term disconnection data interval is marked as the data interval to be interpolated and completed, the Kalman interpolation logic begins to fill in the missing values ​​in this data interval. Kalman interpolation is based on a state-space model and uses the historical state information of the signal before the disconnection to recursively estimate the signal change trend during the disconnection period. Its completion process begins with the construction of a state estimation model. Before the disconnection, the sampled values ​​of the abnormal acquisition channel are continuously output at a fixed sampling period. The buffer inside the FPGA acquisition hardware stores the historical values ​​of several sampling points of this channel before the disconnection. The Kalman interpolation logic reads the last valid sampled value before the disconnection and the rate of change at that sampling point from the buffer. The rate of change is calculated by dividing the difference between the values ​​of the previous two valid sampled points by the sampling interval. This latest valid sampled value represents the amplitude level of the signal at the moment of disconnection, and the latest rate of change represents the change trend of the signal before the disconnection. Together, they constitute the two dimensions of the initial state value—the amplitude dimension and the rate of change dimension. After the initial state values ​​are loaded into the Kalman filter, the Kalman interpolation logic constructs a state estimation model based on these two dimensions. The state estimation model describes the evolution of the signal amplitude and rate of change over time, and its state transition matrix expresses how to deduce the state at the next moment from the state at the current moment.

[0054] After the state estimation model is constructed, the Kalman interpolation logic recursively estimates the signal state during the disconnection period. The recursive process proceeds step by step according to the sampling period of the FPGA acquisition hardware, and each step includes a state prediction stage and an observation update stage. In the state prediction stage, the Kalman interpolation logic uses the state transition matrix to deduce the predicted state at the next moment from the current state. The predicted state includes two components: the predicted amplitude and the predicted rate of change. In the observation update stage, the Kalman interpolation logic uses the observation matrix to correct the predicted state. During the disconnection period, due to the lack of measured sample values ​​as observation input, the observation values ​​in the observation update stage are replaced by the state prediction values, and the gain matrix of the Kalman filter is adjusted to pure prediction mode. In this mode, the Kalman filter no longer relies on external measurement information to correct the predicted state, but relies entirely on the state transition matrix and historical state information for recursion, but it can still generate reasonable interpolation sampling points based on the initial state value and the state transition matrix. The interpolation sampling points are generated point by point according to the sampling period of the FPGA acquisition hardware, and one interpolation sampling point is output in each sampling period, sequentially filling each missing position in the short-term disconnection data interval. As the number of recursion steps increases, the uncertainty of the predicted state gradually increases. However, for short-term disconnection intervals, the number of recursion steps is usually limited to a few sampling periods, and the predicted state is still kept within an acceptable range of accuracy.

[0055] After filling in the short-term disconnection data interval, the Kalman interpolation logic needs to smoothly connect the interpolated sampling points with the measured sampling values ​​after the disconnection is restored. After the disconnection is restored, the abnormal acquisition channel resumes outputting measured sampling values, which reflect the actual numerical level of the signal after the disconnection. Since the interpolated sampling points are recursively estimated based on the initial state value before the disconnection, while the measured sampling values ​​reflect the actual signal state after the disconnection, there may be numerical differences between the two at the connection point. If the interpolated sampling points are directly switched to the measured sampling values, a numerical jump will occur at the connection point. This jump will manifest as a discontinuity in the rate of change of the sampled values. The purpose of smooth connection is to eliminate this jump and make the rate of change of the sampled values ​​before and after the connection point continuous. Smooth connection adopts a weighted fusion method. A certain number of transition points are selected near the connection point, and the interpolated sampling values ​​and measured sampling values ​​at these transition points are weighted and averaged according to gradually changing weights. That is, on the side closer to the interpolation area, the weight of the interpolated sampling values ​​is higher and the weight of the measured sampling values ​​is lower; on the side closer to the measured area, the weight of the interpolated sampling values ​​is lower and the weight of the measured sampling values ​​is higher. After weighted averaging, the sampled values ​​in the transition region smoothly transition from interpolated sampled values ​​to measured sampled values. The rate of change of the sampled values ​​before and after the transition remains continuous, with no abrupt changes. At this point, the missing values ​​in the short-term disconnected data interval are completely filled by Kalman interpolation, and the connection between the filled data sequence and the measured data before and after is smooth, forming a complete and continuous data stream. This data stream can be directly used for subsequent nanosecond-level timestamp alignment and normalization transformation.

[0056] Furthermore, after the step of using the diagnosed and recovered collected data as effective input to participate in control decision-making, the method further includes: The acquired data after diagnosis and recovery is sent to the data alignment buffer inside the FPGA acquisition hardware. The data acquired by each acquisition channel is aligned with nanosecond-level timestamps using the PTP clock reference inside the FPGA acquisition hardware as the time axis. After aligning the nanosecond-level timestamps, the collected data from each channel are normalized according to the channel type. The collected data of different dimensions are uniformly converted into per-unit values, and the converted per-unit value data is sent to the control decision unit.

[0057] In this embodiment, after the recovered data is used as valid input for control decision-making, slight differences in sampling times are inevitable due to the physical distribution of each acquisition channel at different locations within the energy storage system. Even if each channel operates at the same nominal sampling frequency, crystal oscillator drift and signal transmission path delays may still cause the data of each channel to be misaligned on the time axis. Therefore, before sending the recovered data to the control decision unit, the process first sends it to the data alignment buffer within the FPGA acquisition hardware. The data alignment buffer is a dedicated storage area within the FPGA acquisition hardware. This area allocates an independent buffer line for each acquisition channel, and each buffer line stores the acquisition data of the most recent sampling cycles of that channel in the order of sampling time. All buffer lines share a unified read / write control logic, which uses the PTP clock reference as the time axis to perform timestamp alignment operations on the data in each buffer line.

[0058] The specific execution process of nanosecond-level timestamp alignment is as follows: The PTP clock module continuously maintains a global time base with nanosecond-level accuracy and periodically synchronizes with an external PTP clock source via Ethernet to ensure clock consistency with the power grid dispatching system. Each frame of acquired data is timestamped upon entering the FPGA acquisition hardware; the timestamp is directly latched by the PTP clock module at the sampling moment. The read / write control logic of the data alignment buffer reads the acquired data and its timestamp from each channel frame by frame. Using the PTP clock base as a unified time axis, the acquired data from all channels are arranged on the same time axis in ascending order of timestamp. For any target alignment moment, the read / write control logic searches for the acquired data frame with the timestamp closest to the target moment in the buffer line of each channel and extracts it as the alignment data for that channel at that target moment. If a channel does not have a matching timestamp near the target moment, interpolated data for that target moment is generated through linear interpolation between adjacent sampling points to ensure that all channels have corresponding alignment data at each target moment. After nanosecond-level timestamp alignment, the data from all acquisition channels are precisely synchronized on the timeline, eliminating time misalignment errors caused by different sampling times.

[0059] After nanosecond-level timestamp alignment, the data acquired from each channel is normalized. Each acquisition channel acquires different types of physical quantities, with significant differences in their dimensions and numerical ranges. For example, the typical range for cell voltage is 0 to 5 volts, for cell current it is -1000 to 1000 amperes, for temperature it is -40 to 85 degrees Celsius, and for insulation resistance it can reach megaohm levels. If these raw data with different dimensions are directly sent to the control decision unit, the unit needs to process the dimensions and numerical ranges of each channel individually. This not only increases the algorithm complexity but also easily leads to rounding errors and overflow risks in numerical calculations due to differences in numerical ranges. Normalization converts the acquired data with different dimensions into per-unit values. The per-unit values ​​are based on the upper and lower limits of the channel's range, mapping the original sampled values ​​to a standardized numerical range of -1 to +1 or zero to 1.

[0060] The specific execution process of normalization conversion is as follows: The FPGA acquisition hardware internally configures a normalization parameter register group for each channel. This register group stores the upper and lower limits of the range for that channel, and a reference value. The reference value is typically the midpoint between the upper and lower limits. The normalization conversion logic reads the aligned original sampled value from the data alignment buffer, and simultaneously reads the corresponding normalization parameter for that channel. The conversion logic subtracts the reference value from the original sampled value, and then divides the difference by half the range value to obtain the per-unit value. A positive per-unit value indicates that the sampled value is higher than the reference value, and a negative value indicates that the sampled value is lower than the reference value. Its absolute value reflects the relative degree of deviation from the reference value. Since the per-unit value unifies the numerical range of all channels on the same scale, the control decision unit no longer needs to consider the differences in dimensions and ranges of each channel when processing data from different channels. It only needs to perform unified mathematical operations on the per-unit value, simplifying the algorithm design and improving numerical stability. The converted per-unit data is organized into data frames according to channel number and sampling time, and sent to the control decision unit through the high-speed data interface between the FPGA acquisition hardware and the upper-level controller. The control decision unit receives standardized acquisition data that has been precisely aligned on the time axis and unified in units of numerical scale, which can be directly used for power command calculation and generation without additional preprocessing. The timestamp alignment and normalization conversion operations are executed in a pipelined manner within the FPGA acquisition hardware. The total delay experienced by each frame of data from entering the alignment buffer to outputting per-unit data is on the order of nanoseconds, which will not affect the real-time performance of subsequent control decisions.

[0061] Step S30: The power command is sent to each sending channel, and the power command is output to the energy storage converter based on each sending channel. The sending channels include a microsecond-level sending channel, a millisecond-level sending channel, and a second-level sending channel. The microsecond-level sending channel is configured with a first refresh frequency, the millisecond-level sending channel is configured with a second refresh frequency, and the second-level sending channel is configured with a third refresh frequency. The second refresh frequency is less than the first refresh frequency and greater than the third refresh frequency. Each sending channel shares a unified PTP clock reference for timing synchronization. In this embodiment, power commands are sent to various sending channels, and the power commands are output to the energy storage converter based on each sending channel. The sending channels include microsecond-level, millisecond-level, and second-level sending channels. The microsecond-level sending channel is configured with a first refresh frequency, the millisecond-level sending channel with a second refresh frequency, and the second-level sending channel with a third refresh frequency. The second refresh frequency is lower than the first refresh frequency but higher than the third refresh frequency. All sending channels share a unified PTP clock reference for timing synchronization.

[0062] The power command, from its generation by the control decision unit to its final execution by the energy storage converter, undergoes command routing and channel allocation. The command routing stage allocates the power command to the corresponding transmission channel based on the time response tag carried by the command. The time response tag is assigned when the control decision unit generates the power command, and its value reflects the time scale requirement of the control task addressed by the power command. For a power command corresponding to a primary frequency regulation task, its time response tag is in the microsecond range, and the command routing stage allocates the command to a microsecond-level transmission channel. For a power command corresponding to an AGC scheduling task, its time response tag is in the millisecond range, and the command routing stage allocates the command to a millisecond-level transmission channel. For a power command corresponding to a mode switching and start-stop control task, its time response tag is in the second range, and the command routing stage allocates the command to a second-level transmission channel.

[0063] The microsecond-level command transmission channel is deployed within the FPGA hard logic, with its hardware carrier being the hard logic circuitry inside the FPGA chip. The refresh frequency of this channel is configured as the first refresh frequency, significantly higher than that of the millisecond and second-level command transmission channels, to meet the stringent response time requirements of instantaneous power regulation in a single frequency modulation. Power commands output through the microsecond-level command transmission channel are directly mapped to the power drive interface of the energy storage converter via the FPGA hard logic, outputting as hard-wired signals. These hard-wired signals are physical signals in the form of levels and pulses, directly connected to the hardware trigger input of the energy storage converter, without passing through any protocol stack or software intermediate layer, thus achieving the shortest possible command transmission delay.

[0064] The millisecond-level command delivery channel is deployed within the hard real-time controller, whose hardware platform is an embedded controller running a real-time operating system. The refresh rate of this channel is configured as a second refresh rate, falling between the first and third refresh rates, suitable for AGC power scheduling tasks. Power commands output through the millisecond-level command delivery channel are then output to the energy storage converter by the hard real-time controller via bus communication. Bus communication methods include, but are not limited to, CAN bus and Modbus bus. These bus protocols have defined communication timing and predictable transmission delays, ensuring that commands reach the energy storage converter within millisecond cycles.

[0065] The second-level power delivery channel is deployed within the ARM main core, with its hardware carrier being an ARM processor core running Linux or other general-purpose operating systems. This channel's refresh rate is configured as a third refresh rate, lower than the first and second refresh rates, suitable for tasks with relatively relaxed time response requirements, such as operating condition switching and start-stop control. Power commands output through this second-level channel are then sent to the energy storage converter by the ARM main core via network packets. This network packet method, based on the Ethernet communication protocol, can carry a large data load and is suitable for transmitting control commands containing multiple parameters, such as operating condition switching commands that include additional information beyond the power target value, such as operating mode identifiers and parameter configuration tables.

[0066] Before each channel outputs a power command, the output time of the command is synchronized with the PTP clock reference. The PTP clock reference is maintained by the PTP clock module inside the FPGA acquisition hardware. This clock module synchronizes with an external PTP clock source via the network, ensuring clock consistency across all nodes within the system. The time synchronization calibration process ensures that each channel outputs commands under the same timing reference, avoiding timing misalignment of multi-channel commands caused by independent timing of each channel.

[0067] Step S40: Obtain the actual power fed back by the energy storage converter when executing the power command at a preset period, and calculate the difference between the actual power and the power target value carried by the power command; In this embodiment, the actual power fed back by the energy storage converter when executing the current power command is obtained at a preset period, and the difference between the actual power and the power target value carried in the power command is calculated. After receiving the power command, the energy storage converter executes power output according to the set power target value carried in the power command. The actual output active power value is measured in real time by the power detection module inside the energy storage converter. The power detection module typically calculates the active power based on the instantaneous sampled values ​​of voltage and current, and the calculation period is consistent with the control period of the energy storage converter. The energy storage converter feeds back the calculated actual power value to the control system through the communication interface, and this feedback value is reported at a preset period.

[0068] The preset period is matched with the overall control period of the thermal energy storage coordinated control, for example, acquiring the actual power feedback value every 10 milliseconds. This acquisition is triggered by a timed task in the control system. Each time it is triggered, the control system sends a power query command to the energy storage converter, which responds to the command and returns the actual power value at the current moment. The acquired actual power value corresponds in time to the steady-state output stage of the energy storage converter after executing this power command, thus accurately reflecting the execution effect of the power command.

[0069] After the actual power feedback value is sent to the difference calculation unit, the unit simultaneously reads the power target value carried by the issued power command, which is used as the expected output value. The difference calculation unit subtracts the actual power feedback value from the power target value to obtain the difference between the two. The sign of the difference reflects the direction of the deviation of the actual output from the expected output: a positive difference indicates that the actual output is lower than the expected output, and a negative difference indicates that the actual output is higher than the expected output. The absolute value of the difference reflects the magnitude of the deviation. The calculated difference is used as the input to the subsequent closed-loop compensation stage to quantify the command execution accuracy in the current control cycle.

[0070] Furthermore, after calculating the difference between the actual power and the power target value carried by the power command, the method further includes: Determine whether the difference exceeds a preset deviation tolerance value; If not, maintain the current adaptive correction coefficient unchanged, and use the difference as the compensation calculation input for the next control cycle; If so, initiate the adaptive correction coefficient update process, recalculate the adaptive correction coefficient based on the difference and the cumulative historical deviation, and use the updated adaptive correction coefficient for subsequent compensation calculations.

[0071] In this embodiment, after calculating the difference between the actual power and the target power value carried by the power command, the absolute value of this difference directly reflects the degree to which the power output of the energy storage converter deviates from the expected value of the command in the current control cycle, and the magnitude of the deviation determines the selection of subsequent compensation strategies. For deviations of a small magnitude, the system should maintain the existing compensation parameters to ensure control stability; for deviations of a large magnitude, the system needs to adjust the compensation parameters to enhance the compensation strength. Therefore, the first step is to determine whether the difference exceeds the preset deviation tolerance value. The preset deviation tolerance value is a numerical boundary preset by the control system to distinguish the severity of the deviation. This value is usually expressed as a percentage of power or an absolute power value and can be configured according to the rated power of the energy storage converter and the control accuracy requirements.

[0072] When the difference does not exceed the preset deviation tolerance, it indicates that the power output deviation in the current control cycle is within an acceptable range, and this deviation will not have a substantial impact on the control accuracy numerically. At this time, there is no need to adjust the adaptive correction coefficient; the current adaptive correction coefficient remains unchanged. Simultaneously, the current difference is used as the compensation calculation input for the next control cycle. This means that even when the current difference is small, the next control cycle will still calculate and add compensation based on this difference. However, because the difference is small and the adaptive correction coefficient remains unchanged, the magnitude of the compensation is correspondingly small, and it will not cause significant fluctuations in the power command. This strategy of "unchanged coefficients but deviation still participating in compensation" balances the requirements of control stability and continuous compensation. Even if the difference is very small, the system still maintains compensation to prevent deviation accumulation, but because the coefficient remains unchanged and the difference is already less than the tolerance, the magnitude of the compensation action is gentle.

[0073] When the difference exceeds the preset deviation tolerance, it indicates that the power output deviation in the current control cycle has exceeded the acceptable range, is significant, and may substantially affect control accuracy. At this point, the current compensation strategy alone is insufficient to effectively suppress the deviation in subsequent cycles. Therefore, an adaptive correction coefficient update process needs to be initiated to adjust the correction coefficient itself to enhance the compensation capability. The execution logic of the adaptive correction coefficient update process is as follows: using the current difference as one of the inputs, it simultaneously reads the historical cumulative deviation value, which stores historical data of the difference over several past control cycles. The update process weights and combines the current difference with the historical cumulative deviation value to calculate a comprehensive deviation. This comprehensive deviation reflects both the severity of the current deviation and its cumulative trend over time. Based on the comprehensive deviation, the update process calculates a new adaptive correction coefficient; the larger the comprehensive deviation, the larger the new adaptive correction coefficient; the smaller the comprehensive deviation, the smaller the new adaptive correction coefficient. The updated adaptive correction coefficient replaces the original correction coefficient and is used for compensation calculations in all subsequent control cycles. This update mechanism ensures that the correction coefficient can adaptively adjust to changes in the deviation: when the deviation remains large, the correction coefficient gradually increases to enhance the compensation and accelerate deviation convergence; when the deviation gradually decreases, the correction coefficient also decreases to avoid overcompensation. The updated adaptive correction coefficient takes effect from the next control cycle and is used for the calculation of all subsequent compensation amounts. Through this adaptive adjustment mechanism, the closed-loop control system can automatically track the characteristic changes of the energy storage converter caused by cell aging, temperature drift, or changes in system impedance during long-term operation, continuously maintaining effective suppression of power deviation.

[0074] Step S50: Calculate the power compensation value based on the difference and the preset adaptive correction coefficient. Add the power compensation value to the power target value carried in the power command to be sent to the energy storage converter in the next control cycle. In each subsequent control cycle, perform the steps of obtaining the difference between the actual power and the power target value, calculating the power compensation value based on the difference and the adaptive correction coefficient, and adding the power compensation value, until a shutdown command is received or the preset shutdown condition of the system is reached, so as to form a continuously operating closed-loop control.

[0075] In this embodiment, the power compensation amount is calculated based on the difference and the preset adaptive correction coefficient. The power compensation amount is then added to the power target value carried in the power command to be sent to the energy storage converter in the next control cycle. In each subsequent control cycle, the steps of obtaining the difference between the actual power and the power target value, calculating the power compensation amount based on the difference and the adaptive correction coefficient, and adding the power compensation amount are executed until a shutdown command is received or the preset shutdown condition of the system is met, so as to form a continuously operating closed-loop control.

[0076] The calculation logic for the power compensation amount is based on the difference as input. This difference reflects the deviation between the actual power output of the energy storage converter and the desired power command target in the current control cycle. To eliminate this deviation, the control system needs to add a compensation amount to the original power target value in the next control cycle, making the actual output of the converter closer to the desired target. The core of this compensation logic lies in the calculation method of the compensation amount. While theoretically, directly using the difference as the compensation amount could achieve a one-step compensation, in actual systems, due to the converter's response delay and system inertia, direct compensation can easily cause overshoot and oscillations. Therefore, the compensation logic introduces an adaptive correction coefficient to proportionally adjust the difference, thereby controlling the compensation strength and convergence speed.

[0077] The adaptive correction coefficient is configured as a parameter that dynamically adjusts according to the cell's health status. Cell health status is a quantitative indicator reflecting the aging degree of the energy storage battery. As the number of cell cycles increases and operating time accumulates, the cell's internal resistance gradually increases and its capacity gradually decreases, causing changes in the actual power output characteristics of the energy storage converter. When the cell's health status is high, the converter responds more sensitively to power commands, the deviation between the actual output and the command target is small, and convergence is easy. A smaller adaptive correction coefficient is used to prevent overcompensation. When the cell's health status decreases, the converter's response characteristics deteriorate, the deviation between the actual output and the command target increases, and convergence is difficult. A larger adaptive correction coefficient is used to enhance the compensation effect. The adaptive correction coefficient can be read from a parameter table during each power compensation calculation. This parameter table is periodically updated by the battery management system based on the cell's historical operating data and current status.

[0078] After the power compensation is calculated, it does not take effect immediately but is temporarily stored in the compensation buffer. The compensation buffer is a dedicated storage area in the control system for storing currently effective compensation values, and it can be accessed by the instruction generation logic in the control decision unit. At the power instruction generation time of the next control cycle, the instruction generation logic reads the currently effective power compensation from the compensation buffer and adds it to the power target value carried in the power instruction to be issued, forming the corrected power target value. The above data logic can also be viewed... Figure 5 , Figure 5 This is a flowchart of the logic processing based on power command issuance; In each subsequent control cycle, the process of acquiring the difference between the actual power and the target power value, calculating the power compensation amount, and adding it to the power command for the next cycle continues, forming an uninterrupted closed loop. This continuously operating closed loop ensures that the power control deviation will not diverge due to cell aging or environmental changes, and will always be suppressed within the preset tolerance. The operation of the closed-loop control is not time-limited, and will stop when the control system receives a shutdown command or when the system's preset shutdown conditions are met. The shutdown command is usually issued by the operator or the upper-level dispatch system for normal shutdown operations; the system's preset shutdown conditions include, but are not limited to, situations requiring emergency shutdown such as serious faults in the energy storage system or grid-side anomalies. When any of the above shutdown conditions occur, the closed-loop control stops operating, the system enters a shutdown state, and no new power compensation or command issuance operations are performed. The logic shown can be viewed. Figure 6 , Figure 6 This is a schematic diagram of the closed-loop control process.

[0079] Further, see Figure 2 , Figure 2 This is a detailed step diagram of step S30 in one embodiment, based on Figure 2 The step of outputting the power command to the energy storage converter based on each sending channel includes S31~S32: Step S31: Classify the power commands according to time response requirements, allocate the power commands that require instantaneous power response within one control cycle to the microsecond-level transmission channel, and directly map the power commands output through the microsecond-level transmission channel to the power drive interface of the energy storage converter via FPGA hard logic, and output them as hard-wired signals. Step S32: The power command that requires continuous power regulation to be completed within multiple control cycles is allocated to the millisecond-level sending channel and output to the energy storage converter through the hard real-time controller in a bus communication manner; Step S33: The power command used for operating condition switching and start-stop control is allocated to the second-level sending channel and output to the energy storage converter through the ARM main core in the form of network packets; Step S34: Before each channel outputs a power command, the output time of the command of each channel is time-synchronized and calibrated using the PTP clock reference to ensure that each channel outputs under the same timing reference.

[0080] In this embodiment, during the process of outputting power commands to the energy storage converter through various distribution channels, the coordinated control of thermal power and energy storage involves various control tasks with different time response requirements. Different types of power commands have fundamentally different requirements for transmission delay and refresh frequency. Therefore, the power commands are first classified according to their time response requirements. The classification is based on the type of control task the power command addresses; different types of control tasks have different response time constraints. For primary frequency regulation tasks, grid frequency fluctuations need to be responded to within milliseconds. Therefore, the corresponding power commands must be delivered to the energy storage converter and executed in the shortest possible time. These power commands are categorized as those requiring instantaneous power response within one control cycle. For AGC power scheduling tasks, the scheduling cycle is typically tens to hundreds of milliseconds. The corresponding power commands require power tracking within a relatively defined time. These power commands are categorized as those requiring continuous power regulation within multiple control cycles. For operating condition switching and start-stop control tasks, the time response requirements are relatively relaxed, typically requiring completion within hundreds of milliseconds to seconds. These power commands are categorized as those used for operating condition switching and start-stop control. When the power command is output from the control decision unit, it carries a task type label. The classification logic allocates the command to the corresponding distribution channel based on the label.

[0081] For power commands requiring instantaneous power response within a single control cycle, the classification logic allocates these commands to a microsecond-level transmission channel. This microsecond-level transmission channel is deployed within the FPGA hard logic, its hardware carrier being the hard logic circuitry inside the FPGA chip. This channel operates at a first refresh rate, significantly higher than other channels. Power commands output through the microsecond-level transmission channel are directly mapped to the power drive interface of the energy storage converter via the FPGA hard logic, outputting as hard-wired signals. These hard-wired signals are physical level signals, directly connected to the hardware trigger input of the energy storage converter. This output method bypasses any protocol stack, software intermediate layers, and bus bandwidth; therefore, the delay between the command output from the FPGA hard logic and its reception by the energy storage converter is only the signal propagation delay on the wire, achieving the shortest possible command transmission time. In practical implementation, a dedicated output register is configured within the FPGA hard logic for the microsecond-level transmission channel, directly connected to the FPGA's physical pins. When the microsecond-level transmission channel receives the power command, the power target value in the command is immediately written into the output register, and the level state of the output register changes accordingly. This level change is transmitted to the drive interface of the energy storage converter through a hard-wired signal, and the energy storage converter responds to the hard-wired signal and performs power output.

[0082] For power commands requiring continuous power regulation over multiple control cycles, the classification logic allocates these commands to the millisecond-level delivery channel. This millisecond-level delivery channel is deployed within the hard real-time controller, an embedded controller running a real-time operating system that ensures deterministic task scheduling. The millisecond-level delivery channel operates at a second refresh rate, falling between the refresh rates of the microsecond-level and second-level channels. Power commands output through the millisecond-level delivery channel are then output to the energy storage converter by the hard real-time controller via bus communication. This bus communication is based on fieldbus protocols, including but not limited to CAN bus and Modbus bus, which have defined communication timing and predictable transmission delays. In practice, the hard real-time controller encapsulates the power command into a bus protocol message and sends it to the bus within a defined time slot. The energy storage converter's bus communication interface receives the message, parses out the target power value, and then executes the power output. Because the hard real-time controller can guarantee the determinism of message transmission time and the transmission delay of bus communication is relatively fixed, the instruction transmission delay of the millisecond-level downlink channel is controlled within a predictable range, which meets the time response requirements of AGC power scheduling.

[0083] For power commands used for operating condition switching and start-stop control, the classification logic allocates these commands to the second-level dispatch channel. The second-level dispatch channel is deployed in the ARM main core, a processor core running a general-purpose or lightweight operating system, primarily responsible for system management and status monitoring. The second-level dispatch channel operates at a third refresh rate, lower than the refresh rates of the microsecond and millisecond-level dispatch channels. Power commands output through the second-level dispatch channel are then output to the energy storage converter by the ARM main core via network packets. Network packets, based on the Ethernet communication protocol, can carry a large data load and are suitable for transmitting control commands containing multiple parameters. In practice, the ARM main core packages the power command and other parameters required for operating condition switching into a network packet and sends it to the energy storage converter via the Ethernet interface. The energy storage converter's Ethernet communication interface receives the network packet, parses out the target power value and additional parameters, and simultaneously executes the operating condition switching action and power output response.

[0084] Before each of the aforementioned distribution channels outputs power commands, the channel performs time synchronization calibration using a PTP clock reference. The PTP clock reference is maintained by the PTP clock module within the FPGA acquisition hardware. This module synchronizes with an external PTP clock source via Ethernet, ensuring clock consistency across all hardware within the system. Each distribution channel records its current PTP time when outputting a command and executes the output operation at the designated time according to a preset output schedule. The time synchronization calibration process ensures that the microsecond, millisecond, and second-level distribution channels output commands under the same timing reference. Even if commands output by different channels belong to different components of the same power command or to different power commands, their timing relationship is deterministic and predictable, preventing timing misalignment due to independent channel timing. Through PTP synchronization calibration, the three-level distribution channels macroscopically function as a unified command output system. Each channel collaborates according to its own time granularity to jointly complete the multi-timescale command output task for the coordinated control of the thermal power generation and energy storage system. The relevant logic for the power command output can be found in [link to relevant documentation]. Figure 7 , Figure 7 This is a hardware channel architecture diagram for power command output control.

[0085] Further, see Figure 3 , Figure 3 This is a detailed step diagram of step S50 in one embodiment, based on Figure 3 The step of obtaining the difference between the actual power and the target power value in each subsequent control cycle, and calculating the power compensation value and superimposed power compensation value based on the difference and the adaptive correction coefficient, includes S51~S52: Step S51: The power compensation amount calculated in the current control cycle is temporarily stored in the compensation amount buffer. When the power command is issued in the next control cycle, the currently effective power compensation amount is read from the compensation amount buffer and the power compensation amount is added to the power target value carried by the power command to be issued. Step S52: After the power compensation is superimposed, the current compensation in the compensation buffer is marked as effective, and the difference between the actual power feedback value obtained this time and the value calculated this time is stored as historical data for use in the update calculation of the adaptive correction coefficient in subsequent control cycles.

[0086] In this embodiment, during the process of obtaining the difference between the actual power and the target power value in each subsequent control cycle, and calculating and superimposing the power compensation value based on the difference and adaptive correction coefficient, since the calculation and effectiveness of the power compensation amount belong to different control cycles in time, in order to ensure that the compensation amount can be accurately superimposed at the moment the power command is issued in the next control cycle, the power compensation amount calculated in the current control cycle is temporarily stored in the compensation amount buffer. The compensation amount buffer is a storage area in the control system specifically used to store the power compensation amount. This area is physically located in the memory of the upper-level controller or in a dedicated register group inside the FPGA acquisition hardware. The compensation amount buffer is managed according to the timing of the control cycle, and it contains the current compensation amount storage bit and the historical compensation amount storage bit. The power compensation amount calculated in the current control cycle is written to the current compensation amount storage bit after the calculation is completed. The content of this storage bit is read at the moment the power command is issued in the next control cycle. After the read operation is completed, the content of this storage bit is not automatically cleared, but waits for the next write to overwrite.

[0087] At the moment the power command is issued in the next control cycle, the command generation logic reads the currently effective power compensation amount from the compensation buffer and adds this power compensation amount to the power target value carried in the power command to be issued. The power command issuance moment is the point in each control cycle when the control system sends the power command to the energy storage converter. This point in time is controlled by a timer and occurs at a fixed time in each control cycle. At this moment, the command generation logic simultaneously obtains two inputs: one is the original power target value generated by the control decision unit, which reflects the expected output calculated by the control algorithm based on the current system state; the other is the current power compensation amount read from the compensation buffer, which reflects the deviation correction requirement between the actual output and the target value in the previous control cycle. The command generation logic adds the original power target value and the power compensation amount to obtain the corrected power target value, encapsulates the corrected power target value into the power command, and sends it to the energy storage converter through the issuance channel. Since the power compensation is superimposed on the original target value, the command target value received by the energy storage converter already includes the correction for the deviation of the previous cycle, so that the actual output of the current control cycle approaches the expected value based on the open-loop target.

[0088] After the power compensation is superimposed, the current compensation amount in the compensation amount buffer is marked as effective. The effective status flag indicates that the compensation amount has been read and superimposed into the power command of the current control cycle, preventing the compensation amount from being reused in subsequent control cycles. Each compensation amount in the compensation amount buffer is in an ineffective state when written; after being read and superimposed by the instruction generation logic, its status flag is updated to effective. When a new power compensation amount is calculated and written to the compensation amount buffer in the next control cycle, the new compensation amount overwrites the original effective compensation amount, and the status flag is simultaneously reset to ineffective. This flag management mechanism ensures that each compensation amount is used only once in one control cycle, preventing overcompensation due to multiple superpositions.

[0089] After the compensation values ​​are superimposed, the difference between the actual power feedback value and the calculated value is stored as historical data. The historical data storage area is a dedicated region in the control system for storing historical closed-loop control data. This area stores the actual power feedback value and corresponding difference for each control cycle in chronological order. The historical data storage area uses a circular buffer structure; when the stored data reaches a preset capacity, the oldest data is overwritten to store the latest data. The purpose of the historical data storage area is to provide the data basis for updating the adaptive correction coefficients in subsequent control cycles—the update process of the adaptive correction coefficients requires the current difference and the historical cumulative deviation value as input, and the historical cumulative deviation value is obtained by statistically calculating the differences from multiple cycles stored in the historical data storage area. Specifically, when the difference exceeds the preset deviation tolerance value, triggering the correction coefficient update process, the update process reads the differences from the most recent control cycles from the historical data storage area, performs a weighted sum or cumulative average of these differences, and obtains the historical cumulative deviation value. This historical cumulative deviation value reflects the cumulative trend of the deviation over time and participates in the recalculation of the correction coefficients along with the current difference. Through this mechanism, the feedback data generated by each closed-loop control action is recorded and used to optimize subsequent control parameters, enabling the closed-loop system to learn and adjust from historical operating experience, thereby further improving control accuracy.

[0090] This application provides a data sensing command closed-loop device for fire and energy storage coordinated control. The data sensing command closed-loop device for fire and energy storage coordinated control includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the data sensing command closed-loop method for fire and energy storage coordinated control in the above embodiment 1.

[0091] The following is for reference. Figure 8 The diagram illustrates a structural schematic of a data sensing command closed-loop device suitable for implementing fire-storage coordinated control in the embodiments of this application. The data sensing command closed-loop device for fire-storage coordinated control in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 8 The data sensing command closed-loop device for fire and energy storage coordinated control shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0092] like Figure 8As shown, the data sensing command closed-loop device for fire and energy storage coordinated control may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the data sensing command closed-loop device for fire and energy storage coordinated control. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the data sensing command closed-loop device for fire and energy storage coordinated control to exchange data wirelessly or via wired communication with other devices. Although the figure shows a data sensing command closed-loop device for fire and energy storage coordinated control with various systems, it should be understood that it is not required to implement or possess all the systems shown. More or fewer systems can be implemented alternatively.

[0093] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0094] The data sensing and command closed-loop device for thermal power and energy storage coordinated control provided in this application adopts the data sensing and command closed-loop method for thermal power and energy storage coordinated control in the above embodiments. This solves the technical problem that existing thermal power and energy storage coordinated control systems suffer from unreliable data sensing, low command execution accuracy, and chaotic multi-time-sequence task coordination, resulting in overall control performance failing to meet the high dynamic frequency regulation requirements of the power grid. Compared with the prior art, the beneficial effects of the data sensing and command closed-loop device for thermal power and energy storage coordinated control provided in this application are the same as those of the data sensing and command closed-loop method for thermal power and energy storage coordinated control provided in the above embodiments. Furthermore, other technical features of this data sensing and command closed-loop device for thermal power and energy storage coordinated control are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0095] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0096] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0097] This application provides a storage medium, which is a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon. The computer-readable program instructions are used to execute the data sensing instruction closed-loop method for fire and energy storage coordinated control in the above embodiments.

[0098] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0099] The aforementioned computer-readable storage medium may be included in the data sensing command closed-loop device for fire and energy storage coordinated control; or it may exist independently and not be assembled into the data sensing command closed-loop device for fire and energy storage coordinated control.

[0100] The aforementioned computer-readable storage medium carries one or more programs. When the aforementioned one or more programs are executed by the data sensing command closed-loop device for fire and energy storage coordinated control, the data sensing command closed-loop device for fire and energy storage coordinated control implements the technical content of the data sensing command closed-loop method embodiment for fire and energy storage coordinated control as shown above.

[0101] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0102] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0103] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0104] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., computer programs) for executing the above-described data sensing instruction closed-loop method for fire-storage coordinated control. This solves the technical problem that existing fire-storage coordinated control systems suffer from unreliable data sensing, low instruction execution accuracy, and chaotic multi-time-sequence task coordination, resulting in overall control performance failing to meet the high dynamic frequency regulation requirements of the power grid. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the data sensing instruction closed-loop method for fire-storage coordinated control provided in the above embodiments, and will not be elaborated upon here.

Claims

1. A data sensing command closed-loop method for coordinated control of fire storage and thermal power, characterized in that, Includes the following steps: Millimeter-level online diagnostics are performed on each acquisition channel within the FPGA acquisition hardware. The diagnostic indicators for the online diagnostics include signal loss, over-range measurement, excessive noise, and timestamp offset. When any acquisition channel is diagnosed as abnormal based on the diagnostic indicators, the abnormal acquisition channel is switched to a backup acquisition channel of the same type. During the switching, short-term disconnection data is supplemented by Kalman interpolation. The acquired data after diagnosis and recovery is used as a valid input to participate in the control decision. The control decision generates a power command for controlling the operation of the energy storage converter based on the acquired data. The power command is sent to each sending channel, and the power command is output to the energy storage converter based on each sending channel. The sending channel includes a microsecond-level sending channel, a millisecond-level sending channel, and a second-level sending channel. The microsecond-level sending channel is configured with a first refresh frequency, the millisecond-level sending channel is configured with a second refresh frequency, and the second-level sending channel is configured with a third refresh frequency. The second refresh frequency is less than the first refresh frequency and greater than the third refresh frequency. Each sending channel shares a unified PTP clock reference for timing synchronization. The actual power fed back by the energy storage converter when executing the power command is obtained at a preset period, and the difference between the actual power and the power target value carried by the power command is calculated. The power compensation value is calculated based on the difference and the preset adaptive correction coefficient. The power compensation value is then added to the power target value carried in the power command to be sent to the energy storage converter in the next control cycle. In each subsequent control cycle, the steps of obtaining the difference between the actual power and the power target value, calculating the power compensation value based on the difference and the adaptive correction coefficient, and adding the power compensation value are performed until a shutdown command is received or the preset shutdown condition of the system is met, so as to form a continuously operating closed-loop control.

2. The data sensing command closed-loop method for coordinated control of fire and energy storage as described in claim 1, characterized in that, The steps for performing millimeter-level online diagnostics on each acquisition channel within the FPGA acquisition hardware include: Signal loss detection is performed on the data stream of each acquisition channel with a millimeter-level diagnostic cycle. The number of consecutively lost sampling points is counted. When the number of consecutively lost points exceeds the preset loss threshold, a signal loss diagnostic flag is triggered. The upper and lower limits of the current sampled value of each acquisition channel are judged. When the sampled value exceeds the upper limit of the channel range or falls below the lower limit of the channel range, the over-range diagnostic flag is triggered. The high-frequency noise power of the sampling sequence of each acquisition channel is calculated, and the calculated high-frequency noise power is compared with a preset noise threshold. When the high-frequency noise power exceeds the preset noise threshold, the noise exceedance diagnostic flag is triggered. The timestamps of the sampled data frames from each acquisition channel are extracted and compared with the PTP clock reference inside the FPGA acquisition hardware. When the timestamp deviation exceeds the preset deviation threshold, the timestamp offset diagnostic flag is triggered.

3. The data sensing command closed-loop method for coordinated control of fire and energy storage as described in claim 1, characterized in that, After the step of switching the abnormal acquisition channel to a backup acquisition channel of the same type, the method further includes: The abnormal acquisition channels are classified into different types. Abnormal acquisition channels that trigger signal loss diagnostic flags or timestamp offset diagnostic flags are classified into the first type of abnormality, and abnormal acquisition channels that trigger over-range diagnostic flags or noise exceeding standard diagnostic flags are classified into the second type of abnormality. Mark invalid data segments in the data stream of the abnormal acquisition channel of the first type of abnormality, and use the marked invalid data segments as the data range to be interpolated and completed; The sampled values ​​of the abnormal acquisition channel of the second type of abnormality are subjected to amplitude limiting and digital filtering. The sampled values ​​after amplitude limiting and filtering are used as alternative data of the acquisition channel during the period of abnormality to participate in control decision-making.

4. The data sensing command closed-loop method for coordinated control of fire and energy storage as described in claim 1, characterized in that, The step of using Kalman interpolation to complete short-term disconnection data includes: Using the latest valid sampled value and the latest rate of change of the abnormal acquisition channel before the disconnection, as the initial state values, a state estimation model of the abnormal acquisition channel signal is constructed. The state estimation model is used to recursively estimate the signal state during the disconnection period, and interpolation sampling points are generated to fill the short-term disconnection data interval. After the short-term disconnection data interval is filled, the interpolated sampling points are smoothly connected with the measured sampling values ​​after the disconnection is restored, so that the rate of change of the sampling values ​​before and after the connection is continuous.

5. The data sensing command closed-loop method for coordinated control of fire and energy storage as described in claim 1, characterized in that, Following the step of using the diagnosed and recovered collected data as effective input for control decision-making, the method further includes: The acquired data after diagnosis and recovery is sent to the data alignment buffer inside the FPGA acquisition hardware. The data acquired by each acquisition channel is aligned with nanosecond-level timestamps using the PTP clock reference inside the FPGA acquisition hardware as the time axis. After aligning the nanosecond-level timestamps, the collected data from each channel are normalized according to the channel type. The collected data of different dimensions are uniformly converted into per-unit values, and the converted per-unit value data is sent to the control decision unit.

6. The data sensing command closed-loop method for coordinated control of fire and energy storage as described in claim 1, characterized in that, The step of outputting the power command to the energy storage converter based on each sending channel includes: The power commands are classified according to time response requirements. Power commands that require instantaneous power response within one control cycle are allocated to the microsecond-level transmission channel. The power commands output through the microsecond-level transmission channel are directly mapped to the power drive interface of the energy storage converter via FPGA hard logic and output as hard-wired signals. Power commands that require continuous power regulation to be completed within multiple control cycles are allocated to the millisecond-level sending channel and output to the energy storage converter via bus communication through the hard real-time controller. The power commands used for operating condition switching and start-stop control are allocated to the second-level sending channel and output to the energy storage converter via the ARM main core in the form of network packets; Before each channel outputs a power command, the output time of the command is synchronized with the PTP clock reference to ensure that each channel outputs under the same timing reference.

7. The data sensing command closed-loop method for coordinated control of fire and energy storage as described in claim 1, characterized in that, After the step of calculating the difference between the actual power and the power target value carried by the power command, the method further includes: Determine whether the difference exceeds a preset deviation tolerance value; If not, maintain the current adaptive correction coefficient unchanged, and use the difference as the compensation calculation input for the next control cycle; If so, initiate the adaptive correction coefficient update process, recalculate the adaptive correction coefficient based on the difference and the cumulative historical deviation, and use the updated adaptive correction coefficient for subsequent compensation calculations.

8. The data sensing command closed-loop method for coordinated control of fire and energy storage as described in claim 1, characterized in that, The step of obtaining the difference between the actual power and the target power value in each subsequent control cycle, and calculating the power compensation value and the superimposed power compensation value based on the difference and the adaptive correction coefficient, includes: The power compensation amount calculated in the current control cycle is temporarily stored in the compensation amount buffer. When the power command is issued in the next control cycle, the currently effective power compensation amount is read from the compensation amount buffer and the power compensation amount is added to the power target value carried by the power command to be issued. After the power compensation is superimposed, the current compensation in the compensation buffer is marked as effective, and the difference between the actual power feedback value obtained this time and the value calculated this time is stored as historical data for use in the update calculation of the adaptive correction coefficient in subsequent control cycles.

9. A data sensing command closed-loop device for coordinated control of fire and energy storage, characterized in that, The data sensing command closed-loop device for fire and energy storage coordinated control stores a computer program, which, when executed by a processor, implements the data sensing command closed-loop method for fire and energy storage coordinated control as described in any one of claims 1-8.

10. A storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the data sensing instruction closed-loop method for fire and energy storage coordinated control as described in any one of claims 1-8.

Images