Unified timestamp-based multi-node synchronous trigger control method for additive manufacturing

Abstract

Embodiments of the present disclosure provide a unified timestamp-based additive manufacturing multi-node synchronization trigger control method. Applied to the technical field of additive manufacturing, the method comprises: generating a response timestamp by capturing a physical state signal, calculating an instantaneous deviation by comparing with a preset reference, and constructing a global synchronization error topology. Further, the network transmission jitter and the device inherent time delay are separated by using a sliding window, and the time stamp is corrected by feedforward compensation at the master control end. Finally, high-precision control data is generated by dynamically rewriting the network node time base parameters and fine-tuning the stepping pulse, driving the end execution mechanism to realize spatial collaborative cladding forming at the corrected time, and ensuring the precise manufacturing of the formed components. Through time sequence feedforward compensation and dynamic time base fine-tuning, the network jitter and the hardware inherent time delay are eliminated, the distributed multi-node deterministic synchronization is realized, the multi-axis high-precision linkage of the end is guaranteed, and the forming quality of the additive manufacturing components is significantly improved.

Description

Technical Field

[0001] This disclosure relates to the field of additive manufacturing technology, and in particular to a method for synchronous triggering control of multiple nodes in additive manufacturing based on a unified timestamp. Background Technology

[0002] In the spatial collaborative cladding process, multiple distributed execution terminals need to coordinate their cladding actions under strict time coordination. Any time deviation between terminals will directly lead to misalignment of the cladding path and deviation of interlayer overlap, thus affecting the dimensional accuracy and mechanical properties of the additively manufactured components. Since network transmission delay and inherent device response latency are constantly changing, traditional static synchronization methods are difficult to meet the frame-by-frame time alignment requirements of high-precision molding.

[0003] In existing technologies, the master control terminal usually broadcasts a unified reference timestamp to each distributed execution terminal. After receiving the timestamp, each terminal corrects its local clock based on a preset fixed compensation value and then performs the melting action according to the corrected time. In some schemes, the master control terminal periodically collects the response feedback from each terminal, calculates the overall deviation, and then issues a unified correction command. Each terminal adjusts its execution timing for the next cycle accordingly.

[0004] However, fixed compensation values ​​cannot distinguish between network transmission jitter and inherent device latency, resulting in limited compensation accuracy; periodic feedback mechanisms lack feedforward prediction capabilities, and deviations can only be corrected after they occur; batch-issued correction commands cannot achieve real-time fine-tuning at the frame-by-frame level. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this disclosure provides a multi-node synchronous triggering control method for additive manufacturing based on a unified timestamp. This disclosure solves the problems of existing technologies where fixed compensation values ​​cannot distinguish between network transmission jitter and inherent device delays, resulting in limited compensation accuracy; periodic feedback mechanisms lack feedforward prediction capabilities, meaning deviations can only be corrected after they occur; and batch-issued correction commands cannot achieve real-time fine-tuning at the frame-by-frame level.

[0006] According to a first aspect of this disclosure, a multi-node synchronous triggering control method for additive manufacturing based on a unified timestamp is provided, comprising: acquiring physical state change signals generated in real time by a distributed execution end in a spatial collaborative cladding process, and performing frame-by-frame feature stream capture and time axis numerical linear transformation based on the physical state change signals to obtain the actual response timestamp of streaming updates; A preset time base sequence is obtained. Based on the actual response timestamp and the base timestamp extracted from the preset time base sequence, dynamic time domain difference tracing calculation is performed to obtain the instantaneous deviation value. Based on the instantaneous deviation value, the time sequence deviation is encapsulated and asynchronously streamed up to the reverse network channel to obtain a dynamically updated global synchronization error topology. Based on the global synchronization error topology, cross-cycle time-series rolling frequency domain feature extraction and dynamic separation of DC trend terms are performed based on a preset sliding window to obtain the real-time updated network transmission jitter sequence and the device inherent delay component sequence. Based on the inherent time delay component sequence of the device, feedforward trend rolling extrapolation and feedforward compensation prediction are performed in the main control loop at the main control end to obtain the rolling updated corrected synchronization timestamp. The network transmission jitter sequence is sampled in real time to capture the instantaneous value of the current network transmission jitter. Based on the instantaneous value of the current network transmission jitter, the time base parameters of the network control node are dynamically and instantly rewritten, and the step pulse of the time counting sequence is finely adjusted in real time to obtain the target drive control data refreshed frame by frame. Based on the target-driven control data, the control network control node performs a real-time comparison between the local clock and the corrected synchronization timestamp. When the local clock reaches the corrected synchronization timestamp, it drives the distributed execution end to perform spatial collaborative cladding forming to obtain the formed additive manufacturing component.

[0007] According to a second aspect of this disclosure, an additive manufacturing multi-node synchronous triggering control system based on a unified timestamp is provided for executing the method described in the first aspect, comprising: a response timing capture module for acquiring physical state change signals generated in real-time by a distributed execution end during the spatial collaborative cladding process, and performing frame-by-frame feature stream capture and time axis numerical linear transformation based on the physical state change signals to obtain the actual response timestamp updated in a streaming manner. The error topology construction module is used to obtain a preset time base sequence, perform dynamic time domain difference tracing calculation based on the actual response timestamp and the base timestamp extracted from the preset time base sequence to obtain the instantaneous deviation value, and perform time sequence deviation encapsulation and asynchronous streaming reporting of the reverse network channel based on the instantaneous deviation value to obtain a dynamically updated global synchronization error topology. The delay jitter separation module is used to extract cross-cycle time-series rolling frequency domain features and dynamically separate DC trend terms based on a preset sliding window, based on the global synchronization error topology, to obtain a real-time updated network transmission jitter sequence and a device inherent delay component sequence. The feedforward compensation prediction module is used to perform feedforward trend rolling extrapolation and feedforward compensation prediction in the main control loop of the main control terminal based on the inherent time delay component sequence of the device, so as to obtain the rolling updated corrected synchronization timestamp. The time base dynamic adjustment module is used to sample the network transmission jitter sequence in real time to capture the instantaneous value of the current network transmission jitter, dynamically and instantly rewrite the time base parameters of the network control node based on the instantaneous value of the current network transmission jitter, and finely adjust the step pulse of the time counting sequence in real time to obtain the target drive control data refreshed frame by frame. The collaborative molding drive module is used to control the network control node to perform real-time comparison between the local clock and the corrected synchronization timestamp based on the target drive control data. When the local clock reaches the corrected synchronization timestamp, it drives the distributed execution end to perform spatial collaborative cladding molding to obtain the molded additive manufacturing component.

[0008] According to a third aspect of this disclosure, an electronic device is provided, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor executes the program to implement the method described above.

[0009] In the additive manufacturing multi-node synchronous triggering control method based on unified timestamp provided above, the embodiments of this disclosure eliminate network jitter and inherent hardware delay through timing feedforward compensation and dynamic time base fine-tuning, realize distributed multi-node deterministic synchronization, ensure high-precision linkage of multi-axis at the end, and significantly improve the forming quality of additive manufacturing components. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A first flowchart of a multi-node synchronous triggering control method for additive manufacturing based on a unified timestamp, according to an embodiment of the present disclosure, is shown. Figure 2 A second flowchart of a multi-node synchronous triggering control method for additive manufacturing based on a unified timestamp, according to an embodiment of the present disclosure, is shown. Figure 3 A schematic block diagram of an additive manufacturing multi-node synchronous triggering control system based on a unified timestamp is shown according to an embodiment of the present disclosure; Figure 4 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0012] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0013] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them. It should also be understood that in the embodiments of this disclosure, "multiple" can refer to two or more, and "at least one" can refer to one, two, or more. It should also be understood that any component, data, or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless explicitly limited or given a contrary indication in the context. Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this disclosure generally indicates that the related objects before and after are in an "or" relationship. It should also be understood that the descriptions of the various embodiments in this disclosure emphasize the differences between the various embodiments; their similarities or commonalities can be referred to mutually, and for the sake of brevity, they will not be elaborated upon one by one.

[0014] Furthermore, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn to actual scale. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use. Techniques, methods, and apparatus known to those skilled in the art will not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0015] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0016] Figure 1 This is a first flowchart illustrating an additive manufacturing multi-node synchronous triggering control method based on a unified timestamp, provided in an embodiment of this disclosure.

[0017] S101: Obtain the physical state change signal generated in real time by the distributed execution terminal during the spatial collaborative cladding process. Based on the physical state change signal, perform frame-by-frame feature stream capture and time axis numerical linear transformation to obtain the actual response timestamp of the streaming update.

[0018] Distributed execution end units are physical control execution units that are distributed across different topological nodes in a spatial collaborative additive manufacturing system and collaboratively complete motion trajectory interaction and forming operations. They include multi-axis linkage control components, forming operation components, and supporting motion drive components.

[0019] The physical state change signal is a set of time-domain waveform parameters that dynamically evolve with the processing behavior in the spatial collaborative cladding forming process. It is used to instantly map the dynamic evolution of the processing behavior, including characteristic data that characterizes forming features, temperature field evolution, surface morphology profile, and motion position changes.

[0020] The actual response timestamp is a deterministic time reference information that characterizes the occurrence of physical state changes. It is a data label of the physical event trigger time that corresponds to the system reference time axis and has deterministic timing characteristics.

[0021] In the spatial collaborative cladding process, distributed execution terminals deployed on different topological nodes perform collaborative motion trajectory interaction and forming operations. During the dynamic evolution of this processing behavior, the multi-axis linkage control components, forming operation components, and supporting motion drive components contained in the distributed execution terminals synchronously generate electrical signals as time-domain waveform parameters. Using synchronous analog-to-digital conversion technology, the original time-domain waveform parameters generated by the above components are synchronously sampled to obtain feature data characterizing forming features, temperature field evolution, surface morphology contours, and motion positional changes. The acquired feature data is then time-division multiplexed and aggregated using a parallel bus to generate real-time arrayed physical state change signals.

[0022] The generated real-time arrayed physical state change signal is acquired, and using a streaming framing technique based on a circular buffer, the signal is divided into discrete time-domain data frames according to a time-domain sliding window. Within each time-domain data frame, a discrete difference operator is used to calculate the gradient of the feature data characterizing the forming features, temperature field evolution, surface morphology contour, and motion position changes. A dynamic threshold comparison technique is used to capture edge abrupt changes in the gradient values, extracting key transition point features when waveforms undergo abrupt changes. The extracted key transition point features of each frame are then stream-serialized and reassembled according to the generation time order, outputting a frame-by-frame feature stream.

[0023] The frame-by-frame feature stream of the above output is acquired, and each key transition point feature in the stream is time-locked using a local reference clock counter to capture the corresponding local time count value. The captured local time count value is compared with the system reference time axis, and a clock compensation technique based on the drift rate scaling factor is used to perform a linear time axis transformation on the local time count value to correct the accumulated time deviation and establish a linear mapping relationship between the local time axis and the system reference time axis. After the transformation, a physical event trigger time data label corresponding to the system reference time axis and possessing deterministic timing characteristics is formed. This label serves as the deterministic time reference information, and finally, the actual response timestamp of the streaming update is obtained.

[0024] Based on the above technical solution, optionally, frame-by-frame feature stream capture and time-axis numerical linear transformation can be performed based on physical state change signals to obtain the actual response timestamp for streaming updates, including: Based on the physical state change signal, serial time axis alignment and streaming buffer aggregation of multi-channel data streams are performed to obtain synchronous streaming data streams at the same frequency; Based on synchronous streaming data at the same frequency, the manufacturing space coordinate topology matrix projection and space coordinate mapping are performed to obtain the original spatiotemporal array data. Based on the original spatiotemporal array data, spatial neighborhood gradient numerical difference calculation and abrupt edge capture are performed to obtain frame-by-frame feature streams. Based on the frame-by-frame feature stream, a reference clock drift correction and a linear transformation of the time axis values ​​are performed to obtain the actual response timestamp of the streaming update.

[0025] In this scheme, the multi-channel data stream is a multi-channel concurrent digital transmission carrier that characterizes the physical state change signal. It is used to transmit the multi-dimensional physical waveforms of the processing behavior in parallel on the time axis. It covers the forming feature data stream, temperature field data stream, surface contour data stream and motion position data stream corresponding to different physical quantity detection channels.

[0026] Synchronous streaming data is a continuous time-domain data sequence with strict timing consistency and fixed phase alignment. It is characterized by the seamless fusion and equal-frequency convergence of multiple channel data streams on the same system reference time axis, which is used to provide a set of uniform real-time processing behavior waveforms that eliminate asynchronous time delays.

[0027] The original spatiotemporal array data is a multi-dimensional structured matrix set constructed by binding dynamic physical state waveforms with physical processing space in a multi-dimensional mapping. It includes multi-dimensional spatial topological coordinate information of each sampling point in the processing area, as well as multi-channel physical state sampling values ​​that correspond to each coordinate point in real time.

[0028] Frame-by-frame feature stream is a structured spatiotemporal mutation information sequence organized with discrete time frames as the basic unit. It is used to instantly map the local evolution trend of processing behavior in the manufacturing space neighborhood. It includes differential gradient features reflecting the numerical changes in the spatial neighborhood, edge features of sudden temperature field changes, and morphological contour boundary features.

[0029] In spatial collaborative cladding forming, the physical state change signal is first captured. This physical state change signal is converted into a multi-channel data stream, which is transmitted in parallel as forming feature data stream, temperature field data stream, surface contour data stream, and pose data stream. During time axis alignment, the asynchronous data packets of each channel are timestamped using a time base generated by a hardware timer. A streaming buffering and data aggregation method based on a circular buffer is used to push the asynchronous streaming data into the buffer for queue alignment. In this process, a linear interpolation resampling algorithm is used to resample the sampling rate of each channel with a unified system clock base to eliminate the time delay and phase difference between multiple concurrent data streams, achieving alignment and seamless fusion on the time axis. The final output is a continuous time-domain data sequence with strict timing consistency and fixed phase alignment characteristics, i.e., a synchronous streaming data stream with the same frequency.

[0030] After acquiring the aforementioned synchronous streaming data stream, to transform it from a time-domain signal into spatially distributed data, the forming feature data stream, temperature field data stream, surface contour data stream, and pose data stream contained within it are extracted. During spatial coordinate transformation, the real-time coordinates in the pose data stream are directly read. Using matrix multiplication of the homogeneous coordinate transformation matrix, the sampled values ​​of the forming feature, temperature field, and surface contour at the same time stamp are projected onto the three-dimensional control space in real time. Through spatial meshing, these discrete sampling points are filled into preset mesh nodes according to their actual spatial locations. This process maps the dynamic physical state waveform to the processing space in multiple dimensions, ultimately obtaining a structured data array, i.e., the original spatiotemporal array data, which completely contains the spatial coordinate information of each sampling point within the processing area, as well as the multi-channel sampled values ​​that correspond instantly in time to each coordinate point.

[0031] Based on the generated original spatiotemporal array data, spatial gradient calculations are performed on its structured data array to identify abrupt changes in processing status. Within discrete time frames, spatial differential operators are used to perform spatial difference operations on the multi-channel sampled values ​​of adjacent grid nodes within the processing area, calculating their rate of change on the spatial coordinate axes. Subsequently, threshold comparison logic is applied to perform edge detection; when the difference value exceeds a preset adaptive threshold, a processing abrupt change is determined. This process captures and extracts gradient features, temperature field edge features, and contour features within the spatial neighborhood in real time. These features are organized and encapsulated using discrete time frames as basic units, ultimately outputting a continuous spatiotemporal feature sequence, i.e., a frame-by-frame feature stream.

[0032] After acquiring the aforementioned frame-by-frame feature stream, to determine the precise time of the processing action, a reference clock drift correction and time axis transformation must be performed. First, the local hardware timestamps of each discrete time frame are read. The clock drift deviation obtained through least-squares fitting is used to subtract and correct the local hardware timestamps, eliminating crystal oscillator temperature drift and cumulative counting errors. After correction, time axis mapping technology is used to perform multiplication and addition operations on the corrected time using a preset scaling factor and time offset, uniformly mapping and transforming it onto the system reference time axis. Through this standard processing flow, the gradient features, temperature field edge features, and contour features contained in the frame-by-frame feature stream are precisely bound to the deterministic temporal features corresponding to the system reference time axis. The final output is the actual response timestamp, which is represented as an event timestamp and updated in a streaming manner.

[0033] This solution effectively eliminates network jitter and inherent hardware latency through timing feedforward compensation and dynamic time base fine-tuning, achieving deterministic synchronization of distributed multi-nodes. This mechanism ensures high-precision multi-axis linkage at the end point, significantly improving the forming stability of the additive manufacturing process and the final geometric accuracy of the components.

[0034] S102, obtain a preset time base sequence, perform dynamic time domain difference tracing calculation based on the actual response timestamp and the base timestamp extracted from the preset time base sequence to obtain the instantaneous deviation value, and based on the instantaneous deviation value, perform time sequence deviation encapsulation and asynchronous streaming reporting of the reverse network channel to obtain a dynamically updated global synchronization error topology.

[0035] The preset time reference sequence is a set of ideal time reference points pre-configured by the system and arranged in chronological order. It serves as the unified time standard for the entire network's coordinated scheduling and includes the target trigger time sequence, the expected interaction time node matrix, and the theoretical processing trajectory execution time sequence.

[0036] The baseline timestamp is an ideal time reference node extracted from a preset time base sequence. It serves as the expected execution time in the network-wide collaborative scheduling and is used to align and compare with the actual response timestamps of the distributed execution terminals. It is the main supporting point for building time synchronization standards.

[0037] The instantaneous deviation value is the time-domain difference between the actual response timestamp and the reference timestamp at a specific sampling instant, used to quantify the degree of clock misalignment at the current distributed execution end.

[0038] Global synchronization error topology is a dynamic data graph network that characterizes the error correlation between all cooperating nodes in a distributed network in the spatial and temporal dimensions. It includes node identification flow, directional error propagation link matrix, and the relative synchronization deviation state among all nodes in the network.

[0039] Based on the static configuration register address space, an addressing and reading operation is performed to obtain a preset time base sequence, which is a set of ideal timing reference points arranged in chronological order. Based on the target trigger timing sequence, the expected interaction time node matrix, and the theoretical processing trajectory execution timing sequence contained in this preset time base sequence, the network-wide collaborative scheduling guidance is performed to construct a unified time standard main axis for network-wide collaborative scheduling. Based on the streaming update state, the actual response timestamps, which serve as event timestamps, are imported to obtain deterministic time base information on the occurrence of physical state changes. Based on the timing value of the actual response timestamps, retrieval, extraction, and timing matching are performed in the unified time standard main axis of the network-wide collaborative scheduling. Ideal timing reference nodes are traced and extracted as the expected execution time in the network-wide collaborative scheduling, resulting in a reference timestamp used for alignment and comparison with the actual response timestamps and serving as the main axis support point.

[0040] Based on the two time value inputs, namely the obtained reference timestamp and the actual response timestamp of the streaming update, binary two's complement arithmetic subtraction is performed at a specific sampling instant to obtain the time domain difference value between the actual response timestamp and the reference timestamp. Based on this time domain difference value, real-time calculation is performed to quantify the clock offset degree of the current distributed execution end, and finally the instantaneous deviation value is obtained.

[0041] Based on the instantaneous deviation value and the node's unique identifier, binary message format encapsulation is performed to obtain a timing deviation encapsulated data packet. Based on this timing deviation encapsulated data packet, asynchronous streaming reporting is performed through the reverse network channel to obtain a remote concurrent received data stream. Based on the parsing of this concurrent received data stream by the flow graph processing engine, topological adjacency relationship extraction is performed to obtain a node identifier stream. Based on the arrival time sequence of this node identifier stream, real-time matrix reconstruction is performed in the topology space to obtain the directional error propagation link matrix. Based on the directional error propagation link matrix, relative deviation calculation is performed on node pairs to obtain the relative synchronization deviation state among all network nodes. Based on the node identifier stream, the directional error propagation link matrix, and the relative synchronization deviation state among all network nodes, spatiotemporal mapping and aggregation are performed in the spatial and temporal dimensions to construct a global synchronization error topology used to characterize error correlation.

[0042] Based on the above technical solution, optionally, dynamic time-domain difference tracing calculation is performed based on the actual response timestamp and the reference timestamp extracted from the preset time reference sequence to obtain the instantaneous deviation value. Then, based on the instantaneous deviation value, time-series deviation encapsulation and asynchronous streaming reporting via the reverse network channel are performed to obtain a dynamically updated global synchronization error topology, including: Based on the actual response timestamp and the reference timestamp extracted from the preset time reference sequence, time reference alignment and time domain difference calculation are performed to obtain the time axis instantaneous difference. Based on the instantaneous difference value of the time axis, multi-cycle time-domain deviation is traced backward to obtain the instantaneous deviation value; Based on the instantaneous deviation value, timing deviation encapsulation and network protocol packaging are performed to obtain timing deviation data packets; Based on the time-series deviation data packets associated with the reverse network channel, asynchronous streaming reporting and topology node mapping are performed to obtain a dynamically updated global synchronization error topology.

[0043] In this scheme, the time axis, i.e., the time difference, is the transient time-domain deviation after directly subtracting the actual response timestamp from the reference timestamp on a unified time axis. It represents the initial time-series deviation between the ideal trigger time and the actual trigger time at a single time node and serves as the basic input parameter for subsequent multi-cycle deviation reverse tracing.

[0044] Timing deviation data packets are standardized transmission units encapsulated based on instantaneous deviation values. They include instantaneous deviation values, node identification identifiers, timing synchronization confidence parameters, and timestamp-associated check codes, and are used to achieve structured and highly reliable transmission of timing error information in distributed networks.

[0045] The reverse network channel is a dedicated communication path in a distributed control network used for data flow back transmission. It encompasses logically asynchronous bidirectional link resources from the distributed execution end to the main control loop, a dedicated data transmission time slot allocation strategy, and a communication flow control mechanism. It is dedicated to the reporting of network-wide synchronization error information and end-point status monitoring data.

[0046] The actual response timestamp of the distributed execution end is obtained, and a preset time base sequence is read simultaneously. In this process, the preset time base sequence is first parsed, and its included target trigger timing sequence, expected interaction time node matrix, and theoretical processing trajectory execution timing sequence are loaded into a cache. Using a pointer addressing retrieval algorithm, based on the current processing stage index, the corresponding ideal timing reference node is retrieved and extracted from the target trigger timing sequence, expected interaction time node matrix, and theoretical processing trajectory execution timing sequence, and established as the base timestamp. The actual response timestamp, captured by the front-end hardware circuit as a data tag for the physical event trigger moment, is latched with the base timestamp within the same clock cycle to complete time base alignment. Subsequently, time domain difference calculation is performed. On a unified system base time axis, fixed-point subtraction is used to directly subtract the base timestamp value from the actual response timestamp value, outputting the transient time domain deviation between the two, thus obtaining the time axis instantaneous difference value.

[0047] The generated time axis instantaneous difference is input into a multi-stage shift register, which continuously stores historical difference data from multiple sampling periods on the time axis. Historical deviation backtracking is performed, using backward differential operations to trace back along the register chain of the shift register to the historical period. During this process, through sliding window accumulation and iterative elimination, the reference frequency drift and transient jitter caused by kernel scheduling in the historical difference sequence are separated and suppressed, thereby filtering out nondeterministic noise and isolating the deterministic deviation caused by clock accumulation at a specific sampling instant. This quantifies the clock offset degree of the current distributed execution end, yielding the instantaneous deviation value.

[0048] The obtained instantaneous deviation value is used as the instantaneous deviation numerical value and encapsulated in a data structure with the node identity identifier formed by the hardware signature code stored in the fixed memory. Simultaneously, based on the variance statistics of the difference data within the shift register, the current synchronization quality assessment index is calculated and defined as the timing synchronization confidence parameter. Next, the binary data streams of the instantaneous deviation value, node identity identifier, and timing synchronization confidence parameter are merged and encoded using a hardware-level cyclic redundancy check (CRC) algorithm to generate the corresponding timestamp-associated checksum. Finally, timing deviation encapsulation and network protocol packaging are performed, assembling the instantaneous deviation value, node identity identifier, timing synchronization confidence parameter, and timestamp-associated checksum into the data payload and frame trailer according to the standard frame structure of industrial Ethernet, resulting in a timing deviation data packet.

[0049] The generated timing deviation data packets are associated with the reverse network channel. Under the pre-configured dedicated data transmission time slot allocation strategy of the reverse network channel, the timing deviation data packets follow the token scheduling regularization of the communication flow control mechanism and are asynchronously streamed through an asynchronous bidirectional logical link. After receiving the serial data stream, the master control end performs a depacketization operation, continuously extracting the identity information of each node from the frame header to form a node identification stream. Then, topology node mapping is performed, filling the node identification stream and the instantaneous deviation values ​​in the timing deviation data packets into the dynamic graph adjacency matrix. By calculating the error propagation vector between adjacent nodes, the directional error propagation link matrix is ​​updated in real time. Based on this, the entire network graph structure is traversed, and the relative synchronization deviation state between all network nodes is calculated, finally obtaining the global synchronization error topology that characterizes the error correlation between all cooperating nodes in the distributed network in the spatial and temporal dimensions. Among them, the pre-configured dedicated data transmission time slot allocation strategy is a deterministic bandwidth management mechanism based on the time division multiple access principle in the distributed network. This strategy predefines the time slot allocation scheme within the network cycle using a static scheduling table, dividing the total network transmission cycle into multiple mutually exclusive time windows, each reserving and allocating a unique transmission time slot to each distributed execution endpoint. During operation, each node strictly adheres to the preset time slice for data reporting, avoiding conflicts and contention-based delays caused by carrier-sensing multi-access.

[0050] In this scheme, clock jitter is suppressed by multi-cycle timing backtracking, and communication conflicts are eliminated by deterministic time slot reporting, thereby achieving high-precision real-time synchronization and dynamic error topology perception of all network collaborative nodes.

[0051] S103, based on the global synchronization error topology, performs cross-cycle time-series rolling frequency domain feature extraction and dynamic separation of DC trend terms based on a preset sliding window to obtain the real-time updated network transmission jitter sequence and the device inherent time delay component sequence.

[0052] A preset sliding window is a pre-configured data truncation boundary architecture in discrete time domain signal processing, used to extract continuous synchronization error data within a specific time period. It serves as a local time metric boundary for time-series rolling frequency domain feature extraction, including window sample length, sliding step interval, and data overlap coefficient.

[0053] Network transmission jitter sequence is a discrete time sequence that characterizes the high-frequency random fluctuations in network transmission delay. It is used to quantify the timing distortion caused by nondeterministic network channel disturbances, including deterministic bounded jitter components, random high-frequency jitter components, and periodic parasitic jitter components.

[0054] The device-inherent latency component sequence is a DC trend term or an extremely low-frequency discrete time series that characterizes the deterministic latency of the underlying hardware circuitry and kernel scheduling of the distributed execution terminal. It is used to quantify the inherent absolute processing latency of the hardware platform, including physical medium propagation latency, internal hardware bus transmission overhead, and deterministic blocking latency of system kernel scheduling.

[0055] Based on a global synchronization error topology using network-wide collaborative scheduling, relative synchronization deviation data among collaborative nodes is obtained. According to the window sample length, sliding step interval, and data overlap coefficient defined by a pre-configured data truncation boundary architecture used in discrete-time signal processing to extract continuous synchronization error data within a specific time period, and serving as the local time metric boundary for time-series rolling frequency domain feature extraction, temporal segmentation is performed on this continuous relative synchronization deviation. Through index offset calculation, the relative synchronization deviation data sequence is converted into a set of interrelated overlapping segmented synchronization deviation sequences, ensuring the temporal continuity of the data during rolling processing, and thus constructing the computational foundation for subsequent feature extraction and component decomposition.

[0056] The overlapping segmented synchronization deviation sequence is acquired and subjected to finite impulse response low-pass filtering to achieve detrending processing and DC offset suppression of the data. During this process, a preset filter coefficient sequence is loaded, and discrete convolution is performed between the input overlapping segmented synchronization deviation sequence and the filter coefficient sequence to eliminate high-frequency noise caused by reference frequency offset in the data sequence. By configuring the cutoff frequency, high-frequency interference components in the overlapping segmented synchronization deviation sequence are filtered out, separating the component representing the low-frequency trend. Based on the separated low-frequency trend component, delay component decomposition and attribution analysis are performed to map amplitude fluctuations to the underlying hardware characteristic space of the distributed execution terminal. By calculating the physical medium propagation delay, internal hardware bus transmission overhead, and deterministic blocking delay of the system kernel scheduling, a weighted component solution is performed on the total delay to finally obtain the DC trend term or extremely low-frequency discrete time sequence, which serves as the basis for representing the deterministic time consumption of the underlying hardware circuitry and kernel scheduling of the distributed execution terminal. This is used to quantify the device-inherent delay component sequence of the absolute processing latency inherent in the hardware platform. The preset filter coefficient sequence is a set of discrete weighted parameters that characterize the unit impulse response of the finite impulse response filter. It is represented by a set of one-dimensional numerical arrays that are pre-calculated and stored. These arrays are used to scale and superimpose the tap delay components of the input overlapping segmented synchronization deviation sequence during the discrete convolution process, thereby determining the cutoff frequency and stopband attenuation characteristics of the filter.

[0057] The overlapping segmented synchronization deviation sequence is obtained, and frequency domain feature extraction is performed simultaneously using short-time Fourier transform (SFT) while detrending the sequence. By applying a Hanning window or Blackman window function to the data points within a preset sliding window, spectral leakage effects are suppressed. A discrete Fourier transform is then performed on the discrete data sequence within the window to transform the time-domain data to the frequency domain. Based on the power spectral density spectrum calculated using SFT, frequency domain intervals are divided into random jitter bands and deterministic jitter bands. Within the random jitter band, random high-frequency jitter components are extracted using noise power integration; within the deterministic jitter band, periodic parasitic jitter components and deterministic bounded jitter components are separated through spectral peak detection and amplitude analysis. Based on the extracted jitter components, an inverse fast Fourier transform is performed to reconstruct the frequency domain signal back into the time domain. The DC component and low-frequency trend are removed, and finally, a discrete time series characterizing the high-frequency random fluctuations of network transmission delay is calculated. This is used to quantify the real-time updated network transmission jitter sequence caused by nondeterministic network channel disturbances.

[0058] Based on the above technical solution, optionally, based on the global synchronization error topology, cross-cycle time-series rolling frequency domain feature extraction and dynamic separation of DC trend terms are performed using a preset sliding window to obtain a real-time updated network transmission jitter sequence and a device inherent delay component sequence, including: Based on the global synchronization error topology, a time-series rolling topology matrix is ​​obtained by performing a sliding slice of the topology data section based on a preset sliding window; Based on the time-series rolling topology matrix, cross-cycle time-series rolling frequency domain feature extraction is performed to obtain the error frequency domain feature spectrum; Dynamic separation of the DC trend term is performed based on the error frequency domain characteristic spectrum to obtain the device's inherent time delay component sequence; By stripping alternating signal components based on the error frequency domain characteristic spectrum and the device's inherent time delay component sequence, a real-time updated network transmission jitter sequence is obtained.

[0059] In this scheme, the time-series rolling topology matrix is ​​a multi-dimensional time-series feature array formed by the serialization and stacking of the global synchronization error topology along the time axis within the preset sliding window truncation boundary. It is used to carry the evolution trajectory of the spatial and temporal error correlation of the entire network collaborative nodes within the local time scale, including the time-domain discrete node state vector sequence, the time-varying matrix group of directional error propagation links within the sliding window, and the set of relative synchronization deviation snapshots of each slice section.

[0060] Error frequency domain characteristic spectrum is a deterministic multidimensional distribution spectrum that characterizes the dynamic evolution characteristics of errors contained in the time-series rolling topology matrix in the discrete frequency domain space, representing the energy distribution and frequency component structure. It is used to decouple and quantify the synchronization deviation law of all network nodes in the frequency domain, including zero-frequency DC trend component, high-frequency alternating harmonic energy distribution, specific periodic parasitic frequency characteristics, and error power spectral density matrix of each node.

[0061] The system acquires the real-time generated global synchronization error topology and continuously writes its node identifier stream, directional error propagation link matrix, and relative synchronization deviation states among all network nodes into a circular high-speed data buffer. Based on a pre-configured sliding window with a pre-defined window sample length, sliding step interval, and data overlap coefficient, it performs sliding slicing of the topology data sections. During this process, it utilizes memory pointer step-shifting to segment continuous topology data sections in the discrete time domain according to the window sample length and data overlap coefficient. The segmented node identifier stream is time-series converted to reconstruct a discrete node state vector sequence in the time domain. The continuously segmented directional error propagation link matrices are time-series combined and stacked to reconstruct a time-varying matrix group of directional error propagation links within the sliding window. Finally, the relative synchronization deviation states among all network nodes are discretely extracted and reconstructed into a set of relative synchronization deviation snapshots for each slice section. Finally, within the local time metric boundary of the preset sliding window, the time-domain discrete node state vector sequence, the time-varying matrix group of the directional error propagation link within the sliding window, and the set of relative synchronization deviation snapshots of each slice section are integrated in a multi-dimensional feature space to obtain the time-series rolling topology matrix.

[0062] The generated time-series rolling topology matrix is ​​read, and its contained time-domain discrete node state vector sequences, the time-varying matrix group of directional error propagation links within the sliding window, and the set of relative synchronization deviation snapshots for each slice section are loaded into the complex data storage area. Cross-cycle time-series rolling frequency domain feature extraction is performed based on the time-series rolling topology matrix. In this process, the discrete node state vector sequence in the time domain is first subjected to Hanning window weighting, and the amplitude is smoothed by point-by-point multiplication to suppress spectral leakage. Then, the fast Fourier transform algorithm is used to run a one-dimensional discrete Fourier transform on the time-varying matrix group of the directional error propagation link and the set of relative synchronization deviation snapshots within the sliding time window along the time axis, projecting the time domain data into the discrete frequency domain space. Subsequently, the energy distribution at each frequency point is extracted using the periodogram calculation method of power spectral density estimation, and the error power spectral density matrix of each node is reconstructed. Finally, from the reconstructed discrete frequency domain energy components, the zero-frequency DC trend component at the zero frequency of the energy spectrum, the high-frequency alternating harmonic energy distribution in the alternating frequency band, and the specific periodic parasitic frequency characteristics at specific spurious frequency points are decoupled and extracted. The zero-frequency DC trend component, the high-frequency alternating harmonic energy distribution, the specific periodic parasitic frequency characteristics, and the error power spectral density matrix of each node are subjected to multi-dimensional feature mapping to obtain the error frequency domain feature spectrum.

[0063] The generated error frequency domain feature spectrum is read, and its zero-frequency DC trend component, high-frequency alternating harmonic energy distribution, specific periodic parasitic frequency characteristics, and error power spectral density matrix of each node are identified and extracted. Dynamic separation of the DC trend term is performed based on the error frequency domain feature spectrum. In this process, baseband zero-frequency component isolation extraction technology is used to directly retrieve and filter the DC components with corresponding frequencies of zero in the error power spectral density matrix of each node, separating them from the entire spectrum to establish the zero-frequency DC trend component. Then, an inverse fast Fourier transform is performed on this zero-frequency DC trend component, inversely transforming it from the discrete frequency domain space back to the discrete time domain, reconstructing it into a low-frequency discrete time series. This low-frequency discrete time series in the time domain consists of the linear accumulation of physical medium propagation delay, internal hardware bus transmission overhead, and deterministic blocking delay of the system kernel scheduling, used to quantify the deterministic time consumption basis of the underlying hardware circuitry and kernel scheduling of the distributed execution endpoint, obtaining the device's inherent time delay component sequence.

[0064] The generated error frequency domain feature spectrum is correlated with the device's inherent time delay component sequence. Alternating signal components are then stripped based on the error frequency domain feature spectrum and the device's inherent time delay component sequence. In this process, within the discrete frequency domain, the zero-frequency DC trend component corresponding to the inherent time delay component sequence of the device is subtracted from the power spectral density matrix of each node error using spectral subtraction techniques. This strips away the absolute delay component of the substrate, leaving the alternating signal component containing the high-frequency alternating harmonic energy distribution and specific periodic parasitic frequency characteristics. Next, a frequency domain sub-band energy filtering algorithm is used to decouple the high-frequency alternating harmonic energy distribution and specific periodic parasitic frequency characteristics according to frequency band attributes. The inverse fast Fourier transform is then performed on the decoupled frequency domain data stream to convert it into a high-frequency discrete time series in the time domain. Finally, based on the statistical fluctuation characteristics and periodicity of the time domain signal, the jitter component is decomposed and precisely separated into deterministic bounded jitter components that satisfy the prediction boundary, random high-frequency jitter components that satisfy the high-frequency noise characteristics, and periodic parasitic jitter components caused by specific periodic parasitic frequency characteristics. These components are used to quantify the time-series distortion caused by nondeterministic network channel disturbances, ultimately obtaining a discrete time series characterizing the high-frequency random fluctuations of network transmission delay, i.e., a real-time updated network transmission jitter sequence.

[0065] In this solution, the inherent latency and transmission jitter are dynamically separated, and the deterministic timing characteristics of the network are accurately quantified, which effectively improves the accuracy of network-wide collaborative control and hard real-time synchronization performance under complex distributed architecture.

[0066] S104, based on the inherent time delay component sequence of the device, performs feedforward trend rolling extrapolation and feedforward compensation prediction in the main control loop of the main control terminal to obtain the rolling updated corrected synchronization timestamp.

[0067] The master control unit is the core logical unit in a distributed system responsible for global timing management, collaborative strategy scheduling, and clock base publication. As a reference source for the system synchronization architecture, it includes a central time base controller, a topology mapping management module, a collaborative control scheduling decision engine, and system configuration and status monitoring interfaces.

[0068] The main control loop is the logical control link that realizes the closed-loop regulation and error compensation of the distributed system state. It is responsible for integrating the real-time network delay and the inherent deviation of the equipment and generating the compensation control flow. It includes an error information input processing interface, a feedforward extrapolation compensation calculation unit, a control command timing alignment circuit, and a system response state feedback channel.

[0069] The corrected synchronization timestamp is a precise aligned time reference value obtained after compensation for the inherent delay components of the device and feedforward trend prediction. It is used to eliminate the impact of network jitter and hardware physical delay and serves as the final instruction basis for executing node synchronization actions. It includes the time value, the time reference alignment deviation, and the synchronization confidence status flag.

[0070] The system analyzes the device's inherent delay component sequence, consisting of physical medium propagation delay, bus transmission delay, and kernel scheduling delay, stored in the configuration and status monitoring interface. This sequence is then integrated with the spatial node association relationships representing the three-dimensional spatial distribution, topology, and data flow direction of each physical or logical node, forming a multivariate delay matrix with spatial topological characteristics. This delay matrix is ​​used as the initial stimulus and input to the error information input processing interface of the main control loop. In the input processing flow, a discrete sequence sliding window buffer mechanism is used to queue and store the continuously input multivariate delay matrix along the time axis in multiple frames, establishing a continuously rolling data pipeline. This transforms the spatial topology matrix stream into a historical sequence with temporal continuity. Based on this, temporal outlier detection is performed. Outliers are removed by calculating the time series statistical boundaries of each matrix element within the sliding window, eliminating nondeterministic transient scheduling spikes, smoothing and denoising the original data, and extracting the deterministic delay core determined solely by the hardware's inherent characteristics as a control benchmark. Finally, a standardized delay benchmark historical sequence with high reliability is output.

[0071] The standardized latency benchmark historical sequence is obtained and passed to the feedforward trend rolling extrapolation process. To achieve accurate prediction of latency evolution, linear least squares fitting calculation based on the least squares principle is performed on the standardized latency benchmark historical sequence. In this calculation step, the first derivative, which represents the overall trend of latency change over time, and the intercept at time zero are dynamically determined by solving the normal equation system, thereby constructing a deterministic linear evolution trajectory. Subsequently, a step-size extrapolation mechanism is introduced along the positive time axis. The obtained first derivative and intercept are used as the core parameters of the extrapolation operator to perform linear extrapolation to future time nodes, thereby calculating the rolling extrapolated latency prediction value corresponding to a specific future execution cycle, providing a forward-looking latency quantification index for subsequent feedforward compensation.

[0072] The system captures a reference clock source published by the central time base controller. The absolute time base of this reference clock source, along with the calculated rolling extrapolated delay prediction, is introduced into the collaborative control scheduling decision-making process. Feedforward compensation prediction is then performed to generate a rollingly updated corrected synchronization timestamp. First, a subtraction operation for delay reversal compensation is performed. The original time data from the reference clock source is algebraically subtracted from the rolling extrapolated delay prediction, advancing the clock phase forward on the time axis. This completely eliminates phase lag caused by the distributed underlying physical network and hardware scheduling, generating a precisely aligned time value that meets the requirements of spatiotemporal consistency. Second, dynamic variance calculation is performed on the prediction residual between the rolling extrapolated delay prediction and the standardized delay base historical sequence. The divergence and random fluctuation range of the prediction algorithm are quantified in real time by solving for the second moment in statistics, resulting in the calculated extended uncertainty index characterizing the time axis alignment accuracy, i.e., the time base alignment deviation. Subsequently, the time base alignment deviation is compared with a pre-configured confidence threshold. If the alignment deviation remains within the threshold, it is determined to be a high-reliability state. Then, a Boolean synchronization confidence status flag bit is generated to indicate the synchronization reliability rating through logical judgment. Finally, the precisely aligned time value, time base alignment deviation, and synchronization confidence status flag bit generated above are encapsulated in a data structure to output the final rolling update corrected synchronization timestamp.

[0073] S105, sample the network transmission jitter sequence in real time to capture the instantaneous value of the current network transmission jitter, dynamically and instantly rewrite the time base parameters of the network control node based on the instantaneous value of the current network transmission jitter, and finely adjust the step pulse of the time counting sequence in real time to obtain the target drive control data refreshed frame by frame.

[0074] The instantaneous value of current network transmission jitter is a single-point scalar value extracted from the network transmission jitter sequence at a specific discrete sampling time. It is used to qualitatively and quantitatively characterize the amplitude and polarity direction of the instantaneous timing deviation caused by nondeterministic network channel disturbances within the current control cycle.

[0075] A network control node is a physical entity or logical unit deployed at the execution end in a distributed control network. It has independent computing, communication, and local timing adjustment capabilities. It is responsible for receiving global coordination instructions and outputting physical drive signals locally. It includes network communication interface circuits, local hardware timers and counters, clock synchronization adjustment engines, and control instruction generation units.

[0076] The time base parameters are a set of core configuration items that determine the counting behavior of the local timer and counter of the network control node and the clock evolution rate. They are used to quantify and establish the physical properties of the local time reference axis at the underlying register level, including the clock division factor, the timer auto-reload value, the local clock phase offset correction amount, and the expected value of the time base period.

[0077] A step pulse is a discrete periodic pulse signal that triggers the local hardware time counting sequence to perform discrete incremental operations or drives the end effector to perform high-precision step displacement. Its time interval and trigger edge directly determine the counting resolution of the local clock, the timing evolution rate, and the action rhythm of the actuator.

[0078] Target-driven control data is a deterministic structured instruction data frame generated after real-time timing deviation compensation and instant rewriting of time base parameters. It is used to directly control the end effector to complete high-precision coordinated actions. As the final basis for the precise execution of actions in the physical world, it includes the physical quantity of the target moving by the actuator, the timestamp of the action triggering target, the node status identifier, and the communication verification sequence.

[0079] At the real-time communication interface of the distributed control network, interrupt-driven sampling technology triggered by hardware timer interrupts is used to periodically capture the network transmission jitter sequence, which characterizes the high-frequency random fluctuations in network transmission delay. Based on the captured network data stream, data frame parsing and scalar extraction are performed. The jitter dataset, which is dynamically superimposed from deterministic bounded jitter components, random jitter, and periodic jitter, is separated from the current data frame. Then, a single-point scalar value is extracted as a segment from the network transmission jitter sequence at a specific discrete sampling moment. This value is used to qualitatively and quantitatively characterize the instantaneous value of the network transmission jitter, which is caused by the amplitude and polarity of the instantaneous timing deviation due to nondeterministic network channel disturbances within the current control cycle. This instantaneous value is then directly input into the subsequent digital computation pipeline as a quantitative feedback benchmark for network timing adjustment.

[0080] The instantaneous value of the current network transmission jitter obtained above is input into the arithmetic logic unit of the local clock synchronization adjustment engine. Inside the unit, the sign of the input data is inverted, and a phase and frequency deviation correction amount is calculated to offset channel delay fluctuations. Based on this phase and frequency deviation correction amount, dynamic clock parameter reconfiguration is performed on the register group of the network control node, which consists of the network communication interface circuit, local hardware timer / counter, clock synchronization adjustment engine, and control command generation unit. This involves rewriting the core configuration item set that determines the counting behavior of the local timer / counter and the clock evolution rate of the network control node, quantifying and establishing the time base parameters of the local time reference axis's physical attributes at the underlying register level. Specifically, the frequency compensation component in the phase and frequency deviation correction amount is directly loaded into the clock management unit, adjusting the clock division coefficient in real time; simultaneously, the timer auto-reload value is updated to adjust the timing period, and the phase compensation component is input into the addition circuit of the expected time base period value to dynamically correct the local clock phase offset correction amount. By rewriting these specific register parameters, the physical evolution rate of the local time base is re-established at the logic configuration level, achieving dynamic alignment between the local clock reference and global synchronization requirements.

[0081] Based on the rewritten time base parameters, the output comparison logic of the local hardware timer / counter is dynamically adjusted, thereby directly intervening in and fine-tuning the step pulses that trigger the discrete incremental operation of the local hardware time counting sequence or drive the end effector to perform high-precision step displacement. Specifically, the steps are as follows: Based on the updated timer auto-reload value and the local clock phase offset correction, the comparison matching register threshold of the local hardware timer / counter is dynamically modified. The current period of the pulse sequence is changed by shortening or lengthening the trigger interval between adjacent pulses, and the trigger edge phase of the pulse signal is precisely calibrated to keep the frequency adjustment rate of the pulse sequence synchronized with the desired time base period. At this point, the dynamically adjusted step pulses serve as the clock source for the incremental counting of the local counter value sequence. Their time interval and trigger edge directly determine the counting resolution, timing evolution rate, and action rhythm of the local clock, directly constraining the response timing of subsequent actions of the end effector.

[0082] The control commands, which serve as the physical quantity of the actuator's motion target, are time-mapped and bound to the action trigger target timestamp after compensation via step pulse drive clock. During this framing process, the physical quantity of the actuator's motion target and the corresponding action trigger target timestamp are concatenated, and the node status identifier uploaded by the network control node is acquired in real time for multi-field fusion. Subsequently, a cyclic redundancy check (CRC) calculation is performed on the concatenated data stream, generating and appending a checksum as a communication verification sequence to the end of the command frame. Through protocol layer data encapsulation, a deterministic structured command data frame is finally obtained, which is generated after real-time timing deviation compensation and instant rewriting of time base parameters. This frame is used to directly control the end actuator to complete high-precision coordinated actions, and serves as the final basis for precise execution of actions in the physical world—a frame-by-frame updated target-driven control data.

[0083] Based on the above technical solution, optionally, the network transmission jitter sequence is sampled in real time to capture the instantaneous value of the current network transmission jitter. The time base parameters of the network control node are dynamically and instantly rewritten based on the instantaneous value of the current network transmission jitter, and the step pulse of the time counting sequence is finely adjusted in real time to obtain frame-by-frame refreshed target drive control data, including: Based on the network transmission jitter sequence, real-time sampling and discrete extraction of hardware latch state are performed to obtain the instantaneous value of the current network transmission jitter; Based on the instantaneous value of the current network transmission jitter, the underlying control word of the network control node is physically rewritten to dynamically and instantly rewrite the time base parameters of the network control node and obtain time base rewriting feature data. Based on the time base rewriting characteristic data and the instantaneous value of current network transmission jitter, the gated clock phase correction of the time counting sequence is performed and the step pulse of the time counting sequence is finely adjusted in real time to obtain the target drive control data refreshed frame by frame.

[0084] In this scheme, the time base rewrite feature data is a multi-dimensional structured dataset that characterizes the real-time changes in the configuration status of the local timer / counter register after the underlying control word of the network control node has been physically rewritten. It is used to map and lock the dynamic reconstruction results of the time base parameters at the underlying level, and to provide a direct data flow basis for the gated clock phase correction and step pulse fine-tuning of the time counting sequence. This includes the physical writing status word of the register, the clock division and automatic reload update value, the dynamic adjustment deviation of the time base period, and the timing change effective boundary identifier.

[0085] A network transmission jitter sequence, characterizing high-frequency random fluctuations in network transmission delay, is introduced into the sampling latch link. This sequence is composed of deterministic bounded jitter components, random high-frequency jitter components, and periodic parasitic jitter components at the underlying level. Edge-triggered sampling is used to perform clock-synchronized sampling of the network transmission jitter sequence at specific discrete sampling moments. Simultaneously, a latch enable control signal is sent to the latch to perform state latching, storing the current level state in the data register. This qualitatively and quantitatively characterizes the amplitude and polarity direction of the instantaneous timing deviation caused by nondeterministic network channel disturbances within the current control cycle, capturing a single-point scalar value, which is then established as the instantaneous value of the current network transmission jitter.

[0086] The generated instantaneous value of current network transmission jitter is loaded into the underlying register configuration bus of the network control node, which integrates network communication interface circuitry, local hardware timer / counter, clock synchronization adjustment engine, and control command generation unit. Using fixed-point inversion and shift accumulation, the instantaneous timing deviation amplitude and polarity direction contained in the current instantaneous value of network transmission jitter are converted into a guaranteed adjustment vector for the time base parameters. These time base parameters are composed of clock division coefficients, timer auto-reload values, local clock phase offset corrections, and the expected value of the time base period. Register configuration updates are executed using direct memory access control instructions, writing the updated data into the configuration register to dynamically update the time base parameters of the network control node. During the hardware cycle when the configuration takes effect, the hardware status bus instantly reads and generates the register physical write status word, clock division and auto-reload update values, and the dynamic adjustment deviation of the time base period. Simultaneously, the timer update event trigger signal establishes the timing change effective boundary marker, quantifies and establishes the physical attributes of the local time reference axis at the underlying register level, and assembles the time base rewrite characteristic data.

[0087] The generated time base rewrite feature data and the instantaneous value of current network transmission jitter are introduced into the control link of the local hardware timer / counter. The register physical write status word, clock division and auto-reload update value, time base period dynamic adjustment deviation, and timing change effective boundary marker contained in the time base rewrite feature data are extracted. Using digital phase-locked loop phase adjustment and glitch-free gating of the gated clock, at the timing effective flag specified by the timing change effective boundary marker, combined with the amplitude and polarity of the instantaneous value of current network transmission jitter, the gated clock phase correction of the time counting sequence is performed on the local hardware timer / counter. Simultaneously, programmable fractional division, reference clock division and auto-reload update value, and time base period dynamic adjustment deviation are used to fine-tune the step pulse period, thereby fine-tuning the step pulse of the time counting sequence in real time to directly determine the counting resolution of the local clock, the timing evolution rate, and the action rhythm of the actuator. After the timing adjustment is completed, the control command generation unit receives the global coordination command input from the network communication interface circuit. Using data frame encapsulation technology and cyclic redundancy check algorithm, it structures and packages the physical quantity of the actuator's motion target, the corrected and aligned action trigger target timestamp, node status identifier, and communication verification sequence as the final basis for the precise execution of actions in the physical world, and obtains the target drive control data refreshed frame by frame.

[0088] In this scheme, by capturing network jitter in real time and dynamically calibrating the time base parameters, the mechanism can accurately eliminate the impact of random channel disturbances on timing, ensure the absolute consistency of pulse output of distributed end nodes, and thus achieve high-precision motion synchronization control.

[0089] S106, based on the target-driven control data, controls the network control node to perform real-time comparison between the local clock and the corrected synchronization timestamp, and when the local clock reaches the corrected synchronization timestamp, drives the distributed execution end to perform spatial collaborative cladding forming to obtain the formed additive manufacturing component.

[0090] Molded additive manufacturing components are physical entities with pre-set complex geometric shapes that are solidified in three-dimensional space by distributed execution terminals in a spatial collaborative additive manufacturing system. As the final physical carrier of the spatial synergy between multi-axis control commands and cladding physical fields, they include a base part for support and bearing, cladding feature bodies stacked in multiple layers according to a pre-set spatial trajectory, geometric surfaces characterizing the accuracy of the linkage trajectory, and metallurgical interfaces that tightly bond each cladding layer to the base.

[0091] This scheme operates under the guidance of the spatial motion trajectory defined in the drawings of the component to be printed. The network control node uses its internal network communication interface circuit to capture target drive control data and parses the data frame at the hardware bus level, completely separating the physical quantities of the actuator's motion target, the action triggering target timestamp, the node status identifier, and the communication verification sequence. The network control node uses its dedicated hardware logic circuit to perform cyclic redundancy check (CRC) calculation on the separated data stream, and performs consistency verification between the generated verification result and the communication verification sequence to determine data integrity. Simultaneously, the network control node performs legality verification on the node status identifier. After successful verification, the network control node maps the action triggering target timestamp to a corrected synchronization timestamp, performs unpacking operations, and extracts the time value, time base alignment deviation, and synchronization confidence status flag, temporarily storing them in a local register as the timing base for subsequent comparisons by the network control node.

[0092] The network control node, based on the hardware clock reference established by the clock synchronization adjustment engine, reads the current count value of the local hardware timer / counter in real time at a defined counting period and compares it with a temporarily stored corrected synchronization timestamp using a digital comparator. The network control node uses hardware latching logic to detect the valid status of the synchronization confidence flag, converts the time reference alignment deviation into a time window threshold, and inputs it to the comparator threshold input of the digital comparator. The network control node drives the local hardware timer / counter to perform a subtraction operation between the current count value and the time value, controlling the local hardware timer / counter to count down until a match is found. When the difference reaches the zero threshold, the network control node drives the digital comparator to output a hardware trigger pulse signal to the next stage circuit.

[0093] The network control node captures the hardware trigger pulse signal through the control command generation unit, controls the internal latching circuit to instantaneously latch the physical quantity of the moving target of the aforementioned actuator, and drives the hardware multi-axis interpolator to perform trajectory mapping. Based on the position and velocity commands output by the hardware multi-axis interpolator, the network control node converts them into multi-axis pulse commands and power control signals, and drives the output circuit to directly output these timing-aligned drive signals to the input of the distributed execution end, establishing an interlocking control mechanism between the network control node's time comparison and the triggering of the end's physical action.

[0094] The network control node drives the distributed execution terminal to receive the multi-axis pulse commands and power control signals, and controls the matching motion drive components inside the distributed execution terminal to perform closed-loop control of the current loop and speed loop, driving the multi-axis linkage control component to perform multi-axis linkage motion along a preset spatial trajectory. The network control node coordinates the forming operation component to respond to the power control signal, driving the laser cladding system to synchronously apply the laser beam and powder material to the substrate used for support, resulting in a laser molten pool. Based on the trajectory movement of the multi-axis linkage control component, the network control node controls the laser molten pool to continuously solidify on the substrate and perform layer-by-layer deposition, forming a multi-layered cladding feature body stacked according to a preset spatial trajectory. As the multi-layer deposition and forming process continues, the network control node controls the multi-layered cladding body to solidify and form a structural component with a preset complex geometry, giving it a geometric surface that characterizes the accuracy of the linkage trajectory, and internally constructing a metallurgical interface that tightly bonds each cladding layer to the substrate, ultimately obtaining a formed additive manufacturing component.

[0095] In this embodiment, by using timing feedforward compensation and dynamic time base fine-tuning, network jitter and inherent hardware latency are eliminated, distributed multi-node deterministic synchronization is achieved, ensuring high-precision multi-axis linkage at the end and significantly improving the forming quality of additive manufacturing components.

[0096] Based on the above technical solution, optionally, based on target-driven control data, the control network control node performs real-time comparison between the local clock and the corrected synchronization timestamp, and when the local clock reaches the corrected synchronization timestamp, drives the distributed execution end to perform spatial collaborative cladding forming to obtain a shaped additive manufacturing component, including: Based on the target-driven control data and the corrected synchronization timestamp, the control network control node performs real-time comparison of the local clock and the corrected synchronization timestamp and digital coincidence logic determination to obtain the local clock comparison feature value. Based on the local clock comparison feature value, when the local clock reaches the corrected synchronization timestamp, the gated hardware interrupt capture and trigger level latch are executed to obtain the instantaneous synchronization drive signal. Based on real-time synchronous drive signals, distributed execution end-effectors are driven to perform spatial collaborative cladding forming to obtain shaped additive manufacturing components.

[0097] In this scheme, the local clock comparison feature value is a multi-dimensional digital state quantity that characterizes the quantization deviation and logical coincidence state between the current count value of the local hardware timer counter of the network control node and the time value within the correction synchronization timestamp. It is used to quantify the approximation degree between the local timing and the global reference in real time at the underlying logic circuit level, providing an accurate digital closed-loop basis for gating hardware interrupt capture. It includes the absolute deviation of the clock count, the count logic coincidence flag, the delay evolution leading lag indicator, and the validity check bit of the judgment result.

[0098] The instantaneous synchronization drive signal is a time-domain physical pulse signal with deterministic response, directly output by the hardware interrupt-level circuit at the instant when the local clock and the corrected synchronization timestamp are completely consistent. It is used to seamlessly connect the physical quantity of the actuator motion target in the target drive control data at the physical level, and directly drive the distributed execution end to perform high-precision spatial collaborative operations. It includes the pulse leading edge transition type, effective level maintenance width, drive output current amplitude, and execution channel physical mapping word.

[0099] The unpacked target-driven control data and the corrected synchronization timestamp are introduced into the network control node, which consists of a network communication interface circuit, a local hardware timer / counter, a clock synchronization adjustment engine, and a control command generation unit. The local hardware timer / counter executes high-speed local clock counting to generate the current count value. A digital logic comparator compares this current count value with the time value contained in the corrected synchronization timestamp, and controls the network control node to perform real-time comparison between the local clock and the corrected synchronization timestamp, referencing the time base alignment deviation. A binary subtractor calculates the difference between the current count value and the time value, quantizes it as the absolute clock count deviation, and determines the delay evolution leading lag indicator based on the sign of the difference. When the difference returns to zero, an equality check is performed, and a digital coincidence logic check is executed, controlling the combinational logic gates to directly set the counting logic coincidence flag. The synchronization confidence status flag in the corrected synchronization timestamp, the action trigger target timestamp in the target-driven control data, the node status identifier, and the communication verification sequence are extracted and subjected to parity checking and data integrity verification. The output data validity bit serves as the validity check bit of the judgment result. Finally, the absolute deviation of clock count, the coincidence flag of counting logic, the delay evolution leading lag indicator, and the validity check bit of the judgment result are assembled into a register group to quantify the approximation degree of local timing with the global reference in real time at the underlying logic circuit level, and obtain the local clock comparison feature value.

[0100] The generated local clock comparison feature value is transmitted to the hardware interrupt control link in real time. When the counting logic coincidence flag in the local clock comparison feature value is valid and the validity check bit of the judgment result passes, it indicates that the local clock has reached the corrected synchronization timestamp. Using a gated clock circuit and an edge-detecting flip-flop response register state, gated hardware interrupt capture and trigger level latching are executed, instantly eliminating software scheduling overhead and directly triggering the interrupt service routine to achieve hardware interrupt capture. Immediately afterwards, a bistable flip-flop and peripheral latching circuit are used to perform level latching, forcibly locking the high and low level states to the physical output pin. At this state transition instant, based on the physical quantity of the actuator motion target contained in the target drive control data, the physical mapping word of the execution channel is determined through register addressing, and the power drive circuit is controlled to adjust the drive output current amplitude. Simultaneously, the pulse leading edge transition type is set using the timer hardware comparison output channel, and the effective level maintenance width is precisely controlled using the timer overflow clearing mechanism, outputting a physical pulse with a deterministic response to obtain an instantaneous synchronization drive signal.

[0101] The generated real-time synchronous drive signals are streamed into the distributed execution end, which consists of multi-axis linkage control components, forming operation components, and supporting motion drive components. By utilizing the physical mapping word of the execution channel, the real-time synchronous drive signal is precisely guided to the corresponding matching motion drive component. Relying on the amplitude of the drive output current and the pulse leading edge transition type to trigger the conduction of the high-power semiconductor switch, the multi-axis linkage control component is controlled to perform high-precision synchronous displacement according to the effective level and the specified action beat, driving the distributed execution end to perform spatial collaborative cladding forming. The base part for supporting the load is precisely positioned and firmly established on the geometric surface, and the forming operation component is activated synchronously. The high-energy beam is used to perform laser cladding forming on the sprayed material. During the evolution of the physical field of the molten pool, the interpolation trajectory is controlled to move continuously in three-dimensional space to complete the cladding feature body stacked in multiple layers according to the preset spatial trajectory. During the solidification process of the multi-layer stack, the path deviation is eliminated by microsecond-level synchronous motion, directly constraining and precipitating the geometric surface characterizing the accuracy of the linkage trajectory. Laser remelting is used to promote element interdiffusion and phase transformation of the molten metal between the substrate and adjacent layers, constructing a metallurgical interface with a tight bond between each cladding layer and the substrate. Finally, the physical solid structure with a preset complex geometric morphology is solidified in three-dimensional space to obtain the formed additive manufacturing component.

[0102] In this solution, software overhead is eliminated by capturing hardware interrupts, achieving microsecond-level synchronous control, ensuring precise coordination between trajectory and energy field, and significantly improving the geometric accuracy and metallurgical quality of the formed components.

[0103] Figure 2 This is a second flowchart illustrating the additive manufacturing multi-node synchronous triggering control method based on a unified timestamp provided in this embodiment of the disclosure. The method may include the following steps: S201: Obtain the physical state change signal generated in real time by the distributed execution terminal during the spatial collaborative cladding process. Based on the physical state change signal, perform frame-by-frame feature stream capture and time axis numerical linear transformation to obtain the actual response timestamp of the streaming update.

[0104] S202: Obtain a preset time base sequence; perform dynamic time domain difference tracing calculation based on the actual response timestamp and the base timestamp extracted from the preset time base sequence to obtain the instantaneous deviation value; and based on the instantaneous deviation value, encapsulate the time sequence deviation and asynchronously stream it to the reverse network channel to obtain a dynamically updated global synchronization error topology.

[0105] S203, based on the global synchronization error topology, performs cross-cycle time-series rolling frequency domain feature extraction and dynamic separation of DC trend terms based on a preset sliding window to obtain the real-time updated network transmission jitter sequence and the device inherent time delay component sequence.

[0106] S204, in the main control loop of the main control terminal, based on the inherent time delay component sequence of the device, performs feedforward trend rolling extrapolation and timing multi-order differential numerical approximation to obtain the rolling time delay extrapolation vector.

[0107] S205, in the main control loop of the main control terminal, performs feedforward compensation prediction and algebraic accumulation of cumulative clock drift based on the rolling delay extrapolation vector to obtain the timing feedforward prediction compensation value.

[0108] S206, in the master control loop of the master control terminal, based on the timing feedforward prediction compensation value, performs global clock axis streaming numerical superposition correction to obtain the rolling updated correction synchronization timestamp.

[0109] S207, the network transmission jitter sequence is sampled in real time to capture the instantaneous value of the current network transmission jitter, the time base parameters of the network control node are dynamically and instantly rewritten based on the instantaneous value of the current network transmission jitter, and the step pulse of the time counting sequence is finely adjusted in real time to obtain the target drive control data refreshed frame by frame.

[0110] S208, based on target-driven control data, controls the network control node to perform real-time comparison between the local clock and the corrected synchronization timestamp, and when the local clock reaches the corrected synchronization timestamp, drives the distributed execution end to perform spatial collaborative cladding forming to obtain the formed additive manufacturing component.

[0111] In this embodiment, the rolling delay extrapolation vector is a time-domain discrete numerical array that characterizes the evolution trend of the device's inherent delay component sequence over multiple consecutive control cycles in the future. It is used to quantify the transient slip direction of absolute processing delay and kernel scheduling delay in the main control loop, including future multi-step delay prediction feature values, delay multi-order differential discrete components, and extrapolation trend boundary constraint weights.

[0112] The timing feedforward prediction compensation value is a time-domain integrated feedforward control correction variable that integrates the dynamic evolution trend of time delay and the cumulative time deviation of the system. It serves as the direct data flow basis for the global clock axial-flow numerical superposition correction in the main control loop, including the time delay trend feedforward prediction correction amount, the cumulative clock drift algebraic compensation component, and the feedforward dynamic adjustment control factor.

[0113] The device-inherent delay component sequence, representing the underlying hardware circuitry of the distributed execution terminal and the deterministic time consumption basis of kernel scheduling, is introduced into the master control loop of the master control terminal. This sequence is received at the error information input processing interface and is structurally composed of the linear superposition of physical medium propagation delay, internal hardware bus transmission overhead, and deterministic blocking delay of system kernel scheduling, used to quantify the inherent absolute processing delay of the hardware platform. Rolling extrapolation prediction and high-order differential approximation are performed in the feedforward extrapolation compensation calculation unit: First, a high-order backward difference is run on the device-inherent delay component sequence to calculate the delay change rate between adjacent control cycles, reconstructing it into multi-order differential discrete components of delay; then, trend prediction is performed using Taylor series extrapolation towards multiple future consecutive control cycles to quantify the transient slip direction of absolute processing delay and kernel scheduling delay, outputting future multi-step delay prediction characteristic values; subsequently, a stability constraint factor is calculated using saturation constraint divergence boundaries, establishing it as the extrapolation trend boundary constraint weight. Finally, the generated future multi-step delay prediction feature values, delay multi-order difference discrete components, and extrapolation trend boundary constraint weights are assembled into a discrete numerical array in the time domain space to obtain the rolling delay extrapolation vector.

[0114] The generated rolling delay extrapolation vector is continuously maintained in the feedforward extrapolation compensation calculation unit, where feedforward compensation prediction and clock drift accumulation are performed. In this process, firstly, the future multi-step delay prediction feature values, multi-order differential discrete components of delay, and extrapolation trend boundary constraint weights contained in the rolling delay extrapolation vector are extracted. Then, the future multi-step delay prediction feature values ​​and extrapolation trend boundary constraint weights are multiplied point-by-point using a weighted multiplication method to calculate the delay trend feedforward prediction correction amount used to correct for the future control cycle evolution trend. Simultaneously, delay feedback is obtained in real time through the system response state feedback channel, and the deviation generated by the system over time is algebraically summed using discrete integration to generate the cumulative clock drift algebraic compensation component. Next, adaptive gain scheduling is run based on the multi-order differential discrete components of delay to quantify the response step size of the feedforward control and output the feedforward dynamic adjustment control factor. Finally, the delay trend feedforward prediction correction amount, the cumulative clock drift algebraic compensation component, and the feedforward dynamic adjustment control factor are encapsulated into a time-domain integrated feedforward control correction variable to obtain the time-series feedforward prediction compensation value.

[0115] The generated timing feedforward prediction compensation value is streamed into the control command timing alignment circuit to perform streaming superposition correction of the global clock axis. During this process, the central time base controller continuously provides the original time counter value of the global clock axis to the control command timing alignment circuit, while simultaneously introducing topological constraints derived from the topology mapping management module. The control command timing alignment circuit uses hardware-level fixed-point addition to stream-superimpose the delay trend feedforward prediction correction amount and the cumulative clock drift algebraic compensation component contained in the timing feedforward prediction compensation value into the original time counter value according to the control weight specified by the feedforward dynamic adjustment control factor. This eliminates the influence of network jitter and hardware physical delay, obtaining a precisely aligned time base value, which is then established as the time value. Subsequently, a subtraction operation is used to compare this time value with the reference source timeline published by the system configuration and status monitoring interface in real time, quantifying the residual phase difference between the two and outputting the time base alignment deviation. Simultaneously, based on whether the time base alignment deviation is within the hard real-time threshold, a logical set is performed to generate a synchronization confidence status flag. Finally, the generated time value, time base alignment deviation, and synchronization confidence status flag are merged into binary data and delivered to the collaborative control scheduling decision engine as the final instruction basis for executing synchronization actions, resulting in a rolling updated corrected synchronization timestamp.

[0116] In this embodiment, through rolling extrapolation and feedforward compensation, the mechanism can eliminate the nondeterministic disturbances of hardware and network latency in real time, significantly improve the synchronization accuracy of the entire network time reference, and ensure the hard real-time response and consistency of the distributed control system under complex operating conditions.

[0117] Figure 3 This disclosure provides a schematic block diagram of a multi-node synchronous triggering control system for additive manufacturing based on a unified timestamp, as part of an embodiment. The system comprises: The response timing capture module 301 is used to acquire the physical state change signal generated in real time by the distributed execution terminal during the spatial collaborative cladding process. Based on the physical state change signal, it performs frame-by-frame feature stream capture and time axis numerical linear transformation to obtain the actual response timestamp updated in a streaming manner. Error topology construction module 302 is used to obtain a preset time base sequence, perform dynamic time domain difference tracing calculation based on the actual response timestamp and the base timestamp extracted from the preset time base sequence to obtain the instant deviation value, and perform time sequence deviation encapsulation and asynchronous streaming reporting of the reverse network channel based on the instant deviation value to obtain a dynamically updated global synchronization error topology. The delay jitter separation module 303 is used to perform cross-cycle time-series rolling frequency domain feature extraction and dynamic separation of DC trend terms based on a preset sliding window, based on the global synchronization error topology, to obtain a real-time updated network transmission jitter sequence and a device inherent delay component sequence. The feedforward compensation prediction module 304 is used to perform feedforward trend rolling extrapolation and feedforward compensation prediction in the main control loop of the main control terminal based on the inherent time delay component sequence of the device, so as to obtain the rolling updated correction synchronization timestamp. The time base dynamic adjustment module 305 is used to sample the network transmission jitter sequence in real time to capture the instantaneous value of the current network transmission jitter, dynamically and instantly rewrite the time base parameters of the network control node based on the instantaneous value of the current network transmission jitter, and finely adjust the step pulse of the time counting sequence in real time to obtain the target drive control data refreshed frame by frame. The collaborative molding drive module 306 is used to control the network control node to perform real-time comparison between the local clock and the corrected synchronization timestamp based on the target drive control data, and drive the distributed execution end to perform spatial collaborative cladding molding when the local clock reaches the corrected synchronization timestamp, so as to obtain the molded additive manufacturing component.

[0118] Figure 4 An electronic device 400 provided in this application embodiment is shown, including a processor 401, a memory 402, and a program or instructions stored in the memory 402 and executable on the processor 401. When the program or instructions are executed by the processor 401, they implement the various processes of the above-described additive manufacturing multi-node synchronous triggering control method embodiment based on a unified timestamp, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0119] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0120] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described additive manufacturing multi-node synchronous triggering control method based on a unified timestamp, and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0121] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0122] Furthermore, it should be understood that since the various modules are only provided to illustrate the functional units of the device of the present invention, the physical devices corresponding to these modules may be the processor itself, or a part of the processor's software, hardware, or a combination of software and hardware. Therefore, the number of modules shown in the figures is merely illustrative.

[0123] Those skilled in the art will understand that the various modules in the device can be adaptively split or combined. Such splitting or combining of specific modules will not cause the technical solution to deviate from the principles of the present invention; therefore, the technical solutions after splitting or combining will fall within the protection scope of the present invention.

[0124] The technical solution of the present invention has been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after such changes or substitutions will all fall within the scope of protection of the present invention.

Claims

1. A method for synchronous triggering control of multiple nodes in additive manufacturing based on a unified timestamp, characterized in that, The method includes: The physical state change signal generated in real time by the distributed execution terminal during the spatial collaborative cladding process is obtained. Based on the physical state change signal, frame-by-frame feature stream capture and time axis numerical linear transformation are performed to obtain the actual response timestamp of the streaming update. A preset time base sequence is obtained. Based on the actual response timestamp and the base timestamp extracted from the preset time base sequence, dynamic time domain difference tracing calculation is performed to obtain the instantaneous deviation value. Based on the instantaneous deviation value, the time sequence deviation is encapsulated and asynchronously streamed up to the reverse network channel to obtain a dynamically updated global synchronization error topology. Based on the global synchronization error topology, cross-cycle time-series rolling frequency domain feature extraction and dynamic separation of DC trend terms are performed based on a preset sliding window to obtain the real-time updated network transmission jitter sequence and the device inherent delay component sequence. Based on the inherent time delay component sequence of the device, feedforward trend rolling extrapolation and feedforward compensation prediction are performed in the main control loop at the main control end to obtain the rolling updated corrected synchronization timestamp. The network transmission jitter sequence is sampled in real time to capture the instantaneous value of the current network transmission jitter. Based on the instantaneous value of the current network transmission jitter, the time base parameters of the network control node are dynamically and instantly rewritten, and the step pulse of the time counting sequence is finely adjusted in real time to obtain the target drive control data refreshed frame by frame. Based on the target-driven control data, the control network control node performs a real-time comparison between the local clock and the corrected synchronization timestamp. When the local clock reaches the corrected synchronization timestamp, it drives the distributed execution end to perform spatial collaborative cladding forming to obtain the formed additive manufacturing component.

2. The method according to claim 1, characterized in that, in, Based on the physical state change signal, frame-by-frame feature stream capture and time-axis numerical linear transformation are performed to obtain the actual response timestamp for streaming updates, including: Based on the physical state change signal, serial time axis alignment and streaming buffer aggregation of multi-channel data streams are performed to obtain synchronous streaming data streams at the same frequency; Based on synchronous streaming data at the same frequency, the manufacturing space coordinate topology matrix projection and space coordinate mapping are performed to obtain the original spatiotemporal array data. Based on the original spatiotemporal array data, spatial neighborhood gradient numerical difference calculation and abrupt edge capture are performed to obtain frame-by-frame feature streams. Based on the frame-by-frame feature stream, a reference clock drift correction and a linear transformation of the time axis values ​​are performed to obtain the actual response timestamp of the streaming update.

3. The method according to claim 1, characterized in that, in, Based on the actual response timestamp and the reference timestamp extracted from the preset time base sequence, dynamic time-domain difference tracing calculation is performed to obtain the instantaneous deviation value. Based on the instantaneous deviation value, time-series deviation encapsulation and asynchronous streaming reporting through the reverse network channel are performed to obtain a dynamically updated global synchronization error topology, including: Based on the actual response timestamp and the reference timestamp extracted from the preset time reference sequence, time reference alignment and time domain difference calculation are performed to obtain the time axis instantaneous difference. Based on the instantaneous difference value of the time axis, multi-cycle time-domain deviation is traced backward to obtain the instantaneous deviation value; Based on the instantaneous deviation value, timing deviation encapsulation and network protocol packaging are performed to obtain timing deviation data packets; Based on the time-series deviation data packets associated with the reverse network channel, asynchronous streaming reporting and topology node mapping are performed to obtain a dynamically updated global synchronization error topology.

4. The method according to claim 1, characterized in that, in, Based on the global synchronization error topology, cross-cycle time-series rolling frequency domain feature extraction and dynamic separation of the DC trend term are performed using a preset sliding window to obtain a real-time updated network transmission jitter sequence and a device inherent delay component sequence, including: Based on the global synchronization error topology, a time-series rolling topology matrix is ​​obtained by performing a sliding slice of the topology data section based on a preset sliding window; Based on the time-series rolling topology matrix, cross-cycle time-series rolling frequency domain feature extraction is performed to obtain the error frequency domain feature spectrum; Dynamic separation of the DC trend term is performed based on the error frequency domain characteristic spectrum to obtain the device's inherent time delay component sequence; By stripping alternating signal components based on the error frequency domain characteristic spectrum and the device's inherent time delay component sequence, a real-time updated network transmission jitter sequence is obtained.

5. The method according to claim 1, characterized in that, in, Based on the inherent time delay component sequence of the device, feedforward trend rolling extrapolation and feedforward compensation prediction are performed in the main control loop at the main control end to obtain the rolling updated corrected synchronization timestamp, including: In the main control loop at the main control end, based on the inherent time delay component sequence of the device, feedforward trend rolling extrapolation and timing multi-order differential numerical approximation are performed to obtain the rolling time delay extrapolation vector. In the main control loop at the main control end, based on the rolling delay extrapolation vector, feedforward compensation prediction and cumulative clock drift amount are algebraically accumulated to obtain the timing feedforward prediction compensation value. In the master control loop at the master control end, based on the timing feedforward prediction compensation value, the global clock axis is superimposed and corrected in a streaming manner to obtain the corrected synchronization timestamp that is updated on a rolling basis.

6. The method according to claim 1, characterized in that, in, The network transmission jitter sequence is sampled in real time to capture the instantaneous value of the current network transmission jitter. Based on the instantaneous value of the current network transmission jitter, the time base parameters of the network control node are dynamically and instantly rewritten, and the step pulse of the time count sequence is finely adjusted in real time to obtain the target drive control data refreshed frame by frame, including: Based on the network transmission jitter sequence, real-time sampling and discrete extraction of hardware latch state are performed to obtain the instantaneous value of the current network transmission jitter; Based on the instantaneous value of the current network transmission jitter, the underlying control word of the network control node is physically rewritten to dynamically and instantly rewrite the time base parameters of the network control node and obtain time base rewriting feature data. Based on the time base rewriting characteristic data and the instantaneous value of current network transmission jitter, the gated clock phase correction of the time counting sequence is performed and the step pulse of the time counting sequence is finely adjusted in real time to obtain the target drive control data refreshed frame by frame.

7. The method according to claim 1, characterized in that, in, Based on target-driven control data, the control network control node performs real-time comparison between the local clock and the corrected synchronization timestamp. When the local clock reaches the corrected synchronization timestamp, it drives the distributed execution end to perform spatial collaborative cladding forming to obtain a shaped additive manufacturing component, including: Based on the target-driven control data and the corrected synchronization timestamp, the control network control node performs real-time comparison of the local clock and the corrected synchronization timestamp and digital coincidence logic determination to obtain the local clock comparison feature value. Based on the local clock comparison feature value, when the local clock reaches the corrected synchronization timestamp, the gated hardware interrupt capture and trigger level latch are executed to obtain the instantaneous synchronization drive signal. Based on real-time synchronous drive signals, distributed execution end-effectors are driven to perform spatial collaborative cladding forming to obtain shaped additive manufacturing components.

8. A multi-node synchronous triggering control system for additive manufacturing based on a unified timestamp, characterized in that, The system includes: The response timing capture module is used to acquire the physical state change signals generated in real time by the distributed execution terminal during the spatial collaborative cladding process. Based on the physical state change signals, frame-by-frame feature stream capture and time axis numerical linear transformation are performed to obtain the actual response timestamp updated in a streaming manner. The error topology construction module is used to obtain a preset time base sequence, perform dynamic time domain difference tracing calculation based on the actual response timestamp and the base timestamp extracted from the preset time base sequence to obtain the instantaneous deviation value, and perform time sequence deviation encapsulation and asynchronous streaming reporting of the reverse network channel based on the instantaneous deviation value to obtain a dynamically updated global synchronization error topology. The delay jitter separation module is used to extract cross-cycle time-series rolling frequency domain features and dynamically separate DC trend terms based on a preset sliding window, based on the global synchronization error topology, to obtain a real-time updated network transmission jitter sequence and a device inherent delay component sequence. The feedforward compensation prediction module is used to perform feedforward trend rolling extrapolation and feedforward compensation prediction in the main control loop of the main control terminal based on the inherent time delay component sequence of the device, so as to obtain the rolling updated corrected synchronization timestamp. The time base dynamic adjustment module is used to sample the network transmission jitter sequence in real time to capture the instantaneous value of the current network transmission jitter, dynamically and instantly rewrite the time base parameters of the network control node based on the instantaneous value of the current network transmission jitter, and finely adjust the step pulse of the time counting sequence in real time to obtain the target drive control data refreshed frame by frame. The collaborative molding drive module is used to control the network control node to perform real-time comparison between the local clock and the corrected synchronization timestamp based on the target drive control data. When the local clock reaches the corrected synchronization timestamp, it drives the distributed execution end to perform spatial collaborative cladding molding to obtain the molded additive manufacturing component.

9. An electronic device, characterized in that, It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein when the program or instructions are executed by the processor, they implement the steps of the additive manufacturing multi-node synchronous triggering control method based on a unified timestamp as described in any one of claims 1-7.

10. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the additive manufacturing multi-node synchronous triggering control method based on a unified timestamp as described in any one of claims 1-7.

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