Low-dropout linear voltage regulator and electronic device

Abstract

The application discloses a low-dropout linear voltage regulator and electronic equipment. The low-dropout linear voltage regulator comprises a reference voltage generating circuit and a voltage stabilizing circuit. The voltage stabilizing circuit comprises a first bias current providing module, a driving current providing module, a common-gate tube, a source follower, a target capacitor and a first resistor. A coupling point between the first resistor and a second end of the driving current providing module serves as an output end of the low-dropout linear voltage regulator. In this way, the phase margin of the loop can be improved, and the stability can be improved.

Description

Technical Field

[0001] This application relates to the field of low dropout linear regulator technology, and in particular to low dropout linear regulators and electronic devices. Background Technology

[0002] A flipped voltage follower (FVF) is a commonly used driving method, featuring level shifting and voltage following capabilities. Because its output stage operates in a partially closed-loop mode (with the dominant pole at extremely high frequencies), it exhibits very low output impedance and strong driving capability. FVFs can be applied to low dropout regulators (LDOs), offering advantages over conventional LDOs, including simpler structure and lower quiescent power consumption due to fewer current branches.

[0003] In related technologies, due to the influence of circuit structure, it is not easy for loops to obtain a high phase margin. Summary of the Invention

[0004] The low-dropout linear regulator and electronic equipment provided in this application can improve the phase margin of the loop and enhance stability.

[0005] In a first aspect, this application provides a low-dropout linear regulator, comprising: a reference voltage generation circuit; and a voltage regulator circuit, comprising: a first bias current providing module, the first terminal of which is coupled to a power supply voltage terminal; a drive current providing module, the first terminal of which is coupled to a power supply voltage terminal; wherein the second terminals of the first bias current providing module and the drive current providing module are coupled through a compensation capacitor; a common-gate transistor, the first terminal of which is coupled to the second terminal of the first bias current providing module; and a source follower, the first terminal of which is coupled to the second terminal of the drive current providing module through a first resistor, and the second terminal of the source follower being coupled to... The second terminal of the common-gate transistor; the control terminal of the source follower is coupled to the output terminal of the reference voltage generation circuit to receive the bias voltage; the target capacitor, the first terminal of which is coupled to the second terminal of the drive current supply module, and the second terminal of the target capacitor is coupled to the second terminal of the source follower; the second bias current supply module, the first terminal of which is coupled to the second terminal of the common-gate transistor, and the second terminal of which is coupled to the reference voltage generation circuit; wherein, the coupling point between the first resistor and the second terminal of the drive current supply module serves as the output terminal of the low-dropout linear regulator, and the output terminal of the low-dropout linear regulator and the second terminal of the second bias current supply module are coupled through a decoupling capacitor.

[0006] The reference voltage generation circuit includes: an amplification unit, the first input terminal of which is used to receive the reference voltage; a negative feedback unit, the first terminal of which is coupled to the output terminal of the amplification unit, the second terminal of which is coupled to the second input terminal of the amplification unit, and the third terminal of which is grounded; and a bias voltage generation unit, the first terminal of which is coupled to the output terminal of the amplification unit, the second terminal of which serves as the output terminal of the reference voltage generation circuit and is coupled to the control terminal of the source follower, and the third terminal of which is coupled to the second terminal of the second bias current supply module.

[0007] The negative feedback unit includes: a second resistor, the first end of which is coupled to the output terminal of the amplifier unit; and a third resistor, the first end of which is coupled to the second end of the second resistor and the second input terminal of the amplifier unit, and the second end of the third resistor is grounded.

[0008] The bias voltage generating unit includes: a first transistor, the first end of which is coupled to the output terminal of the amplification unit, and the second end of which is coupled to the control terminal of the first transistor and the control terminal of the source follower; and a second transistor, the first end of which is coupled to the second end of the first transistor, and the second end of which is coupled to the second terminal of the second bias current providing module.

[0009] The first terminal of the first transistor is coupled to the output terminal of the amplification unit through the fourth resistor.

[0010] The resistance value of the fourth resistor is determined by the resistance values ​​of the first bias current providing module, the second bias current providing module, and the first resistor.

[0011] The target capacitor is also used to introduce a zero in the left half-plane; the zero frequency in the left half-plane is less than the pole frequency of the target coupling point, which is the coupling point between the second terminal of the source follower and the second terminal of the common gate transistor.

[0012] The control terminal of the drive current supply module is coupled to the second terminal of the first bias current supply module.

[0013] Among them, the first bias current providing module, the drive current providing module and the source follower are PMOS transistors, and the common gate transistor and the second bias current providing module are NMOS transistors.

[0014] In a second aspect, this application provides an electronic device including a low-dropout linear regulator as provided in the first aspect.

[0015] The beneficial effects of this application are as follows: Unlike the prior art, the low dropout linear regulator and electronic device provided by this application form a parallel path by connecting a target capacitor in parallel across the two ends of the source follower, thereby introducing a zero in the left half-plane and increasing the equivalent resistance of the branch by the series resistance of the source follower. This can reduce the frequency of the zero in the left half-plane without being limited by the current ratio, while not affecting the frequency of the pole at the second terminal node of the source follower, thereby improving the phase margin of the loop and improving stability.

[0016] Furthermore, to compensate for the effect of this resistor on the output voltage, the reference voltage generation circuit adds a corresponding resistor, so that the bias voltage is reduced by the same amount, maintaining the target value of the output voltage unchanged. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0018] Figure 1 This is a schematic diagram of an embodiment of the low dropout linear regulator provided in this application;

[0019] Figure 2 This is a schematic diagram of another embodiment of the low-dropout linear regulator provided in this application;

[0020] Figure 3 This is a schematic diagram of the main zeros and poles in the low dropout linear regulator provided in this application;

[0021] Figure 4 This application provides Figure 1 A schematic diagram of the simulation results of a low-dropout linear regulator;

[0022] Figure 5 This application provides Figure 2 A schematic diagram of the simulation results of a low-dropout linear regulator;

[0023] Figure 6 This is a schematic diagram of another embodiment of the low-dropout linear regulator provided in this application;

[0024] Figure 7 This application provides Figure 6 A schematic diagram of the simulation results of a low-dropout linear regulator;

[0025] Figure 8 This is a schematic diagram of another embodiment of the low-dropout linear regulator provided in this application;

[0026] Figure 9 This application provides Figure 2 Another simulation result diagram of a low-dropout linear regulator;

[0027] Figure 10 This application provides Figure 8 A schematic diagram of the simulation results of a low-dropout linear regulator;

[0028] Figure 11 This is a schematic diagram of another embodiment of the low-dropout linear regulator provided in this application;

[0029] Figure 12 This application provides Figure 11 A schematic diagram of the simulation results of a low-dropout linear regulator;

[0030] Figure 13 This is a schematic diagram of the structure of an embodiment of the electronic device provided in this application. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0032] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0033] See Figure 1 , Figure 1 This is a schematic diagram of an embodiment of the low dropout linear regulator provided in this application. The low dropout linear regulator 100 includes: a reference voltage generation circuit 10 and a voltage regulation circuit 20.

[0034] In some embodiments, the reference voltage generation circuit 10 is used to generate the target voltage required by the voltage regulator circuit 20, such as the subsequent first bias voltage VBIAS.

[0035] In some embodiments, the voltage regulator circuit 20 includes: a first bias current supply module, a drive current supply module, a common gate transistor MN1, a source follower, a second bias current supply module, a compensation capacitor CC, and a decoupling capacitor CL. Specifically, the first bias current supply module is composed of transistor MP2, the drive current supply module is composed of transistor MP3, the source follower is composed of transistor MP1, and the second bias current supply module is composed of transistor MN2.

[0036] In some embodiments, the first terminal of the first bias current providing module is coupled to the power supply voltage terminal VCC.

[0037] In some embodiments, the first terminal of the drive current providing module is coupled to the power supply voltage terminal VCC. The second terminals of the first bias current providing module and the drive current providing module are coupled through a compensation capacitor CC.

[0038] In some embodiments, the first terminal of the common gate transistor MN1 is coupled to the second terminal of the first bias current providing module.

[0039] In some embodiments, the first terminal of the source follower is coupled to the second terminal of the drive current providing module, and the second terminal of the source follower is coupled to the second terminal of the common gate transistor MN1. The control terminal of the source follower is coupled to the output terminal of the reference voltage generating circuit to receive the first bias voltage VBIAS.

[0040] In some embodiments, the first terminal of the second bias current providing module is coupled to the second terminal of the common gate transistor MN1, and the second terminal of the second bias current providing module is coupled to the reference voltage generating circuit 10.

[0041] In some embodiments, the coupling point between the first terminal of the source follower and the second terminal of the drive current providing module serves as the output terminal of the low dropout linear regulator 100, which can output a corresponding output voltage VOUT.

[0042] For example, such as Figure 1 As shown, the reference voltage generation circuit 10 includes a first amplification unit AMP1, resistor R1, resistor R2, transistor MP4, and transistor MN4.

[0043] The reference voltage generation circuit 10 generates the target voltage required by the voltage regulator circuit 20. The first amplification unit AMP1, along with resistors R1 and R2, forms a negative feedback circuit to convert the reference voltage VREF into the required target voltage VREF_LDO. VREF_LDO = VREF * (1 + R2 / R1).

[0044] The gate-drain shorted transistors MP4 and MN4 serve as the load branch, driven by the first amplification unit AMP1. The bias voltage VBIAS is VREF_LDO minus the gate-source voltage of transistor MP4 (the gate-source voltage is determined by the current of transistor MN4 and the size of transistor MP4).

[0045] The voltage regulator circuit 20 includes: transistor MN2, transistor MP2, transistor MP3, transistor MP1, common gate transistor MN1, compensation capacitor CC, and decoupling capacitor CL.

[0046] Transistors MN2 and MP2 provide bias current for the two branches. The control terminal of transistor MN2 receives the second bias voltage Vbn1, and the control terminal of transistor MP2 receives the third bias voltage Vbp.

[0047] The MP3 transistor is a driver transistor used to provide drive current to the output load.

[0048] Transistor MP1 is a source follower used to determine the stable value of the output voltage VOUT. At the same time, it generates an error current when the output voltage VOUT deviates from the stable value (this function is equivalent to the input transistor of the error amplifier in a traditional LDO). Common gate transistor MN1 is used to introduce the error current into node Vpass, change the voltage of node Vpass, and thus adjust the current of transistor MP3.

[0049] Under steady-state conditions, the output voltage VOUT is equal to the bias voltage VBIAS plus the gate-source voltage of transistor MP1. By properly setting the size of transistor MP1 and the current flowing through transistor MP1 (current of transistor MN2 minus current of transistor MP2), the current flowing through transistor MP1 and transistor MP4 per unit width-to-length ratio is the same. At the same time, transistor MP1 and transistor MP4 use the same type of device to ensure that the gate-source voltages of transistor MP1 and transistor MP4 are the same, and the stable value of the output voltage VOUT is equal to the VREF_LDO voltage.

[0050] CL is the decoupling capacitor of the load, and CC is the compensation capacitor. Since the loop has only one high-impedance node Vpass, node Vpass is used as the dominant pole. The loop bandwidth is limited by the Miller effect of the compensation capacitor CC. At the same time, the poles of node Vpass and the output voltage VOUT are separated in frequency to ensure a certain phase margin.

[0051] against Figure 1The applicant found that the impedance of the output node VOUT of the low-dropout linear regulator 100 is limited by the transconductance of the transistor MP1, and therefore it is not a high-impedance node even at low frequencies. This limits the Miller effect of the compensation capacitor CC, making it difficult for the loop to obtain a high phase margin. Based on this, the applicant proposes the following solution.

[0052] See Figure 2 , Figure 2 This is a schematic diagram of another embodiment of the low dropout linear regulator provided in this application. The low dropout linear regulator 100 includes: a reference voltage generation circuit 10 and a voltage regulation circuit 20.

[0053] The voltage regulator circuit 20 includes: a first bias current supply module 21, a drive current supply module 22, a common gate transistor MN1, a compensation capacitor CC, a source follower 23, a second bias current supply module 24, and a target capacitor CF.

[0054] The first terminal of the first bias current providing module 21 is coupled to the power supply voltage terminal VCC.

[0055] The first terminal of the drive current supply module 22 is coupled to the power supply voltage terminal VCC. The second terminals of the first bias current supply module 21 and the drive current supply module 22 are coupled through a compensation capacitor CC.

[0056] The first terminal of the common gate transistor MN1 is coupled to the second terminal of the first bias current supply module 21.

[0057] The first terminal of the source follower 23 is coupled to the second terminal of the drive current supply module 22, the second terminal of the source follower 23 is coupled to the second terminal of the common gate transistor MN1, and a target capacitor is connected in parallel between the first terminal and the second terminal of the source follower 23.

[0058] The control terminal of the source follower 23 is coupled to the output terminal of the reference voltage generation circuit 10 and is used to receive the first bias voltage VBIAS.

[0059] The first terminal of the second bias current providing module 24 is coupled to the second terminal of the common gate transistor MN1, and the second terminal of the second bias current providing module 24 is coupled to the reference voltage generating circuit 10.

[0060] In some embodiments, the coupling point between the first terminal of the source follower 23 and the second terminal of the drive current supply module 22 serves as the output terminal of the low-dropout linear regulator 100. The output terminal of the low-dropout linear regulator 100 and the second terminal of the second bias current supply module 24 are coupled through a decoupling capacitor. That is, the corresponding output voltage VOUT can be output through the output terminal of the low-dropout linear regulator 100.

[0061] In some embodiments, the target capacitor CF is also used to introduce a zero in the left half-plane, providing a positive phase shift within the loop bandwidth.

[0062] In some embodiments, the transconductance of the source follower 23 is less than the transconductance of the common gate transistor MN1. By setting the transconductance of the source follower 23 to be less than the transconductance of the common gate transistor MN1, it can be ensured that the pole frequency at the second end of the source follower 23 is greater than the frequency of the zero point in the left half-plane.

[0063] In some embodiments, the ratio of the first bias current providing module 21 and the second bias current providing module 24 can be set so that the current flowing through the source follower 23 is less than the current flowing through the common gate transistor MN1, which can also ensure that the second terminal V of the source follower 23 is V S The frequency of the pole at that point is greater than the frequency of the zero point in the left half-plane.

[0064] In other embodiments, the common gate transistor MN1 can be selected to have a larger aspect ratio. That is, the aspect ratio of the common gate transistor MN1 is greater than that of the source follower 23.

[0065] In some embodiments, the control terminal of the drive current providing module 22 is coupled to the second terminal of the first bias current providing module 21.

[0066] In this configuration, the first bias current providing module 21, the drive current providing module 22, and the source follower 23 are PMOS transistors, while the common-gate transistor MN1 and the second bias current providing module 24 are NMOS transistors. For example, as shown... Figure 2 As shown, the first bias current supply module 21 is composed of transistor MP2. The drive current supply module 22 is composed of transistor MP3. The source follower 23 is composed of transistor MP1. The second bias current supply module 24 is composed of transistor MN2. The control terminal of transistor MP2 receives the second bias voltage Vbp. The control terminal of transistor MP1 receives the first bias voltage VBIAS. The control terminal of transistor MN1 receives voltage Vbn2. The control terminal of transistor MN2 receives voltage Vbn1.

[0067] Furthermore, the reference voltage generation circuit 10 includes: a first amplification unit AMP1, a negative feedback unit 11, and a bias voltage generation unit 12.

[0068] The first input terminal of the first amplification unit AMP1 is used to receive the reference voltage VREF.

[0069] The first end of the negative feedback unit 11 is coupled to the output end of the first amplification unit AMP1, the second end of the negative feedback unit 11 is coupled to the second input end of the first amplification unit AMP1, and the third end of the negative feedback unit 11 is grounded.

[0070] The first end of the bias voltage generating unit 12 is coupled to the output end of the first amplification unit AMP1. The second end of the bias voltage generating unit 12 serves as the output end of the reference voltage VREF generating circuit 10 and is coupled to the control end of the source follower 23. The third end of the bias voltage generating unit 12 is coupled to the second end of the second bias current providing module 24.

[0071] Furthermore, the negative feedback unit 11 includes a resistor R2 and a resistor R1. The first end of resistor R2 is coupled to the output terminal of the first amplification unit AMP1. The first end of resistor R1 is coupled to the second end of resistor R2 and the second input terminal of the first amplification unit AMP1, and the second end of resistor R1 is grounded.

[0072] Furthermore, the bias voltage generating unit 12 includes a transistor MP4 and a transistor MN4. The first terminal of transistor MP4 is coupled to the output terminal of the first amplification unit AMP1, and the second terminal of transistor MP4 is coupled to the control terminal of transistor MP4 and the control terminal of the source follower 23. The first terminal of transistor MN4 is coupled to the second terminal of transistor MP4, and the second terminal of transistor MN4 is coupled to the second terminal of the second bias current providing module 24.

[0073] The following explains the specific logic, such as Figure 2 As shown, the target capacitor CF is connected in parallel with the source follower 23 (transistor MP1), creating two parallel paths from the output voltage VOUT to node Vs. This allows for an additional zero in the left half-plane with the following frequency: ω Z1 =-gm P1 / CF.

[0074] Among them, gm P1 CF is the transconductance of source follower 23 (transistor MP1), and CF is the capacitance of the target capacitor CF.

[0075] The poles at node Vs are determined by the equivalent resistance and capacitance (approximately equal to CF) of node Vs. Due to the presence of the common-gate transistor MN1, the equivalent resistance of node Vs is approximately 1 / gm. N1 , of which gm N1 Given the transconductance of the common-gate transistor MN1, the pole frequencies corresponding to node Vs are as follows:

[0076] ω P3 =-gm N1 / CF.

[0077] By setting the ratio of transistor MN2 to transistor MP2, the current flowing through transistor MP1 is made smaller than the current flowing through transistor MN1 (the current flowing through transistor MN1 is IMP2, and the current flowing through transistor MP1 is IMN2-IMP2). Meanwhile, transistor MN1 is selected with a larger aspect ratio, and is biased at a smaller overdrive voltage compared with transistor MP1, which helps to further improve the transconductance of transistor MN1. The above two points can ensure gmP1 < gmN1, thereby ensuring ω Z1 <ω P3 . After the magnitude relationship between the two is determined, the frequencies of the two can be adjusted overall through the target capacitor CF, and generally ω Z1 is set at a position slightly higher than the loop bandwidth GBW (the value of the compensation capacitor CC ensures that the GBW frequency is near the first non-dominant pole), so that the two have almost no effect on the amplitude-frequency characteristic of the loop within GBW, and generate positive phase shift near the bandwidth GBW (since GBW<ω Z1 <ω P3 , therefore, near GBW, the positive phase shift generated by ω Z1 is greater than the negative phase shift generated by ω P3 , and the two overall generate a positive phase shift), thereby increasing the phase margin of the loop near the bandwidth and improving the stability of the loop.

[0078] The frequency distribution of the main poles and zeros of the loop is shown in Figure 3 , wherein P1 is the dominant pole corresponding to the node Vpass, P2 is the first non-dominant pole corresponding to the node at the output voltage VOUT, and Z1 and P3 are as described above. The presence of Z1 reduces the phase shift near GBW and results in better stability. Otherwise, to achieve an approximate phase margin, it is necessary to increase the compensation capacitor CC to lower GBW, which will affect the response speed of the loop. This embodiment can improve the stability of the loop without affecting the bandwidth GBW.

[0079] In an application scenario, the description is made with reference to Figure 4 and Figure 5 :

[0080] For the low-dropout linear regulator 100 shown in Figure 1 , which is implemented by 28nm NAND FLASH process, with a 30pF load decoupling capacitor, simulation is performed through hspice software, Figure 1 the simulation result of the low-dropout linear regulator 100 shown in Figure 4 is shown in, the loop bandwidth is 1.256MHz, and the phase margin is 36 degrees.

[0081] For Figure 2The low-dropout linear regulator 100 shown has a target capacitor CF increased by 2pF, and the current ratio of transistor MP1 and transistor MN1 is set to 1:3. Figure 2 The simulation results of the low-dropout linear regulator 100 shown are as follows: Figure 5 As shown, the loop bandwidth is 1.336MHz, which remains basically unchanged, while the phase margin is increased from 36 degrees to 45 degrees, thus improving stability.

[0082] In this embodiment, by connecting a target capacitor CF across the two ends of the source follower 23 in parallel, a parallel path is formed, thereby introducing a zero point in the left half-plane. Then, by reasonably setting the capacitance value to adjust the position of the zero point, a positive phase shift can be provided within the loop bandwidth. This can improve the phase margin of the loop and enhance stability without affecting the GBW (Gain-Bandwidth).

[0083] The introduction of the target capacitor will reduce the pole frequency at the second terminal of the source follower. Furthermore, by reasonably setting the current ratio of the first bias current supply module 21 and the second bias current supply module 24, the current flowing through the drive current supply module 22 is less than the current flowing through the common gate transistor MN1, ensuring that the pole frequency at the second terminal Vs of the source follower 23 is higher than the introduced zero frequency, thereby reducing the adverse effect of this pole on stability.

[0084] against Figure 1 The applicant found that the impedance of the output node VOUT of the low-dropout linear regulator 100 shown is limited by the transconductance of transistor MP1, thus it is not a high-impedance node even at low frequencies. This limits the Miller effect of the compensation capacitor CC, making it difficult for the loop to achieve a high phase margin. And regarding... Figure 2 The applicant found that, to obtain a higher phase margin, the ratio of the currents of transistor MN1 to transistor MP1 needs to be very large in the low-dropout linear regulator 100 shown. This is difficult to achieve due to power consumption and device mismatch. First, a large current in the common-gate transistor MN1 leads to excessive power consumption. Second, a large current ratio between the common-gate transistor MN1 and transistor MP1 requires the currents of transistors MN2 and MP2 to be very close. This makes the current flowing into transistor MP1 (the difference between the currents of transistors MN2 and MP2) easily affected by the mismatch between transistors MN2 and MP2. Once the current of transistor MP1 deviates significantly, the output voltage VOUT will deviate from the target value, which is unacceptable for an LDO. Based on this, the applicant proposes the following embodiment.

[0085] See Figure 6 , Figure 6This is a schematic diagram of another embodiment of the low dropout linear regulator provided in this application. The low dropout linear regulator 100 includes: a reference voltage generation circuit 10 and a voltage regulation circuit 20.

[0086] The voltage regulator circuit 20 includes: a first bias current supply module 21, a drive current supply module 22, a common gate transistor MN1, a compensation capacitor CC, a source follower 23, a second bias current supply module 24, a target capacitor CF, and a resistor R4.

[0087] The first terminal of the first bias current providing module 21 is coupled to the power supply voltage terminal VCC.

[0088] The first terminal of the drive current supply module 22 is coupled to the power supply voltage terminal VCC. The second terminals of the first bias current supply module 21 and the drive current supply module 22 are coupled through a compensation capacitor CC.

[0089] The first terminal of the common gate transistor MN1 is coupled to the second terminal of the first bias current supply module 21.

[0090] The first terminal of the source follower 23 is coupled to the second terminal of the drive current supply module 22 through resistor R4, and the second terminal of the source follower 23 is coupled to the second terminal of the common gate transistor MN1; the control terminal of the source follower 23 is coupled to the output terminal of the reference voltage generation circuit 10 and is used to receive the first bias voltage VBIAS.

[0091] The first terminal of the target capacitor CF is coupled to the second terminal of the drive current supply module 22, and the second terminal of the target capacitor CF is coupled to the second terminal of the source follower 23.

[0092] The first terminal of the second bias current providing module 24 is coupled to the second terminal of the common gate transistor MN1, and the second terminal of the second bias current providing module 24 is coupled to the reference voltage generating circuit 10.

[0093] The coupling point between resistor R4 and the second terminal of drive current supply module 22 serves as the output terminal of low dropout linear regulator 100. The output terminal of low dropout linear regulator 100 and the second terminal of second bias current supply module 24 are coupled through decoupling capacitor CL.

[0094] In some embodiments, the target capacitor CF is also used to introduce a zero in the left half-plane; wherein the zero frequency of the left half-plane is less than the pole frequency of the target coupling point, and the target coupling point is the coupling point between the second terminal of the source follower 23 and the second terminal of the common gate transistor MN1 (e.g., Figure 6 (Node Vs in the middle).

[0095] In some embodiments, the control terminal of the drive current providing module 22 is coupled to the second terminal of the first bias current providing module 21.

[0096] In some embodiments, the first bias current providing module 21, the drive current providing module 22, and the source follower 23 are PMOS transistors, and the common-gate transistor MN1 and the second bias current providing module 24 are NMOS transistors. For example, as... Figure 6 As shown, the first bias current supply module 21 is composed of transistor MP2. The drive current supply module 22 is composed of transistor MP3. The source follower 23 is composed of transistor MP1. The second bias current supply module 24 is composed of transistor MN2. The control terminal of transistor MP2 receives the bias voltage Vbp. The control terminal of transistor MP1 receives the bias voltage VBIAS. The control terminal of transistor MN1 receives voltage Vbn2. The control terminal of transistor MN2 receives voltage Vbn1.

[0097] Furthermore, the reference voltage generation circuit 10 includes: a first amplification unit AMP1, a negative feedback unit 11, and a bias voltage generation unit 12.

[0098] The first input terminal of the first amplification unit AMP1 is used to receive the reference voltage VREF.

[0099] The first end of the negative feedback unit 11 is coupled to the output end of the first amplification unit AMP1, the second end of the negative feedback unit 11 is coupled to the second input end of the first amplification unit AMP1, and the third end of the negative feedback unit 11 is grounded.

[0100] The first end of the bias voltage generating unit 12 is coupled to the output end of the first amplification unit AMP1. The second end of the bias voltage generating unit 12 serves as the output end of the reference voltage generating circuit 10 and is coupled to the control end of the source follower 23. The third end of the bias voltage generating unit 12 is coupled to the second end of the second bias current providing module 24.

[0101] Furthermore, the negative feedback unit 11 includes resistors R1 and R2. The first end of resistor R2 is coupled to the output terminal of the first amplification unit AMP1. The first end of resistor R1 is coupled to the second end of resistor R2 and the second input terminal of the first amplification unit AMP1, and the second end of resistor R1 is grounded.

[0102] Furthermore, the bias voltage generating unit 12 includes transistor MP4 and transistor MN4.

[0103] The first terminal of transistor MP4 is coupled to the output terminal of the first amplification unit AMP1, and the second terminal of transistor MP4 is coupled to the control terminal of transistor MP4 and the control terminal of source follower 23.

[0104] The first terminal of transistor MN4 is coupled to the second terminal of transistor MP4, and the second terminal of transistor MN4 is coupled to the second terminal of the second bias current supply module 24.

[0105] Furthermore, the first terminal of transistor MP4 is coupled to the output terminal of the first amplification unit AMP1 through resistor R3.

[0106] The resistance value of resistor R3 is determined by the resistance values ​​of the first bias current providing module 21, the second bias current providing module 24, and resistor R4.

[0107] The following explains the specific logic, such as Figure 6 As shown, resistor R4 is connected in series with the source of source follower 23 (transistor MP1), causing the equivalent resistance of this branch to change from 1 / gm. P1 Increase to R4+1 / gm P1 This causes the frequency of the zero point in the left half-plane to become:

[0108] ω Z1 =-gm P1 / [(1+gm P1 *R4)*CF].

[0109] Among them, gm P1 R is the transconductance of source follower 23MP1, CF is the capacitance of capacitor CF, and R4 is the resistance of added resistor R4.

[0110] The pole frequency at node Vs remains unchanged:

[0111] ω P3 =-gm N1 / CF.

[0112] Among them gm N1 It represents the transconductance of MN1.

[0113] From the above expression, it can be seen that by introducing resistor R4, the zero frequency is reduced to... Figure 2 The structure shown is 1 / (1+gm) P1 *R4), the pole frequency at node Vs remains unchanged. Even without specifying the bias currents of transistors MP1 and MN1, it is easy to ensure ω. Z1 <ω P3 Once the magnitude relationship between the two is determined, their frequencies can be adjusted as a whole using the target capacitor CF. Generally, ω... Z1 The compensation capacitor CC is positioned slightly above the loop bandwidth GBW (the value of CC ensures that the GBW frequency is near the first non-dominant pole), so that neither has much impact on the loop amplitude-frequency characteristics within GBW, and produces a positive phase shift near the bandwidth GBW (GBW < ω). Z1 <ω P3 Therefore, near GBW, ω Z1 The resulting positive phase shift is greater than ω P3The negative phase shift generated (and the overall positive phase shift) increases the phase margin of the loop near the bandwidth, thereby improving the stability of the loop.

[0114] The distribution of the main zeros and poles of the loop at frequency can be as follows Figure 3 As shown, P1 is the dominant pole, corresponding to node Vpass, and P2 is the first non-dominant pole, corresponding to node VOUT at the output voltage. Z1 and P3 are described above. The presence of R4 makes the relative relationship between Z1 and P3 not limited by the bias current ratio, thus making it easier to separate them in frequency, obtain a larger phase margin, and improve the stability of the loop.

[0115] To compensate for the effect of resistor R4 on the output voltage VOUT, a resistor R3 is added to the reference voltage generation circuit 10. Its connection method is the same as that of resistor R4 in the voltage regulator circuit, i.e., it is connected in series with the source terminal of transistor MP4. The resistance value is chosen to ensure that the voltage drop across the two resistors is the same under stable conditions, i.e., R3 / R4 = (IMN2 - IMP2) / IMN4, where IMN2 represents the current flowing through transistor MN2, IMP2 represents the current flowing through transistor MP2, and IMN4 represents the current flowing through transistor MN4. The resistance value of resistor R3 can be easily selected by comparing the current ratio of transistors MN2 and MP2 with the resistance value of resistor R4.

[0116] In one application scenario, combined Figure 5 and Figure 7 Explanation:

[0117] against Figure 2 The low-dropout linear regulator 100 is implemented using a 28nm NAND FLASH process, with a 30pF decoupling capacitor CL in the load. The current ratio of transistor MP1 and common-gate transistor MN1 is set to 1:3. It is simulated using Hspice software. Figure 2 The simulation results of the low dropout linear regulator 100 are as follows: Figure 5 As shown, the loop bandwidth is 1.336MHz and the phase margin is 45 degrees.

[0118] against Figure 6 In the low-dropout linear regulator 100, a 100k ohm resistor R4 is connected in series with the source terminal of transistor MP1 in the voltage regulator circuit 20, and a 50k ohm resistor R3 is connected in series with the source terminal of transistor MP4 in the reference voltage generation circuit 10. All other components remain unchanged. Under the same conditions... Figure 6 The simulation results of the low dropout linear regulator 100 are as follows: Figure 7 As shown, the loop bandwidth was increased to 1.756MHz, and the phase margin was increased from 45 degrees to 65 degrees, thus improving stability.

[0119] In this embodiment, by connecting a target capacitor CF across the two ends of the source follower 23 in parallel to form a parallel path, a zero in the left half-plane is introduced, and the series resistor R4 of the source follower 23 increases the equivalent resistance of the branch. This can reduce the frequency of the zero in the left half-plane without being limited by the current ratio, while not affecting the frequency of the pole at node Vs, thereby improving the phase margin of the loop and improving stability.

[0120] Furthermore, to compensate for the effect of resistor R4 on the output voltage VOUT, the reference voltage generation circuit 10 adds a corresponding resistor R3, so that the first bias voltage VBIAS is reduced by the same voltage, maintaining the target value of the output voltage VOUT unchanged.

[0121] against Figure 1 The applicant found that the impedance of the output node VOUT of the low-dropout linear regulator 100 shown is limited by the transconductance of transistor MP1, thus it is not a high-impedance node even at low frequencies. This limits the Miller effect of the compensation capacitor CC, making it difficult for the loop to achieve a high phase margin. And regarding... Figure 2 The applicant found that, to obtain a higher phase margin, the ratio of the currents of transistor MN1 to transistor MP1 needs to be very large in the low-dropout linear regulator 100 shown. This is difficult to achieve due to power consumption and device mismatch. First, a large current in the common-gate transistor MN1 leads to excessive power consumption. Second, a large current ratio between the common-gate transistor MN1 and transistor MP1 requires the currents of transistors MN2 and MP2 to be very close. This makes the current flowing into transistor MP1 (the difference between the currents of transistors MN2 and MP2) easily affected by the mismatch between transistors MN2 and MP2. Once the current of transistor MP1 deviates significantly, the output voltage VOUT will deviate from the target value, which is unacceptable for an LDO. Based on this, the applicant proposes the following embodiment.

[0122] See Figure 8 , Figure 8 This is a schematic diagram of another embodiment of the low dropout linear regulator provided in this application. The low dropout linear regulator 100 includes: a reference voltage generation circuit 10 and a voltage regulation circuit 20.

[0123] The voltage regulator circuit 20 includes: a first bias current supply module 21, a drive current supply module 22, a common gate transistor MN1, a compensation capacitor CC, a source follower 23, a second bias current supply module 24, a target capacitor CF, and an inverting amplifier module 25.

[0124] The first terminal of the first bias current providing module 21 is coupled to the power supply voltage terminal VCC.

[0125] The first terminal of the drive current supply module 22 is coupled to the power supply voltage terminal VCC. The second terminals of the first bias current supply module 21 and the drive current supply module 22 are coupled through a compensation capacitor CC.

[0126] The first terminal of the common gate transistor MN1 is coupled to the second terminal of the first bias current supply module 21.

[0127] The first terminal of source follower 23 is coupled to the second terminal of drive current supply module 22, and the second terminal of source follower 23 is coupled to the second terminal of common gate transistor MN1. A target capacitor CF is connected in parallel between the first and second terminals of source follower 23. The control terminal of source follower 23 is coupled to the output terminal of reference voltage generation circuit 10 and is used to receive the first bias voltage VBIAS.

[0128] The first terminal of the second bias current providing module 24 is coupled to the second terminal of the common gate transistor MN1, and the second terminal of the second bias current providing module 24 is coupled to the reference voltage generating circuit 10.

[0129] The first terminal of the inverting amplifier module 25 is coupled to the power supply voltage terminal VCC, the second terminal of the inverting amplifier module 25 is coupled to the control terminal of the common gate transistor MN1, the third terminal of the inverting amplifier module 25 is coupled to the second terminal of the common gate transistor MN1, and the fourth terminal of the inverting amplifier module 25 is coupled to the second terminal of the second bias current supply module 24.

[0130] The coupling point between the first end of the source follower 23 and the second end of the drive current supply module 22 serves as the output end of the low dropout linear regulator 100. The output end of the low dropout linear regulator 100 and the second end of the second bias current supply module 24 are coupled through the decoupling capacitor CL.

[0131] In some embodiments, the target capacitor CF is used to introduce a zero in the left half-plane; wherein the zero frequency of the left half-plane is less than the pole frequency of the target coupling point, and the target coupling point is the coupling point between the second terminal of the source follower 23 and the second terminal of the common gate transistor MN1.

[0132] In some embodiments, the positive phase shift generated by the frequency of the zero point in the left half-plane is greater than the negative phase shift generated by the frequency of the pole point of the target coupling point.

[0133] In some embodiments, the control terminal of the drive current providing module 22 is coupled to the second terminal of the first bias current providing module 21.

[0134] In some embodiments, the first bias current providing module 21, the drive current providing module 22, and the source follower 23 are PMOS transistors, and the common-gate transistor MN1 and the second bias current providing module 24 are NMOS transistors. For example, as... Figure 8As shown, the first bias current supply module 21 is composed of transistor MP2. The drive current supply module 22 is composed of transistor MP3. The source follower 23 is composed of transistor MP1. The second bias current supply module 24 is composed of transistor MN2. The control terminal of transistor MP2 receives the bias voltage Vbp. The control terminal of transistor MP1 receives the first bias voltage VBIAS. The control terminal of transistor MN1 receives voltage Vbn2. The control terminal of transistor MN2 receives voltage Vbn1.

[0135] Furthermore, the reference voltage generation circuit 10 includes: a first amplification unit AMP1, a negative feedback unit 11, and a bias voltage generation unit 12.

[0136] The first input terminal of the first amplification unit AMP1 is used to receive the reference voltage VREF.

[0137] The first end of the negative feedback unit 11 is coupled to the output end of the first amplification unit AMP1, the second end of the negative feedback unit 11 is coupled to the second input end of the first amplification unit AMP1, and the third end of the negative feedback unit 11 is grounded.

[0138] The first end of the bias voltage generating unit 12 is coupled to the output end of the first amplification unit AMP1. The second end of the bias voltage generating unit 12 serves as the output end of the reference voltage generating circuit 10 and is coupled to the control end of the source follower 23. The third end of the bias voltage generating unit 12 is coupled to the second end of the second bias current providing module 24.

[0139] Furthermore, the negative feedback unit 11 includes a resistor R2 and a resistor R1. The first end of resistor R2 is coupled to the output terminal of the first amplification unit AMP1. The first end of resistor R1 is coupled to the second end of resistor R2 and the second input terminal of the first amplification unit AMP1, and the second end of resistor R1 is grounded.

[0140] Furthermore, the bias voltage generating unit 12 includes a transistor MP4 and a transistor MN4. The first terminal of transistor MP4 is coupled to the output terminal of the first amplification unit AMP1, and the second terminal of transistor MP4 is coupled to the control terminal of transistor MP4 and the control terminal of the source follower 23. The first terminal of transistor MN4 is coupled to the second terminal of transistor MP4, and the second terminal of transistor MN4 is coupled to the second terminal of the second bias current providing module 24.

[0141] Furthermore, the inverting amplifier module 25 includes: resistor R5 and transistor MN3.

[0142] The first end of resistor R5 is coupled to the power supply voltage terminal VCC, and the second end of resistor R5 is coupled to the control terminal of common gate transistor MN1. The first end of transistor MN3 is coupled to the control terminal of common gate transistor MN1, the second end of transistor MN3 is coupled to the second terminal of the second bias current supply module 24, and the control terminal of transistor MN3 is coupled to the second terminal of common gate transistor MN1.

[0143] The following explains the specific logic, such as Figure 8 As shown, transistor MN3 and resistor R3 constitute an inverting amplifier module 25 with a gain of -gm. N3 *R3, where gm N3 This is the transconductance of transistor MN3. The inverting amplifier module 25 is connected between the source and gate of the common-gate transistor MN1, forming a parallel negative feedback. Its gain booster effect will reduce the input impedance of the common-gate transistor MN1 seen from the source from 1 / gm. N1 Reduced to 1 / [gm N1 *(1+gm N3 *R3)]. Where gm N1 The transconductance of the common-gate transistor MN1 is affected by this, resulting in the pole frequency ω corresponding to node Vs. P3 By -gm N1 / CF becomes -[gm] N1 *(1+gm N3 *R3)] / CF, which is to increase to the original value (1+gm) N3 *R3) times, while the frequency ω of the zero point in the left half-plane Z1 Then maintain -gm P1 Since / CF remains constant, even without specifying the bias currents of transistors MP1 and MN1, the frequency of the pole corresponding to node Vs can be adjusted by controlling the amplification factor of the inverting amplifier module 25. Typically, the amplification factor gm... N3 *R3>>1, therefore it is easy to guarantee ω Z1 <ω P3 Once the magnitude relationship between the two is determined, their frequencies can be adjusted as a whole using the target capacitor CF. Generally, ω... Z1 The compensation capacitor CC is positioned slightly above the loop bandwidth GBW (the value of CC ensures that the GBW frequency is near the first non-dominant pole), so that neither has much impact on the loop amplitude-frequency characteristics within GBW, and produces a positive phase shift near the bandwidth GBW (GBW < ω). Z1 <ω P3 Therefore, near GBW, ω Z1 The resulting positive phase shift is greater than ω P3 The negative phase shift generated (and the overall positive phase shift) increases the phase margin of the loop near the bandwidth, thereby improving the stability of the loop.

[0144] The distribution of the main zeros and poles of the loop at frequency is as follows Figure 3 As shown, P1 is the dominant pole, corresponding to node Vpass, and P2 is the first non-dominant pole, corresponding to node VOUT at the output voltage. Z1 and P3 are described above. The presence of the inverting amplifier makes the relative relationship between Z1 and P3 not limited by the bias current ratio, thus making it easier to separate them in frequency, obtain a larger phase margin, and improve the stability of the loop.

[0145] In one application scenario, combined Figure 9 and Figure 10 Explanation:

[0146] against Figure 2 The low-dropout linear regulator 100 is implemented using a 28nm NAND FLASH process, with a 30pF decoupling capacitor CL as the load, and is simulated using Hspice software. Figure 2 The simulation results of the low dropout linear regulator 100 are as follows: Figure 9 As shown, the loop bandwidth is 1.278MHz and the phase margin is 35 degrees.

[0147] against Figure 8 The low dropout linear regulator 100, in Figure 2 Based on the existing model, an inverting amplifier module 25 with a gain of 12 is added, while other parts remain unchanged. The simulation results under the same conditions are as follows. Figure 10 As shown, the loop bandwidth was increased to 1.52MHz, and the phase margin was increased from 35 degrees to 48 degrees, thus improving stability.

[0148] In this embodiment, a target capacitor CF is connected in parallel across the two ends of the source follower 23 to form a parallel path, thereby introducing a zero in the left half-plane. In addition, an inverting amplifier module 25 is added to reduce the input impedance of the source terminal of the common gate transistor MN1, thereby increasing the frequency of the corresponding pole at the source terminal of the common gate transistor MN1, reducing the phase shift generated by the pole near the loop bandwidth, increasing the phase margin, and thus improving the stability of the loop.

[0149] Furthermore, by adding an inverting amplifier module 25 to reduce the input impedance of the source terminal of the common gate transistor MN1, the frequency of the corresponding pole at the source terminal of the common gate transistor MN1 can be increased without being limited by the current ratio, and the frequency of the zero point in the left half-plane is not affected, thereby improving the phase margin of the loop and improving stability.

[0150] In other embodiments, the low-dropout linear regulator 100 described above may include the reference voltage generation circuit 10 and the voltage regulator circuit 20 described above. The voltage regulator circuit 20 includes the first bias current supply module 21, the drive current supply module 22, the common-gate transistor MN1, the compensation capacitor CC, the source follower 23, the second bias current supply module 24, the target capacitor CF, the resistor R4, and the inverting amplifier module 25 described above. The reference voltage generation circuit 10 may be as follows: Figure 6 The reference voltage generation circuit 10 is shown.

[0151] The first terminal of the first bias current providing module 21 is coupled to the power supply voltage terminal VCC.

[0152] The first terminal of the drive current supply module 22 is coupled to the power supply voltage terminal VCC. The second terminals of the first bias current supply module 21 and the drive current supply module 22 are coupled through a compensation capacitor CC.

[0153] The first terminal of the common gate transistor MN1 is coupled to the second terminal of the first bias current supply module 21.

[0154] The first terminal of the source follower 23 is coupled to the second terminal of the drive current supply module 22 through resistor R4, and the second terminal of the source follower 23 is coupled to the second terminal of the common gate transistor MN1; the control terminal of the source follower 23 is coupled to the output terminal of the reference voltage generation circuit 10 and is used to receive the first bias voltage VBIAS.

[0155] The first terminal of the target capacitor CF is coupled to the second terminal of the drive current supply module 22, and the second terminal of the target capacitor CF is coupled to the second terminal of the source follower 23. The target capacitor CF is used to reduce the pole frequency of the second terminal of the source follower 23.

[0156] The first terminal of the second bias current providing module 24 is coupled to the second terminal of the common gate transistor MN1, and the second terminal of the second bias current providing module 24 is coupled to the reference voltage generating circuit 10.

[0157] The coupling point between resistor R4 and the second terminal of drive current supply module 22 serves as the output terminal of low dropout linear regulator 100. The output terminal of low dropout linear regulator 100 and the second terminal of second bias current supply module 24 are coupled through decoupling capacitor CL.

[0158] The control terminal of the drive current supply module 22 is coupled to the second terminal of the drive current supply module 22.

[0159] The first terminal of the inverting amplifier module 25 is coupled to the power supply voltage terminal VCC, the second terminal of the inverting amplifier module 25 is coupled to the control terminal of the common gate transistor MN1, the third terminal of the inverting amplifier module 25 is coupled to the second terminal of the common gate transistor MN1, and the fourth terminal of the inverting amplifier module 25 is coupled to the second terminal of the second bias current supply module 24.

[0160] Furthermore, the inverting amplifier module 25 includes: resistor R5 and transistor MN3.

[0161] The first end of resistor R5 is coupled to the power supply voltage terminal VCC, and the second end of resistor R5 is coupled to the control terminal of common gate transistor MN1. The first end of transistor MN3 is coupled to the control terminal of common gate transistor MN1, the second end of transistor MN3 is coupled to the second terminal of the second bias current supply module 24, and the control terminal of transistor MN3 is coupled to the second terminal of common gate transistor MN1.

[0162] In this embodiment, a target capacitor CF is connected in parallel across the two ends of the source follower 23 to form a parallel path, thereby introducing a zero in the left half-plane. The series resistor R4 of the source follower 23 increases the equivalent resistance of the branch, which can reduce the frequency of the zero in the left half-plane without being limited by the current ratio. In addition, an inverting amplifier module 25 is added to reduce the input impedance of the source terminal of the common gate transistor MN1, thereby increasing the frequency of the corresponding pole at the source terminal of the common gate transistor MN1, reducing the phase shift generated by the pole near the loop bandwidth, increasing the phase margin, and thus improving the stability of the loop.

[0163] against Figure 1 The applicant found that the impedance at the output voltage VOUT of the low-dropout linear regulator 100 is limited by the transconductance of transistor MP1, and therefore is not a high-impedance node even at low frequencies. This limits the Miller effect of the compensation capacitor CC, making it difficult for the loop to obtain a high phase margin. Based on this, the applicant proposes the following embodiments.

[0164] See Figure 11 , Figure 11 This is a schematic diagram of another embodiment of the low dropout linear regulator provided in this application. The low dropout linear regulator 100 includes: a reference voltage generation circuit 10 and a voltage regulation circuit 20.

[0165] The voltage regulator circuit 20 includes: a first bias current supply module 21, a drive current supply module 22, a common gate transistor MN1, a first source follower 27, a second bias current supply module 24, and an AC current generation module 26.

[0166] The first terminal of the first bias current providing module 21 is coupled to the power supply voltage terminal VCC.

[0167] The first terminal of the drive current providing module 22 is coupled to the power supply voltage terminal VCC; the second terminals of the first bias current providing module 21 and the drive current providing module 22 are coupled through the compensation capacitor CC.

[0168] The first end of the common gate transistor MN1 is coupled to the second end of the first bias current supply module 21.

[0169] The first end of the first source follower 27 is coupled to the second end of the drive current providing module 22, the second end of the first source follower 27 is coupled to the second end of the common gate transistor MN1, and the control end of the first source follower 27 is coupled to the output end of the reference voltage generating circuit 10 to receive the bias voltage VBIAS. The coupling point between the first end of the first source follower 27 and the second end of the drive current providing module 22 serves as the output end of the low dropout linear regulator 100.

[0170] In this circuit, the first terminal of the second bias current providing module 24 is coupled to the second terminal of the common-gate transistor MN1, and the second terminal of the second bias current providing module 24 is coupled to the reference voltage generating circuit 10. For example, as shown... Figure 11 As shown, the first bias current supply module 21 is composed of transistor MP2. The drive current supply module 22 is composed of transistor MP3. The first source follower 27 is composed of transistor MP1. The second bias current supply module 24 is composed of transistor MN2. The control terminal of transistor MP2 receives the second bias voltage Vbp. The control terminal of transistor MP1 receives the first bias voltage VBIAS. The control terminal of transistor MN1 receives voltage Vbn2. The control terminal of transistor MN2 receives voltage Vbn1.

[0171] The input terminal of the AC current generating module 26 is coupled to the output terminal of the low dropout linear regulator 100, and the output terminal of the AC current generating module 26 is coupled to the second terminal of the first source follower 27. The AC current generating module 26 is used to introduce AC current related to the output voltage of the low dropout linear regulator 100 into the second terminal of the source follower 23.

[0172] Furthermore, the AC current generating module 26 includes: a current mirror unit 261, a second source follower 262, and a target capacitor CF.

[0173] The first terminal of the current mirror unit 261 is coupled to the power supply voltage terminal VCC, and the output terminal of the current mirror unit 261 is coupled to the second terminal of the first source follower 27.

[0174] The first terminal of the second source follower 262 is coupled to the output terminal of the low dropout linear regulator 100, the second terminal of the second source follower 262 is coupled to the second terminal of the current mirror unit 261, and the third terminal of the second source follower 262 is coupled to the fourth terminal of the second source follower 262, forming negative feedback.

[0175] The first terminal of the target capacitor CF is coupled to the third terminal of the second source follower 262, and the second terminal of the target capacitor CF is coupled to the second terminal of the second bias current providing module 24.

[0176] Furthermore, the second source follower 262 includes a second amplification unit AMP2 and a transistor MN3.

[0177] The first input terminal of the second amplification unit AMP2 is coupled to the output terminal of the low dropout linear regulator 100.

[0178] The control terminal of transistor MN3 is coupled to the output terminal of the second amplification unit AMP2, the first terminal of transistor MN3 is coupled to the second terminal of the current mirror unit, and the second terminal of transistor MN3 is coupled to the second input terminal of the second amplification unit AMP2.

[0179] Furthermore, the current mirror unit includes transistors MP5, MP6, MN5, and MN6.

[0180] The first terminal of transistor MP5 is coupled to the power supply voltage terminal VCC, and the second terminal of transistor MP5 is connected to the control terminal and coupled to the second terminal of the second source follower 262.

[0181] The first terminal of transistor MP6 is coupled to the power supply voltage terminal VCC, and the second terminal of transistor MP6 is coupled to the second terminal of the first source follower 27; the control terminal of transistor MP6 is coupled to the control terminal of transistor MP5.

[0182] The first terminal of transistor MN5 is coupled to the third terminal of the second source follower 262, and the second terminal of transistor MN5 is coupled to the second terminal of the second bias current providing module 24.

[0183] The first terminal of transistor MN6 is coupled to the second terminal of the first source follower 27, and the second terminal of transistor MN6 is coupled to the second terminal of the second bias current providing module 24.

[0184] In some embodiments, transistors MN5 and MN6, along with the second bias current providing module 24, are configured to receive the same control signal, i.e., all receive the bias voltage Vbn1.

[0185] In some embodiments, the scaling factor between transistor MP6 and transistor MP5 is equal to the scaling factor between transistor MN6 and transistor MN5.

[0186] In some embodiments, the AC current generating module 26 is further configured to introduce a zero in the left half-plane; wherein the zero frequency of the left half-plane is less than the pole frequency of the target coupling point, and the target coupling point is the coupling point between the second end of the first source follower 27 and the second end of the common gate transistor MN1.

[0187] Furthermore, the reference voltage generation circuit 10 includes: a first amplification unit AMP1, a negative feedback unit 11, and a bias voltage generation unit 12.

[0188] The first input terminal of the first amplification unit AMP1 is used to receive the reference voltage VREF.

[0189] The first end of the negative feedback unit 11 is coupled to the output end of the second amplification unit AMP1, the second end of the negative feedback unit 11 is coupled to the second input end of the first amplification unit AMP1, and the third end of the negative feedback unit 11 is grounded.

[0190] The first end of the bias voltage generating unit 12 is coupled to the output end of the first amplification unit AMP1. The second end of the bias voltage generating unit 12 serves as the output end of the reference voltage generating circuit 10 and is coupled to the control end of the first source follower 27. The third end of the bias voltage generating unit 12 is coupled to the second end of the second bias current providing module 24.

[0191] Furthermore, the bias voltage generating unit 12 includes transistor MP4 and transistor MN4.

[0192] The first terminal of transistor MP4 is coupled to the output terminal of the first amplification unit AMP1, and the second terminal of transistor MP4 is coupled to the control terminal of transistor MP4 and the control terminal of the first source follower 27.

[0193] The first terminal of transistor MN4 is coupled to the second terminal of transistor MP4, and the second terminal of transistor MN4 is coupled to the second terminal of the second bias current supply module 24.

[0194] The following explains the specific logic, such as Figure 11 As shown, transistor MN3 and the second amplification unit AMP2 (AMP2 can be a simple single-stage amplifier) ​​constitute a source follower with a gain booster (such as the second source follower 262 mentioned above). This source follower transfers the AC portion of the output voltage VOUT to node Vfb (the negative feedback node), generating an AC current across the target capacitor CF. This AC current is then input to node Vs through the current mirror unit 261. Together with transistor MP1, this creates two parallel paths from the output voltage VOUT to node Vs, resulting in a zero in the left half-plane with the following frequency:

[0195] ω Z1 =-gm P1 / (K*CF).

[0196] Among them, gm P1 The transconductance of source follower 27 (transistor MP1), CF is the capacitance of the target capacitor CF, and K is the scaling factor of transistors MP6 and MP5 (the scaling factor of transistors MN6 and MN5 is the same, K, used to offset the DC current injected into node Vs by transistor MP6, avoiding its influence on the DC bias of voltage regulator circuit 20). The position of the zero point can be adjusted by adjusting the target capacitor CF or the scaling factor K. Generally, ω is... Z1The compensation capacitor CC is set at a position slightly above the loop bandwidth GBW (the value of the compensation capacitor CC ensures that the GBW frequency is near the first non-dominant pole), so that it has almost no effect on the loop amplitude-frequency characteristics within GBW, and generates a positive phase shift near the bandwidth GBW, thereby improving the phase margin.

[0197] Because the target capacitor CF is connected to the Vfb node in the AC current generation module 26, a low-frequency pole may appear, affecting the stability of the loop. Therefore, through the gain booster effect of the second amplification unit AMP2 on the transistor MN3, the equivalent resistance of the Vfb node is reduced from 1 / gm. N3 Reduced to 1 / [gm N3 *(1+A2)], where gm N3 A1 is the transconductance of the common-gate transistor MN3, and A2 is the gain of the second amplification unit AMP2. As a result, the pole frequency ω corresponding to node Vs... P3 Determined by the following expression:

[0198] ω P3 =-[gm N3 *(1+A2)] / CF.

[0199] Because of the gain A2, which is a relatively high frequency, the impact on phase shift near the bandwidth GBW is reduced, thus avoiding a decrease in phase margin.

[0200] The distribution of the main zeros and poles of the loop at frequency is as follows Figure 3 As shown, P1 is the dominant pole, corresponding to node Vpass, and P2 is the first non-dominant pole, corresponding to the node at the output voltage VOUT. Z1 and P3 are explained above. The presence of Z1 reduces the phase shift near GBW, resulting in better stability. Otherwise, to achieve an approximate phase margin, the compensation capacitor CC needs to be increased to lower GBW, which would affect the loop response speed. This solution can improve loop stability without affecting the bandwidth GBW.

[0201] In one application scenario, combined Figure 4 and Figure 12 Explanation:

[0202] against Figure 1 The low-dropout linear regulator 100 shown is implemented using a 28nm NAND FLASH process, with a 30pF decoupling capacitor as the load, and is simulated using Hspice software. Figure 1 The simulation results of the low-dropout linear regulator 100 shown are as follows: Figure 4 As shown, the loop bandwidth is 1.256MHz and the phase margin is 36 degrees.

[0203] against Figure 11The low-dropout linear regulator 100 shown has a target capacitor CF of 4pF and a proportional gain K = 1. Figure 11 The simulation results of the low-dropout linear regulator 100 shown are as follows: Figure 12 As shown, the loop bandwidth is 1.354MHz, which remains basically unchanged, while the phase margin is increased from 36 degrees to 47 degrees, thus improving stability.

[0204] In this embodiment, by adding an AC current generation module 26, a zero point in the left half-plane is introduced, which improves the phase margin of the loop and enhances stability without affecting GBW. Furthermore, the adverse effects of the poles of the AC current generation module 26 on stability are reduced through gain booster technology.

[0205] Furthermore, by adding an AC current generation module 26, the AC current related to VOUT is introduced into node Vs, forming a parallel path with the current of transistor MP1, thereby introducing a zero in the left half-plane. The position of the zero is adjusted by reasonably setting the magnitude of the AC current (adjusting capacitor CF or current mirror ratio K), so that it provides a positive phase shift within the loop bandwidth. The pole frequency related to node Vfb in the AC current generation circuit 26 is pushed to a higher frequency through the gain booster effect of the second amplification unit AMP2, thereby reducing the adverse effect on stability.

[0206] See Figure 13 , Figure 13 This is a schematic diagram of an embodiment of the electronic device provided in this application. The electronic device 1000 includes a low-dropout linear regulator 100. The low-dropout linear regulator 100 is as described in any of the above embodiments.

[0207] In some embodiments, electronic device 1000 can be any type of electronic device, such as a mobile phone, computer, walkie-talkie, etc.

[0208] In some embodiments, electronic device 1000 may be a storage device, such as a memory chip.

[0209] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0210] If the integrated units in the other embodiments described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0211] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A low-dropout linear regulator, characterized in that, The low-dropout linear regulator includes: Reference voltage generation circuit; A voltage regulator circuit, the voltage regulator circuit comprising: The first bias current providing module has its first terminal coupled to the power supply voltage terminal. A drive current providing module, wherein a first terminal of the drive current providing module is coupled to the power supply voltage terminal; wherein the second terminal of the first bias current providing module and the drive current providing module are coupled through a compensation capacitor; A common gate transistor, wherein the first end of the common gate transistor is coupled to the second end of the first bias current providing module; A source follower, wherein the first terminal of the source follower is coupled to the second terminal of the drive current providing module through a first resistor, and the second terminal of the source follower is coupled to the second terminal of the common gate transistor; the control terminal of the source follower is coupled to the output terminal of the reference voltage generating circuit for receiving bias voltage. A target capacitor, the first end of which is coupled to the second end of the drive current providing module, and the second end of which is coupled to the second end of the source follower; The second bias current providing module has a first terminal coupled to the second terminal of the common gate transistor and a second terminal coupled to the reference voltage generating circuit. The coupling point between the first resistor and the second terminal of the drive current providing module serves as the output terminal of the low dropout linear regulator.

2. The low-dropout linear regulator according to claim 1, characterized in that, The reference voltage generation circuit includes: An amplification unit, wherein the first input terminal of the amplification unit is used to receive a reference voltage; A negative feedback unit, wherein the first end of the negative feedback unit is coupled to the output end of the amplification unit, the second end of the negative feedback unit is coupled to the second input end of the amplification unit, and the third end of the negative feedback unit is grounded; A bias voltage generating unit, wherein the first terminal of the bias voltage generating unit is coupled to the output terminal of the amplification unit, the second terminal of the bias voltage generating unit serves as the output terminal of the reference voltage generating circuit and is coupled to the control terminal of the source follower, and the third terminal of the bias voltage generating unit is coupled to the second terminal of the second bias current providing module.

3. The low-dropout linear regulator according to claim 2, characterized in that, The negative feedback unit includes: The second resistor has its first end coupled to the output terminal of the amplification unit. The third resistor has its first end coupled to the second end of the second resistor and the second input terminal of the amplification unit, and its second end is grounded.

4. The low-dropout linear regulator according to claim 2, characterized in that, The bias voltage generating unit includes: A first transistor, the first terminal of which is coupled to the output terminal of the amplification unit, and the second terminal of which is coupled to the control terminal of the first transistor and the control terminal of the source follower; The second transistor has a first terminal coupled to the second terminal of the first transistor, and the second terminal of the second transistor is coupled to the second terminal of the second bias current providing module.

5. The low-dropout linear regulator according to claim 4, characterized in that, The first terminal of the first transistor is coupled to the output terminal of the amplification unit through a fourth resistor.

6. The low-dropout linear regulator according to claim 5, characterized in that, The resistance value of the fourth resistor is determined by the resistance values ​​of the first bias current providing module, the second bias current providing module, and the first resistor.

7. The low-dropout linear regulator according to claim 1, characterized in that, The target capacitor is also used to introduce a zero in the left half-plane; wherein the zero frequency of the left half-plane is less than the pole frequency of the target coupling point, and the target coupling point is the coupling point between the second terminal of the source follower and the second terminal of the common gate transistor.

8. The low-dropout linear regulator according to claim 1, characterized in that, The control terminal of the drive current providing module is coupled to the second terminal of the first bias current providing module.

9. The low-dropout linear regulator according to claim 1, characterized in that, The first bias current providing module, the drive current providing module, and the source follower are PMOS transistors, while the common gate transistor and the second bias current providing module are NMOS transistors.

10. An electronic device, characterized in that, Including the low dropout linear regulator as described in any one of claims 1-9.

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