Low-dropout linear voltage regulator with on-chip capacitor and electronic device

Abstract

The present disclosure provides a low dropout linear regulator with on-chip capacitor and electronic equipment, the regulator comprising: a transconductance amplifier module, a compensation network module, a buffer electrode module, a reverse current absorption module, a transient enhancement module, a feedback network module, an N-type output power tube and an on-chip capacitor; the transconductance amplifier module amplifies a reference voltage; the compensation network module separates the pole of the transconductance amplifier module from the pole of the N-type output power tube; the buffer electrode module drives the gate of the N-type output power tube; the reverse current absorption module absorbs reverse current; the transient enhancement module accelerates the transient response to a voltage signal with a large amplitude; the feedback network module detects the output voltage and transmits the divided voltage back to the input end of the transconductance amplifier module. The present disclosure is suitable for the working of an isolated chip in a CMT interference environment with high voltage and high frequency, and has the ability of fast transient response and reverse current absorption, and can have good output voltage stability when the load current is transient.

Description

[0001] This disclosure claims priority to Chinese Patent Application No. 2026105254613, filed on April 21, 2026, entitled "Low Dropout Linear Regulator and Electronic Device Using On-Chip Capacitors". The full text of the aforementioned Chinese Patent Application is incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of analog integrated circuit technology, and more particularly to a low dropout linear regulator and electronic device employing on-chip capacitors. Background Technology

[0003] Currently, digital isolators (drivers) using low dropout linear regulators (LDOs) consist of a transmitter (TX), an isolation barrier, and a receiver (RX). The input communication signal Vin is modulated by a high-frequency carrier at the transmitter (TX) to pass through the isolation barrier, and then the modulated signal is restored to the communication signal Vin at the receiver (RX) to achieve communication between TX and RX.

[0004] Digital isolators (drivers) often encounter scenarios where the voltage between ground and TX and RX fluctuates drastically, resulting in a high-speed, high-amplitude common-mode transient voltage V. CM This could lead to the risk of equipment damage or even personal injury. Summary of the Invention

[0005] The technical problem to be solved by this disclosure is the aforementioned deficiencies in the prior art, and a low dropout linear regulator and electronic device employing on-chip capacitors is provided.

[0006] This disclosure solves the above-mentioned technical problems through the following technical solution:

[0007] This disclosure provides a low dropout linear regulator using an on-chip capacitor. The low dropout linear regulator includes: a transconductance amplifier module, a compensation network module, a buffer module, a reverse current absorption module, a transient enhancement module, a feedback network module, an N-type output power transistor, and the on-chip capacitor.

[0008] The output terminal of the transconductance amplifier module is electrically connected to the input terminal of the compensation network module, the input terminal of the buffer module, and the input terminal of the transient enhancement module, respectively.

[0009] The gate of the N-type output power transistor is electrically connected to the output terminal of the compensation network module, the output terminal of the buffer module, and the input terminal of the reverse current absorption module, respectively.

[0010] The source of the N-type output power transistor is electrically connected to the output terminal of the reverse current absorption module, the output terminal of the transient enhancement module, the first terminal of the feedback network module, and the first terminal of the on-chip capacitor, respectively.

[0011] The second terminal of the feedback network module is electrically connected to the inverting input terminal of the transconductance amplifier module;

[0012] The power supply terminal of the transconductance amplifier module and the drain of the N-type output power transistor are both connected to the power supply voltage.

[0013] The non-inverting input terminal of the transconductance amplifier module is connected to a reference voltage;

[0014] The ground terminal of the feedback network module and the second terminal of the on-chip capacitor are both grounded;

[0015] The non-inverting input terminal of the transconductance amplifier module is used as the input terminal of the low dropout linear regulator, and the source of the N-type output power transistor is used as the output terminal of the low dropout linear regulator to provide the output voltage.

[0016] The transconductance amplifier module is used to amplify the reference voltage;

[0017] The compensation network module is used to separate the poles of the transconductance amplifier module from the poles of the N-type output power transistor.

[0018] The buffer module is used to drive the gate of the N-type output power transistor;

[0019] The backflow current absorption module is used to absorb backflow current;

[0020] The transient enhancement module is used to accelerate the transient response to voltage signals with large amplitude;

[0021] The feedback network module is used to detect the output voltage and transmit the obtained voltage back to the input terminal of the transconductance amplifier module.

[0022] Optionally, the transconductance amplifier module includes a common-source cascode amplifier and a CLASS AB bias circuit;

[0023] The first control terminal of the common-source cascode amplifier is electrically connected to the first control terminal of the CLASS AB bias circuit, and the second control terminal of the common-source cascode amplifier is electrically connected to the second control terminal of the CLASS AB bias circuit.

[0024] The first output terminal of the common source cascode amplifier is electrically connected to the first input terminal of the compensation network module, the first input terminal of the buffer module, and the first input terminal of the transient enhancement module, respectively.

[0025] The second output terminal of the common-source cascode amplifier is electrically connected to the second input terminal of the compensation network module, the second input terminal of the buffer module, and the second input terminal of the transient enhancement module, respectively.

[0026] Optionally, the common-source cascode amplifier includes: a first current source, a second current source, a third current source, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a first resistor;

[0027] The gate of the first PMOS transistor is used as the non-inverting input terminal of the transconductance amplifier module, and the gate of the second PMOS transistor is used as the inverting input terminal of the transconductance amplifier module.

[0028] The input terminal of the first current source is connected to the power supply voltage. The output terminal of the first current source is electrically connected to the source of the first PMOS transistor and the source of the second PMOS transistor. The drain of the second PMOS transistor is electrically connected to the source of the first NMOS transistor and the input terminal of the second current source. The gate of the first NMOS transistor is electrically connected to the gate of the second NMOS transistor. The drain of the first PMOS transistor is electrically connected to the source of the second NMOS transistor and the input terminal of the third current source.

[0029] The drain of the first NMOS transistor is electrically connected to the first terminal of the first resistor, the gate of the third PMOS transistor, and the gate of the fifth PMOS transistor, respectively. The sources of the third PMOS transistor and the fifth PMOS transistor are both connected to the power supply voltage. The drain of the third PMOS transistor is electrically connected to the source of the fourth PMOS transistor. The drain of the fourth PMOS transistor is electrically connected to the second terminal of the first resistor. The gate of the fourth PMOS transistor is electrically connected to the gate of the sixth PMOS transistor. The drain of the fifth PMOS transistor is electrically connected to the source of the sixth PMOS transistor.

[0030] The drain of the sixth PMOS transistor is electrically connected to the drain of the third NMOS transistor and the source of the seventh PMOS transistor, respectively; the drain of the second PMOS transistor is electrically connected to the source of the third NMOS transistor and the drain of the seventh PMOS transistor, respectively.

[0031] The source of the seventh PMOS transistor is used as the first output terminal of the common-source common-gate amplifier, the gate of the seventh PMOS transistor is used as the first control terminal of the common-source common-gate amplifier, the source of the third NMOS transistor is used as the second output terminal of the common-source common-gate amplifier, and the gate of the third NMOS transistor is used as the second control terminal of the common-source common-gate amplifier.

[0032] Optionally, the CLASS AB bias circuit includes: a fourth current source, a fifth current source, an eighth PMOS transistor, a ninth PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor;

[0033] The gate of the ninth PMOS transistor is used as the first control terminal of the CLASS AB bias circuit, and the gate of the fourth NMOS transistor is used as the second control terminal of the CLASS AB bias circuit.

[0034] The input terminal of the fourth current source and the source of the eighth PMOS transistor are both connected to the power supply voltage.

[0035] The output terminal of the fourth current source is electrically connected to the gate and drain of the fourth NMOS transistor, respectively, and the source of the fourth NMOS transistor is electrically connected to the drain and gate of the fifth NMOS transistor.

[0036] The source of the ninth PMOS transistor is electrically connected to the gate and drain of the eighth PMOS transistor, respectively.

[0037] The input terminal of the fifth current source is electrically connected to the gate and the drain of the ninth PMOS transistor, respectively.

[0038] The source of the fifth NMOS transistor and the output of the fifth current source are both grounded.

[0039] Optionally, the compensation network module includes: a second resistor, a third resistor, a second capacitor, and a third capacitor;

[0040] The first end of the second resistor is used as the first input terminal of the compensation network module, and the first end of the third resistor is used as the second input terminal of the compensation network module.

[0041] The second terminal of the second resistor is electrically connected to the first terminal of the second capacitor, the second terminal of the second capacitor is electrically connected to the first terminal of the third capacitor, and the second terminal of the third capacitor is electrically connected to the second terminal of the third resistor.

[0042] The second terminal of the second capacitor is used as the output terminal of the compensation network module.

[0043] Optionally, the buffer module includes: a tenth PMOS transistor and a sixth NMOS transistor;

[0044] The gate of the tenth PMOS transistor is used as the first input terminal of the buffer module, and the gate of the sixth NMOS transistor is used as the second input terminal of the buffer module.

[0045] The source of the tenth PMOS transistor is connected to the power supply voltage, the drain of the tenth PMOS transistor is electrically connected to the drain of the sixth NMOS transistor, and the source of the sixth NMOS transistor is grounded.

[0046] The drain of the tenth PMOS transistor is used as the output terminal of the buffer module.

[0047] Optionally, the reverse current absorption module includes: an eleventh PMOS transistor;

[0048] The gate of the eleventh PMOS transistor is used as the input terminal of the reverse current absorption module, the source of the eleventh PMOS transistor is used as the output terminal of the reverse current absorption module, and the drain of the eleventh PMOS transistor is grounded.

[0049] Optionally, the transient enhancement module includes: a first capacitor and a fourth capacitor;

[0050] The first terminal of the first capacitor is used as the first input terminal of the transient enhancement module, and the first terminal of the fourth capacitor is used as the second input terminal of the transient enhancement module.

[0051] The second terminal of the first capacitor is electrically connected to the second terminal of the fourth capacitor;

[0052] The second terminal of the first capacitor is used as the output terminal of the transient enhancement module.

[0053] Optionally, the feedback network module includes: a fourth resistor, a fifth resistor, and a seventh capacitor;

[0054] The first end of the fourth resistor is used as the first end of the feedback network module, and the second end of the fourth resistor is used as the second end of the feedback network module.

[0055] The first end of the fourth resistor is electrically connected to the first end of the seventh capacitor, and the second end of the fourth resistor is electrically connected to the second end of the seventh capacitor and the first end of the fifth resistor, respectively.

[0056] The second end of the fifth resistor is used as the ground terminal of the feedback network module.

[0057] This disclosure also provides an electronic device comprising the aforementioned low-dropout linear regulator employing on-chip capacitors.

[0058] Based on common knowledge in the field, the above-mentioned preferred conditions can be combined arbitrarily to obtain various preferred embodiments of this disclosure.

[0059] The positive improvements of this disclosure are as follows: the transconductance amplifier module amplifies the reference voltage; the compensation network module separates the poles of the transconductance amplifier module from the poles of the N-type output power transistor; the buffer module drives the gate of the N-type output power transistor; the reverse current absorption module absorbs the reverse current; the transient enhancement module accelerates the transient response to large-amplitude voltage signals; and the feedback network module detects the output voltage and transmits the obtained voltage back to the input of the transconductance amplifier module. In particular, the transient enhancement module accelerates the transient response to large-amplitude voltage signals through the first capacitor C1 and the fourth capacitor C4. When the output voltage VLDO of the LDO is pulled down rapidly, and the voltage across the first capacitor C1 and the fourth capacitor C4 cannot change instantaneously, the gate voltages of the tenth PMOS transistor PM10 and the sixth NMOS transistor NM6 will be coupled down instantaneously, thereby raising the gate voltage of the N-type output power transistor NM7 and pulling up VLDO. Similarly, when VLDO is raised rapidly, the gate voltage of NM7 will be pulled down, thereby quickly turning off NM7. Furthermore, the reverse current absorption module absorbs reverse current through the eleventh PMOS transistor PM11. When the LDO is operating normally, PM11 is off. When current flows into the LDO output, VLDO is raised. The voltage divider network composed of the fourth resistor R4 and the fifth resistor R5 feeds the output voltage back to the input of the transconductance amplifier module. The output of the transconductance amplifier module is thus pulled high, causing the output of the buffer module to pull low and turn off NM7. At this time, the source and gate voltage difference of PM11 is greater than one V. GSPM11 This allows the current drawn in from the LDO output to be absorbed. This low-dropout linear regulator is suitable for operation of isolated chips in environments with high voltage and high frequency CMT interference. It also features fast transient response and the ability to absorb reverse current, providing good output voltage stability during load current transients and anti-reverse current protection to suppress output voltage rise when the load current direction changes. Specifically, when the LDO's load capacitance is 100pF and the load current is 500uA, for a 10mA / ns forward jump and a 2mA / ns reverse jump in the load current Iload, the output VLDO fluctuation can be limited to within 200mV. Attached Figure Description

[0060] Figure 1 This is a schematic diagram of a low-dropout linear regulator using on-chip capacitors provided in Embodiment 1 of this disclosure;

[0061] Figure 2 A schematic diagram of the common-mode transient voltage in a prior art digital isolator for a low-dropout linear regulator using on-chip capacitors, provided for Embodiment 1 of this disclosure;

[0062] Figure 3 The prior art of a low-dropout linear regulator using on-chip capacitors, as provided in Embodiment 1 of this disclosure, is in the prior art.CMT Two paths;

[0063] Figure 4 This is a circuit gate-level schematic diagram of a low-dropout linear regulator using on-chip capacitors, provided in Embodiment 1 of this disclosure.

[0064] Figure 5 This invention provides a test method for an LDO (Low Dropout Linear Regulator) using an on-chip capacitor, as described in Embodiment 1 of this disclosure.

[0065] Figure 6 The current waveform of Iload and the waveform of VLDO are provided for an embodiment 1 of this disclosure of a low dropout linear regulator using an on-chip capacitor. Detailed Implementation

[0066] The present disclosure is further illustrated below by way of embodiments, but the present disclosure is not limited to the scope of the embodiments described herein.

[0067] The prefixes such as "first" and "second" used in this disclosure are merely for distinguishing different descriptive objects and do not limit the position, order, priority, quantity, or content of the described objects. The use of ordinal numbers and other prefixes used to distinguish descriptive objects in this disclosure does not constitute a limitation on the described objects. The description of the described objects is given in the claims or the context of the embodiments, and should not be construed as an unnecessary limitation. Furthermore, in the description of this embodiment, unless otherwise stated, "multiple" means two or more.

[0068] Example 1

[0069] Reference Figure 1 This disclosure provides a low dropout linear regulator using an on-chip capacitor. The low dropout linear regulator includes: a transconductance amplifier module 1 (OTA), a compensation network module 2, a buffer module 3, a reverse current absorption module 4, a transient enhancement module 5, a feedback network module 6, an N-type output power transistor NM7, and an on-chip capacitor CL.

[0070] The output terminal of the transconductance amplifier module 1 is electrically connected to the input terminal of the compensation network module 2, the input terminal of the buffer module 3, and the input terminal of the transient enhancement module 5, respectively.

[0071] The gate of the N-type output power transistor NM7 is electrically connected to the output terminal of the compensation network module 2, the output terminal of the buffer module 3, and the input terminal of the reverse current absorption module 4, respectively.

[0072] The source of the N-type output power transistor NM7 is electrically connected to the output terminal of the reverse current absorption module 4, the output terminal of the transient enhancement module 5, the first terminal of the feedback network module 6, and the first terminal of the on-chip capacitor CL.

[0073] The second terminal of the feedback network module 6 is electrically connected to the inverting input terminal of the transconductance amplifier module 1.

[0074] The power supply terminal of transconductance amplifier module 1 and the drain of N-type output power transistor NM7 are both connected to the power supply voltage VCC.

[0075] The non-inverting input terminal of transconductance amplifier module 1 is connected to the reference voltage Vref.

[0076] The ground terminal of feedback network module 6 and the second terminal of on-chip capacitor CL are both grounded.

[0077] The non-inverting input terminal of the transconductance amplifier module 1 is used as the input terminal of the low dropout linear regulator, and the source of the N-type output power transistor NM7 is used as the output terminal of the low dropout linear regulator to provide the output voltage VLDO.

[0078] Transconductance amplifier module 1 is used to amplify the reference voltage Vref.

[0079] The compensation network module 2 is used to separate the poles of the transconductance amplifier module 1 from the poles of the N-type output power transistor NM7.

[0080] The buffer module 3 is used to drive the gate of the N-type output power transistor NM7.

[0081] The backflow current absorption module 4 is used to absorb backflow current.

[0082] The transient enhancement module 5 is used to accelerate the transient response to voltage signals with large amplitude.

[0083] Feedback network module 6 is used to detect the output voltage VLDO and transmit the obtained voltage back to the input of transconductance amplifier module 1.

[0084] in, Figure 2 This illustrates a prior art digital isolator and a common-mode transient voltage V applied between ground on the TX and RX sides. CM Digital isolators or drives are frequently used in systems such as motor drives, inverters, communication buses, medical systems, and electric drives for new energy vehicles. In these applications, scenarios often arise where the voltage between ground (TX and RX) fluctuates drastically, generating a high-speed, large-amplitude common-mode transient voltage V. CM .

[0085] For example, when an isolated drive operates a three-phase inverter bridge composed of power switching transistors such as IGBTs (Insulated Gate Bipolar Transistors), the voltage across the transistors switches rapidly between 0V and the bus voltage (typically several hundred to several thousand volts), at a rate of tens of kV / µs (kilovolts per microsecond). This rapidly changing voltage generates a large current flowing through the ground wire via the parasitic capacitance between the motor windings and the high-voltage side ground. Because the ground wire itself has parasitic inductance, according to the formula V = L * di / dt, where i represents current and t represents time, di / dt represents the rate of change of current i with time t (differential form), this rapidly transient current generates a momentary voltage spike across the inductor, resulting in a high-speed, large-amplitude common-mode transient voltage V0 relative to the reference ground (TX ground). CM .

[0086] For example, in the use of medical devices such as defibrillators, the device applies a high-voltage pulse of several thousand volts to the patient, which can cause extreme potential transients at the ground at both ends of the device.

[0087] For example, in industrial automation communication buses, communication networks such as CAN (a type of communication bus) connect devices with different power ratings. The start-up and shutdown of high-power devices, noise from switching power supplies, or lightning strikes can all cause instantaneous potential fluctuations in the ground loop of the communication network. In the main drive systems of new energy electric vehicles, more and more manufacturers are using silicon carbide (SiC) MOSFETs (silicon carbide metal-oxide-semiconductor field-effect transistors) to drive the motor. Compared to IGBTs, these have a faster switching speed, resulting in a faster voltage fluctuation between the TX and RX ground lines. CM A well-designed digital isolator can ensure that the internal components of TX and RX will not be damaged in this environment, and that communication signals can be transmitted normally.

[0088] In the above application examples, when the voltage on both sides of the digital isolator or isolation driver changes instantaneously, the voltage across the isolation medium will also change by the same magnitude.

[0089] Figure 3 The prior art is shown as follows Figure 2 The I shown CMTThere are two paths: Path 1 goes through the channel of the PMOS transistor in the drive output or "Body-Diode + Channel of the PMOS transistor in the drive output" through the power transistor of the LDO to VCCTX; Path 2 goes through the channel of the NMOS transistor in the drive output or "Body-Diode + Channel of the NMOS transistor in the drive output" to GND (ground). In practical applications, whether the isolation medium is capacitive or magnetic, there will be capacitance C at both ends of the isolation medium. P Existence, within the containment C P The value of C is the capacitance of the isolation capacitor. P This is the parasitic capacitance between the primary and secondary coils. C in the capacitance... P The C in the magnetic separator is approximately on the order of tens of fF. P It will be smaller. When V CM When the event occurs, capacitor C P The transient change in voltage across the terminals generates a current I. CMT =C P *V CM / ∆t is injected or extracted through the isolation medium and then through the TX-driven channel or the "TX-driven channel + diode".

[0090] I CMT =C P *V CM / ∆t is injected or extracted through the isolation medium or through the "TX-driven channel + diode".

[0091] I CMT Whether the current flows through Path1 or Path2 depends on the on-state of the driving pull-up PMOS transistor and the pull-down NMOS transistor. When the driving NMOS transistor is on, I... CMT The current flows from the channel of the NMOS transistor or the "channel-plus diode" of the NMOS transistor to ground at TX. When the driving PMOS transistor is turned on, I... CMT The current flows from the channel of the PMOS transistor or the "channel-plus diode" through the power transistor NM1 of the LDO and then to the input power supply (i.e., the power supply voltage) of the LDO. When the PMOS transistor is turned on and V... CM When I is positive, it means that when the ground at TX rises relative to the ground at RX. CM The voltage of VCCL drops momentarily as it flows out from the LDO's output VCCL; when the PMOS transistor is turned on and V... CM When I is negative, it means that the ground of TX decreases relative to the ground of RX. CMThe inflow from the LDO's output VCCL causes a momentary spike in VCCL voltage. This momentary drop in VCCL voltage reduces the amplitude of the communication signal transmitted by TX, making demodulation by RX difficult. Conversely, the rise in VCCL voltage can cause the loop of an LDO without backflow protection to break, resulting in voltage regulation failure, especially when V... CM When I jumps back and forth between ground on TX and RX at a very high frequency CM This will have a significant impact on the output voltage of the LDO. Existing traditional LDO architectures cannot meet the requirements in terms of transient response and lack reverse current protection. The static output voltage of a basic FVF LDO (folded cascode low dropout regulator) with a fast loop will fluctuate significantly under PVT (process, voltage, temperature) conditions. Furthermore, the low loop gain of the FVF LDO will result in a low load regulation, leading to an output lower than the design value under heavy loads. On the other hand, FVF LDOs with DC regulation enhancement will require the introduction of additional loops and analysis, which will bring difficulties to the design of practical engineering applications.

[0092] To address the aforementioned shortcomings, this embodiment employs an on-chip capacitor-based low-dropout linear regulator, as follows: Figure 1 The structure is shown. Specifically, the gate-level schematic of the low-dropout linear regulator can be shown as follows: Figure 4 As shown.

[0093] In transconductance amplifier module 1, PM1 and PM2 are the PMOS input differential transistors of the amplifier. The gate voltages of NM1 and NM2 are both provided by the bias voltage VCAS. R1 and PM3-PM6 form a low-voltage current mirror. PM1-PM6, NM1-NM2, and bias current sources I2 and I3 form the main body of the folded cascode amplifier. NM3 and PM7 form a floating current source to drive PM10 and NM6 (buffer module 3). The bias current I5 and PM8 and PM9 bias the gate voltage of PM7 at VCC-V GSPM8 -V GSPM9 At the potential, the bias current I4 and NM4 and NM5 bias the gate voltage of NM3 at GND+V. GSNM5 +V GSNM4 Therefore, the gate bias voltage of PM10 is VCC-V at the given potential. GSPM8 -V GSPM9 +V GSPM7 The gate bias voltage of NM6 is GND+V. GSNM5 +V GSNM4 -V GSNM3 .

[0094] By adjusting the aspect ratios of PM7, PM9, NM3, and NM4, V can be...GSPM7 With V GSPM9 They are basically equal, V GSNM3 With V GSNM4 They are essentially equal; therefore, the gate bias voltage V of PM10 is... GSPM10 =VCC-V GSPM8 The gate bias voltage V of NM6 GSNM6 =GND+V GSNM5 .

[0095] By adjusting the magnitudes of bias currents I4 and I5 and the W (width) / L (length) dimensions of PM8 and NM5, the gate bias potentials of PM10 and NM6 are adjusted so that the static on-current of PM10 and NM6 is adjusted to a suitable magnitude and they operate in CLASSAB state to drive the gate of the subsequent LDO power transistor NM7.

[0096] In compensation network module 2, R2, C2 and R3, C3 form a Miller compensation network that separates the poles at the output of the common source cascode amplifier from the poles at the gate of the output stage power transistor NM7.

[0097] The buffer module 3 consists of PM10 and NM6.

[0098] In the reverse current absorption module 4, PM11 acts as a PMOS transistor to absorb reverse current. During normal operation, its source voltage is equal to the output voltage VLDO of the LDO, and its gate voltage is equal to VLDO + V. GSNM7 Therefore, V GSPM11 =V GSNM7 At this time, PM11 is in the off state. When current flows into the LDO output port, VLDO will be raised. The voltage divider network composed of R4 and R5 in feedback network module 6 feeds the output voltage back to the input of the amplifier. The output of the amplifier is thus pulled high, thereby pulling down the output of the buffer stage and turning off the power transistor NM7. At this time, the source and gate voltage difference of PM11 is greater than one V. GSPM11 This allows the current injected into the LDO output port to be absorbed.

[0099] In transient enhancement module 5, capacitors C1 and C4 are used to accelerate the large-signal transient response of the LDO. When the LDO output VLDO is rapidly pulled low, the voltage across capacitors C1 and C4 cannot change instantaneously. The gate voltages of PM10 and NM6 will be coupled down momentarily, thereby raising the gate voltage of NM7 and pulling VLDO up. Similarly, when VLDO is rapidly raised, the gate voltage of NM7 will be pulled down, thereby quickly turning off the power transistor NM7.

[0100] Feedback network module 6, composed of R4, R5, and C7, is used to detect the output voltage and transmit the obtained voltage back to the amplifier's input. Because the negative feedback characteristic of the entire LDO loop makes the amplifier's input voltages equal, the gate input reference voltage of PM1, Vref = VLDO * R5 / (R4 + R5), and the LDO's output voltage, VLDO = Vref * (R4 + R5) / R5. C7, R4, and R5 form a zero-pole pair to increase the unity-gain bandwidth (GBW) of the entire LDO loop.

[0101] Capacitor C5 is used to stabilize the gate voltage of NM7. Since NM7 is used as the power transistor in an LDO, its relatively large area results in a large gate-to-source parasitic capacitance C. GSNM7 After adding C5, the moment the LDO output is pulled down / up can be considered as C. GSNM7 The voltage divider C5 and C5 reduce the impact of the LDO output on the power transistor gate due to transient output changes.

[0102] R6 provides a resistive load to the LDO, and when the LDO is unloaded, it provides a static bias current to the output stage, thereby reducing the impact of the output poles on the phase margin.

[0103] The on-chip capacitor CL serves as the load, and in this embodiment, it is used to be several tens of pF (picofarads).

[0104] For example Figure 1 and Figure 4 The low-dropout linear regulator shown is... Figure 5 The test method for LDO is shown. Figure 6 The waveforms of Iload and VLDO are shown. At time t0, Iload draws 500µA from the LDO to simulate the quiescent current supplying power to the chip under normal conditions. At time t1, the rise time of Iload from 500µA to 10mA is 1ns. At time t2, the fall time of Iload from 10mA back to 500µA is 1ns. At time t3, the fall time of Iload from 500µA to -2mA is 1ns. The test results show that the LDO's output voltage has good stability, fast transient response, and can absorb reverse current.

[0105] In addition, under normal circumstances, the minimum operating voltage of an LDO is VLDO + V. GSNM7 +V OVPM10 When the LDO needs to operate at low voltage, the NM7 can be replaced with a native transistor. In this case, the minimum operating voltage is approximately equal to VLDO + V. OVPM10 .

[0106] The feedback mode of LDO can also be changed from the existing Miller compensation to nested Miller compensation or cascode compensation according to actual needs.

[0107] In this embodiment, the transconductance amplifier module amplifies the reference voltage, the compensation network module separates the poles of the transconductance amplifier module from the poles of the N-type output power transistor, the buffer module drives the gate of the N-type output power transistor, the reverse current absorption module absorbs the reverse current, the transient enhancement module accelerates the transient response to voltage signals with large amplitude, and the feedback network module detects the output voltage and transmits the obtained voltage back to the input of the transconductance amplifier module. In particular, the transient enhancement module accelerates the transient response to voltage signals with large amplitude through the first capacitor C1 and the fourth capacitor C4. When the output voltage VLDO of the LDO is pulled down rapidly, and the voltage across the first capacitor C1 and the fourth capacitor C4 cannot change instantaneously, the gate voltages of the tenth PMOS transistor PM10 and the sixth NMOS transistor NM6 will be coupled down instantaneously, thereby raising the gate voltage of the N-type output power transistor NM7 and pulling up VLDO. Similarly, when VLDO is raised rapidly, the gate voltage of NM7 will be pulled down, thereby quickly turning off NM7. Furthermore, the reverse current absorption module absorbs reverse current through the eleventh PMOS transistor PM11. When the LDO is operating normally, PM11 is off. When current flows into the LDO output, VLDO is raised. The voltage divider network composed of the fourth resistor R4 and the fifth resistor R5 feeds the output voltage back to the input of the transconductance amplifier module. The output of the transconductance amplifier module is thus pulled high, causing the output of the buffer module to pull low and turn off NM7. At this time, the source and gate voltage difference of PM11 is greater than one V. GSPM11 This allows the current drawn in from the LDO output to be absorbed. This low-dropout linear regulator is suitable for operation of isolated chips in environments with high voltage and high frequency CMT interference. It also features fast transient response and the ability to absorb reverse current, providing good output voltage stability during load current transients and anti-reverse current protection to suppress output voltage rise when the load current direction changes. Specifically, when the LDO's load capacitance is 100pF and the load current is 500uA, for a 10mA / ns forward jump and a 2mA / ns reverse jump in the load current Iload, the output VLDO fluctuation can be limited to within 200mV.

[0108] In an optional embodiment, the transconductance amplifier module 1 includes a common-source cascode amplifier 11 and a CLASS AB bias circuit 12.

[0109] The first control terminal of the common source cascode amplifier 11 is electrically connected to the first control terminal of the CLASS AB bias circuit 12, and the second control terminal of the common source cascode amplifier 11 is electrically connected to the second control terminal of the CLASS AB bias circuit 12.

[0110] The first output terminal of the common source cascode amplifier 11 is electrically connected to the first input terminal of the compensation network module 2, the first input terminal of the buffer module 3, and the first input terminal of the transient enhancement module 5, respectively.

[0111] The second output terminal of the common-source common-gate amplifier 11 is electrically connected to the second input terminal of the compensation network module 2, the second input terminal of the buffer module 3, and the second input terminal of the transient enhancement module 5, respectively.

[0112] In the transconductance amplifier module 1, PM1 and PM2 are the PMOS input differential transistors of the amplifier. The gate voltages of NM1 and NM2 are both provided by the bias voltage VCAS. R1 and PM3-PM6 form a low-voltage current mirror. PM1-PM6, NM1-NM2, and bias current sources I2 and I3 form the main body of the folded cascode amplifier. NM3 and PM7 form a floating current source to drive PM10 and NM6 (buffer module 3). The bias current I5 and PM8 and PM9 bias the gate voltage of PM7 at VCC-V GSPM8 -V GSPM9 At the potential, the bias current I4 and NM4 and NM5 bias the gate voltage of NM3 at GND+V. GSNM5 +V GSNM4 Therefore, the gate bias voltage of PM10 is VCC-V at the given potential. GSPM8 -V GSPM9 +V GSPM7 The gate bias voltage of NM6 is GND+V. GSNM5 +V GSNM4 -V GSNM3 .

[0113] By adjusting the aspect ratios of PM7, PM9, NM3, and NM4, V can be... GSPM7 With V GSPM9 They are basically equal, V GSNM3 With V GSNM4 They are essentially equal; therefore, the gate bias voltage V of PM10 is... GSPM10 =VCC-V GSPM8 The gate bias voltage V of NM6 GSNM6 =GND+V GSNM5 .

[0114] By adjusting the magnitudes of bias currents I4 and I5 and the W (width) / L (length) dimensions of PM8 and NM5, the gate bias potentials of PM10 and NM6 are adjusted so that the static on-current of PM10 and NM6 is adjusted to a suitable magnitude and they operate in CLASSAB state to drive the gate of the subsequent LDO power transistor NM7.

[0115] This embodiment provides a specific implementation of a transconductance amplifier module.

[0116] In an optional embodiment, the common-source common-gate amplifier 11 includes: a first current source I1, a second current source I2, a third current source I3, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, and a first resistor R1.

[0117] The gate of the first PMOS transistor PM1 is used as the non-inverting input terminal of the transconductance amplifier module 1, and the gate of the second PMOS transistor PM2 is used as the inverting input terminal of the transconductance amplifier module 1.

[0118] The input terminal of the first current source I1 is connected to the power supply voltage. The output terminal of the first current source I1 is electrically connected to the source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2. The drain of the second PMOS transistor PM2 is electrically connected to the source of the first NMOS transistor NM1 and the input terminal of the second current source I2. The gate of the first NMOS transistor NM1 is electrically connected to the gate of the second NMOS transistor NM2. The drain of the first PMOS transistor PM1 is electrically connected to the source of the second NMOS transistor NM2 and the input terminal of the third current source I3.

[0119] The drain of the first NMOS transistor NM1 is electrically connected to the first terminal of the first resistor R1, the gate of the third PMOS transistor PM3, and the gate of the fifth PMOS transistor PM5. The sources of the third PMOS transistor PM3 and the fifth PMOS transistor PM5 are both connected to the power supply voltage VCC. The drain of the third PMOS transistor PM3 is electrically connected to the source of the fourth PMOS transistor PM4. The drain of the fourth PMOS transistor PM4 is electrically connected to the second terminal of the first resistor R1. The gate of the fourth PMOS transistor PM4 is electrically connected to the gate of the sixth PMOS transistor PM6. The drain of the fifth PMOS transistor PM5 is electrically connected to the source of the sixth PMOS transistor PM6.

[0120] The drain of the sixth PMOS transistor PM6 is electrically connected to the drain of the third NMOS transistor NM3 and the source of the seventh PMOS transistor PM7, respectively. The drain of the second PMOS transistor PM2 is electrically connected to the source of the third NMOS transistor NM3 and the drain of the seventh PMOS transistor PM7, respectively.

[0121] The source of the seventh PMOS transistor PM7 is used as the first output terminal of the common-source common-gate amplifier 11, the gate of the seventh PMOS transistor PM7 is used as the first control terminal of the common-source common-gate amplifier 11, the source of the third NMOS transistor NM3 is used as the second output terminal of the common-source common-gate amplifier 11, and the gate of the third NMOS transistor NM3 is used as the second control terminal of the common-source common-gate amplifier 11.

[0122] This embodiment provides a specific implementation of a common-source cascode amplifier.

[0123] In an optional embodiment, the CLASS AB bias circuit 12 includes: a fourth current source I4, a fifth current source I5, an eighth PMOS transistor PM8, a ninth PMOS transistor PM9, a fourth NMOS transistor NM4, and a fifth NMOS transistor NM5.

[0124] The gate of the ninth PMOS transistor PM9 is used as the first control terminal of the CLASS AB bias circuit 12, and the gate of the fourth NMOS transistor NM4 is used as the second control terminal of the CLASS AB bias circuit 12.

[0125] The input terminal of the fourth current source I4 and the source terminal of the eighth PMOS transistor PM8 are both connected to the power supply voltage VCC.

[0126] The output terminal of the fourth current source I4 is electrically connected to the gate and drain of the fourth NMOS transistor NM4, respectively. The source of the fourth NMOS transistor NM4 is electrically connected to the drain and gate of the fifth NMOS transistor NM5.

[0127] The source of the ninth PMOS transistor PM9 is electrically connected to the gate and drain of the eighth PMOS transistor PM8, respectively.

[0128] The input terminal of the fifth current source I5 is electrically connected to the gate and drain of the ninth PMOS transistor PM9, respectively.

[0129] The source of the fifth NMOS transistor NM5 and the output of the fifth current source I5 are both grounded.

[0130] This embodiment provides a specific implementation of the CLASS AB bias circuit.

[0131] In an optional embodiment, the compensation network module 2 includes: a second resistor R2, a third resistor R3, a second capacitor C2, and a third capacitor C3.

[0132] The first end of the second resistor R2 is used as the first input terminal of the compensation network module 2, and the first end of the third resistor R3 is used as the second input terminal of the compensation network module 2.

[0133] The second terminal of the second resistor R2 is electrically connected to the first terminal of the second capacitor C2, the second terminal of the second capacitor C2 is electrically connected to the first terminal of the third capacitor C3, and the second terminal of the third capacitor C3 is electrically connected to the second terminal of the third resistor R3.

[0134] The second terminal of the second capacitor C2 is used as the output terminal of the compensation network module 2.

[0135] Among them, R2, C2 and R3, C3 form a Miller compensation network that separates the poles at the output of the cascode amplifier from the poles at the gate of the output stage power transistor NM7.

[0136] This embodiment provides a specific implementation of the compensation network module.

[0137] In an optional embodiment, the buffer module 3 includes a tenth PMOS transistor PM10 and a sixth NMOS transistor NM6.

[0138] The gate of the tenth PMOS transistor PM10 is used as the first input terminal of the buffer module 3, and the gate of the sixth NMOS transistor NM6 is used as the second input terminal of the buffer module 3.

[0139] The source of the tenth PMOS transistor PM10 is connected to the power supply voltage VCC, the drain of the tenth PMOS transistor PM10 is electrically connected to the drain of the sixth NMOS transistor NM6, and the source of the sixth NMOS transistor NM6 is grounded.

[0140] The drain of the tenth PMOS transistor PM10 is used as the output terminal of the buffer module 3.

[0141] In this module, NM3 and PM7 form a floating current source to drive PM10 and NM6. The bias current I5, along with PM8 and PM9, biases the gate voltage of PM7 at VCC-V. GSPM8 -V GSPM9 At the potential, the bias current I4 and NM4 and NM5 bias the gate voltage of NM3 at GND+V. GSNM5 +V GSNM4 Therefore, the gate bias voltage of PM10 is VCC-V at the given potential. GSPM8 -V GSPM9 +V GSPM7 The gate bias voltage of NM6 is GND+V.GSNM5 +V GSNM4 -V GSNM3 .

[0142] By adjusting the aspect ratios of PM7, PM9, NM3, and NM4, V can be... GSPM7 With V GSPM9 They are basically equal, V GSNM3 With V GSNM4 They are essentially equal; therefore, the gate bias voltage V of PM10 is... GSPM10 =VCC-V GSPM8 The gate bias voltage V of NM6 GSNM6 =GND+V GSNM5 .

[0143] By adjusting the magnitudes of bias currents I4 and I5 and the W (width) / L (length) dimensions of PM8 and NM5, the gate bias potentials of PM10 and NM6 are adjusted so that the static on-current of PM10 and NM6 is adjusted to a suitable magnitude and they operate in CLASSAB state to drive the gate of the subsequent LDO power transistor NM7.

[0144] This embodiment provides a specific implementation of the buffer pole module.

[0145] In an optional embodiment, the backflow current absorption module 4 includes an eleventh PMOS transistor PM11.

[0146] The gate of the eleventh PMOS transistor PM11 is used as the input terminal of the reverse current absorption module 4, the source of the eleventh PMOS transistor PM11 is used as the output terminal of the reverse current absorption module 4, and the drain of the eleventh PMOS transistor PM11 is grounded.

[0147] Among them, PM11, as a PMOS transistor that absorbs reverse current, has its source voltage equal to the output voltage VLDO of the LDO and its gate voltage equal to VLDO + V during normal operation. GSNM7 Therefore, V GSPM11 =V GSNM7 At this time, PM11 is in the off state. When current flows into the LDO output port, VLDO will be raised. The voltage divider network composed of R4 and R5 in feedback network module 6 feeds the output voltage back to the input of the amplifier. The output of the amplifier is thus pulled high, thereby pulling down the output of the buffer stage and turning off the power transistor NM7. At this time, the source and gate voltage difference of PM11 is greater than one V. GSPM11 This allows the current injected into the LDO output port to be absorbed.

[0148] This embodiment provides a specific implementation of a backflow current absorption module.

[0149] In an optional embodiment, the transient enhancement module 5 includes a first capacitor C1 and a fourth capacitor C4.

[0150] The first terminal of the first capacitor C1 is used as the first input terminal of the transient enhancement module 5, and the first terminal of the fourth capacitor C4 is used as the second input terminal of the transient enhancement module 5.

[0151] The second terminal of the first capacitor C1 is electrically connected to the second terminal of the fourth capacitor C4.

[0152] The second terminal of the first capacitor C1 is used as the output terminal of the transient enhancement module 5.

[0153] Capacitors C1 and C4 are used to accelerate the large-signal transient response of the LDO. When the LDO output VLDO is pulled low rapidly, the voltage across capacitors C1 and C4 cannot change instantaneously. The gate voltages of PM10 and NM6 will be instantly coupled down, thereby raising the gate voltage of NM7 and pulling VLDO up. Similarly, when VLDO is rapidly raised, the gate voltage of NM7 will be pulled down, thereby quickly turning off the power transistor NM7.

[0154] This embodiment provides a specific implementation of the transient enhancement module.

[0155] In an optional embodiment, the feedback network module 6 includes a fourth resistor R4, a fifth resistor R5, and a seventh capacitor C7.

[0156] The first end of the fourth resistor R4 is used as the first end of the feedback network module 6, and the second end of the fourth resistor R4 is used as the second end of the feedback network module 6.

[0157] The first end of the fourth resistor R4 is electrically connected to the first end of the seventh capacitor C7, and the second end of the fourth resistor R4 is electrically connected to the second end of the seventh capacitor C7 and the first end of the fifth resistor R5.

[0158] The second end of the fifth resistor R5 is used as the ground terminal of the feedback network module 6.

[0159] In this circuit, feedback network module 6 is used to detect the output voltage and transmit the obtained voltage back to the input of the amplifier. Because the negative feedback characteristic of the entire LDO loop makes the input voltage of the amplifier equal, the gate input reference voltage of PM1, Vref = VLDO * R5 / (R4 + R5), and the output voltage of the LDO, VLDO = Vref * (R4 + R5) / R5. C7, R4, and R5 form a zero-pole pair to increase the unity-gain bandwidth (GBW) of the entire LDO loop.

[0160] This embodiment provides a specific implementation of the feedback network module.

[0161] In an optional embodiment, the low-dropout linear regulator may further include a fifth capacitor C5 and a sixth resistor R6.

[0162] The first terminal of the fifth capacitor C5 is electrically connected to the gate of the N-type output power transistor NM7, and the second terminal of the fifth capacitor C5 is grounded.

[0163] The fifth capacitor, C5, is used to stabilize the gate voltage of the N-type output power transistor NM7. Since NM7 is the power transistor of the LDO, its relatively large area results in a large gate-to-source parasitic capacitance C. GSNM7 After adding the fifth capacitor C5, the moment the LDO output is pulled low / high can be considered as C. GSNM7 The voltage division of the output transients by the fifth capacitor C5 reduces the impact of the LDO output on the gate of the power transistor.

[0164] The first terminal of the sixth resistor R6 is electrically connected to the source of the N-type output power transistor NM7, and the second terminal of the sixth resistor R6 is grounded. The sixth resistor R6 provides a resistive load for the LDO, and when the LDO is unloaded, it provides a static bias current to the output stage, thereby reducing the influence of the output poles on the phase margin.

[0165] This embodiment provides another specific implementation of a low-dropout linear regulator.

[0166] Example 2

[0167] This embodiment provides an electronic device, which includes the low dropout linear regulator with on-chip capacitors as described in Embodiment 1.

[0168] In this embodiment, the transconductance amplifier module amplifies the reference voltage, the compensation network module separates the poles of the transconductance amplifier module from the poles of the N-type output power transistor, the buffer module drives the gate of the N-type output power transistor, the reverse current absorption module absorbs the reverse current, the transient enhancement module accelerates the transient response to voltage signals with large amplitude, and the feedback network module detects the output voltage and transmits the obtained voltage back to the input of the transconductance amplifier module. In particular, the transient enhancement module accelerates the transient response to voltage signals with large amplitude through the first capacitor C1 and the fourth capacitor C4. When the output voltage VLDO of the LDO is pulled down rapidly, and the voltage across the first capacitor C1 and the fourth capacitor C4 cannot change instantaneously, the gate voltages of the tenth PMOS transistor PM10 and the sixth NMOS transistor NM6 will be coupled down instantaneously, thereby raising the gate voltage of the N-type output power transistor NM7 and pulling up VLDO. Similarly, when VLDO is raised rapidly, the gate voltage of NM7 will be pulled down, thereby quickly turning off NM7. Furthermore, the reverse current absorption module absorbs reverse current through the eleventh PMOS transistor PM11. When the LDO is operating normally, PM11 is off. When current flows into the LDO output, VLDO is raised. The voltage divider network composed of the fourth resistor R4 and the fifth resistor R5 feeds the output voltage back to the input of the transconductance amplifier module. The output of the transconductance amplifier module is thus pulled high, causing the output of the buffer module to pull low and turn off NM7. At this time, the source and gate voltage difference of PM11 is greater than one V. GSPM11 This allows the current drawn in from the LDO output to be absorbed. This low-dropout linear regulator is suitable for operation of isolated chips in environments with high voltage and high frequency CMT interference. It also features fast transient response and the ability to absorb reverse current, providing good output voltage stability during load current transients and anti-reverse current protection to suppress output voltage rise when the load current direction changes. Specifically, when the LDO's load capacitance is 100pF and the load current is 500uA, for a 10mA / ns forward jump and a 2mA / ns reverse jump in the load current Iload, the output VLDO fluctuation can be limited to within 200mV.

[0169] While specific embodiments of this disclosure have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of this disclosure is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of this disclosure, but all such changes and modifications fall within the scope of protection of this disclosure.

Claims

1. A low-dropout linear regulator employing on-chip capacitors, characterized in that, The low dropout linear regulator includes: a transconductance amplifier module, a compensation network module, a buffer module, a reverse current absorption module, a transient enhancement module, a feedback network module, an N-type output power transistor, and the on-chip capacitor. The output terminal of the transconductance amplifier module is electrically connected to the input terminal of the compensation network module, the input terminal of the buffer module, and the input terminal of the transient enhancement module, respectively. The gate of the N-type output power transistor is electrically connected to the output terminal of the compensation network module, the output terminal of the buffer module, and the input terminal of the reverse current absorption module, respectively. The source of the N-type output power transistor is electrically connected to the output terminal of the reverse current absorption module, the output terminal of the transient enhancement module, the first terminal of the feedback network module, and the first terminal of the on-chip capacitor, respectively. The second terminal of the feedback network module is electrically connected to the inverting input terminal of the transconductance amplifier module; The power supply terminal of the transconductance amplifier module and the drain of the N-type output power transistor are both connected to the power supply voltage. The non-inverting input terminal of the transconductance amplifier module is connected to a reference voltage; The ground terminal of the feedback network module and the second terminal of the on-chip capacitor are both grounded; The non-inverting input terminal of the transconductance amplifier module is used as the input terminal of the low dropout linear regulator, and the source of the N-type output power transistor is used as the output terminal of the low dropout linear regulator to provide the output voltage. The transconductance amplifier module is used to amplify the reference voltage; The compensation network module is used to separate the poles of the transconductance amplifier module from the poles of the N-type output power transistor. The buffer module is used to drive the gate of the N-type output power transistor; The backflow current absorption module is used to absorb backflow current; The transient enhancement module is used to accelerate the transient response to voltage signals with large amplitude; The feedback network module is used to detect the output voltage and transmit the obtained voltage back to the input terminal of the transconductance amplifier module.

2. The low-dropout linear regulator employing on-chip capacitors as described in claim 1, characterized in that, The transconductance amplifier module includes a common-source cascode amplifier and a CLASS AB bias circuit; The first control terminal of the common-source cascode amplifier is electrically connected to the first control terminal of the CLASS AB bias circuit, and the second control terminal of the common-source cascode amplifier is electrically connected to the second control terminal of the CLASS AB bias circuit. The first output terminal of the common source cascode amplifier is electrically connected to the first input terminal of the compensation network module, the first input terminal of the buffer module, and the first input terminal of the transient enhancement module, respectively. The second output terminal of the common-source cascode amplifier is electrically connected to the second input terminal of the compensation network module, the second input terminal of the buffer module, and the second input terminal of the transient enhancement module, respectively.

3. The low-dropout linear regulator employing on-chip capacitors as described in claim 2, characterized in that, The common-source common-gate amplifier includes: a first current source, a second current source, a third current source, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a first resistor; The gate of the first PMOS transistor is used as the non-inverting input terminal of the transconductance amplifier module, and the gate of the second PMOS transistor is used as the inverting input terminal of the transconductance amplifier module. The input terminal of the first current source is connected to the power supply voltage. The output terminal of the first current source is electrically connected to the source of the first PMOS transistor and the source of the second PMOS transistor. The drain of the second PMOS transistor is electrically connected to the source of the first NMOS transistor and the input terminal of the second current source. The gate of the first NMOS transistor is electrically connected to the gate of the second NMOS transistor. The drain of the first PMOS transistor is electrically connected to the source of the second NMOS transistor and the input terminal of the third current source. The drain of the first NMOS transistor is electrically connected to the first terminal of the first resistor, the gate of the third PMOS transistor, and the gate of the fifth PMOS transistor, respectively. The sources of the third PMOS transistor and the fifth PMOS transistor are both connected to the power supply voltage. The drain of the third PMOS transistor is electrically connected to the source of the fourth PMOS transistor. The drain of the fourth PMOS transistor is electrically connected to the second terminal of the first resistor. The gate of the fourth PMOS transistor is electrically connected to the gate of the sixth PMOS transistor. The drain of the fifth PMOS transistor is electrically connected to the source of the sixth PMOS transistor. The drain of the sixth PMOS transistor is electrically connected to the drain of the third NMOS transistor and the source of the seventh PMOS transistor, respectively; the drain of the second PMOS transistor is electrically connected to the source of the third NMOS transistor and the drain of the seventh PMOS transistor, respectively. The source of the seventh PMOS transistor is used as the first output terminal of the common-source common-gate amplifier, the gate of the seventh PMOS transistor is used as the first control terminal of the common-source common-gate amplifier, the source of the third NMOS transistor is used as the second output terminal of the common-source common-gate amplifier, and the gate of the third NMOS transistor is used as the second control terminal of the common-source common-gate amplifier.

4. The low-dropout linear regulator employing on-chip capacitors as described in claim 2, characterized in that, The CLASS AB bias circuit includes: a fourth current source, a fifth current source, an eighth PMOS transistor, a ninth PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor; The gate of the ninth PMOS transistor is used as the first control terminal of the CLASS AB bias circuit, and the gate of the fourth NMOS transistor is used as the second control terminal of the CLASS AB bias circuit. The input terminal of the fourth current source and the source of the eighth PMOS transistor are both connected to the power supply voltage. The output terminal of the fourth current source is electrically connected to the gate and drain of the fourth NMOS transistor, respectively, and the source of the fourth NMOS transistor is electrically connected to the drain and gate of the fifth NMOS transistor. The source of the ninth PMOS transistor is electrically connected to the gate and drain of the eighth PMOS transistor, respectively. The input terminal of the fifth current source is electrically connected to the gate and the drain of the ninth PMOS transistor, respectively. The source of the fifth NMOS transistor and the output of the fifth current source are both grounded.

5. The low-dropout linear regulator employing on-chip capacitors as described in claim 2, characterized in that, The compensation network module includes: a second resistor, a third resistor, a second capacitor, and a third capacitor; The first end of the second resistor is used as the first input terminal of the compensation network module, and the first end of the third resistor is used as the second input terminal of the compensation network module. The second terminal of the second resistor is electrically connected to the first terminal of the second capacitor, the second terminal of the second capacitor is electrically connected to the first terminal of the third capacitor, and the second terminal of the third capacitor is electrically connected to the second terminal of the third resistor. The second terminal of the second capacitor is used as the output terminal of the compensation network module.

6. The low-dropout linear regulator employing on-chip capacitors as described in claim 2, characterized in that, The buffer module includes: a tenth PMOS transistor and a sixth NMOS transistor; The gate of the tenth PMOS transistor is used as the first input terminal of the buffer module, and the gate of the sixth NMOS transistor is used as the second input terminal of the buffer module. The source of the tenth PMOS transistor is connected to the power supply voltage, the drain of the tenth PMOS transistor is electrically connected to the drain of the sixth NMOS transistor, and the source of the sixth NMOS transistor is grounded. The drain of the tenth PMOS transistor is used as the output terminal of the buffer module.

7. The low-dropout linear regulator employing on-chip capacitors as described in claim 1, characterized in that, The reverse current absorption module includes: an eleventh PMOS transistor; The gate of the eleventh PMOS transistor is used as the input terminal of the reverse current absorption module, the source of the eleventh PMOS transistor is used as the output terminal of the reverse current absorption module, and the drain of the eleventh PMOS transistor is grounded.

8. The low-dropout linear regulator employing on-chip capacitors as described in claim 2, characterized in that, The transient enhancement module includes: a first capacitor and a fourth capacitor; The first terminal of the first capacitor is used as the first input terminal of the transient enhancement module, and the first terminal of the fourth capacitor is used as the second input terminal of the transient enhancement module. The second terminal of the first capacitor is electrically connected to the second terminal of the fourth capacitor; The second terminal of the first capacitor is used as the output terminal of the transient enhancement module.

9. The low-dropout linear regulator employing on-chip capacitors as described in claim 1, characterized in that, The feedback network module includes: a fourth resistor, a fifth resistor, and a seventh capacitor; The first end of the fourth resistor is used as the first end of the feedback network module, and the second end of the fourth resistor is used as the second end of the feedback network module. The first end of the fourth resistor is electrically connected to the first end of the seventh capacitor, and the second end of the fourth resistor is electrically connected to the second end of the seventh capacitor and the first end of the fifth resistor, respectively. The second end of the fifth resistor is used as the ground terminal of the feedback network module.

10. An electronic device, characterized in that, The electronic device includes a low-dropout linear regulator employing on-chip capacitors as described in any one of claims 1 to 9.

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