A reference voltage circuit and a dynamic compensation method thereof

Abstract

The application relates to the field of analog and mixed signal integrated circuit design, and provides a reference voltage circuit and a dynamic compensation method thereof, which comprises a reference voltage core module configured to generate a reference voltage; an aging monitoring module comprising a first test device group bearing a working stress and a second test device group in a reference bias state, and used for acquiring an electrical characteristic difference between the two groups of devices in a test mode; a quantization module used for converting the electrical characteristic difference into an aging quantization signal; a digital compensation logic module used for generating a trimming signal based on the aging quantization signal; and a trimming module used for outputting a compensation signal to the reference voltage core module to correct the reference voltage in response to the trimming signal. The application effectively eliminates the full life cycle time drift through differential aging monitoring and digital closed-loop compensation, and the power consumption is extremely low.

Description

Technical Field

[0001] This application relates to the field of analog and mixed-signal integrated circuit design, specifically to a reference voltage circuit and its dynamic compensation method. Background Technology

[0002] In high-precision signal chain systems, the reference voltage source is the cornerstone determining system accuracy. The main sources of error in the reference voltage include initial offset, temperature drift, and time drift. With the miniaturization of semiconductor process nodes, the effects of negative bias temperature instability, hot carrier injection, and packaging stress on devices during long-term operation become increasingly significant, leading to a unidirectional drift in the reference voltage that accumulates over time—i.e., time drift. Existing technologies include ceramic packaging, which reduces stress but is costly; high-temperature aging baking before shipment can only screen out early failures and cannot compensate for long-term drift during end-user use; and chopping or dynamic component matching techniques mainly target periodic noise or random offset, offering limited unidirectional aging compensation for the intrinsic characteristics of devices. Furthermore, traditional analog compensation circuits themselves age over time, introducing new errors. Therefore, there is an urgent need for a reference voltage technology solution that can autonomously monitor the aging degree of devices and perform real-time dynamic compensation throughout the entire chip lifecycle. Summary of the Invention

[0003] To address the problem that existing reference voltage circuits experience unpredictable time drift due to device aging during long-term operation, and that traditional compensation methods cannot effectively eliminate this drift throughout their entire lifespan, this application proposes a reference voltage circuit and its dynamic compensation method. By utilizing a differential aging monitoring structure to extract pure aging characteristics and combining it with a digital closed loop for real-time adjustment, high-precision dynamic compensation for reference voltage time drift is achieved.

[0004] To achieve the above objectives, this application adopts the following technical solution:

[0005] This application provides a reference voltage circuit, comprising: a reference voltage core module configured to generate a reference voltage; an aging monitoring module including a first test device group and a second test device group, wherein the first test device group is configured to withstand working stress in a normal operating mode, and the second test device group is configured to be in a reference bias state in the normal operating mode, and the aging monitoring module is configured to acquire the electrical characteristic difference between the first test device group and the second test device group in a test mode; a quantization module configured to convert the electrical characteristic difference into an aging quantization signal; a digital compensation logic module configured to generate a trimming signal based on the aging quantization signal; and a trimming module configured to output a compensation signal to the reference voltage core module in response to the trimming signal to correct the reference voltage.

[0006] In one implementation, the aging monitoring module further includes a switching unit; in the test mode, the switching unit is configured to switch the first test device group and the second test device group to the same test bias conditions to output a differential signal characterizing the difference in electrical characteristics.

[0007] In one implementation, both the first test device group and the second test device group include PMOS transistors; the gate of the PMOS transistor in the first test device group is grounded to withstand negative bias temperature instability stress.

[0008] The PMOS transistors in the second test device group switch their operating modes via a working switch; the drains of the PMOS transistors in the first test device group and the drains of the PMOS transistors in the second test device group are respectively connected to the differential output node via corresponding test switches, and the differential output node is used to output the differential signal.

[0009] In one implementation, the digital compensation logic module is configured to read lookup table parameters and process corner information from a non-volatile memory, and generate the adjustment signal by two-dimensional interpolation based on the aging quantization signal, the lookup table parameters, and the process corner information.

[0010] In one implementation, the adjustment module includes a switched capacitor network; the switched capacitor network is configured to output a compensation current to the current summing node of the reference voltage core module according to the adjustment signal.

[0011] In one implementation, the reference voltage circuit further includes a timer module; the timer module is configured to periodically trigger a wake-up signal to control the quantization module and the aging monitoring module to power on in the test mode and to power off and go into sleep mode after the test, while controlling the trimming module to maintain the current output state.

[0012] In one implementation, the quantization module is an incremental Sigma-Delta analog-to-digital converter or a successive approximation analog-to-digital converter; the operational amplifier inside the reference voltage core module adopts a chopper-stabilized structure.

[0013] Furthermore, this application also provides a dynamic compensation method for a reference voltage, comprising: applying working stress to a first test device group and placing a second test device group in a reference bias state under normal operating mode; acquiring the electrical characteristic difference between the first test device group and the second test device group in a test mode in response to a periodically triggered wake-up signal; quantizing the electrical characteristic difference into an aging quantization signal; generating a trimming signal based on the aging quantization signal; and outputting a compensation signal to a reference voltage core module that generates the reference voltage in response to the trimming signal, so as to correct the reference voltage.

[0014] As one implementation, obtaining the electrical characteristic difference between the first test device group and the second test device group in the test mode includes: in the test mode, connecting the first test device group and the second test device group to the same test bias node by closing the test switch; and extracting the threshold voltage difference or resistance difference between the first test device group and the second test device group as the electrical characteristic difference.

[0015] As one implementation, generating a trimming signal based on the aging quantization signal includes: reading the process code and the aging quantization signal from a non-volatile memory; performing joint interpolation calculations using a two-dimensional lookup table based on the process code and the aging quantization signal; and outputting the trimming signal for controlling the magnitude and direction of the compensation current.

[0016] Beneficial effects:

[0017] The reference voltage circuit and its dynamic compensation method provided in this application constitute a differential aging monitoring structure by setting up a first group of test devices subjected to working stress and a second group of test devices in a reference bias state. This structure can obtain the difference in electrical characteristics between the two groups of devices in the test mode. Since the two groups of devices are in the same chip environment, the effects of environmental common-mode interference such as temperature fluctuations and power supply noise on both are basically the same. By using a differential method, these environmental factors can be effectively isolated, and the pure aging characteristics caused only by the time accumulation effect can be accurately extracted. This solves the problem that traditional monitoring methods cannot distinguish between environmental interference and true aging.

[0018] Furthermore, this application utilizes a quantization module to convert the extracted electrical characteristic differences into an aging quantization signal, and generates a trimming signal through a digital compensation logic module to control the output compensation signal of the trimming module. This digital closed-loop compensation mechanism avoids the defect of secondary aging drift caused by traditional pure analog compensation circuits due to long-term operation, because the parameters of digital logic and non-volatile memory have extremely high time stability, ensuring the accuracy and reliability of the compensation algorithm throughout its entire life cycle.

[0019] Furthermore, by introducing process corner information and aging quantization signals for two-dimensional interpolation calculations, this application can adapt to the differences in aging rates between different manufacturing batches of chips, significantly improving compensation accuracy. Combined with the periodic wake-up and sleep mechanism controlled by the timer module, the quantization module and aging monitoring module are only powered on during brief testing phases, remaining in a power-off sleep state for the rest of the time, while the trimming module maintains static output. This allows the entire dynamic compensation system to achieve high-precision time drift elimination throughout its entire lifecycle while almost not increasing the system's average static power consumption, meeting the dual requirements of low power consumption and high reliability for high-precision signal chain systems. Attached Figure Description

[0020] Figure 1 This is a block diagram of the reference voltage circuit system architecture according to an embodiment of this application;

[0021] Figure 2 This is a schematic diagram of the differential aging monitoring array principle according to an embodiment of this application;

[0022] Figure 3 This is a topology diagram of the bandgap reference core and the tuned DAC current injection of an embodiment of this application;

[0023] Figure 4 This is a flowchart of the reference voltage dynamic compensation method according to an embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0026] Example 1

[0027] like Figure 1 As shown in the figure, this application provides a reference voltage circuit. This circuit adopts a system architecture that combines differential aging monitoring and digital closed-loop compensation, aiming to achieve dynamic correction of the time drift of the reference voltage throughout its entire life cycle. The reference voltage circuit mainly includes a reference voltage core module, an aging monitoring module, a quantization module, a digital compensation logic module, and a trimming module.

[0028] The reference voltage core module is configured to generate a reference voltage. Specifically, the reference voltage core module serves as the reference source for the entire system, and its output provides a high-precision reference voltage signal for use by external loads or internal circuits. In this embodiment, the reference voltage core module not only has basic voltage generation functions but also reserves a compensation signal injection interface to receive correction amounts from the adjustment module, thereby achieving dynamic adjustment of the output voltage at the physical level. It should be understood that although this embodiment uses a bandgap reference as an example, in other embodiments, the reference voltage core module can also be a reference source built based on Zener diodes, CMOS threshold voltages, or other principles, as long as it has the ability to accept external compensation signals to adjust the output voltage.

[0029] The aging monitoring module includes a first test device group and a second test device group. The first test device group is configured to withstand operating stress in normal operation mode, while the second test device group is configured to be in a reference bias state in normal operation mode. The aging monitoring module is configured to acquire the electrical characteristic difference between the first and second test device groups in test mode. Specifically, the aging monitoring module is the core sensing unit for sensing the degree of chip aging. During normal system operation, the first test device group is subjected to the same or even more stringent bias conditions as the actual working circuit, accelerating the accumulation of aging effects such as negative bias temperature instability or hot carrier injection; while the second test device group remains in a zero bias or low stress state, serving as a reference unaffected by aging. When the system enters test mode, the aging monitoring module, through an internal switching mechanism, places the two groups of devices under identical measurement conditions, thereby outputting a differential signal that only characterizes the pure aging accumulation. The key advantage of this differential structure is that, since the two sets of devices are located on the same chip substrate and are physically close, the common-mode interference such as ambient temperature fluctuations, power supply voltage noise, and packaging stress changes has almost the same effect on both. By performing difference operations, these environmental factors can be effectively isolated, and the device parameter degradation characteristics caused only by time accumulation can be accurately extracted. This solves the technical problem that traditional single-end monitoring methods cannot distinguish between environmental interference and actual aging.

[0030] The quantization module is configured to convert electrical characteristic differences into aging quantization signals. Specifically, the quantization module acts as a bridge between the analog physical world and the digital processing domain. Since the differential signal output by the aging monitoring module is typically a weak analog voltage or current difference, the quantization module uses high-precision analog-to-digital conversion technology to map this analog difference into discrete digital codewords, i.e., the aging quantization signal. This digital signal accurately reflects the aging offset of the chip relative to its initial state at the current moment, providing standardized input data for subsequent digital calculations. In this embodiment, the design focus of the quantization module is on balancing low speed, high precision, and low power consumption, because aging is an extremely slow process that does not require high-speed sampling, but demands extremely high resolution of minute changes.

[0031] The digital compensation logic module is configured to generate a trimming signal based on the aging quantization signal. Specifically, the digital compensation logic module is the computational center of the entire dynamic compensation system. It receives the aging quantization signal from the quantization module and, according to a preset compensation algorithm or lookup table mapping relationship, calculates the correction amount required to eliminate the current aging drift, and then generates the corresponding trimming signal. Unlike traditional analog compensation loops, the processing of the digital compensation logic module is completed entirely in the digital domain. Its computational logic and stored parameters will not undergo aging drift over time, fundamentally avoiding the vicious cycle problem of "compensation circuit aging leading to compensation failure". In addition, digital domain processing facilitates the integration of complex nonlinear compensation algorithms or multidimensional interpolation strategies to adapt to the differences in device aging characteristics under different process corners.

[0032] The adjustment module is configured to respond to the adjustment signal and output a compensation signal to the reference voltage core module to correct the reference voltage. Specifically, the adjustment module, acting as an actuator, converts the digital adjustment signal generated by the digital compensation logic module into a compensation current or voltage in the analog domain and injects it into a specific node of the reference voltage core module. The magnitude and direction of this compensation signal are precisely calculated to precisely offset the reference voltage offset caused by device aging, restoring the output voltage to the nominal accuracy range. Through the coordinated work of the above modules, this embodiment constructs a complete "monitoring-quantification-calculation-correction" digital closed-loop system, realizing the autonomous sensing and real-time compensation of time drift of the reference voltage throughout its entire life cycle, significantly improving the long-term stability and reliability of the high-precision signal chain system.

[0033] Example 2

[0034] like Figure 2As shown, in this embodiment, the aging monitoring module also includes a switching unit. In test mode, the switching unit is configured to switch the first test device group and the second test device group to the same test bias conditions to output a differential signal characterizing the difference in electrical characteristics. Specifically, the switching unit is a key execution component for realizing the differential aging monitoring function. When the chip is in normal operating mode, the first test device group and the second test device group are in different bias states to simulate or avoid aging stress; when the system response timer triggers the test mode, the switching unit operates, forcibly connecting the measurement terminals of the two groups of devices to the same set of test bias circuits or sampling nodes. This dynamic switching mechanism ensures that at the moment of aging characteristic reading, the external electrical environment of the two groups of devices is completely consistent, so that the subsequent output differential signal can truly reflect the intrinsic parameter differences caused by the different historical stress accumulation, rather than the illusion caused by instantaneous environmental fluctuations.

[0035] Furthermore, both the first and second test device groups include PMOS transistors. The gate of the PMOS transistor in the first test device group is grounded to withstand the stress of negative bias temperature instability; the PMOS transistor in the second test device group switches its operating mode via a working switch. Specifically, this embodiment selects PMOS transistors as aging sensing elements because, in advanced CMOS processes, the negative bias temperature instability effect of PMOS transistors is one of the main factors leading to circuit performance degradation. For the first test device group, the gate of its PMOS transistor is continuously connected to ground potential (GND) in normal operating mode, while the source is usually connected to the power supply voltage (VDD). This results in a strong electric field existing at the gate oxide interface for a long time, thereby accelerating the accumulation of interface state trap charges and inducing a significant threshold voltage drift. This drift is closely related to the actual operating time and operating temperature of the chip, effectively simulating the aging trajectory of PMOS devices in the core circuit. In contrast, the PMOS transistors in the second test device group have their gates directly connected to the power supply voltage (VDD) in normal operating mode, making their gate-source voltage approximately zero, thus placing them in a cutoff or zero-bias state. This avoids the application of negative bias temperature instability stress and preserves the initial electrical characteristics of the devices as a pristine reference. It should be understood that although this embodiment uses a PMOS transistor as an example, in other embodiments, if it is necessary to monitor the hot carrier injection effect of NMOS or the aging of other types of devices, the device type and bias polarity can be adjusted accordingly, as long as a differential architecture with one set for stress resistance and one set for reference is met.

[0036] Furthermore, the drains of the PMOS transistors in the first and second test device groups are connected to the differential output node via corresponding test switches. The differential output node is used to output differential signals. Specifically, the test switches here are one of the specific implementations of the aforementioned switch unit. In test mode, these test switches are closed, leading out the drain potentials of the two PMOS transistors and converging them to the differential output node, or directly connecting them to the differential input of the quantization module. Since the two groups of devices typically adopt a matching layout with common centroid or cross-coupling on the layout, and their physical positions are close together, the interference signals they experience, such as ambient temperature gradients, power supply voltage ripple, and substrate noise, are highly correlated and manifest as common-mode signals. When the drain voltage difference or current difference between the two is extracted differentially, these rapidly changing environmental common-mode interferences are largely canceled out, while the threshold voltage mismatch caused by long-term stress accumulation is completely preserved as a differential-mode signal. This hardware-level common-mode rejection capability fundamentally solves the technical problem that traditional single-ended aging monitoring solutions are easily misled by environmental noise and have difficulty distinguishing between real aging and transient interference, providing a high signal-to-noise ratio pure aging data foundation for subsequent digital compensation logic.

[0037] Example 3

[0038] In this embodiment, the digital compensation logic module is configured to read lookup table parameters and process corner information from the non-volatile memory, and generate a trimming signal through two-dimensional interpolation based on the aging quantization signal, lookup table parameters, and process corner information. Specifically, this feature constitutes the core algorithm of the dynamic compensation system, aiming to address the impact of inherent process deviations in semiconductor manufacturing on the accuracy of aging compensation. Because transistors at different process corners (such as TT, SS, FF, etc.) exhibit significant differences in the degradation rate of negative bias temperature instability or hot carrier injection effect under the same stress conditions, one-dimensional compensation based solely on a single aging quantization signal can easily lead to overcompensation or undercompensation in different batches of chips. Therefore, this embodiment introduces process corner information as a second dimension for compensation calculation. The non-volatile memory pre-stores lookup table parameters characterizing the three-dimensional relationship of "aging degree - process corner - compensation amount," which are typically calibrated and programmed during the chip factory testing phase through accelerated aging experiments. In actual operation, the digital compensation logic module uses the real-time acquired aging quantization signal and the chip's inherent process corner code as a joint index, and performs two-dimensional interpolation in a lookup table to accurately map the adjustment signal required for the specific chip in its current aging state. It should be understood that although this embodiment uses two-dimensional lookup table interpolation as an example, in other embodiments, polynomial fitting based on process corner partitioning, neural network models, or other equivalent mathematical mapping methods can also be used to achieve the above multidimensional compensation calculation, as long as the compensation amount can be jointly determined based on the aging state and process characteristics. This adaptive compensation mechanism effectively eliminates the impact of wafer-level and even batch-level process discreteness on long-term stability, ensuring that each chip receives personalized and accurate correction.

[0039] Furthermore, the adjustment module includes a switched capacitor network, which is configured to output a compensation current to the current summation node of the reference voltage core module based on the adjustment signal. For example... Figure 3As shown, the trimming module employs a switched-capacitor architecture with excellent anti-aging characteristics in its physical implementation, rather than a traditional resistive digital-to-analog converter. This is because, over tens of thousands of hours of operation, polysilicon resistors or diffused resistors themselves will experience resistance drift due to factors such as electromigration and thermal stress. If a resistive DAC is used as the compensation execution unit, its own drift will be directly superimposed on the reference voltage, leading to the paradox of "using aged devices to compensate for aging," ultimately causing compensation failure. In contrast, the equivalent impedance of the switched-capacitor network depends only on the capacitance ratio and the clock frequency. On-chip metal-insulator-metal capacitors or metal-oxide-metal capacitors have extremely high time and temperature stability, and the clock frequency is usually provided by a high-stability crystal oscillator or phase-locked loop, which hardly degrades over time. Therefore, the trimming module built based on the switched-capacitor network can maintain a constant conversion gain throughout its entire lifespan, fundamentally ensuring the long-term accuracy of the compensation signal. In the specific circuit connection, the switched-capacitor network selectively conducts the forward compensation current source or the reverse compensation current source according to the control of the trimming signal, corresponding to... Figure 3 The I_comp+ and I_comp- branches are used in the reference voltage core module. These two compensation currents are precisely injected into the current summation node inside the reference voltage core module. This node is typically the confluence point of the positive and negative temperature coefficient currents in the bandgap reference core, or a critical node in the operational amplifier's feedback loop. By superimposing or extracting microampere-level or even nanoampere-level compensation current at this node, the output level of the reference voltage can be directly adjusted, achieving closed-loop correction of aging drift. Furthermore, the operating frequency of the switched capacitor network is much higher than the reference voltage loop bandwidth; the high-frequency ripple it generates can be naturally filtered out by the low-pass filter characteristics inside the reference voltage core module, without negatively impacting the noise performance of the output voltage.

[0040] Example 4

[0041] In this embodiment, the reference voltage circuit also includes a timer module. The timer module is configured to periodically trigger a wake-up signal to control the quantization module and aging monitoring module to power on in test mode and power off and go into sleep mode after the test, while simultaneously controlling the trimming module to maintain its current output state. Specifically, the timer module is the key timing control center for achieving ultra-low power operation of the system. Given that the aging of semiconductor devices is an extremely slow physical accumulation process, with parameter changes typically measured in hours, days, or even months, continuous real-time monitoring is completely unnecessary. Therefore, this embodiment employs a duty cycle operating mode, with the timer module generating periodic wake-up pulses. When the wake-up signal is valid, the quantization module and aging monitoring module switch from deep sleep to operating state, performing a complete aging feature extraction and digitization conversion; once data processing is complete, these two modules immediately power off and enter sleep mode, thereby cutting off the main dynamic power consumption path. Simultaneously, the trimming module is designed with a state-holding function; even during the power-off period of the quantization module and aging monitoring module, the trimming module can still latch the previously calculated trimming signal and continuously provide a stable compensation current or voltage to the reference voltage core module. This design ensures that the reference voltage output remains continuous and corrected with high precision throughout its entire lifespan, avoiding reference voltage jumps or interruptions caused by intermittent operation of auxiliary circuits. Through this mechanism combining time-division multiplexing and state maintenance, the average static current increase of the entire dynamic compensation system is negligible, perfectly resolving the contradiction between high-precision monitoring and low-power consumption requirements.

[0042] Furthermore, the quantization module is either an incremental Sigma-Delta analog-to-digital converter (ADC) or a successive approximation ADC. Specifically, this selection is a targeted optimization based on the unique physical properties of the aging monitoring signal. The electrical characteristic difference caused by aging is typically a weak DC signal in the microvolt or even nanovolt range, with an extremely low rate of change. This places special requirements on the DC accuracy, low-frequency noise suppression capability, and power consumption of the ADC, while the conversion speed requirement is not high. The incremental Sigma-Delta ADC, through oversampling and digital filtering techniques, can effectively suppress low-frequency 1 / f noise and thermal noise, achieving extremely high resolution and linearity, making it very suitable for extracting minute aging drift. The successive approximation ADC, while ensuring sufficient accuracy, has lower power consumption and faster settling time, making it suitable for applications sensitive to area and instantaneous power consumption. Both architectures belong to the low-speed, high-precision type, naturally matching the low-frequency characteristics of aging monitoring. This avoids the resource waste caused by using high-performance but high-power ADCs such as high-speed pipelined ADCs, ensuring that the quantization stage meets the detection sensitivity requirements without becoming a power bottleneck for the system.

[0043] Furthermore, the operational amplifier within the reference voltage core module employs a chopper-stabilized structure. Specifically, the performance stability of the reference voltage core module itself is crucial during long-term aging monitoring and compensation. If the core op-amp has a large initial offset or offset drift that varies with time and temperature, these errors will be directly superimposed on the reference voltage output, potentially even drowning out the valid aging differential signal and causing misjudgment by the compensation algorithm. Chopper stabilization technology, by modulating the input signal to a high-frequency band for amplification and then demodulating it back to baseband, can shift the op-amp's DC offset and 1 / f noise to a high frequency and have them filtered out by subsequent filters, thereby achieving near-zero offset and high common-mode rejection ratio DC amplification performance. In this embodiment, the op-amp employing a chopper-stabilized structure not only ensures the long-term purity of the reference voltage core module's output but also provides an extremely stable reference for the aging monitoring module, enabling weak aging characteristic signals to be accurately perceived without interference from the non-ideal characteristics of the core circuit itself. It should be understood that although the preferred structure in this embodiment is chopper stabilization, in other embodiments, if the process conditions allow or the system accuracy requirements are different, other offset elimination techniques such as automatic zeroing can also be used, as long as the purpose of eliminating the influence of the operational amplifier's own drift on aging monitoring can be achieved.

[0044] Example 5

[0045] like Figure 4 As shown, this application provides a dynamic compensation method for a reference voltage. This method is implemented based on the circuit architecture described in the foregoing embodiments and aims to dynamically eliminate the time drift of the reference voltage throughout its entire lifecycle through a time-sequential closed-loop control process. This dynamic compensation method mainly includes a stress application stage, a periodic wake-up monitoring stage, a quantization evaluation stage, a lookup and calculation stage, a current injection compensation stage, and a sleep and hold stage. It should be understood that although... Figure 4 The method demonstrates a linear process sequence, but in actual operation, it is executed continuously in a loop iteration manner, and the timing of each stage is uniformly scheduled by the timer module.

[0046] Step S100: In normal operating mode, working stress is applied to the first test device group, and the second test device group is placed in a reference bias state. Specifically, this is the passive accumulation stage of aging characteristics, which occupies most of the chip's operating time. During this stage, the reference voltage circuit is in a normal voltage output operating state, while the first and second test device groups inside the aging monitoring module maintain preset bias conditions. For example, referring to the description of Embodiment 2, the PMOS transistor in the first test device group has its gate grounded and its source connected to the power supply voltage, thereby bearing the negative bias temperature instability stress and simulating the aging trajectory of the PMOS device in the core circuit during actual operation; while the PMOS transistor in the second test device group has its gate connected to the power supply voltage and is in a zero bias or off state, serving as an original reference unaffected by stress. This stage does not require the intervention of additional monitoring circuits, relying solely on physical mechanisms to naturally accumulate aging differences, thus not increasing the real-time power consumption burden of the system. Through this differentiated stress application strategy, it is ensured that the subsequently extracted difference signal can truly reflect the time accumulation effect, rather than instantaneous environmental fluctuations.

[0047] Step S200: In response to a periodically triggered wake-up signal, the electrical characteristic difference between the first test device group and the second test device group is acquired in test mode. Specifically, when the wake-up signal generated by the timer module is valid, the system briefly switches from normal operating mode to test mode. In this mode, in order to accurately extract pure aging characteristics, the measurement error introduced by the different current operating environments of the two groups of devices must be eliminated. Therefore, this step further includes: in test mode, connecting the first test device group and the second test device group to the same test bias node by closing the test switch. For example, the switch unit operates, forcing the drains of the first test device group and the second test device group to be simultaneously connected to the differential input terminal of the quantization module or the same set of test current sources. Since the two groups of devices are highly matched and physically adjacent on the layout, the environmental common-mode interference they experience, such as temperature and power supply noise, is completely consistent, and these common-mode components can be canceled out by differential means. Subsequently, the threshold voltage difference or resistance difference between the first test device group and the second test device group is extracted as the electrical characteristic difference. This difference is the pure aging characterization quantity after eliminating environmental interference, and its value directly corresponds to the degree of aging accumulated by the chip since it left the factory. This mechanism of "differentiated stress during normal operation and comparison under the same conditions during measurement" is the core prerequisite for achieving high-precision aging monitoring.

[0048] Step S300 involves quantizing the electrical characteristic difference into an aging quantization signal. Specifically, the quantization module powers on during the wake-up period and converts the analog-domain electrical characteristic difference obtained in step S200 into a digital-domain aging quantization signal. As described in Example 4, the quantization module can employ an incremental Sigma-Delta analog-to-digital converter or a successive approximation analog-to-digital converter to adapt to the weak and slowly changing characteristics of the aging signal. The resulting aging quantization signal is a discrete digital codeword, and its resolution determines the adjustment accuracy of the compensation system. This step completes the transition from the physical world to the digital processing domain, providing a standardized data foundation for subsequent algorithm calculations.

[0049] Step S400: Generate a trimming signal based on the aging quantization signal. Specifically, after receiving the aging quantization signal, the digital compensation logic module does not simply map it to a compensation amount, but rather performs adaptive calculations based on the individual chip's process characteristics. This step further includes: reading the process corner code and aging quantization signal from the non-volatile memory; and performing joint interpolation calculations using a two-dimensional lookup table based on the process corner code and aging quantization signal to output a trimming signal used to control the magnitude and direction of the compensation current. For example, the non-volatile memory pre-stores a two-dimensional lookup table calibrated during the factory testing phase. This table records the optimal compensation code value corresponding to different aging levels under different process corners (such as TT, SS, FF). The digital compensation logic module uses the current process corner code and the real-time aging quantization signal as two-dimensional indices to perform interpolation operations in the lookup table, thereby obtaining a precisely matched trimming signal. This joint interpolation mechanism effectively solves the problem of inconsistent aging rates caused by differences in manufacturing batches, avoiding the risks of overcompensation or undercompensation caused by "one-size-fits-all" compensation. Meanwhile, the generated adjustment signal contains directional information, which can instruct the adjustment module to output positive or negative compensation current to cope with the positive or negative drift of the reference voltage that may be caused by aging.

[0050] In step S500, in response to the adjustment signal, a compensation signal is output to the reference voltage core module that generates the reference voltage to correct the reference voltage. Specifically, the adjustment module adjusts the conduction state or equivalent impedance of its internal switched capacitor network according to the adjustment signal generated in step S400, thereby injecting a precisely calculated compensation current into the current summation node of the reference voltage core module. This compensation current is superimposed on the original PTAT and CTAT currents of the reference voltage core module, directly changing the level of the output voltage and bringing it back to the nominal accuracy range. For example, if aging is detected to have caused the reference voltage to deviate by +50uV, the adjustment module will output a compensation current corresponding to a correction of -50uV to offset it. Because the adjustment module adopts an anti-aging switched capacitor architecture, its own conversion gain remains highly stable throughout its entire life cycle, ensuring the long-term effectiveness of the compensation action.

[0051] In step S600, after the test is completed, the quantization module and aging monitoring module are powered off and put into sleep mode, while the adjustment module maintains its current output state until the next wake-up. Specifically, after a complete monitoring and compensation update is completed, the timer module controls the quantization module and aging monitoring module to immediately power off and enter a deep sleep state to cut off the dynamic power consumption path. At the same time, the registers or latches inside the adjustment module keep the adjustment signal set in step S500 unchanged and continue to provide a stable compensation current to the reference voltage core module. This "intermittent monitoring, continuous compensation" working mode enables the entire dynamic compensation system to achieve time drift elimination throughout its entire life cycle while the average static current increase is almost zero, perfectly balancing the dual requirements of high accuracy and low power consumption. The system then returns to step S100 to enter the next monitoring cycle (e.g., 24 hours), and so on, achieving lifelong protection against time drift of the reference voltage.

[0052] Example 6

[0053] To more clearly illustrate the implementation process and beneficial effects of the technical solution of this application in practical engineering applications, the following uses a 1.2V bandgap reference voltage circuit applied in a high-precision analog-to-digital converter or power management chip as an example to provide a detailed description of the full life-cycle dynamic compensation mechanism provided by this application. It should be understood that the following description is merely an exemplary application scenario and is not intended to limit the scope of protection of this application. Other types of reference voltage sources or other application environments can also be implemented with reference to this embodiment.

[0054] During the chip manufacturing testing phase, automated testing equipment extracts and programs individual process features and parameters for each chip. Specifically, the automated testing equipment accurately determines the process corner type of the chip, such as typical, slow, or fast, by measuring the frequency of the on-chip ring oscillator or the threshold voltage of a specific test structure. Subsequently, this process corner information, along with pre-calibrated two-dimensional lookup table parameters, is programmed into non-volatile memory. This process lays the data foundation for adaptive compensation during subsequent terminal operation, ensuring that the digital compensation logic module can accurately correct for individual chip manufacturing differences, rather than using a uniform average compensation strategy. This effectively eliminates the negative impact of wafer-level and even batch-level process dispersion on long-term stability.

[0055] When the chip is first powered on in the terminal system, the reference voltage core module starts up and immediately loads the initial calibration code from non-volatile memory, outputting a 1.2V reference voltage with compliant accuracy for system use. Simultaneously, the timer module begins timing and enters a low-power standby state. In this application scenario, the timer module is configured to trigger a wake-up signal every 24 hours to perform periodic self-calibration. This 24-hour monitoring cycle is based on the physical mechanism of semiconductor device aging. Because aging effects such as negative bias temperature instability are extremely slow cumulative processes, high-frequency monitoring is not only unnecessary but also wastes valuable system power resources.

[0056] When the 24-hour countdown is complete, the timer module sends a wake-up pulse, and the quantization module and aging monitoring module immediately switch from deep sleep to power-on operation. Within a brief test window (typically a few microseconds to milliseconds), the switching unit inside the aging monitoring module activates, switching the first test device group, which has undergone 24 hours of operating stress, and the second test device group, which is in a zero-bias reference state, to the same test bias condition, extracting the threshold voltage difference between the two as a pure aging characteristic signal. The quantization module converts this analog difference into a digital aging quantization signal. Subsequently, the digital compensation logic module reads the process code from the non-volatile memory and the current aging quantization signal, performs joint interpolation calculations using a two-dimensional lookup table, and generates a precise adjustment signal. For example, if the monitoring calculates that aging has caused a positive drift of +50uV in the reference voltage, the digital compensation logic module will output the corresponding adjustment code, controlling the adjustment module to inject a compensation current equivalent to a -50uV correction into the current summation node of the reference voltage core module, thereby accurately pulling the output voltage back to the nominal value. After the compensation update is completed, the quantization module and aging monitoring module immediately power off and go into sleep mode, while the trimming module latches the current trimming code and maintains the compensation current output unchanged until the next 24-hour cycle arrives. The average static current increase during the entire self-calibration process is almost zero, perfectly balancing the requirements of high-precision monitoring and ultra-low power consumption.

[0057] Through the aforementioned closed-loop dynamic compensation throughout the entire lifecycle, the reference voltage circuit provided in this application exhibits significantly superior long-term stability compared to traditional solutions. In traditional technologies, bandgap references relying solely on factory-calibrated or analog-compensated bandgap references typically exhibit time drift of around 100ppm / 1000 hours, which is insufficient to meet the stringent requirements of 16-bit and higher precision signal chain systems. However, by adopting the technical solution of this application, the differential aging monitoring structure effectively isolates common-mode interference from environmental factors such as temperature fluctuations and power supply noise. The digital compensation logic avoids secondary aging of the analog circuit itself, and the switched-capacitor type trimming module possesses extremely high time stability. This allows the long-term time drift of the reference voltage to be reduced to below 10ppm / 1000 hours, an improvement of more than an order of magnitude. This performance leap is not a simple parameter optimization but rather stems from the qualitative change brought about by the systematic architectural innovation of "differential sensing - digital closed loop - anti-aging execution," fully demonstrating the practical value and innovative level of this application in high-precision, long-life application scenarios.

[0058] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A reference voltage circuit, characterized in that, include: The core module for reference voltage is configured to generate a reference voltage. An aging monitoring module includes a first test device group and a second test device group. The first test device group is configured to withstand working stress in a normal operating mode, and the second test device group is configured to be in a reference bias state in the normal operating mode. The aging monitoring module is configured to acquire the electrical characteristic difference between the first test device group and the second test device group in a test mode. The quantization module is configured to convert the electrical characteristic difference into an aging quantization signal; The digital compensation logic module is configured to generate a trimming signal based on the aging quantization signal; The adjustment module is configured to output a compensation signal to the reference voltage core module in response to the adjustment signal, so as to correct the reference voltage.

2. The reference voltage circuit according to claim 1, characterized in that, The aging monitoring module also includes a switching unit; In the test mode, the switching unit is configured to switch the first test device group and the second test device group to the same test bias conditions to output a differential signal characterizing the difference in electrical characteristics.

3. The reference voltage circuit according to claim 2, characterized in that, Both the first test device group and the second test device group contain PMOS transistors; The gate of the PMOS transistor in the first test device group is grounded to withstand the stress of negative bias temperature instability. The PMOS transistors in the second test device group switch their operating modes via a working switch; The drains of the PMOS transistors in the first test device group and the drains of the PMOS transistors in the second test device group are respectively connected to the differential output node through corresponding test switches. The differential output node is used to output the differential signal.

4. The reference voltage circuit according to claim 1, characterized in that, The digital compensation logic module is configured to read the lookup table parameters and process corner information in the non-volatile memory, and generate the adjustment signal by two-dimensional interpolation based on the aging quantization signal, the lookup table parameters, and the process corner information.

5. The reference voltage circuit according to claim 4, characterized in that, The tuning module includes a switched capacitor network; The switched capacitor network is configured to output a compensation current to the current summation node of the reference voltage core module according to the adjustment signal.

6. The reference voltage circuit according to claim 1, characterized in that, It also includes a timer module; The timer module is configured to periodically trigger a wake-up signal to control the quantization module and the aging monitoring module to power on in the test mode and power off and go into sleep mode after the test is completed, while controlling the tuning module to maintain the current output state.

7. The reference voltage circuit according to claim 6, characterized in that, The quantization module is an incremental Sigma-Delta analog-to-digital converter or a successive approximation analog-to-digital converter. The operational amplifier inside the reference voltage core module adopts a chopper-stabilized structure.

8. A dynamic compensation method for a reference voltage, characterized in that, include: In normal operating mode, working stress is applied to the first test device group, and the second test device group is in a reference bias state. In response to a periodically triggered wake-up signal, the electrical characteristic difference between the first test device group and the second test device group is acquired in test mode; The electrical characteristic difference is quantized into an aging quantization signal; A trimming signal is generated based on the aging quantization signal; In response to the adjustment signal, a compensation signal is output to the reference voltage core module that generates the reference voltage to correct the reference voltage.

9. The dynamic compensation method according to claim 8, characterized in that, The step of obtaining the electrical characteristic difference between the first test device group and the second test device group in test mode includes: In the test mode, the first test device group and the second test device group are connected to the same test bias node by closing the test switch; The threshold voltage difference or resistance difference between the first test device group and the second test device group is extracted as the electrical characteristic difference.

10. The dynamic compensation method according to claim 8, characterized in that, The generation of the adjustment signal based on the aging quantization signal includes: Read the process corner code and the aging quantization signal from the non-volatile memory; Based on the process corner code and the aging quantization signal, a joint interpolation calculation is performed using a two-dimensional lookup table to output the adjustment signal used to control the magnitude and direction of the compensation current.

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