A high-precision chirp frequency control system and method based on multi-stage DDS cooperative regulation

Abstract

The application relates to a high-precision chirp frequency control system and method based on multi-stage DDS cooperative regulation, belonging to the field of quantum precision measurement, and comprising a high-stability reference clock source, a front-stage DDS system, a rear-stage DDS system and a cooperative control module. The front-stage DDS system provides a working reference clock for the rear-stage DDS system, and the rear-stage DDS system generates a ladder-shaped linear chirp signal through a digital ramp generator. The cooperative control module updates the front-stage frequency control word according to the target chirp rate of each chirp under the condition that the rear-stage time control word and the frequency increment control word remain unchanged, thereby changing the working reference clock frequency and making the chirp rate change by a preset chirp rate step, and simultaneously updating the rear-stage sweep upper and lower limit control word to compensate for the sweep boundary offset. The application breaks the coupling between the chirp rate resolution and the frequency update time precision, improves the chirp rate resolution while maintaining the microsecond-level frequency update capability, and can be used for Raman light frequency difference control of an atomic interference gravimeter.

Description

Technical Field

[0001] This invention relates to the fields of direct digital frequency synthesis and quantum precision measurement technology, specifically to a high-precision chirped frequency control system and method based on the coordinated control of multi-level direct digital frequency synthesizers. It can be used for chirped control of Raman laser frequency difference in atomic interferometers such as atomic interferometers, atomic interferometers, and gravity gradiometers, and can also be used in other quantum precision measurement and radio frequency control scenarios that require high-resolution linear frequency sweep signals. Background Technology

[0002] An atomic interferometer is a precision measuring device that utilizes the coherent superposition effect of atomic matter waves to measure physical quantities. It can be used to measure physical quantities such as gravitational acceleration, inertial acceleration, rotational angular velocity, and gravitational gradient. In cold atom absolute gravimeters, stimulated Raman transitions are typically used to split, reflect, and combine atomic matter wave packets. A typical atomic interference sequence consists of three Raman laser pulses spaced T apart. Atomic interference fringes are obtained by detecting the populations of atoms in different internal states, and the measured physical quantity is deduced from the interference phase.

[0003] Cold atoms fall freely under gravity, and their velocity along the Raman light propagation direction changes continuously over time, causing a constant alteration in the Doppler frequency shift of the atoms relative to the Raman laser. To compensate for the constantly changing Doppler frequency shift during the free fall of the atoms and to maintain the resonance condition for two-photon Raman transitions, an approximately linear frequency chirp needs to be applied to the frequency difference between the two Raman laser beams. Let the chirp rate of the Raman frequency difference be... Ignoring phase shifts in other systems, the atomic interference phase can be expressed as:

[0004] in, For the effective wave vector of the Raman transition, It is the acceleration due to gravity. Let be the time interval between adjacent Raman pulses. The above equation shows that the atomic interference phase caused by gravitational acceleration is... The compensation phase introduced by the additional Raman light frequency chirp is When the Raman light frequency difference chirp rate is adjusted to an appropriate value, the two cancel each other out, causing the total interference phase to approach zero, thus positioning the atomic interference output at the central fringe. Simultaneously, an appropriate frequency chirp helps maintain the resonance condition and high transition efficiency of two-photon Raman transitions during Raman pulses, reducing the adverse effects of frequency detuning on the contrast of the interference fringes. Therefore, in actual measurements using an atomic gravimeter, gravitational acceleration is usually not obtained by directly measuring the distance the atoms fall, but rather by adjusting the Raman light frequency difference chirp rate to position the atomic interferometer at the central fringe or a preset phase operating point. When the system locks onto the central fringe, Thus, we obtain the acceleration due to gravity:

[0005] The above relationship also shows that chirp rate error directly translates into gravity measurement error. If there is an error in the Raman optical frequency difference chirp rate... The corresponding equivalent gravity error is:

[0006] For 780nm backpropagating Raman light, 1μGal (i.e. The equivalent change in gravity corresponds to a chirp rate change of approximately 0.0255 Hz / s. Therefore, as atomic gravimeters develop towards micro-gal, sub-micro-gal, and even higher precision, the resolution setting of the Raman optical frequency difference chirp rate, frequency step error, phase continuity, and long-term stability will all become important factors affecting the final gravity measurement performance.

[0007] Existing atomic gravimeters typically use a single Direct Digital Synthesizer (DDS) chip to generate Raman chirp signals via linear frequency sweep or digital ramp functions. While DDS offers advantages such as programmability, fast switching speed, and phase controllability, its output frequency can only be updated according to finite time intervals and integer frequency control words. Therefore, the actual output is a stepped chirp, not an ideal continuous linear chirp. Consequently, DDS generation of Raman chirp presents at least two problems related to finite resolution. The first is chirp rate quantization error, meaning the target chirp rate cannot be precisely represented by the integer frequency increment control word of the DDS, but only by adjacent discrete values. This error is directly mapped to gravity calculation error according to the aforementioned relationship. The second type is stepped chirp deviation. Even if the average chirp rate is correct, the DDS output is still not an ideal continuous ramp, but maintains a constant frequency within each frequency step time interval. This stepped waveform has a periodic frequency residual relative to the ideal linear chirp, which will introduce additional phase deviation during the Raman pulse action. Its magnitude is related to the frequency step height, the frequency step time interval, the Raman pulse width, and the relative timing between the chirp start time and the interference pulse sequence.

[0008] Further analysis of the mechanism by which a single-stage DDS generates a stepped linear chirp reveals that the DDS forms a stepped frequency sweep by accumulating an integer frequency increment control word within a fixed update interval. Let the system clock frequency of the DDS be... The frequency increment control word width is The frequency increment control word is DFTW, and the time interval between two adjacent frequency steps is... Then the frequency change of a single frequency step is Therefore, the chirp rate is:

[0009] Since DFTW can only take integer values, at the system clock frequency and frequency step time interval Under fixed conditions, the chirp rate can only be determined according to... The variation in frequency step length. Shortening the time interval between adjacent frequency steps. While increasing the time interval can improve the temporal precision of frequency updates, it increases the minimum chirp rate adjustment step size. Increasing this time interval can decrease the minimum chirp rate adjustment step size and improve the chirp rate adjustment resolution, but it will reduce the temporal precision of frequency updates and prolong the duration of a single frequency step. In other words, in a single-stage DDS scheme, the chirp rate adjustment resolution and the temporal precision of frequency updates are coupled and cannot be optimized simultaneously.

[0010] The closest prior art to this invention is a scheme that uses a high-resolution DDS with automatic linear frequency sweeping to generate Raman optical frequency difference chirp signals. Among these, the AD9852 and AD9854 employ 48-bit frequency control words, 48-bit frequency increment control words, and 20-bit ramp rate control words, representing high-resolution single-chip chirp signal generation devices. They can automatically generate stepped linear chirp signals by setting the start frequency, frequency increment, and time interval between adjacent frequency steps. Taking the AD9854 operating at a 300MHz system clock as an example, its minimum frequency increment is approximately... That is, about When the frequency step time interval is 1 μs, the minimum chirp rate adjustment interval corresponding to adjacent integer frequency increments is approximately 1.066 Hz / s, which corresponds to an equivalent gravity change of approximately 41.6 μGal according to the above conversion relationship. When the frequency step time interval increases to 10 μs, the chirp rate adjustment interval can be reduced to approximately 0.1066 Hz / s, which corresponds to an equivalent gravity change of approximately 4.16 μGal.

[0011] It is evident that even when using a high-resolution DDS with 48-bit frequency increment control capability, its chirp rate adjustment resolution is still coupled with the frequency step time interval. The existing technology has the following drawbacks: First, to obtain sub-microgal level chirp rate adjustment capability, the frequency step time interval must be significantly increased, which will prolong the duration of a single frequency step, increase the frequency deviation of the actual step chirp from the ideal linear chirp, and introduce additional interference phase during Raman pulse action; Second, if the frequency step time interval is shortened to maintain microsecond level frequency update capability, the minimum adjustment step size of the chirp rate will increase to the equivalent gravity level of tens of microgal, which cannot meet the sub-microgal measurement requirements; Third, in closed-loop feedback measurement, the chirp rate correction amount calculated by the feedback loop is usually not an integer multiple of the above-mentioned inherent quantization interval, and can only be rounded to the nearest possible value. The chirp rate rounding error introduced by this can be up to half a quantization interval, which is about 0.533 Hz / s under the condition of 1 μs frequency step time interval, corresponding to a gravity measurement deviation of about 20.9 μGal, directly limiting the accuracy of operating point locking and gravity tracking.

[0012] Therefore, how to break free from the coupling between chirp rate adjustment resolution and frequency update time precision while maintaining the advantages of DDS digitization, phase continuity and high-speed update, and further improve the chirp rate adjustment accuracy, is a key technical problem that urgently needs to be solved in atomic interferometric gravity measurement and related quantum precision measurement systems. Summary of the Invention

[0013] To address the problems of excessive coupling between chirp rate adjustment resolution and frequency update time precision, as well as excessive chirp rate quantization and rounding errors in existing technologies, this invention provides a high-precision chirp frequency control system and method based on multi-level DDS collaborative control. This invention no longer relies on changing the integer frequency increment control word of the subsequent DDS system to adjust the chirp rate. Instead, while keeping the time control word and frequency increment control word of the subsequent DDS system unchanged, it utilizes the high-bit-width frequency control word of the preceding DDS system to finely adjust the working reference clock frequency of the subsequent DDS system and synchronously compensates for the sweep boundary offset caused by changes in the working reference clock frequency. This improves the chirp rate adjustment resolution by several orders of magnitude while maintaining microsecond-level frequency update capability.

[0014] One of the technical solutions of this invention is a high-precision chirped frequency control system based on multi-level DDS coordinated regulation, comprising a highly stable reference clock source, a front-stage DDS system, a rear-stage DDS system, and a coordinated control module. The highly stable reference clock source provides a reference clock to the front-stage DDS system; the output of the front-stage DDS system is connected to the external reference clock input of the rear-stage DDS system, used to generate and adjust the working reference clock of the rear-stage DDS system; the rear-stage DDS system includes a digital ramp generator, used to generate a stepped linear chirped signal driven by the working reference clock, and its output is used to connect to the controlled object; the coordinated control module is connected to the configuration port and synchronization control port of the front-stage DDS system, and also to the configuration port and synchronization control port of the rear-stage DDS system.

[0015] The collaborative control module is configured to: in the output sequence consisting of multiple chirps, keep the time control word and frequency increment control word of the subsequent DDS system unchanged, update the frequency control word of the preceding DDS system according to the target chirp rate of each chirp, so as to change the working reference clock frequency of the subsequent DDS system, so that the chirp rate between two adjacent chirps changes according to the preset chirp rate step; and synchronously update the sweep frequency lower limit control word and sweep frequency upper limit control word of the subsequent DDS system according to the updated working reference clock frequency, so as to compensate for the sweep frequency lower limit frequency and sweep frequency upper limit frequency offset caused by the change of the working reference clock frequency.

[0016] The multi-stage DDS system referred to in this invention means that the overall system contains at least two DDS systems that work collaboratively according to a reference clock transmission or chirp signal synthesis relationship. The preceding-stage DDS system specifically refers to the DDS system that directly provides the working reference clock to the following-stage DDS system, and the following-stage DDS system specifically refers to the DDS system that generates chirp signals under the drive of this working reference clock. The preceding-stage and following-stage DDS systems constitute the core functional combination of this invention, but it is not limited to the overall system containing only two DDS systems; in other embodiments, one or more additional DDS systems can be set upstream of the preceding-stage DDS system to form a three-stage or more DDS structure. Regardless of how many stages of DDS the overall system contains, as long as the aforementioned collaborative control relationship between the preceding-stage and following-stage DDS systems exists, the parameter calculation and synchronization control method described in this invention can be used. For ease of symbol representation, this invention uses symbol (1) to represent the control parameters corresponding to the front-end DDS system and symbol (2) to represent the control parameters corresponding to the back-end DDS system. For parameters that need to distinguish between target values ​​and actual values, an asterisk is used to represent the target value or ideal value before control word quantization, and the corresponding symbol without an asterisk represents the actual value after control word rounding and quantization.

[0017] The collaborative control module determines the first according to the following formula. The ideal operating reference clock frequency corresponding to this chirp :

[0018] in, For the first The target chirp rate for each chirp. This is the clock scaling factor for the ramp timer inside the subsequent DDS system. This is the time control word for the subsequent DDS system. For the frequency increment control word of the subsequent DDS system, This is the frequency increment control word width for the subsequent DDS system. The target chirp rate is determined by... This indicates that the sweep direction is determined by the digital ramp control signal of the subsequent DDS system.

[0019] The collaborative control module determines the first according to the following formula. The frequency control word of the preceding DDS system corresponding to this chirp. and the actual reference clock frequency after quantization. :

[0020]

[0021] in, This is the reference clock frequency input to the preceding DDS system. The frequency control word width of the preceding DDS system, This indicates rounding to the nearest integer. The actual reference clock frequency after quantization of the frequency control word of the preceding DDS system. Typically compared to the ideal operating reference clock frequency There are slight quantitative differences.

[0022] At the actual reference clock frequency Below, the single frequency step variation and the time interval between adjacent frequency steps in the subsequent DDS system are as follows:

[0023]

[0024] Therefore, the first The actual chirp rate achieved by each chirp is:

[0025] As can be seen from the above formula, the chirp rate is proportional to the square of the reference clock frequency. Therefore, the relative change in the reference clock frequency is approximately half the relative change in the chirp rate. The obtained ideal operating reference clock frequency should be within the suitable output frequency range preset by the preceding DDS system; if the calculation result exceeds this range, the initial calculation reference can be reselected. Or adjust the time control word .

[0026] Since different target chirps correspond to different output reference clock frequencies of the front-end DDS system, if the sweep lower limit control word and sweep upper limit control word of the rear-end DDS system remain unchanged, its actual sweep lower limit frequency and sweep upper limit frequency will also change proportionally with the corresponding reference clock frequency. To keep the actual sweep upper and lower limits corresponding to different chirps near preset values, let the sweep boundary control word width of the rear-end DDS system be [value missing]. The target frequency sweep lower limit frequency is The target frequency sweep upper limit is ,and Then the first The lower and upper sweep control words corresponding to the next chirp are as follows:

[0027]

[0028] The compensated lower limit frequency and upper limit frequency of the actual frequency sweep are as follows:

[0029]

[0030] Therefore, between each chirp, the frequency increment control word of the subsequent DDS system... and time control words The frequency control word of the pre-stage DDS system remains unchanged. and the frequency sweep lower limit control word of the subsequent DDS system and sweep frequency upper limit control word The chirp rate is updated accordingly based on the target chirp rate. Through the above collaborative calculation, on the one hand, the high-bit-width frequency control capability of the front-end DDS system is used to achieve fine-step adjustment of the chirp rate, and on the other hand, the upper and lower limit offsets of the sweep frequency caused by the change of the reference clock of the back-end DDS system are compensated, so that each chirp can achieve high-resolution step changes of the chirp rate while maintaining the preset upper and lower limit frequencies of the sweep frequency.

[0031] The second technical solution of this invention is a high-precision chirp frequency control method based on multi-level DDS collaborative regulation, comprising: acquiring the target sweep frequency lower limit, the target sweep frequency upper limit, the initial target chirp rate, the target frequency step time interval, the chirp rate step, and the number of chirps; using a frequency near the preset output frequency of the preceding DDS system as the initial calculation reference, determining the time control word and frequency increment control word of the following DDS system, and keeping them unchanged throughout the entire output sequence; for the nth chirp in the output sequence, calculating the required ideal operating reference clock frequency according to its target chirp rate, and determining the frequency of the preceding DDS system accordingly. The frequency control word is calculated, and the sweep frequency lower limit control word and sweep frequency upper limit control word of the subsequent DDS system are calculated according to the actual working reference clock frequency after quantization; a parameter sequence is formed according to the chirp sequence number and stored; during the parameter switching stage between two adjacent chirps, the next set of parameters is called from the parameter sequence, the next set of parameters is written into the configuration buffer register of the front-end DDS system and the subsequent DDS system, and parameter update signals are simultaneously output to the two-stage DDS system to make the corresponding parameters take effect synchronously. Then, a digital ramp control signal is output to the subsequent DDS system to determine the sweep frequency direction and control the subsequent DDS system to output the corresponding linear chirp signal.

[0032] Compared with the prior art, the present invention has the following beneficial effects.

[0033] First, improve chirp rate adjustment resolution. While keeping the time control word and frequency increment control word of the subsequent DDS system constant, the high-bit-width frequency control word of the preceding DDS system finely adjusts the operating reference clock frequency of the subsequent DDS system. This allows the chirp rate variation between adjacent chirps to be significantly smaller than the inherent quantization interval of the subsequent DDS system under a fixed reference clock, determined by the integer frequency increment control word. This improves chirp rate adjustment resolution while maintaining microsecond-level frequency update capability. Since the parameters of the preceding DDS system only need to be updated between adjacent chirps and are not directly limited by the frequency step time interval within a single chirp of the subsequent DDS system, finer chirp rate steps can be achieved. The actual achievable minimum step size is mainly affected by factors such as the bit width of the preceding DDS system's frequency control word, reference clock stability, phase noise, and device quantization errors.

[0034] Second, it reduces stepped chirp error. Traditional single-stage DDS systems typically require increasing the frequency step time interval to achieve higher chirp rate adjustment resolution, but this also prolongs the duration of the frequency step and increases the frequency deviation of the actual stepped chirp from the ideal linear chirp. This invention finely adjusts the operating reference clock of the subsequent DDS system through the preceding DDS system, eliminating the need to increase the frequency step time interval of the subsequent DDS system to refine the chirp rate step between adjacent chirps. Therefore, it can maintain a shorter frequency step time interval while improving chirp rate adjustment resolution. This helps reduce the additional interference phase caused by stepped frequency error during Raman pulse application, thus reducing the impact of stepped chirp deviation on gravity measurement results.

[0035] Third, it improves the adjustment accuracy of closed-loop feedback compensation. During continuous measurements with an atomic gravimeter, the required chirp rate correction for the next measurement cycle can be determined based on the gravity value, interference phase, or corresponding error signal obtained from the previous atomic interferometry measurement or a previous set of measurements. For traditional single-stage DDS systems using a fixed reference clock, limited by the integer frequency increment control word quantization interval, when the required chirp rate correction is less than the inherent quantization interval, or cannot be expressed as an integer multiple of the inherent quantization interval, it can only be rounded to an adjacent realizable value. This introduces chirp rate rounding error during the feedback update process, causing the actual applied feedback correction to deviate from the theoretically required value. This invention allows the chirp rate used in two consecutive measurement cycles to be adjusted with smaller variations, thereby more accurately realizing the chirp rate correction calculated by the feedback control. It reduces chirp rate rounding error and residual compensation error during the feedback update process, which helps to keep the atomic interferometer's operating point more stably near the center fringe or other preset operating points, and improves the accuracy and stability of gravity acceleration tracking and measurement results.

[0036] Fourth, improve the synchronization of sequence switching. The configuration parameters of the preceding and following DDS systems corresponding to each chirp in the output sequence are pre-calculated by the host computer and stored and retrieved by the MCU according to the chirp sequence number. The FPGA generates parameter switching trigger signals according to a preset timing sequence. Based on this, the MCU reads the next set of configuration parameters from the parameter array in the running memory and writes them into the two-stage DDS systems. After writing is completed, the corresponding parameters of the two-stage DDS systems are synchronized and take effect through parameter update signals. The FPGA then controls the following-stage DDS system to complete the corresponding linear chirped output through digital ramp control signals. This enables deterministic switching and continuous automatic output of multiple sets of chirped parameters, reduces the uncertainty introduced by host computer communication, real-time parameter calculation, and software execution delay between each chirp, and improves the synchronization, repeatability, and automation of the chirped sequence output.

[0037] Fifth, maintain stable sweep frequency boundaries. While adjusting the operating reference clock frequency of the subsequent DDS system using the preceding DDS system, recalculate the lower and upper sweep frequency control words of the subsequent DDS system based on the change in the operating reference clock frequency. This compensates for the actual sweep frequency lower and upper limit offsets caused by changes in the operating reference clock. This ensures that signals corresponding to different chirp rates maintain a basically consistent sweep frequency range, avoiding the introduction of additional overall frequency offsets during chirp rate adjustment. This is beneficial for maintaining the frequency matching conditions for two-photon transitions between atoms and Raman light and improves the consistency of the Doppler frequency shift compensation process. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of a two-stage structure of a high-precision chirped frequency control system with multi-stage DDS coordinated regulation according to the present invention.

[0039] Figure 2 This is a schematic diagram showing the composition of the collaborative control module in this invention, as well as the connection between the parameter switching trigger signal, configuration interface, parameter update signal, and digital ramp control signal and the two-level DDS system.

[0040] Figure 3 This is a flowchart of the high-precision chirp frequency control method of the present invention.

[0041] Figure 4 This is a timing diagram of the chirp sequence parameter switching and sweep direction control in this invention.

[0042] Figure 5 This is a schematic diagram of a three-stage structure of a high-precision chirped frequency control system with multi-stage DDS coordinated regulation according to the present invention.

[0043] In the diagram: 100 - High-stability reference clock source, 110 - Frequency reference unit, 120 - Frequency synthesis unit, 200 - Pre-stage DDS system, 210 - Pre-stage DDS chip, 220 - Pre-stage output filtering and amplitude adjustment circuit, 300 - Post-stage DDS system, 310 - Post-stage DDS chip, 320 - Digital ramp generator, 330 - Post-stage output filtering and amplitude adjustment circuit, 400 - Cooperative control module, 410 - Host computer parameter calculation unit, 420 - MCU configuration control unit, 421 - Non-volatile memory unit, 422 - Running memory parameter array, 430 - FPGA timing control unit, 500 - Frequency modulation link, 510 - Controlled object, 600 - Additional DDS system. Detailed Implementation

[0044] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The following embodiments are only used to illustrate the technical solution of the present invention and do not constitute a limitation on the scope of protection of the present invention. Equivalent substitutions, parameter adjustments, and device replacements made by those skilled in the art based on the following embodiments without departing from the concept of the present invention all fall within the scope of protection of the present invention.

[0045] Example 1.

[0046] like Figure 1 As shown, the high-precision chirped frequency control system based on multi-level DDS collaborative regulation in this embodiment employs a front-stage DDS system 200 and a rear-stage DDS system 300 to form a two-stage DDS structure, and includes a highly stable reference clock source 100 and a collaborative control module 400. The two-stage DDS structure is a specific implementation of the multi-stage DDS system of this invention and does not constitute a limitation on the overall number of DDS stages.

[0047] A high-stability reference clock source 100 provides a low-phase-noise, high-stability reference signal to the preceding DDS system 200. It includes a frequency reference unit 110 and a frequency synthesis unit 120. The frequency reference unit 110 can employ a temperature-controlled crystal oscillator, a rubidium atomic clock, or other frequency references. The frequency synthesis unit 120 converts the low-frequency reference signal output from the frequency reference unit 110 into a high-frequency reference clock required by the preceding DDS system 200 through multi-stage frequency multiplication or phase-locked loop frequency synthesis. The output of the high-stability reference clock source 100 is connected to the reference clock input of the preceding DDS system 200, providing it with a frequency of [frequency value missing]. The reference clock.

[0048] The pre-stage DDS system 200, serving as a fine-tuning clock stage, includes a pre-stage DDS chip 210 and the peripheral circuitry required for its normal operation. The peripheral circuitry includes a power supply circuit, a control interface circuit, and a pre-stage output filtering and amplitude adjustment circuit 220. The pre-stage DDS chip 210 has a bit width of [missing information]. The frequency control word can be used to... The frequency interval is finely adjusted to adjust the output reference clock frequency. The signal generated by the front-end DDS chip 210 is subjected to harmonic suppression and amplitude shaping by the front-end output filtering and amplitude adjustment circuit 220, and then sent from the output terminal of the front-end DDS system 200 to the external reference clock input terminal of the rear-end DDS system 300 as the working reference clock of the rear-end DDS chip 310.

[0049] The post-stage DDS system 300, serving as a chirp signal synthesis stage, includes a post-stage DDS chip 310 and its peripheral circuitry required for normal operation. The peripheral circuitry includes a power supply circuit, a control interface circuit, and a post-stage output filtering and amplitude adjustment circuit 330. The post-stage DDS chip 310 internally houses a digital ramp generator 320, whose sweep frequency lower limit control word is configured by the collaborative control module 400. Frequency sweep upper limit control word Frequency increment control word and time control words The configuration parameters become the currently valid configuration under the action of the parameter update signal. The digital ramp generator then generates a stepped linear chirp signal according to the corresponding frequency sweep direction under the control of the digital ramp control signal. The chirp signal output by the subsequent DDS system 300 is processed by the subsequent output filtering and amplitude adjustment circuit 330 and then applied to the controlled object 510 through the frequency modulation link 500. The controlled object 510 can be an acousto-optic modulator, an electro-optic modulator, a microwave device, or a phase-locked loop, used to apply the generated chirp signal to the frequency difference of the Raman laser or other controlled physical quantities.

[0050] The collaborative control module 400 is connected to the configuration ports and parameter update ports of the front-end DDS system 200 and the rear-end DDS system 300, respectively, and is also connected to the digital ramp control port of the rear-end DDS system 300. It is used to collaboratively calculate, configure and time-control the control parameters of the front-end DDS system 200 and the rear-end DDS system 300 based on the target sweep frequency lower limit, target sweep frequency upper limit, target chirp rate, target frequency step time interval and chirp rate step.

[0051] like Figure 2 As shown, the collaborative control module 400 includes a host computer parameter calculation unit 410, an MCU configuration control unit 420, and an FPGA timing control unit 430.

[0052] The host computer parameter calculation unit 410 allows users to set the target sweep frequency lower limit. Target sweep frequency limit Initial target chirp rate Target frequency step time interval Chirp rate step size between adjacent chirps The system calculates the number of chirps and pre-calculates the configuration parameters of the preceding DDS system 200 and the following DDS system 300 corresponding to each chirp. A parameter sequence corresponding to each chirp is then formed according to the chirp sequence number and sent to the MCU configuration control unit 420. Since all parameters are calculated at once before the chirp sequence starts, no real-time floating-point operations or host computer communication are required during the chirp sequence output process.

[0053] The MCU configuration control unit 420 stores the received parameter sequence in the non-volatile memory unit 421. During system initialization or parameter loading operations, the MCU reads and parses each set of parameters from the non-volatile memory unit 421, stores them sequentially in the running memory parameter array 422 according to the chirp sequence number, and reads the first set of parameters from the running memory parameter array 422. It then writes the first set of parameters into the configuration buffer registers of the front-end DDS system 200 and the back-end DDS system 300 through the SPI interface or other configuration interfaces. After writing, the MCU outputs parameter update signals to the two-stage DDS systems, so that the first set of parameters becomes the initial valid configuration.

[0054] The FPGA timing control unit 430 generates two types of cooperating timing control signals. The first type is a parameter switching trigger signal, which is sent to the MCU configuration control unit 420 to trigger the MCU to call the next set of chirp parameters. The second type is a digital ramp control signal, which only acts on the downstream DDS system 300 and is used to control the sweep direction of the current linear chirp, thereby realizing a linear sweep from low frequency to high frequency or from high frequency to low frequency. The parameter update signal is different from the above-mentioned digital ramp control signal. The parameter update signal is generated by the MCU configuration control unit 420 after the configuration parameters of the two-stage DDS system are written, and acts on both the upstream DDS system 200 and the downstream DDS system 300.

[0055] like Figure 4 As shown, after the current chirping process ends, the FPGA timing control unit 430 sends a parameter switching trigger signal to the MCU configuration control unit 420. The MCU reads the next set of configuration parameters from the running memory parameter array 422 according to the current parameter index, and writes the set of configuration parameters into the corresponding configuration buffer registers of the front-end DDS system 200 and the back-end DDS system 300 through the configuration interface. After the parameters are written, the MCU configuration control unit 420 outputs parameter update signals to both the front-end DDS system 200 and the back-end DDS system 300, so that the frequency control word of the front-end DDS system 200 and the sweep frequency lower limit control word and sweep frequency upper limit control word of the back-end DDS system 300 are synchronized to become the current valid configuration. Subsequently, the FPGA timing control unit 430 sends a digital ramp control signal to the back-end DDS system 300. The level of this signal controls the sweep frequency direction of the next linear chirping, where a high level corresponds to scanning from low frequency to high frequency, and a low level corresponds to scanning from high frequency to low frequency. By repeating the above parameter calling, configuration writing, synchronous update and frequency sweep control process, the chirp rate of each chirp in the output sequence is finely adjusted according to a predetermined step size.

[0056] Example 2.

[0057] like Figure 3As shown, this embodiment provides the collaborative calculation process for the control parameters of the front-end DDS system 200 and the back-end DDS system 300. To unify the notation, the frequency tuning word (FTW) of the DDS is denoted as FTW, and the superscripts (1) and (2) are used to represent the control parameters corresponding to the front-end DDS system and the back-end DDS system, respectively; the superscript "" is used to represent the target value or ideal value before the control word is quantized, and the corresponding symbol without the superscript "" represents the value actually realized after the control word is rounded and quantized.

[0058] Step S1: Set the target sweep frequency lower limit through the host computer parameter calculation unit 410. Target sweep frequency limit Initial target chirp rate Target frequency step time interval Chirp rate step size between adjacent chirps And the number of chirps. For an output sequence consisting of multiple chirps, the number of chirps is... The target chirp rate for each chirp is:

[0059] in, The chirp sequence number is used, and in this invention, the chirp sequence number starts counting from 0, i.e. Corresponding to the first chirp, The second chirp corresponds to the second chirp, and so on. Indicates the first The actual chirp rate per chirp.

[0060] Step S2: Determine the fixed control parameters of the downstream DDS system 300. Select a suitable frequency near the preset output frequency of the upstream DDS system 200 as the initial calculation reference, denoted as . The aforementioned This is only used for the initial calculation of integer control parameters in the subsequent DDS system and does not represent the ideal operating reference clock frequency or the actual reference clock frequency after control word quantization that the preceding DDS system ultimately needs to output. Assume the time control word of the subsequent DDS system 300 is an integer control quantity. This is used to determine the time interval between two adjacent frequency updates, and its internal ramp timer clock scaling factor is... The corresponding time control word is:

[0061] Based on the initial target chirp rate Time interval between the target frequency step The initial target single-step frequency change is calculated as follows:

[0062] Assume the frequency increment control word of the downstream DDS system 300 is an integer control quantity. Its width is The corresponding frequency increment control word is:

[0063] After determining the time control word of the downstream DDS system 300 and frequency increment control word Subsequently, all subsequent chirps in the output sequence remain unchanged. Instead of adjusting the chirp rate by changing the integer frequency increment control word of the subsequent DDS system, the chirp rate is adjusted by adjusting the reference clock frequency of the output of the preceding DDS system.

[0064] Step S3: Inverse calculation of the first... The ideal operating reference clock frequency required for the chirp. Let the chirp be... The target chirping rate for each chirp is... The ideal operating reference clock frequency that the front-end DDS system 200 needs to provide to the back-end DDS system 300 is: When the reference clock frequency of the downstream DDS system 300 is At that time, the change in a single frequency step corresponding to the frequency increment control word is:

[0065] At the reference clock frequency, the time interval between two adjacent frequency steps corresponding to the time control word is:

[0066] According to the definition of linear chirp rate, the target chirp rate is equal to the ratio of the change in a single frequency step to the time interval between the corresponding frequency steps, that is:

[0067] Therefore, we can find the first... The ideal operating reference clock frequency corresponding to this chirp:

[0068] As can be seen from the above formula, the chirp rate is proportional to the square of the reference clock frequency. Therefore, the relative change in the reference clock frequency is approximately half the relative change in the chirp rate. The obtained ideal operating reference clock frequency should be within the suitable output frequency range preset by the front-end DDS system 200; if the calculation result exceeds this range, the initial calculation reference can be reselected. Or adjust the time control word .

[0069] Step S4: Determine the frequency control word of the front-end DDS system 200. Assume the reference clock frequency input to the front-end DDS system 200 is... The frequency control word width of the pre-stage DDS system is Then the first The frequency control word of the preceding DDS system corresponding to this chirp is:

[0070] Since the frequency control word must be an integer, the actual reference clock frequency output by the front-end DDS system 200 and provided to the back-end DDS system 300 is:

[0071] At the actual reference clock frequency, the actual single frequency step variation, actual frequency step time interval, and actual chirp rate of the subsequent DDS system 300 are as follows:

[0072]

[0073]

[0074] Step S5: Compensation of sweep frequency upper and lower limit control words. Since different target chirp rates correspond to different output reference clock frequencies of the front-end DDS system, if the sweep frequency lower limit control word and sweep frequency upper limit control word of the rear-end DDS system 300 remain unchanged, then its actual sweep frequency lower limit and sweep frequency upper limit will also change proportionally with the corresponding reference clock frequency. Let the sweep frequency boundary control word width of the rear-end DDS system be... The target frequency sweep lower limit frequency is The target frequency sweep upper limit is ,and Then the first The lower and upper sweep control words corresponding to the next chirp are as follows:

[0075]

[0076] The compensated lower limit frequency and upper limit frequency of the actual frequency sweep are as follows:

[0077]

[0078] Therefore, between each chirp, the frequency increment control word of the subsequent DDS system... and time control words The frequency control word of the front-end DDS system and the lower and upper sweep control words of the back-end DDS system remain unchanged, and are updated accordingly based on the target chirp rate.

[0079] Step S6: Formation and storage of parameter sequences. The host computer parameter calculation unit 410 forms multiple sets of configuration parameters according to the chirp sequence number and sends them to the MCU configuration control unit 420. The MCU saves each set of configuration parameters in the non-volatile storage unit 421, and reads and parses the configuration parameters during system initialization or parameter loading operation, stores them in the running memory parameter array 422 according to the chirp sequence number, and writes the initial parameter set into the two-level DDS system as the initial valid configuration.

[0080] Step S7: When it is necessary to switch to the configuration parameters corresponding to the next chirp, the FPGA timing control unit 430 generates a parameter switching trigger signal. The MCU selects the next set of configuration parameters from the parameter array in a predetermined order and writes them into the configuration buffer registers of the front-end DDS system 200 and the back-end DDS system 300 respectively through the configuration interface. After the parameters are written, the MCU outputs parameter update signals to both the front-end DDS system 200 and the back-end DDS system 300, so that the frequency control word of the front-end DDS system and the sweep frequency lower limit control word and sweep frequency upper limit control word of the back-end DDS system take effect synchronously. Subsequently, the FPGA timing control unit 430 outputs a digital ramp control signal to the back-end DDS system 300. The sweep frequency direction is determined by the level state of this signal. The back-end DDS system 300 performs a linear sweep frequency according to the currently configured frequency increment and frequency step time interval.

[0081] Example 3.

[0082] To verify the high-precision chirp frequency control method proposed in this invention, this embodiment uses the AD9912 chip and its supporting peripheral circuits to construct a front-end DDS system 200, and the AD9910 chip and its supporting peripheral circuits to construct a rear-end DDS system 300. Both DDS systems are equipped with corresponding power supply, control interfaces, output filtering, and amplification circuits. The front-end DDS system will be referred to as the AD9912 system, and the rear-end DDS system as the AD9910 system. The AD9910 serves as the main chirp signal generator, generating a stepped linear chirp signal through an internal digital ramp generator 320. The AD9912 system serves as a high-resolution reference clock adjustment unit, achieving fine adjustment of the chirp rate between adjacent chirps by changing the operating reference clock frequency of the AD9910 system.

[0083] The system uses a highly stable reference clock source 100 to generate a 1GHz reference clock as the reference clock for the AD9912 system. The AD9912 system outputs a signal of approximately 350MHz as the reference clock for the AD9910 system. The AD9912 system has a 48-bit frequency control word, i.e. Its theoretical frequency adjustment step size at a 1GHz reference clock is Approximately Therefore, the reference clock of the AD9910 system can be fine-tuned with high precision without changing the frequency increment control parameters and time control parameters during a single chirp of the AD9910. For the AD9910 system used in this embodiment, its frequency increment control word width... Frequency sweep boundary control word width Clock scaling factor of internal digital ramp timer .

[0084] This embodiment takes the AD9910 system output frequency linearly scanned from 30MHz to 40MHz as an example, which is the target sweep frequency lower limit frequency. Target frequency sweep upper limit Initial target chirp rate (Right now ), the target chirp rate step between adjacent chirps Target frequency step time interval The frequency sweep range described above is only used to illustrate the parameter calculation process and does not constitute a limitation on the output frequency range of this invention; the actual frequency sweep range can be set according to the specific experimental system and subsequent frequency modulation link.

[0085] Determine the fixed control parameters of the AD9910 system Let the forward time control word of the AD9910 system be... The positive frequency increment control word is In this embodiment, 350MHz is selected near the preset output frequency of the AD9912 system as the initial calculation reference for the integer control parameters of the subsequent DDS system. Based on the target frequency step time interval The forward time control word for the AD9910 system is:

[0086] Based on the initial target chirp rate Time interval between the target frequency step The target single-step frequency change is:

[0087] For the AD9910 system used in this embodiment, its frequency increment control word width is 32 bits, i.e. Therefore, the positive frequency increment control word is:

[0088] Therefore, in this embodiment, the forward time control word and the forward frequency increment control word of the AD9910 system are determined to be:

[0089]

[0090] Both remain unchanged throughout the chirping sequence.

[0091] Calculate the AD9912 system control word corresponding to the first chirp. The ideal initial reference clock frequency required for the AD9912 system output is derived from the initial target chirp rate:

[0092] This is approximately 350.8747199087016MHz, which is still close to the preset operating frequency of approximately 350MHz. The AD9912 system has a reference clock of 1GHz and a frequency control word width of 48 bits; therefore, its frequency control word is:

[0093] After rounding the control word, the actual reference clock frequency output by the AD9912 system and provided to the AD9910 system is:

[0094] Under this actual reference clock, the actual frequency step time interval of the AD9910 system is:

[0095] It is evident that the frequency step time interval is not strictly equal to 1 μs, but rather remains on the order of approximately 1 μs. The actual frequency step for each update by the AD9910 system is:

[0096] This yields the actual chirp rate:

[0097] Its error compared to the target value of 25,000,000 Hz / s is:

[0098] For those using reverse propagation Raman light For an atomic gravimeter, the equivalent gravitational acceleration error corresponding to this chirp rate error is:

[0099] Therefore, the quantized actual chirp rate is highly consistent with the target value, and its corresponding equivalent gravitational acceleration error is several orders of magnitude lower than the actual measurement accuracy of existing atomic gravimeters, which is in the sub-microgal to microgal range. Thus, this invention can reduce the error caused by the quantization of frequency chirp control words to a level far below the actual measurement accuracy of existing atomic gravimeters, making chirp rate quantization error no longer a major technical bottleneck restricting the improvement of the measurement sensitivity and accuracy of atomic gravimeters.

[0100] Calculate the reference clock for the next chirp. The target chirp rate for the second chirp is:

[0101] Maintaining the time control word of the AD9910 system and frequency increment control word Under the condition that remains unchanged, the ideal operating reference clock frequency required for the AD9912 system output can be calculated by reverse calculation:

[0102] Therefore, the change in the ideal operating reference clock frequency output by the AD9912 system between two consecutive chirps is:

[0103] This change is consistent with the aforementioned relationship that "the relative change in the reference clock frequency is approximately one-half of the relative change in the chirp rate".

[0104] The AD9912 system frequency control word corresponding to the second chirp is:

[0105] The phase difference of the AD9912 system frequency control word corresponding to the two chirps:

[0106] After frequency control word quantization, the actual output frequency of the AD9912 system corresponding to the second chirp is:

[0107] The actual output frequency corresponding to the first chirp is approximately 350874719.9087026Hz. Therefore, the change in the actual output frequency of the AD9912 system after quantization between two adjacent chirps is:

[0108] Its value is basically consistent with the aforementioned ideal operating reference clock frequency variation of 0.0701749Hz, and the difference between the two is only about 1.7e-6Hz, indicating that the error caused by the 48-bit frequency control word quantization of the AD9912 system to the adjacent chirped reference clock frequency step is small.

[0109] The actual frequency step time interval, actual frequency step, and actual chirp rate of the second chirp are as follows:

[0110]

[0111]

[0112] Therefore, the actual change in chirp rate between the two chirps is:

[0113] Relative to target step size The error is:

[0114] This demonstrates that when the AD9912 system works in conjunction with the AD9910 system, it can achieve a high-resolution chirp rate step of close to 0.01 Hz / s.

[0115] Frequency sweep upper and lower limit control word compensation For the AD9910 system used in this embodiment, the bit width of both the lower sweep limit control word and the upper sweep limit control word is 32 bits, i.e. The lower and upper frequency sweep control words for the first chirp are as follows:

[0116]

[0117] The corresponding actual lower limit frequency and actual upper limit frequency for frequency sweep are as follows:

[0118]

[0119] The deviations from the target values ​​of 30MHz and 40MHz are approximately 0.007Hz and 0.018Hz, respectively.

[0120] For the second chirp with a chirp rate increase of 0.01 Hz / s, after recalculating the upper and lower limit control words, the integer rounding result is still:

[0121] This is because a single 0.01Hz / s step corresponds to a reference clock change of only about 0.07Hz, which is insufficient to change the least significant bit of the 32-bit sweep frequency upper and lower limit control word. Nevertheless, the host computer parameter calculation unit 410 recalculates the corresponding sweep frequency upper and lower limit control word for each target chirp rate: when a single change or cumulative change in the chirp rate causes a change in the recalculated sweep frequency upper and lower limit control word, the system writes the new control word into the AD9910 system to compensate for the sweep frequency lower and upper limit frequency offsets caused by changes in the reference clock frequency; when the rounding result of the control word remains unchanged, the original control word is kept unchanged. Through this method, sweep frequency boundary offsets can be continuously compensated under conditions of large-range chirp rate scanning or long-term cumulative adjustment.

[0122] Corresponding equivalent change in gravity For backpropagation Raman spectroscopy has the following properties:

[0123] in, The effective wave vector for the Raman transition. When the chirp rate step size is approximately At that time, the corresponding equivalent change in gravity is approximately:

[0124] Therefore, the chirp rate step implemented in this embodiment corresponds to the equivalent gravity adjustment step size on the submicrogal scale, which is beneficial to improving the precision of chirp rate scanning and interference fringe locking in the atomic gravimeter.

[0125] If only the AD9910 system is used to generate the chirp signal, under the conditions of a reference clock of approximately 350MHz and an adjacent frequency step time interval of approximately 1μs, the change in chirp rate corresponding to each change of the least significant bit of its 32-bit frequency increment control word is approximately Therefore, while the AD9910 system can achieve microsecond-level frequency updates and high-speed linear frequency sweeps, it struggles to achieve fine-grained chirp rate adjustment below 1 Hz / s using only its integer frequency increment control word. The AD9854 system, employing a 48-bit frequency control word and a 48-bit frequency increment control word, exhibits high frequency and increment resolution under a 300 MHz reference clock. When the time interval between adjacent frequency steps is 1 μs, its minimum chirp rate adjustment interval is approximately 1.066 Hz / s, corresponding to an equivalent gravitational change of approximately 41.6 μGal. When the time interval between adjacent frequency steps increases to 10 μs, its minimum chirp rate adjustment interval can be reduced to approximately 0.1066 Hz / s, corresponding to an equivalent gravitational change of approximately 4.16 μGal. Therefore, traditional single-stage DDS usually needs to increase the time interval between adjacent frequency steps to obtain higher chirp rate adjustment resolution, but at the same time, it will prolong the duration of a single frequency step, increase the frequency deviation of the actual step chirp from the ideal linear chirp, and may introduce additional interference phase during Raman pulse action, thus forming step chirp deviation and affecting the gravity measurement results.

[0126] In contrast, this embodiment employs a two-stage DDS collaborative control structure consisting of the AD9912 and AD9910 systems. While maintaining an adjacent frequency step time interval of approximately 1 μs, it can achieve an adjacent chirp rate step of 0.01 Hz / s, corresponding to an equivalent gravitational change of approximately 0.39 μGal; its theoretical chirp rate step is approximately... , corresponding to The equivalent change in gravity. In other words, under the same frequency step time interval, the chirp rate adjustment resolution of the present invention is improved by about six orders of magnitude compared with the AD9854 scheme.

[0127] In the closed-loop measurement process of the atomic gravimeter, to ensure the atomic interferometer continues to operate near the central fringe, the control system calculates the chirp rate correction required for the next measurement cycle based on the atomic interferometry error signal obtained in the previous measurement cycle, and updates the target chirp rate accordingly. Since the correction amount is determined by the actual measurement results, its value usually does not correspond exactly to an integer multiple of the inherent chirp rate quantization interval of the DDS. Therefore, the target chirp rate needs to be quantized to a discrete value achievable by the DDS, resulting in a chirp rate rounding error. Under the same approximately 1 μs frequency step time interval, the minimum chirp rate adjustment step size generated by the conventional AD9854 system is approximately 1.066 Hz / s, and its maximum chirp rate rounding error is approximately 0.533 Hz / s, corresponding to a gravity measurement deviation of approximately 20.9 μGal. Under the same conditions, the maximum theoretical chirp rate rounding error in this embodiment is approximately... The corresponding gravity measurement deviation is approximately This reduces costs by about six orders of magnitude compared to traditional solutions.

[0128] Therefore, while maintaining the microsecond-level frequency update capability, this invention significantly reduces the chirp rate quantization interval and the rounding error it causes, so that the chirp rate quantization error no longer constitutes the main technical bottleneck restricting the further improvement of the measurement sensitivity and accuracy of the atomic gravimeter.

[0129] Example 4.

[0130] This embodiment applies the high-precision chirped frequency control system described above to the Raman laser frequency difference control of an atomic interferometric gravimeter. The atomic interferometric gravimeter of this embodiment includes an atomic source, a Raman laser system, a detection system, and the aforementioned high-precision chirped frequency control system. The atomic source provides a cold atom sample; the Raman laser system generates two counter-propagating Raman beams, the frequency difference of which is modulated by the chirped signal described in this invention; the detection system detects the final population of atoms and outputs an interference signal. The chirped signal output by the subsequent DDS system 300 is applied to the Raman laser system via the subsequent output filtering and amplitude adjustment circuit 330 and the frequency modulation link 500, causing the frequency difference between the two Raman beams to change according to a set chirped rate.

[0131] The working process is as follows: First, atoms are cooled, trapped, and magnetically insensitive states are prepared. Then, the atoms are released or thrown upwards to allow them to undergo a free evolution process under gravity. During this free evolution process, a time interval of [time value missing] is used. The Raman pulse sequence enables the splitting, reflection, and combining of atomic matter waves, forming a Mach-Zehnder type atomic interferometer. Since the atomic velocity changes continuously with the free fall time, the Doppler frequency shift corresponding to the Raman two-photon transition also changes accordingly. Therefore, this system generates a linear chirped signal and applies it to the Raman light frequency modulation link, causing the frequency difference between the two Raman beams to change according to a set chirp rate to compensate for the Doppler frequency shift caused by the free fall of atoms.

[0132] Between adjacent measurement cycles, the system successively changes the chirp rate according to a preset chirp rate step size, while simultaneously compensating and correcting the lower and upper sweep frequencies to maintain a basically consistent sweep range for each chirp. Interference fringes are obtained by detecting the atomic final-state population at different chirp rates, and the chirp rate corresponding to the central fringe is then used to... Determine the acceleration due to gravity.

[0133] After determining the operating point near the central fringe, the system constructs an error signal based on the atomic final-state population and corresponding phase modulation state obtained from continuous atomic interferometry, and calculates the chirp rate correction for the next measurement cycle accordingly. The cooperative control module 400 superimposes this correction onto the current target chirp rate, recalculates and updates the frequency control word of the preceding DDS system 200 and the sweep frequency upper and lower limit control words of the subsequent DDS system 300, keeping the atomic interferometry phase near the central fringe and achieving chirp rate closed-loop feedback and continuous tracking of gravitational acceleration. Because the chirp rate adjustment step size achievable in this invention is much smaller than the typical correction required by the feedback loop, the feedback correction can be applied with high fidelity, avoiding the residual compensation error introduced by rounding in traditional single-stage DDS schemes.

[0134] During closed-loop operation, the FPGA timing control unit 430 follows... Figure 4 The timing sequence shown generates parameter switching trigger signals according to the beat of the atomic interference sequence, ensuring that the parameter update process strictly occurs within the idle period between two adjacent measurement cycles, thus avoiding phase jumps caused by changing the DDS configuration during Raman pulse action.

[0135] Example 5.

[0136] like Figure 5 As shown, this embodiment, based on Embodiment 1, adds an additional DDS system 600 upstream of the front-end DDS system 200, forming a three-stage DDS structure. The output of the high-stability reference clock source 100 is connected to the reference clock input of the additional DDS system 600; the output of the additional DDS system 600 is connected to the reference clock input of the front-end DDS system 200, providing an adjustable reference clock to the front-end DDS system 200; the output of the front-end DDS system 200 remains connected to the external reference clock input of the rear-end DDS system 300. The collaborative control module 400 is connected to the configuration ports and parameter update ports of both the front-end DDS system 200 and the rear-end DDS system 300, ensuring that the corresponding configuration parameters of the front-end DDS system 200 and the rear-end DDS system 300 take effect synchronously; the collaborative control module 400 is also connected to the digital ramp control port of the rear-end DDS system 300. The collaborative control module 400 and the additional DDS system 600 maintain at least a configuration connection.

[0137] In the three-stage architecture, the additional DDS system 600 can be used to extend the adjustable range of the output frequency of the preceding DDS system 200. This is because the additional DDS system 600 alters the reference clock frequency of the preceding DDS system 200. Therefore, when calculating the frequency control word of the preceding DDS system according to the above formula, it is only necessary to... Simply replace it with the actual output frequency of the additional DDS system; the rest of the calculation process is exactly the same as in Example 2. This shows that the parameter co-calculation method of the present invention can be directly extended to three-level or more DDS structures.

[0138] It should be noted that the device models, bit widths, frequency values, and step sizes in the above embodiments are merely examples. In the above embodiments, the frequency of the working reference clock output by the pre-stage DDS system 200 can be selected within the range of 340MHz to 360MHz according to actual conditions, and the frequency step time interval of the post-stage DDS system 300 can be selected within the range of 0.5μs to 2μs according to actual conditions. In other embodiments, the frequency of the working reference clock output by the pre-stage DDS system 200 is not limited according to actual conditions. The frequency of the post-stage DDS system 300 is also not limited according to actual conditions. It is only necessary to recalculate the corresponding time control word, frequency increment control word, pre-stage frequency control word, and sweep upper and lower limit control word according to the above formulas. The larger the bit width of the frequency control word of the pre-stage DDS system, the smaller the frequency adjustment interval of its output working reference clock, and the finer the chirp rate step can be achieved. Those skilled in the art can select other DDS chips with external reference clock input and digital ramp functions as the subsequent DDS system, and other DDS chips with high-bit-width frequency control words as the pre-stage DDS system, according to actual needs. The host computer parameter calculation unit, MCU configuration control unit, and FPGA timing control unit in the collaborative control module can also be implemented by one or more combinations of single-chip microcontrollers, digital signal processors, system-on-a-chip, or programmable logic devices, as long as they can complete the aforementioned parameter collaborative calculation, parameter sequence storage and retrieval, and synchronous timing control functions. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A high-precision chirped frequency control system based on multi-level DDS coordinated regulation, comprising a highly stable reference clock source, a front-stage DDS system, a rear-stage DDS system, and a coordinated control module, wherein the highly stable reference clock source provides a reference clock to the front-stage DDS system, the output of the front-stage DDS system is connected to the external reference clock input of the rear-stage DDS system, the front-stage DDS system generates and adjusts the working reference clock of the rear-stage DDS system, the rear-stage DDS system includes a digital ramp generator, the rear-stage DDS system generates a stepped linear chirped signal under the drive of the working reference clock, the output of the rear-stage DDS system is connected to a controlled object, the coordinated control module is connected to the configuration port and synchronization control port of the front-stage DDS system, and the coordinated control module is also connected to the configuration port and synchronization control port of the rear-stage DDS system, characterized in that... The collaborative control module is configured as follows: In the output sequence consisting of multiple chirps, the time control word of the subsequent DDS system is maintained. and frequency increment control word constant; The frequency control word of the front-end DDS system is updated according to the target chirp rate of each chirp to change the operating reference clock frequency of the back-end DDS system, so that the chirp rate between two adjacent chirps changes according to the preset chirp rate step. as well as The sweep frequency lower limit control word and sweep frequency upper limit control word of the subsequent DDS system are synchronously updated according to the updated working reference clock frequency to compensate for the sweep frequency lower limit frequency and sweep frequency upper limit frequency offset caused by the change of the working reference clock frequency.

2. The high-precision chirped frequency control system based on multi-level DDS coordinated regulation according to claim 1, characterized in that, The collaborative control module operates according to the following formula, based on the... Target chirp rate for each chirp Determine the ideal operating reference clock frequency for the subsequent DDS system. The frequency control word of the front-end DDS system and the actual working reference clock frequency after quantization. And the actual chirp rate : in, This refers to the time control word of the subsequent DDS system. This refers to the frequency increment control word of the subsequent DDS system. This refers to the clock scaling factor of the ramp timer within the subsequent DDS system. The frequency increment control word width of the subsequent DDS system, The frequency control word width of the aforementioned front-end DDS system. This is the reference clock frequency input to the preceding DDS system. For the first The actual chirp rate achieved per chirp. This indicates rounding to the nearest integer.

3. The high-precision chirped frequency control system based on multi-level DDS coordinated regulation according to claim 2, characterized in that, The collaborative control module determines the first according to the following formula. The lower limit control word of the sweep frequency of the subsequent DDS system corresponding to the second chirp. and sweep frequency upper limit control word And determine the actual lower limit frequency of the frequency sweep after compensation. and the actual upper limit frequency of the sweep : in, The target frequency sweep lower limit frequency, The target frequency sweep upper limit frequency and , The sweep frequency boundary control word width of the subsequent DDS system. The actual lower limit frequency of the frequency sweep after compensation. The actual upper limit frequency for frequency sweeping after compensation.

4. The high-precision chirped frequency control system based on multi-level DDS coordinated regulation according to claim 1, characterized in that, The collaborative control module includes a host computer parameter calculation unit, an MCU configuration control unit, and an FPGA timing control unit. The output of the host computer parameter calculation unit is connected to the communication port of the MCU configuration control unit. The configuration interface of the MCU configuration control unit is connected to the configuration ports of the front-end DDS system and the back-end DDS system, respectively. The parameter update output of the MCU configuration control unit is connected to the synchronization control ports of the front-end DDS system and the back-end DDS system, respectively. The FPGA timing control unit is connected to the digital ramp control ports of the MCU configuration control unit and the back-end DDS system, respectively. The FPGA timing control unit is used to generate two types of timing control signals: the first type is a parameter switching trigger signal sent to the MCU configuration control unit to trigger the MCU configuration control unit to call the next set of chirp parameters; the second type is a digital ramp control signal that only acts on the back-end DDS system to control the sweep direction of the current linear chirp.

5. The high-precision chirped frequency control system based on multi-level DDS coordinated regulation according to claim 4, characterized in that, The host computer parameter calculation unit is used to pre-calculate the frequency control word of the front-end DDS system and the sweep frequency lower limit control word and sweep frequency upper limit control word of the back-end DDS system for each chirp before the chirp sequence is started, according to the target sweep frequency lower limit, target sweep frequency upper limit, initial target chirp rate, target frequency step time interval, chirp rate step amount and chirp number, and form a parameter sequence corresponding to each chirp one by one according to the chirp sequence number; The MCU configuration control unit includes a non-volatile memory unit and a runtime memory parameter array. It stores the parameter sequence in the non-volatile memory unit and reads and parses the parameter sequence during system initialization or parameter loading operations, storing it in the runtime memory parameter array according to the chirp sequence number. Upon receiving the parameter switching trigger signal, the MCU configuration control unit reads the next set of configuration parameters from the runtime memory parameter array, writes the next set of configuration parameters into the configuration buffer registers of the front-end DDS system and the back-end DDS system respectively through the configuration interface, and outputs parameter update signals to the front-end DDS system and the back-end DDS system after writing, so that the frequency control word of the front-end DDS system is synchronously activated with the sweep frequency lower limit control word and sweep frequency upper limit control word of the back-end DDS system.

6. The high-precision chirped frequency control system based on multi-level DDS coordinated regulation according to claim 1, characterized in that, The high-stability reference clock source includes a frequency reference unit and a frequency synthesis unit. The frequency reference unit is a temperature-controlled crystal oscillator or a rubidium atomic clock. The frequency synthesis unit is used to convert the low-frequency reference signal output by the frequency reference unit into a high-frequency reference clock required by the front-end DDS system through multi-stage frequency multiplication or phase-locked loop frequency synthesis. The system also includes an additional DDS system disposed between the high-stability reference clock source and the front-end DDS system. The output terminal of the high-stability reference clock source is connected to the reference clock input terminal of the additional DDS system, and the output terminal of the additional DDS system is connected to the reference clock input terminal of the front-end DDS system. The cooperative control module is also connected to the configuration port of the additional DDS system to form a three-level or more DDS structure.

7. The high-precision chirped frequency control system based on multi-level DDS coordinated regulation according to claim 1, characterized in that, The front-end DDS system includes a front-end DDS chip and a front-end output filtering and amplitude adjustment circuit, and the rear-end DDS system includes a rear-end DDS chip and a rear-end output filtering and amplitude adjustment circuit. The controlled object is an acousto-optic modulator, an electro-optic modulator, a microwave device, or a phase-locked loop.

8. A high-precision chirped frequency control method based on multi-level DDS coordinated regulation, applied to a chirped frequency control system including a highly stable reference clock source, a front-end DDS system, a back-end DDS system, and a coordinated control module, characterized in that, The method includes the following steps: S1, Obtain the target sweep frequency lower limit. Target sweep frequency limit Initial target chirp rate Target frequency step time interval Chirp rate step size and the number of chirps, and determine the number of chirps as follows: The target chirp rate for each chirp. Chirp numbers starting from 0: S2, using a frequency near the preset output frequency of the preceding DDS system. As a reference used only for the initial calculation of integer control parameters of the subsequent DDS system, the time control word of the subsequent DDS system is determined by the following formula. and frequency increment control word And maintain throughout the entire output sequence and constant: S3, inverse calculation of the... The ideal operating reference clock frequency required for this chirp; S4, determine the frequency control word of the front-end DDS system, obtain the actual working reference clock frequency after quantization, and determine the actual chirp rate; S5, determine the first The lower and upper sweep control words of the subsequent DDS system corresponding to the second chirp are used to compensate for the sweep boundary offset caused by the change in the operating reference clock frequency. S6, arranging the chirps according to their chirp sequence numbers. , and Form a parameter sequence and store it; S7, between two adjacent chirps, the next set of parameters is called from the parameter sequence and written, and then the frequency control word of the front-end DDS system and the sweep frequency upper and lower limit control word of the rear-end DDS system are synchronized and activated through the parameter update signal; then the sweep frequency direction is determined by the digital ramp control signal, and the rear-end DDS system is controlled to output the corresponding linear chirp signal. Repeat step S7 until all chirps corresponding to the number of chirps are completed.

9. The high-precision chirp frequency control method based on multi-level DDS coordinated regulation according to claim 8, characterized in that, The parameter switching stage in step S7 is initiated by a parameter switching trigger signal generated by the FPGA timing control unit. The parameter switching stage includes calling the next set of configuration parameters, writing the next set of configuration parameters into the configuration buffer registers of the front-end DDS system and the back-end DDS system, and making the next set of configuration parameters effective synchronously through a parameter update signal. The process of writing the next set of parameters into the two-stage DDS system to make it effective strictly occurs during the idle period between two adjacent measurement cycles to avoid changing the current effective configuration of the front-end DDS system and the back-end DDS system during Raman pulse action. The method also includes step S8: constructing an error signal based on the atomic final state population obtained by atomic interferometry, determining the chirp rate correction amount for the next measurement cycle based on the error signal, superimposing the chirp rate correction amount onto the current target chirp rate, and returning to step S3 to achieve chirp rate closed-loop feedback and continuous tracking of gravitational acceleration.

10. An atomic interferometer gravimeter, comprising an atomic source, a Raman laser system, and a detection system, characterized in that, It also includes a high-precision chirped frequency control system based on multi-level DDS coordinated control as described in claim 1, wherein the output of the subsequent DDS system of the high-precision chirped frequency control system is connected to the Raman laser system via a frequency modulation link, for making the frequency difference between the two Raman beams output by the Raman laser system change according to a set chirp rate to compensate for the Doppler frequency shift caused by free fall of atoms; the coordinated control module of the high-precision chirped frequency control system is further configured to: determine the chirp rate correction amount for the next measurement cycle based on the error signal constructed from the atomic interferometry measurement results of the previous measurement cycle, superimpose the chirp rate correction amount onto the current target chirp rate to obtain the target chirp rate for the next measurement cycle, and re-determine the frequency control word of the preceding DDS system and the sweep frequency lower limit control word and sweep frequency upper limit control word of the subsequent DDS system according to the target chirp rate.

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