Clock sharing circuit and method

Abstract

The application provides a clock sharing circuit and method, which comprises an SOC chip, a clock circuit, a functional module, a clock adjusting circuit and a power supply module. The clock circuit is connected with the SOC chip to provide a reference working clock. The clock adjusting circuit is connected in series between a clock output end of the SOC chip and a clock input end of the functional module, and is used for adjusting the clock signal output by the SOC chip to adapt to the clock signal of the functional module. The power supply module provides working power for the SOC chip, the functional module and the clock adjusting circuit. By using the above scheme, the hardware material cost is effectively reduced, the circuit required board space is reduced, the electromagnetic radiation problem caused by multiple clock sources is reduced, and the overall performance and reliability of the system are improved under the premise of ensuring stable work of each module.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and more specifically, to a clock sharing circuit and method. Background Technology

[0002] As the functions of electronic devices such as monitoring products and smart terminals continue to expand and develop, the number of functional modules integrated within these devices is increasing. A stable clock signal is a necessary foundation for the normal operation of all functional modules, and the clock supply method directly affects the hardware design cost and operational stability of the equipment.

[0003] Currently, for electronic devices with multiple integrated modules, the existing technology generally adopts the approach of configuring a crystal oscillator clock circuit independently for each functional module. Multiple independent crystal oscillator circuits provide dedicated operating clocks for the corresponding functional modules, thereby ensuring the stable operation of each module.

[0004] This implementation method, which configures a separate clock source for each module, requires each functional module to be equipped with an additional crystal oscillator and supporting peripheral components. This not only increases the hardware material cost of the device, but also occupies more printed circuit board area, increasing the design difficulty of hardware layout. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a clock sharing circuit and method. Through the design of single-source multiplexing and adaptive adjustment, the hardware material cost is effectively reduced, the board space required for the circuit is reduced, and the electromagnetic radiation problem caused by multiple clock sources is reduced, thereby improving the overall performance and reliability of the system, while ensuring the stable operation of each module.

[0006] In a first aspect, embodiments of this application provide a clock-sharing circuit, including: The SOC chip has a clock output terminal; A clock circuit, connected to the SOC chip, is used to provide a reference operating clock for the SOC chip; The functional module has a clock input terminal; A clock adjustment circuit, whose input terminal is connected to the clock output terminal of the SOC chip and whose output terminal is connected to the clock input terminal of the functional module, is used to adjust the clock signal output by the SOC chip to adapt to the clock signal of the functional module. The power supply module is connected to the SOC chip, the functional module and the clock adjustment circuit respectively, and is used to supply power to the SOC chip, the functional module and the clock adjustment circuit.

[0007] Optionally, the clock circuit is a crystal resonator, i.e., a passive crystal oscillator; The second and fourth pins of the passive crystal oscillator are both grounded, the first pin is connected to the XIN pin of the SOC chip, and the third pin is connected to the XOUT pin of the SOC chip. A resistor R1 is connected between the first and third pins of the passive crystal oscillator. The resistor R1 is used to stabilize the oscillation and improve the clock waveform to reduce interference. The first pin of the passive crystal oscillator is also grounded through capacitor C1, and the third pin is also grounded through capacitor C2. The clock frequency offset can be reduced by adjusting the capacitance values ​​of capacitors C1 and C2.

[0008] Optionally, the power supply module includes a first power supply module, a second power supply module, and a third power supply module; The first power supply module is connected to the power input terminal of the SOC chip and is used to supply power to the SOC chip; The second power supply module is connected to the power input terminal of the functional module and is used to supply power to the functional module; The third power supply module is connected to the power input terminal of the clock adjustment circuit and is used to provide a reference voltage for the clock adjustment circuit.

[0009] Optionally, the first power supply module is a multi-channel regulated power supply circuit, including a DC-DC switching power supply and / or an LDO low-dropout linear regulator, the number of power supplies and voltage values ​​of which are determined by the power domain of the SOC chip. The second power supply module is a multi-channel regulated power supply circuit, including a DC-DC switching power supply and / or an LDO low-dropout linear regulator. The number of power supplies and their voltage values ​​are determined by the power domain of the functional module.

[0010] Optionally, the third power supply module is an LDO (low dropout linear regulator) used to provide a stable reference voltage for the clock adjustment circuit.

[0011] Optionally, when the power supply voltage of the functional module is the same as the power supply voltage of the SOC chip, the first power supply module and the second power supply module share the same power supply output.

[0012] Optionally, the clock adjustment circuit includes a capacitor C3, a resistor R2, and a resistor R3; One end of the capacitor C3 is connected to the clock output terminal of the SOC chip, and is used to receive the initial clock signal output by the SOC chip and isolate the DC component in the initial clock signal. The other end of the capacitor C3 is connected to the clock input terminal of the functional module, one end of the resistor R2, and one end of the resistor R3, respectively. The other end of the resistor R2 is connected to the output terminal of the third power supply module, and is used to receive the reference voltage provided by the third power supply module. The other end of the resistor R3 is grounded; The resistors R2 and R3 form a voltage divider circuit, which is used to divide the reference voltage provided by the third power supply module to generate a DC bias voltage. The DC bias voltage is superimposed on the clock signal after isolating the DC component to obtain the adjusted clock signal.

[0013] Optionally, the capacitance of capacitor C3 is 100nF.

[0014] Optionally, when the voltage swing and DC bias level of the clock signal output by the SOC chip can directly meet the clock input requirements of the functional module, the capacitor C3 is replaced with a 0-ohm resistor, and the resistors R2 and R3 and the third power supply module are omitted.

[0015] Secondly, embodiments of this application provide a clock sharing method applied to the clock sharing circuit described in the first aspect, the method comprising: A clock circuit provides a reference operating clock for the SOC chip. The initial clock signal is output through the clock output terminal of the SOC chip; The initial clock signal output by the SOC chip is adjusted to the clock signal of the adaptive functional module through a clock adjustment circuit. The power supply module provides power to the SOC chip, the functional module, and the clock adjustment circuit respectively.

[0016] Optionally, the step of supplying power to the SOC chip, the functional module, and the clock adjustment circuit via the power supply module specifically includes: The SOC chip is powered by the first power supply module; The functional modules are powered by a second power supply module; The clock adjustment circuit is provided with a reference voltage via a third power supply module.

[0017] Optionally, the step of adjusting the initial clock signal output by the SOC chip to the clock signal of the adaptive functional module through the clock adjustment circuit specifically includes: The DC component in the initial clock signal output by the SOC chip is isolated by capacitor C3. The reference voltage provided by the third power supply module is divided by resistors R2 and R3 to obtain the DC bias voltage. The clock signal after isolating the DC component is superimposed with the DC bias voltage to obtain the adjusted clock signal.

[0018] Optionally, when the voltage swing and DC bias level of the clock signal output by the SOC chip can directly meet the clock input requirements of the functional module, the capacitor C3 is replaced with a 0-ohm resistor, and the voltage division steps of resistors R2 and R3 and the reference voltage supply steps of the third power supply module are omitted.

[0019] The technical solution provided in this application includes, but is not limited to, the following beneficial effects: By providing a reference clock for the SOC chip through a clock circuit, the system only needs to set up one reference clock source to support the clock requirements of the core chip and peripheral modules. There is no need to equip the peripheral functional modules with separate independent clock circuits, which effectively reduces the number of clock components used.

[0020] The SOC chip's built-in clock output allows it to derive and output the internal reference clock, enabling the reuse of clock resources. Furthermore, the output clock is derived from the SOC's own operating clock, ensuring timing synchronization between the main controller and peripherals.

[0021] By setting a clock adjustment circuit between the SOC chip and the functional module, the clock signal output by the SOC can be adapted and adjusted to match the clock input specifications of the functional module, thus avoiding abnormal operation of the functional module due to clock mismatch.

[0022] By using a unified power supply module to supply power to the SOC chip, functional modules and clock adjustment circuit, a stable operating power can be provided to each circuit unit in a centralized manner, simplifying the power supply architecture of the system.

[0023] In summary, this clock-sharing circuit, through single-source multiplexing and adaptive adjustment design, effectively reduces hardware material costs and circuit board space requirements while ensuring stable operation of each module. It also reduces electromagnetic radiation issues caused by multiple clock sources, thereby improving the overall performance and reliability of the system.

[0024] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1This paper shows a schematic diagram of the structure of a clock sharing circuit provided in Embodiment 1 of this application; Figure 2 This paper shows a schematic diagram of the structure of the second clock-sharing circuit provided in Embodiment 1 of this application; Figure 3 This paper shows a schematic diagram of the third clock-sharing circuit provided in Embodiment 1 of this application; Figure 4 This paper shows a schematic diagram of the fourth clock-sharing circuit provided in Embodiment 1 of this application; Figure 5 This paper shows a schematic diagram of the structure of the fifth clock-sharing circuit provided in Embodiment 1 of this application; Figure 6 This paper shows a schematic diagram of the clock sharing circuit of a module-side clock source provided in Embodiment 1 of this application; Figure 7 This paper shows a schematic diagram of a shared clock circuit with shared power supply provided in Embodiment 1 of this application; Figure 8 This paper shows a schematic diagram of an integrated power supply type clock sharing circuit provided in Embodiment 1 of this application; Figure 9 A flowchart of a clock sharing method provided in Embodiment 2 of this application is shown; Figure 10 A flowchart of an initial clock signal adjustment method provided in Embodiment 2 of this application is shown. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0028] Example 1 To facilitate understanding of this application, the following is combined with... Figure 1 The schematic diagram of a clock-sharing circuit provided in Embodiment 1 of this application illustrates the structure of Embodiment 1 in detail.

[0029] See Figure 1As shown, Figure 1 This diagram illustrates a clock-sharing circuit according to Embodiment 1 of this application. The clock circuit is connected to the XIN (CrystalInput) and XOUT (CrystalOutput) pins of the System on Chip (SOC) chip, forming an oscillation circuit to provide a stable reference clock for the SOC chip. The power supply module is an integrated power supply unit that outputs power at corresponding voltage levels to the SOC chip, clock adjustment circuit, and functional modules, providing operating power to each circuit unit. The SOC chip outputs an initial clock signal derived from the reference clock via the CLK_OUT (ClockOutput) pin, transmitting it to the input of the clock adjustment circuit. The clock adjustment circuit performs DC bias and voltage swing adjustment on the input initial clock signal, outputting an adapted clock signal conforming to the electrical specifications of the functional module to the clock input of the functional module. Multiple bidirectional communication connections are established between the SOC chip and the functional modules to realize data interaction and control command transmission between them.

[0030] Furthermore, the clock-sharing circuitry includes: A System on Chip (SoC) chip has a clock output terminal.

[0031] Specifically, the clock output terminal of the SOC chip is a dedicated pin on the chip for outputting clock signals, such as the CLKOUT (Clock Output) pin.

[0032] Specifically, this pin is used to provide a clock reference to external functional modules, and the initial clock signal output is derived from the reference clock circuit.

[0033] A clock circuit, connected to the SOC chip, is used to provide a reference operating clock for the SOC chip.

[0034] Specifically, the clock circuit works in conjunction with the clock input and output pins of the SOC chip to form a complete oscillation circuit, generating a stable reference frequency signal.

[0035] Specifically, this reference clock provides a unified time reference for all functional units within the SOC chip, including logic operations, peripheral control, and data interaction.

[0036] The functional module has a clock input terminal.

[0037] Specifically, the functional module refers to an integrated module or chip that requires an independent clock to work stably, such as a WiFi (Wireless Fidelity) module or a Bluetooth module.

[0038] Specifically, the clock input terminal of the functional module is used to receive clock signals that conform to its own electrical specifications, thereby driving the internal circuits to operate normally.

[0039] A clock adjustment circuit, whose input terminal is connected to the clock output terminal of the SOC chip and whose output terminal is connected to the clock input terminal of the functional module, is used to adjust the clock signal output by the SOC chip to adapt to the clock signal of the functional module.

[0040] Specifically, the clock adjustment circuit mainly adjusts the amplitude of the clock signal to avoid signal transmission abnormalities or even module failure due to clock level mismatch.

[0041] Specifically, with this circuit design, the system only needs a single clock circuit to simultaneously meet the requirements of peripheral modules with different clock amplitudes, without the need to configure a separate crystal oscillator circuit for each functional module.

[0042] Specifically, this design can reduce hardware BOM (Bill of Materials) costs and PCB (Printed Circuit Board) layout difficulty, while reducing electromagnetic radiation from multi-crystal oscillator circuits and making it easier for products to pass electromagnetic compatibility certification.

[0043] The power supply module is connected to the SOC chip, the functional module and the clock adjustment circuit respectively, and is used to supply power to the SOC chip, the functional module and the clock adjustment circuit.

[0044] Specifically, the power supply module can be split into multiple independent power supply outputs according to the voltage requirements of the three types of loads, or the power supply paths can be combined when the load voltage specifications are the same.

[0045] Specifically, this design can maximize the optimization of hardware costs and board space while ensuring stable power supply to each unit.

[0046] Specifically, the SOC chip and the functional module are provided with at least one set of bidirectional communication interfaces for data interaction between the two.

[0047] Specifically, the types of bidirectional communication interfaces include common communication protocols such as SDIO (Secure Digital Input and Output), SPI (Serial Peripheral Interface), and I2C (Inter-Integrated Circuit), all of which are suitable for this clock-sharing circuit scheme.

[0048] Specifically, this communication interface is a conventional data path and has no direct functional connection with the clock sharing circuit; it only undertakes the function of transmitting control commands and business data.

[0049] In an optional implementation, see Figure 2 As shown, Figure 2 A schematic diagram of the structure of the second clock sharing circuit provided in Embodiment 1 of this application is shown, wherein the clock circuit is a crystal resonator, i.e., a passive crystal oscillator.

[0050] Specifically, compared to active crystal oscillators, passive crystal oscillators have lower hardware costs and do not require additional power supply, which can reduce the overall power consumption of the entire board.

[0051] Specifically, passive crystal oscillators are smaller in size, which can reduce the area occupied by the PCB board and further reduce hardware design costs.

[0052] The second pin 2 and the fourth pin 4 of the passive crystal oscillator are both grounded, the first pin 1 is connected to the XIN (Crystal Input) pin of the SOC chip, and the third pin 3 is connected to the XOUT (Crystal Output) pin of the SOC chip.

[0053] Specifically, the XIN pin is the clock input pin of the SOC chip, and the XOUT pin is the clock output pin of the SOC chip.

[0054] Specifically, together with the passive crystal oscillator, the two form the Pierce oscillator circuit, which realizes the generation of the reference clock signal and reliable oscillation.

[0055] A resistor R1 is connected between the first pin 1 and the third pin 3 of the passive crystal oscillator. The resistor R1 is used to stabilize the oscillation and improve the clock waveform to reduce interference.

[0056] Specifically, resistor R1 is the feedback resistor of the oscillation circuit, which enables the inverting amplifier inside the SOC to operate in the linear amplification region.

[0057] Specifically, this configuration ensures that the circuit can reliably start oscillation after power-on, avoiding problems such as oscillation failure or slow oscillation.

[0058] Specifically, this resistor can also optimize the waveform quality of the clock signal, reduce signal distortion, and reduce electromagnetic radiation generated by the clock circuit.

[0059] The first pin 1 of the passive crystal oscillator is also grounded through capacitor C1, and the third pin 3 is also grounded through capacitor C2. The clock frequency offset can be reduced by adjusting the capacitance values ​​of capacitor C1 and capacitor C2.

[0060] Specifically, capacitors C1 and C2 are the load capacitors of the oscillation circuit. By adjusting their capacitance values, the nominal load capacitance parameters of the passive crystal oscillator can be matched.

[0061] Specifically, by precisely matching the load capacitor value, the frequency deviation of the clock signal can be controlled within the allowable range of the device, making the clock frequency more accurate.

[0062] In an optional implementation, see Figure 3 As shown, Figure 3 A schematic diagram of the structure of the third clock sharing circuit provided in Embodiment 1 of this application is shown, wherein the power supply module includes a first power supply module, a second power supply module and a third power supply module.

[0063] Specifically, the three power supply modules correspond to three different types of power supply loads: SOC chip, functional module, and clock adjustment circuit.

[0064] Specifically, the three power supplies can independently set the output voltage parameters to accurately match the rated operating voltage requirements of each load.

[0065] The first power supply module is connected to the power input terminal of the SOC chip and is used to supply power to the SOC chip.

[0066] Specifically, the first power supply module provides a stable operating voltage for each power domain of the SOC chip, ensuring that the SOC chip can operate stably under different workloads.

[0067] The second power supply module is connected to the power input terminal of the functional module and is used to supply power to the functional module.

[0068] Specifically, the second power supply module provides corresponding voltage outputs according to the power domain division of the functional modules, so as to meet the power supply requirements of the functional modules under different working states.

[0069] The third power supply module is connected to the power input terminal of the clock adjustment circuit and is used to provide a reference voltage for the clock adjustment circuit.

[0070] Specifically, the reference voltage output by the third power supply module is the reference voltage source of the voltage divider network in the clock adjustment circuit.

[0071] Specifically, the accuracy and stability of the reference voltage directly affect the accuracy of the bias level of the final output clock signal.

[0072] In an optional implementation, the first power supply module is a multi-channel regulated power supply circuit, including a DC-DC (Direct Current to Direct Current) switching power supply and / or an LDO (Low Dropout Regulator), the number of power supplies and their voltage values ​​being determined by the power domain of the SOC chip.

[0073] Specifically, DC-DC switching power supplies have high conversion efficiency and are suitable for power domains such as digital cores that require high current supply, which can reduce the overall power consumption of the system.

[0074] Specifically, LDO (low dropout linear regulator) has low output ripple and low noise, making it suitable for power domains such as analog circuits and clock circuits that are sensitive to power supply noise.

[0075] Specifically, the two can be flexibly combined and used according to the power consumption and noise requirements of different power domains of the SOC chip.

[0076] The second power supply module is a multi-channel regulated power supply circuit, including a DC-DC switching power supply and / or an LDO low-dropout linear regulator. The number of power supplies and their voltage values ​​are determined by the power domain of the functional module.

[0077] Specifically, when a functional module includes multiple independent power domains such as a digital core, RF front-end, and communication interface, the second power supply module can be configured with multiple regulated outputs.

[0078] Specifically, each output is matched to the voltage level and power consumption requirements of the corresponding power domain to ensure stable operation of each unit in the module.

[0079] Specifically, the selection of DC-DC converters and LDOs is also flexibly determined based on the current requirements and noise sensitivity of each power domain.

[0080] In an optional implementation, the third power supply module is an LDO (low dropout linear regulator) used to provide a stable reference voltage for the clock adjustment circuit.

[0081] Specifically, the LDO output voltage has the characteristics of low ripple and high stability, which can ensure that the DC bias voltage output by the voltage divider circuit is accurate and without significant fluctuations.

[0082] Specifically, a stable reference voltage can prevent clock signal levels from exceeding the acceptable range of the functional module due to voltage fluctuations, thus ensuring the reliability of clock transmission.

[0083] In an optional implementation, when the power supply voltage of the functional module is the same as the power supply voltage of the SOC chip, the first power supply module and the second power supply module share the same power supply output.

[0084] Specifically, sharing a power supply output can reduce the number of components used in one voltage regulator circuit, thereby reducing BOM material costs and PCB layout area.

[0085] Specifically, this design simplifies the design complexity of the power supply system and improves the integration of the circuit.

[0086] In an optional implementation, see Figure 4 As shown, Figure 4 The diagram illustrates the structure of the fourth clock sharing circuit provided in Embodiment 1 of this application. The clock adjustment circuit includes a capacitor C3, resistors R2 and R3. CLK is the clock signal input terminal, connected to the initial clock signal output by the SOC. Capacitor C3 is connected in series between the CLK and CLKA lines to isolate the DC component in the clock signal, allowing the AC clock signal to oscillate symmetrically around 0V. One end of resistor R2 is connected to the reference voltage V_CLK, and the other end is connected to the CLKA line node. One end of resistor R3 is connected to the CLKA line node, and the other end is grounded. Resistors R2 and R3 form a voltage divider circuit to divide the reference voltage V_CLK to generate a DC bias voltage, which is superimposed on the DC-blocked clock signal. CLKA is the clock signal output terminal after adjustment, directly connected to the clock input pin of the functional module.

[0087] Specifically, this clock adjustment circuit can achieve signal amplitude adjustment through a simple resistor-capacitor combination design, without the need for an additional dedicated clock conversion chip.

[0088] Specifically, this design effectively reduces hardware costs, and the discrete resistors and capacitors occupy very little PCB board space, which is conducive to product miniaturization.

[0089] One end of the capacitor C3 is connected to the clock output terminal of the SOC chip, and is used to receive the initial clock signal output by the SOC chip and isolate the DC component in the initial clock signal.

[0090] Specifically, capacitor C3 has the electrical characteristics of blocking DC and passing AC, which can filter out the DC bias component carried in the initial clock signal.

[0091] Specifically, after DC blocking, the center point of the sine wave signal will shift to the 0V position and swing symmetrically up and down around 0V.

[0092] Specifically, for example, if the SOC outputs a sine wave clock signal with a maximum swing of 1.6V, after being blocked by capacitor C3, it will become a sine wave signal with a voltage of ±0.8V.

[0093] The other end of the capacitor C3 is connected to the clock input terminal of the functional module, one end of the resistor R2, and one end of the resistor R3, respectively.

[0094] Specifically, the AC clock signal, after being blocked by DC, is superimposed on the DC bias voltage generated by the voltage divider circuit at this node.

[0095] Specifically, the superimposed final clock signal will be directly input to the clock input pin of the functional module to provide the working clock for the functional module.

[0096] The other end of the resistor R2 is connected to the output terminal of the third power supply module to receive the reference voltage provided by the third power supply module.

[0097] Specifically, resistor R2 acts as the pull-up arm of the voltage divider circuit, with one end connected to the reference voltage V_CLK output by the third power supply module and the other end connected to the clock signal node.

[0098] Specifically, together with the pull-down arm resistor R3, it forms a complete voltage divider circuit to provide DC bias for the clock signal.

[0099] The other end of the resistor R3 is grounded.

[0100] Specifically, resistor R3 acts as a pull-down arm of the voltage divider circuit, with one end connected to the system ground plane and the other end connected to the clock signal node.

[0101] Specifically, it works in conjunction with pull-up resistor R2 to divide the reference voltage and generate a fixed DC bias voltage.

[0102] The resistors R2 and R3 form a voltage divider circuit, which is used to divide the reference voltage provided by the third power supply module to generate a DC bias voltage. The DC bias voltage is superimposed on the clock signal after isolating the DC component to obtain the adjusted clock signal.

[0103] Specifically, the formula for calculating the DC bias voltage is as follows:

[0104] Specifically, in the formula, This is the DC bias voltage obtained by voltage division, in volts (V).

[0105] Specifically, in the formula, The reference voltage output by the third power supply module, in volts (V).

[0106] Specifically, in the formula, This is the resistance value of the pull-up resistor in the clock adjustment circuit, expressed in ohms (Ω).

[0107] Specifically, in the formula, This is the resistance value of the pull-down resistor in the clock adjustment circuit, expressed in ohms (Ω).

[0108] Specifically, after superimposing a DC bias voltage, the new sine wave signal will be biased by the DC bias voltage. It swings up and down around the center.

[0109] Specifically, the maximum and minimum voltage values ​​of the adjusted clock signal satisfy the following calculation formula:

[0110] Specifically, in the formula, The maximum voltage value of the clock signal after adjustment, in volts (V).

[0111] Specifically, in the formula, The minimum voltage value of the adjusted clock signal, measured in volts (V).

[0112] Specifically, in the formula, The voltage swing of the initial clock signal output by the SOC is the difference between the highest and lowest values ​​of the signal, measured in volts (V).

[0113] Specifically, after the clock signal is adjusted, two level constraints must be met: .

[0114] Specifically, in the formula, The minimum permissible high-level value required for the clock input pin of the functional module, in volts (V).

[0115] Specifically, in the formula, This is the maximum permissible low-level value required by the clock input pin of the functional module, in volts (V).

[0116] Specifically, meeting the above constraints ensures that the functional module can correctly identify the high and low levels of the clock signal, thus guaranteeing stable module operation.

[0117] In one alternative implementation, the capacitance of capacitor C3 is 100nF.

[0118] Specifically, 100nF is a typical recommended value for nanofarad capacitance, which can effectively isolate DC components while ensuring low-loss passage of clock AC signals within the commonly used frequency range.

[0119] Specifically, this capacitance value is compatible with the clock frequency requirements of most conventional peripheral modules, and can be fine-tuned according to the specific clock frequency in practical applications.

[0120] Specifically, there are no fixed recommended values ​​for resistors R2 and R3; they need to be designed based on the actual clock signal amplitude and the voltage divider formula mentioned above.

[0121] Specifically, the actual resistance value selection also needs to take into account the clock frequency and the clock output drive capability of the SOC chip to avoid signal quality degradation due to impedance mismatch.

[0122] In an optional implementation, see Figure 5 As shown, Figure 5 The diagram shows a fifth clock sharing circuit provided in Embodiment 1 of this application. When the voltage swing and DC bias level of the clock signal output by the SOC chip can directly meet the clock input requirements of the functional module, the capacitor C3 is replaced with a 0-ohm resistor, and the resistors R2 and R3 and the third power supply module are omitted.

[0123] Specifically, when the voltage swing and DC bias level of the initial clock signal output by the SOC can directly meet the clock input requirements of the functional module, the voltage divider resistor and the reference voltage power supply unit can be omitted. A 0R (0 ohm) resistor can be connected in series between the CLK and CLKA lines to achieve direct transmission of the clock signal. This mode can further simplify circuit components and reduce hardware costs and board space.

[0124] Specifically, in this configuration, the clock signal is transmitted directly from the SOC chip to the functional module without the need for level conversion.

[0125] Specifically, this design can further simplify the number of components in the circuit, reducing hardware costs and board layout difficulty.

[0126] Specifically, the pass-through configuration reduces component losses along the signal transmission path, thereby improving the quality and integrity of the clock signal.

[0127] In an optional implementation, if the functional module has its own clock circuit and supports clock output, the functional module can be used as the clock circuit side, and the clock adjustment circuit can provide an adapted clock signal to the SOC chip.

[0128] Specifically, the clock circuit connects to the clock pin of the functional module, providing a stable reference clock for the functional module.

[0129] Specifically, the functional module outputs an initial clock signal through its own clock output pin, which is then input to the clock adjustment circuit for level adaptation.

[0130] Specifically, the clock adjustment circuit outputs the adjusted clock signal and connects it to the CLK_SOC (Clock for System on Chip) pin of the SOC chip to provide the operating clock for the SOC chip.

[0131] Specifically, this solution allows for flexible selection of the clock circuit location based on actual component selection and PCB layout, enhancing the flexibility of board layout design.

[0132] In an alternative implementation, the clock-sharing circuit can be extended to systems containing multiple functional modules.

[0133] Specifically, when a system contains multiple functional modules, each functional module is typically configured with an independent clock adjustment circuit.

[0134] Specifically, each functional module can independently adjust the parameters of its corresponding clock adjustment circuit according to its own level requirements to adapt to different clock input specifications.

[0135] Specifically, if multiple functional modules have the same clock amplitude requirement, they can theoretically share the same clock adjustment circuit.

[0136] Specifically, in practical applications, it is necessary to evaluate the driving capability of the clock output pin of the SOC chip and verify the stability and reliability of the clock signal through actual tests.

[0137] Specifically, a design using a shared clock adjustment circuit can only be adopted after confirming that the clock requirements of all modules are met.

[0138] In addition to the multi-module system expansion schemes mentioned above, this scheme can also be adapted into various modified implementation structures to meet different hardware layout, component selection, and cost control requirements. The corresponding figures are illustrated below: See Figure 6 As shown, Figure 6This diagram illustrates a clock sharing circuit for a module-side clock source according to Embodiment 1 of this application. The clock circuit is connected to the XIN and XOUT pins of the functional module, respectively, forming an oscillation circuit to provide a stable reference clock for the functional module. A first power supply module outputs a working voltage to the power supply terminal of the SOC chip, providing power for the normal operation of the SOC chip. A second power supply module outputs a working voltage to the power supply terminal of the functional module, providing an independent working power supply for the functional module. A third power supply module outputs a reference voltage to the power supply terminal of the clock adjustment circuit, providing a bias reference voltage for the clock adjustment circuit. The functional module connects to C... The LK_OUT pin outputs an initial clock signal derived from the reference clock, which is transmitted to the input of the clock adjustment circuit. The clock adjustment circuit performs DC bias and voltage swing adjustment on the input initial clock signal, and outputs an adapted clock signal that conforms to the SOC chip's electrical specifications to the SOC chip's CLK_SOC pin. Multiple bidirectional communication connections are set between the SOC chip and the functional modules to realize data interaction and control command transmission between them. This solution sets the clock source on the functional module side, which is suitable for scenarios where the functional module has its own crystal oscillator and supports clock output. The clock source position can be flexibly selected according to the PCB layout, improving the flexibility of the board layout design.

[0139] See Figure 7 As shown, Figure 7 This diagram illustrates a shared clock circuit with shared power supply according to Embodiment 1 of this application. The clock circuit is connected to the XIN and XOUT pins of the SOC chip, forming an oscillation loop to provide a stable reference clock for the SOC chip. The first power supply module is an integrated output power unit that simultaneously outputs operating voltage to the power terminals of both the SOC chip and the functional modules, providing operating power to both types of circuit units. The third power supply module outputs a reference voltage to the power terminal of the clock adjustment circuit, providing a bias reference voltage for the clock adjustment circuit. The SOC chip outputs an initial clock signal derived from the reference clock through its CLK_OUT pin, transmitting it to the input terminal of the clock adjustment circuit. The clock adjustment circuit performs DC bias and voltage swing adjustment on the input initial clock signal, outputting an adapted clock signal conforming to the electrical specifications of the functional module to the CLK_A pin of the functional module. Multiple bidirectional communication connections are established between the SOC chip and the functional modules to realize data interaction and control command transmission between them. This solution is suitable for scenarios where the SOC chip and the functional modules have the same power supply voltage, reducing the number of independent voltage regulator circuits, lowering hardware BOM costs, and reducing PCB board area.

[0140] See Figure 8 As shown, Figure 8This diagram illustrates the structure of an integrated power supply clock sharing circuit according to Embodiment 1 of this application. The clock circuit is connected to the XIN and XOUT pins of the SOC chip, respectively, forming an oscillation circuit to provide a stable reference clock for the SOC chip. A first power supply module outputs operating voltage to the power supply terminal of the SOC chip, providing power for its normal operation. A second power supply module outputs operating voltage to the power supply terminal of a first functional module, providing an independent operating power supply for the first functional module. A fourth power supply module outputs operating voltage to the power supply terminal of the second functional module, providing an independent operating power supply for the second functional module. A third power supply module outputs a reference voltage to the power supply terminals of two clock adjustment circuits, providing a unified bias reference voltage for the two clock adjustment circuits. The SOC chip outputs two identical initial clock signals through the CLK pin, which are then input to two independent clock adjustment circuits. The first clock adjustment circuit adjusts the level of the input initial clock signal and outputs the adapted CLK_A clock signal to the clock input of the first functional module. The second clock adjustment circuit adjusts the level of the input initial clock signal and outputs the adapted CLK_B clock signal to the clock input of the second functional module. The SOC chip has bidirectional communication connections with the first and second functional modules to enable data interaction and control command transmission between multiple peripherals. This solution provides a single clock source for multiple peripheral functional modules, and each module can independently adjust its clock level parameters, making it suitable for complex system scenarios with multiple integrated peripherals.

[0141] Example 2 See Figure 9 As shown, Figure 9 The flowchart of a clock sharing method provided in Embodiment 2 of this application is shown. It is applied to the clock sharing circuit as described in Embodiment 1 above, and includes the following steps S901~S904: S901: Provides a reference operating clock for the SOC chip through the clock circuit.

[0142] Specifically, the clock circuit uses a crystal resonator, i.e., a passive crystal oscillator, which, together with the clock input pin and clock output pin of the SOC chip, forms a complete oscillation circuit to generate a stable reference frequency signal, providing a unified time reference for all functional units inside the SOC chip, such as logic operations, peripheral control, and data interaction.

[0143] S902: Output the initial clock signal through the clock output terminal of the SOC chip.

[0144] Specifically, the clock output terminal is a pin on the SOC chip specifically used to output clock signals. Its initial clock signal is derived from the reference working clock and is synchronized with the reference clock to provide a clock reference for external functional modules.

[0145] S903: The clock adjustment circuit adjusts the initial clock signal output by the SOC chip to a clock signal that is compatible with the functional module.

[0146] Specifically, the clock adjustment circuit mainly adjusts the voltage swing and DC bias level of the clock signal to solve problems such as abnormal signal transmission and module failure to start normally caused by clock level mismatch between SOC chip and functional module, and realizes the adaptation of a single clock source to peripheral modules with different level requirements.

[0147] S904: The power supply module provides power to the SOC chip, the functional module, and the clock adjustment circuit respectively.

[0148] Specifically, the power supply module can be configured with multiple independent regulated outputs according to the voltage requirements of the three types of loads, and can also merge the power supply paths when the load voltage specifications are the same, thereby reducing the cost of hardware materials and the difficulty of printed circuit board layout while ensuring the stable power supply of each circuit unit.

[0149] In an optional implementation, see Figure 10 As shown, Figure 10 The flowchart illustrates an initial clock signal adjustment method according to Embodiment 2 of this application. The step of adjusting the initial clock signal output by the SOC chip to a clock signal adapted to the functional module through the clock adjustment circuit includes steps S1001 to S1003: S1001: The DC component of the clock signal output by the SOC chip is isolated by the capacitor C3.

[0150] Specifically, capacitor C3 has the electrical characteristic of blocking DC and passing AC, which can filter out the DC bias component carried in the initial clock signal, causing the center point of the AC sine wave clock signal to shift to the 0V position and swing symmetrically up and down around 0V.

[0151] S1002: The reference voltage provided by the power supply module is divided by the resistors R2 and R3 to obtain the DC bias voltage.

[0152] Specifically, resistors R2 and R3 form a voltage divider circuit. One end of resistor R2 is connected to the reference voltage provided by the third power supply module, and one end of resistor R3 is grounded. The two work together to divide the reference voltage and generate a fixed DC bias voltage.

[0153] Specifically, the formula for calculating the DC bias voltage is as follows:

[0154] Specifically, in the formula, The DC bias voltage obtained by voltage division is expressed in volts (V). The reference voltage output by the third power supply module, in volts (V). This is the resistance value of the pull-up resistor in the clock adjustment circuit, in ohms (Ω). This is the resistance value of the pull-down resistor in the clock adjustment circuit, expressed in ohms (Ω).

[0155] S1003: The DC bias voltage is superimposed on the clock signal after isolating the DC component to obtain the adjusted clock signal.

[0156] Specifically, after the DC bias voltage is superimposed, the new clock signal will swing up and down around the bias voltage to form the final clock signal that meets the input level requirements of the functional module.

[0157] Specifically, the maximum and minimum voltage values ​​of the adjusted clock signal satisfy the following calculation formula:

[0158] Specifically, in the formula, The maximum voltage value of the clock signal after adjustment, in volts (V). The minimum voltage value of the clock signal after adjustment, in volts (V). The voltage swing of the initial clock signal output by the SOC is the difference between the highest and lowest values ​​of the signal, measured in volts (V).

[0159] Specifically, after the clock signal is adjusted, two level constraints must be met: and ,in This is the minimum permissible high-level value required by the clock input pin of the functional module. This is the maximum allowable low-level value required by the clock input pin of the functional module. Meeting this constraint ensures that the functional module can correctly identify the high and low levels of the clock signal.

[0160] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0161] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application. All should be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A clock-sharing circuit, characterized in that, include: The SOC chip has a clock output terminal; A clock circuit, connected to the SOC chip, is used to provide a reference operating clock for the SOC chip; The functional module has a clock input terminal; A clock adjustment circuit, whose input terminal is connected to the clock output terminal of the SOC chip and whose output terminal is connected to the clock input terminal of the functional module, is used to adjust the clock signal output by the SOC chip to adapt to the clock signal of the functional module. The power supply module is connected to the SOC chip, the functional module and the clock adjustment circuit respectively, and is used to supply power to the SOC chip, the functional module and the clock adjustment circuit.

2. The clock-sharing circuit according to claim 1, characterized in that, The clock circuit is a crystal resonator, i.e., a passive crystal oscillator; The second and fourth pins of the passive crystal oscillator are both grounded, the first pin is connected to the XIN pin of the SOC chip, and the third pin is connected to the XOUT pin of the SOC chip. A resistor R1 is connected between the first and third pins of the passive crystal oscillator. The resistor R1 is used to stabilize the oscillation and improve the clock waveform to reduce interference. The first pin of the passive crystal oscillator is also grounded through capacitor C1, and the third pin is also grounded through capacitor C2. The clock frequency offset can be reduced by adjusting the capacitance values ​​of capacitors C1 and C2.

3. The clock-sharing circuit according to claim 1, characterized in that, The power supply module includes a first power supply module, a second power supply module, and a third power supply module; The first power supply module is connected to the power input terminal of the SOC chip and is used to supply power to the SOC chip; The second power supply module is connected to the power input terminal of the functional module and is used to supply power to the functional module; The third power supply module is connected to the power input terminal of the clock adjustment circuit and is used to provide a reference voltage for the clock adjustment circuit.

4. The clock-sharing circuit according to claim 3, characterized in that, The first power supply module is a multi-channel regulated power supply circuit, including a DC-DC switching power supply and / or an LDO low dropout linear regulator. The number of power supplies and their voltage values ​​are determined by the power domain of the SOC chip. The second power supply module is a multi-channel regulated power supply circuit, including a DC-DC switching power supply and / or an LDO low-dropout linear regulator. The number of power supplies and their voltage values ​​are determined by the power domain of the functional module.

5. The clock-sharing circuit according to claim 3, characterized in that, The third power supply module is an LDO (low dropout linear regulator) used to provide a stable reference voltage for the clock adjustment circuit.

6. The clock-sharing circuit according to claim 3, characterized in that, When the power supply voltage of the functional module is the same as the power supply voltage of the SOC chip, the first power supply module and the second power supply module share the same power supply output.

7. The clock-sharing circuit according to claim 3, characterized in that, The clock adjustment circuit includes capacitor C3, resistor R2, and resistor R3; One end of the capacitor C3 is connected to the clock output terminal of the SOC chip, and is used to receive the initial clock signal output by the SOC chip and isolate the DC component in the initial clock signal. The other end of the capacitor C3 is connected to the clock input terminal of the functional module, one end of the resistor R2, and one end of the resistor R3, respectively. The other end of the resistor R2 is connected to the output terminal of the third power supply module, and is used to receive the reference voltage provided by the third power supply module. The other end of the resistor R3 is grounded; The resistors R2 and R3 form a voltage divider circuit, which is used to divide the reference voltage provided by the third power supply module to generate a DC bias voltage. The DC bias voltage is superimposed on the clock signal after isolating the DC component to obtain the adjusted clock signal.

8. The clock-sharing circuit according to claim 7, characterized in that, The capacitance of capacitor C3 is 100nF.

9. The clock-sharing circuit according to claim 7, characterized in that, When the voltage swing and DC bias level of the clock signal output by the SOC chip can directly meet the clock input requirements of the functional module, the capacitor C3 is replaced with a 0-ohm resistor, and the resistors R2 and R3 and the third power supply module are omitted.

10. A clock sharing method, applied to a clock sharing circuit as described in any one of claims 1 to 9, characterized in that, Includes the following steps: The clock circuit provides a reference operating clock for the SOC chip. The initial clock signal is output through the clock output terminal of the SOC chip; The clock adjustment circuit adjusts the initial clock signal output by the SOC chip to a clock signal that is compatible with the functional module. The power supply module provides power to the SOC chip, the functional module, and the clock adjustment circuit respectively.

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