Reset circuit, system on chip, reset method, apparatus and chip
Patent Information
- Application Number
- CN202611233290.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-14
- Publication Date
- 2026-10-09
AI Technical Summary
然而，这种独立复位机制容易导致跨域通信链路状态异常，引发数据访问错误或系统故障
[0033]上述复位电路、片上系统、复位方法、装置和芯片，通过引入复位电路，并将该复位电路的输入端分别与第一复位发生器的输出端和第二复位发生器的输出端连接，使得复位电路能够接收来自不同硬件域的复位信号，从而在任一硬件域发起复位时，复位电路均可捕获相应的复位事件。同时，通过将复位电路的输出端与目标异步桥接模块连接，目标异步桥接模块为第一异步桥接模块和/或第二异步桥接模块，使得复位电路能够在任一关联硬件域发起复位时直接触发目标异步桥接模块执行复位操作，从而无需依赖各硬件域之间对跨域复位指示进行时钟同步与解析，规避了因跨时钟传输所导致的复位延迟问题。同时，由于目标异步桥接模块能够在任一关联硬件域复位发起时及时完成复位，有效避免了复位期间因异步桥接模块状态不确定而引发跨域通信链路异常的风险，从而降低了数据错误及系统故障的发生概率，提升了多域SOC系统的复位可靠性和运行稳定性。
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Figure CN122884332A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a reset circuit, system-on-a-chip, reset method, apparatus and chip. Background Technology
[0002] A System on a Chip (SoC) typically employs a multi-domain partitioning architecture, dividing the chip into multiple hardware domains. These hardware domains communicate and interact across domains via asynchronous bridging modules.
[0003] In related technologies, multi-domain SOCs support a single-domain independent reset mechanism. However, this independent reset mechanism is prone to causing abnormal cross-domain communication link states, leading to data access errors or system failures. Summary of the Invention
[0004] Therefore, it is necessary to provide a reset circuit, on-chip system, reset method, device and chip to address the above-mentioned technical problems, so as to realize cross-domain reset linkage and avoid cross-domain communication link status abnormalities caused by independent reset mechanisms.
[0005] In a first aspect, this application provides a reset circuit applied to a system-on-a-chip (SoC). The SoC includes a first hardware domain and a second hardware domain associated with the first hardware domain. The first hardware domain is provided with a first reset generator and a first asynchronous bridge module, and the second hardware domain is provided with a second reset generator and a second asynchronous bridge module. The first asynchronous bridge module and the second asynchronous bridge module are connected in cross-domain communication.
[0006] The input terminal of the reset circuit is connected to the output terminal of the first reset generator and the output terminal of the second reset generator;
[0007] The output of the reset circuit is connected to the target asynchronous bridge module, which is the first asynchronous bridge module and / or the second asynchronous bridge module.
[0008] The reset circuit is configured as follows:
[0009] Receives a first reset signal output from a first reset generator and a second reset signal output from a second reset generator;
[0010] If at least one of the first reset signal and the second reset signal is valid, a bridging reset signal is sent to the target asynchronous bridging module. The bridging reset signal is used to trigger the target asynchronous bridging module to reset.
[0011] In one embodiment, the reset circuit is a logic circuit; when the reset circuit sends a bridge reset signal to the target asynchronous bridge module if at least one of the first and second reset signals is valid, it is configured to:
[0012] Perform logical operations on the first reset signal and the second reset signal; and,
[0013] If at least one of the first reset signal and the second reset signal is valid, a valid bridged reset signal is generated.
[0014] If both the first and second reset signals are invalid, an invalid bridged reset signal is generated.
[0015] In one embodiment, the reset circuit includes: a first reset sub-circuit, disposed in a first hardware domain, with its input connected to the output of a first reset generator and the output of a second reset generator, and its output connected to a first asynchronous bridge module; the first reset sub-circuit is used to send a bridged reset signal to the first asynchronous bridge module when at least one of the first reset signal and the second reset signal is valid; and a second reset sub-circuit, disposed in a second hardware domain, with its input connected to the output of the first reset generator and the output of the second reset generator, and its output connected to a second asynchronous bridge module; the second reset sub-circuit is used to send a bridged reset signal to the second asynchronous bridge module when at least one of the first reset signal and the second reset signal is valid.
[0016] In one embodiment, the first hardware domain is a host domain, the second hardware domain is a slave domain, and a delay unit is provided between the input terminal of the first reset sub-circuit and the output terminal of the first reset generator to delay the transmission of the first reset signal to the first reset sub-circuit.
[0017] In one embodiment, the first asynchronous bridging module is configured to: send a target reset signal to the second asynchronous bridging module when the first asynchronous bridging module receives a bridging reset signal, the target reset signal being used to trigger the second asynchronous bridging module to reset; and send a peripheral chip select (PSEL) control signal to the second asynchronous bridging module, the PSEL control signal being used to enable the second asynchronous bridging module to generate a PSEL signal.
[0018] In one embodiment, the second asynchronous bridging module resets the PSEL signal at a first moment via the bridging reset signal, earlier than the second asynchronous bridging module receives the target reset signal at a second moment.
[0019] Secondly, this application provides an on-chip system, including:
[0020] The first hardware domain includes a first reset generator and a first asynchronous bridge module.
[0021] The second hardware domain includes a second reset generator and a second asynchronous bridge module. The first asynchronous bridge module and the second asynchronous bridge module are connected for cross-domain communication.
[0022] A reset circuit, the input of which is connected to the output of the first reset generator and the output of the second reset generator; the output of the reset circuit is connected to the target asynchronous bridge module, which is the first asynchronous bridge module and / or the second asynchronous bridge module.
[0023] The reset circuit is configured as follows:
[0024] Receives a first reset signal output from a first reset generator and a second reset signal output from a second reset generator;
[0025] If at least one of the first reset signal and the second reset signal is valid, a bridging reset signal is sent to the target asynchronous bridging module. The bridging reset signal is used to trigger the target asynchronous bridging module to reset.
[0026] Thirdly, this application provides a reset method applied to a reset circuit in various possible implementations of the first aspect described above, the method comprising:
[0027] Receives a first reset signal output from a first reset generator and a second reset signal output from a second reset generator;
[0028] If at least one of the first reset signal and the second reset signal is valid, a bridging reset signal is sent to the target asynchronous bridging module. The bridging reset signal is used to trigger the target asynchronous bridging module to reset.
[0029] Fourthly, this application provides a reset device configured in various possible implementations of the reset circuit of the first aspect described above, the device comprising:
[0030] The receiving module is used to receive the first reset signal output by the first reset generator and the second reset signal output by the second reset generator.
[0031] The transmitting module is configured to send a bridging reset signal to the target asynchronous bridging module when at least one of the first reset signal and the second reset signal is valid. The bridging reset signal is used to trigger the target asynchronous bridging module to reset.
[0032] Fifthly, this application provides a chip that includes a reset circuit in various possible implementations of the first aspect described above.
[0033] The aforementioned reset circuit, on-chip system, reset method, device, and chip, by introducing a reset circuit and connecting its input terminals to the output terminals of a first reset generator and a second reset generator respectively, enable the reset circuit to receive reset signals from different hardware domains. This allows the reset circuit to capture the corresponding reset event when a reset is initiated in any hardware domain. Simultaneously, by connecting the output terminal of the reset circuit to a target asynchronous bridge module (which is either the first or second asynchronous bridge module), the reset circuit can directly trigger the target asynchronous bridge module to perform a reset operation when a reset is initiated in any associated hardware domain. This eliminates the need for clock synchronization and parsing between hardware domains for cross-domain reset indications, avoiding reset delay issues caused by cross-clock transmission. Furthermore, because the target asynchronous bridge module can complete the reset promptly when a reset is initiated in any associated hardware domain, the risk of cross-domain communication link anomalies due to the uncertain state of the asynchronous bridge module during the reset period is effectively avoided. This reduces the probability of data errors and system failures, improving the reset reliability and operational stability of the multi-domain SOC system. Attached Figure Description
[0034] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0035] Figure 1 This is a diagram illustrating the application environment of the reset circuit in one embodiment;
[0036] Figure 2 This is a schematic diagram of the connection relationship of the reset circuit in one embodiment;
[0037] Figure 3 This is a schematic diagram of the connection relationship of the reset circuit in another embodiment;
[0038] Figure 4 This is a schematic diagram of the system architecture of a system-on-a-chip in one embodiment;
[0039] Figure 5 This is a flowchart illustrating a reset method in one embodiment;
[0040] Figure 6 This is a diagram of the internal mechanism of the reset device in one embodiment. Detailed Implementation
[0041] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0042] The reset circuit provided in this embodiment can be applied to, for example... Figure 1 The application environment shown is as follows. The SOC (System on a Chip) includes multiple hardware domains, which may include a first hardware domain 10 and a second hardware domain 20. The first hardware domain 10 contains a first reset generator 11 and a first asynchronous bridge module 12, while the second hardware domain 20 contains a second reset generator 21 and a second asynchronous bridge module 22. The first asynchronous bridge module 12 and the second asynchronous bridge module 22 are connected for cross-domain communication.
[0043] For example, to achieve functional isolation, low-power management, and security compliance, SoCs typically adopt a multi-domain architecture, dividing the chip into multiple independent functional units. A hardware domain is a collection of hardware resources, which may include processor cores, interrupt controllers, clock controllers, and memory. A hardware domain supports the independent running of an operating system, and different hardware domains can run different operating systems. Each domain communicates and interacts with data across domains through an asynchronous bridging module.
[0044] For example, when a functional domain (or hardware domain) malfunctions, becomes idle, or has security level requirements, fault isolation and rapid recovery of that functional domain can be achieved through independent reset. For instance, the first reset generator 11 can generate a first reset signal to reset the first asynchronous bridge module 12.
[0045] For example, in at least two hardware domains with communication interaction, if the asynchronous bridging module of one hardware domain is reset while the asynchronous bridging module of the other hardware domain is not reset, it can easily lead to abnormal cross-domain communication link status. For instance, the first asynchronous bridging module may generate a glitch signal during the reset process, which may be transmitted to the second asynchronous bridging module that has not yet been reset through cross-domain communication interaction. This glitch signal may be recognized by the second asynchronous bridging module as a valid peripheral chip select signal, thereby selecting the peripheral interface in the second hardware domain and triggering unexpected read / write operations, i.e., triggering abnormal access to the second hardware domain. In severe cases, this may lead to system errors or even system crashes.
[0046] The applicant's research revealed that one possible implementation involves the first asynchronous bridge module in the first hardware domain sending a reset instruction (i.e., a target reset signal) to the second asynchronous bridge module in the second hardware domain when a reset is required, causing the second asynchronous bridge module to reset accordingly. For example, after receiving a reset signal, the first asynchronous bridge module 12 sends a reset instruction to the second asynchronous bridge module 22, instructing it to also reset. However, since each hardware domain uses an independent clock design, the reset signal is received through its own clock module during reset. This means the reset signal may not be received and processed in a timely manner, potentially leading to cross-domain communication link status anomalies, data access errors, or system failures.
[0047] In this embodiment, a reset circuit is introduced, and its input is connected to the outputs of a first reset generator and a second reset generator, respectively. This allows the reset circuit to receive reset signals from different hardware domains, enabling it to capture the corresponding reset event when a reset is initiated in any hardware domain. Furthermore, by connecting the output of the reset circuit to a target asynchronous bridge module (either the first or second asynchronous bridge module), the reset circuit can directly trigger the target asynchronous bridge module to perform a reset operation when a reset is initiated in any associated hardware domain. This eliminates the need for clock synchronization and parsing between hardware domains for cross-domain reset indications, avoiding reset delay issues caused by cross-clock transmission. Additionally, because the target asynchronous bridge module can complete the reset promptly when a reset is initiated in any associated hardware domain, the risk of cross-domain communication link anomalies due to uncertain asynchronous bridge module states during the reset period is effectively avoided. This reduces the probability of data errors and system failures, improving the reset reliability and operational stability of the multi-domain SOC system.
[0048] In an exemplary embodiment, a reset circuit is provided, which is applied to a system-on-a-chip (SoC). The SoC includes a first hardware domain and a second hardware domain associated with the first hardware domain. The first hardware domain includes a first reset generator and a first asynchronous bridge module, and the second hardware domain includes a second reset generator and a second asynchronous bridge module.
[0049] The input terminal of the reset circuit is connected to the output terminal of the first reset generator and the output terminal of the second reset generator;
[0050] The output of the reset circuit is connected to the target asynchronous bridge module, which is the first asynchronous bridge module and / or the second asynchronous bridge module.
[0051] The reset circuit is configured as follows:
[0052] Receives a first reset signal output from a first reset generator and a second reset signal output from a second reset generator;
[0053] If at least one of the first reset signal and the second reset signal is valid, a bridging reset signal is sent to the target asynchronous bridging module. The bridging reset signal is used to trigger the target asynchronous bridging module to reset.
[0054] The first hardware domain and the second hardware domain are related, for example, the first hardware domain and the second hardware domain are in a master-slave relationship, or there is a cross-domain communication connection between the asynchronous bridging module of the first hardware domain and the asynchronous bridging module of the second hardware domain.
[0055] In some embodiments, the first hardware domain can be a host domain (domain A), and the first asynchronous bridging module is an asynchronous bridge master module (AAPB MST, Asynchronous Advanced Peripheral Bus Bridge Master); the second hardware domain can be a slave domain (domain B), and the second asynchronous bridging module is an asynchronous bridge slave module (AAPB SLV, Asynchronous Advanced Peripheral Bus Bridge Slave). It should be noted that the bus protocol bridged by the asynchronous bridging module is not limited to APB (Advanced Peripheral Bus), but can also be other bus protocols such as AHB and AXI. The corresponding chip select control signals can be implemented with reference to the PSEL signal processing method in this application.
[0056] Asynchronous communication is established between the first asynchronous bridging module and the second asynchronous bridging module. The asynchronous communication logic may include data transmission logic and reset signal processing logic.
[0057] For example, the first asynchronous bridging module is configured to: upon receiving the bridging reset signal, send a target reset signal to the second asynchronous bridging module, the target reset signal being used to trigger a reset of the second asynchronous bridging module; and send a peripheral chip select (PSEL) control signal to the second asynchronous bridging module, the PSEL control signal being used by the second asynchronous bridging module to generate a PSEL signal. Optionally, the PSEL control signal can be sent to the second asynchronous bridging module via a D flip-flop (DFF) of the first asynchronous bridging module. The second asynchronous bridging module can be reset via the target reset signal and / or the bridging reset signal.
[0058] For example, the first asynchronous bridging module is also configured to: send a cross-domain access request to the second asynchronous bridging module; and pass address signals (Paddr) and data signals (pwdata) to the second asynchronous bridging module to avoid data loss.
[0059] For example, the second asynchronous bridging module is configured to: respond to a cross-domain access request by sending a request response back to the first asynchronous bridging module; process the PSEL control signal using double sync to generate a PSEL signal locally and send the PSEL signal to the peripheral interface. Optionally, the peripheral interface may include an IP module, also known as an Intellectual Property Core. An IP module can be understood as a peripheral function module. The double sync can be implemented using two cascaded D flip-flops, both of which use the local clock of the second hardware domain. Therefore, the PSEL control signal, transmitted from the first asynchronous bridging module to the second asynchronous bridging module and generated locally, undergoes at least two local clock cycles of the second hardware domain.
[0060] refer to Figure 2 As shown, the input terminal of the reset circuit 30 is connected to the output terminal of the first reset generator 11 and the output terminal of the second reset generator 21; the output terminal of the reset circuit 30 is connected to the target asynchronous bridge module 40, which is the first asynchronous bridge module and / or the second asynchronous bridge module.
[0061] The first reset signal output by the first reset generator 11 is used to indicate the first asynchronous bridge module to be reset, and the second reset signal output by the second reset generator 21 is used to indicate the second asynchronous bridge module to be reset.
[0062] Understandably, the reset circuit 30 receives the first reset signal output by the first reset generator 11 and the second reset signal output by the second reset generator 21, and sends a bridging reset signal to the target asynchronous bridging module when at least one of the first and second reset signals is valid. This enables the reset circuit to directly trigger the target asynchronous bridging module to perform a reset operation when a reset is initiated in any associated hardware domain, effectively avoiding the risk of cross-domain communication link abnormalities caused by the uncertain state of the asynchronous bridging module during the reset period.
[0063] In some embodiments, the reset circuit is a logic circuit; correspondingly, logical operations can be performed on the first reset signal and the second reset signal; and, if at least one of the first reset signal and the second reset signal is valid, a valid bridged reset signal is generated; if both the first reset signal and the second reset signal are invalid, an invalid bridged reset signal is generated. The logic circuit can be a combinational logic circuit. Since the reset circuit is implemented using a combinational logic circuit, it can complete the above logical operations and output the bridged reset signal without relying on the clock of any hardware domain.
[0064] refer to Figure 3 As shown, the reset circuit may include a first reset sub-circuit 31 and a second reset sub-circuit 32, wherein:
[0065] The input terminal of the first reset sub-circuit 31 is connected to the output terminal of the first reset generator 11 and the output terminal of the second reset generator 21, and the output terminal of the first reset sub-circuit 31 is connected to the first asynchronous bridge module 12. The first reset sub-circuit 31 is used to send a bridged reset signal to the first asynchronous bridge module 12 when at least one of the first reset signal and the second reset signal is valid.
[0066] The input terminal of the second reset sub-circuit 32 is connected to the output terminal of the first reset generator 11 and the output terminal of the second reset generator 21, and the output terminal of the second reset sub-circuit 32 is connected to the second asynchronous bridge module 22. The second reset sub-circuit 32 is used to send a bridged reset signal to the second asynchronous bridge module 22 when at least one of the first reset signal and the second reset signal is valid.
[0067] For example, the output of the first reset sub-circuit 31 can be connected to the reset rst pin in the first asynchronous bridge module 12; the output of the second reset sub-circuit 32 can be connected to the reset rst pin in the second asynchronous bridge module 22. For example, the reset rst pin of the asynchronous bridge module is connected to the reset synchronizer rst_sync inside the module. The reset synchronizer can be implemented by two cascaded D flip-flops, whose asynchronous reset terminal receives the bridged reset signal, and whose clock terminal is connected to the local clock of this hardware domain. In this way, when the bridged reset signal is valid, the asynchronous bridge module can immediately enter the reset state without waiting for the local clock, and the reset release process after the bridged reset signal is withdrawn is synchronized with the local clock to avoid metastability.
[0068] Understandably, when the first reset generator 11 in the first hardware domain responds to a reset event, it generates a valid first reset signal. At this time, regardless of whether the second reset signal is valid, both the first reset sub-circuit 31 and the second reset sub-circuit 32 will determine that at least one signal is valid. The first reset sub-circuit 31 sends a bridged reset signal to the first asynchronous bridge module 12, resetting the first asynchronous bridge module. The second reset sub-circuit 32 sends a bridged reset signal to the second asynchronous bridge module 22, resetting the second asynchronous bridge module. In this way, the associated reset of the first asynchronous bridge module 12 and the second asynchronous bridge module 22 is achieved.
[0069] Similarly, when the second reset generator 21 in the second hardware domain responds to a reset event, it generates a valid second reset signal. At this time, regardless of whether the first reset signal is valid, both the first reset sub-circuit 31 and the second reset sub-circuit 32 will determine that at least one signal is valid. The first reset sub-circuit 31 sends a bridge reset signal to the first asynchronous bridge module 12, resetting the first asynchronous bridge module. The second reset sub-circuit 32 sends a bridge reset signal to the second asynchronous bridge module 22, resetting the second asynchronous bridge module. In this way, the associated reset of the first asynchronous bridge module 12 and the second asynchronous bridge module 22 is achieved. Optionally, a target reset signal can be sent to the second asynchronous bridge module at or after the first asynchronous bridge module is reset. The target reset signal is used to trigger the reset of the second asynchronous bridge module. In the conventional method, if the first asynchronous bridge module resets before the second asynchronous bridge module, the first asynchronous bridge module is prone to generating glitches during the reset process, triggering abnormal access of the unreset second asynchronous bridge module. By introducing the above-mentioned reset circuit in this embodiment, when any reset signal is valid, the first asynchronous bridge module and the second asynchronous bridge module can be reset in a coordinated manner. Any glitches that may be generated will be shielded by the reset state, avoiding abnormal access due to the second asynchronous bridge module not being reset in time.
[0070] It should be noted that when the second hardware domain initiates a reset and causes the first asynchronous bridge module in the first hardware domain to reset in conjunction, cross-domain access transactions that have been initiated but not yet completed in the first hardware domain will be interrupted. For example, the first hardware domain can stop issuing new cross-domain access requests before requesting a reset; for cross-domain access requests that have already been issued, the bus within the first hardware domain can terminate the transaction through a timeout mechanism or an error response mechanism, thereby preventing the bus within the first hardware domain from hanging due to waiting for a response.
[0071] The aforementioned reset circuit, on-chip system, reset method, device, and chip, by introducing a reset circuit and connecting its input terminals to the output terminals of a first reset generator and a second reset generator respectively, enable the reset circuit to receive reset signals from different hardware domains. This allows the reset circuit to capture the corresponding reset event when a reset is initiated in any hardware domain. Simultaneously, by connecting the output terminal of the reset circuit to a target asynchronous bridge module (which is either the first or second asynchronous bridge module), the reset circuit can directly trigger the target asynchronous bridge module to perform a reset operation when a reset is initiated in any associated hardware domain. This eliminates the need for clock synchronization and parsing between hardware domains for cross-domain reset indications, avoiding reset delay issues caused by cross-clock transmission. Furthermore, because the target asynchronous bridge module can complete the reset promptly when a reset is initiated in any associated hardware domain, the risk of cross-domain communication link anomalies due to the uncertain state of the asynchronous bridge module during the reset period is effectively avoided. This reduces the probability of data errors and system failures, improving the reset reliability and operational stability of the multi-domain SOC system. Meanwhile, no additional complex clamping circuits or isolation logic are required; safe reset can be achieved simply through the logic fusion and timing control of the reset signal, reducing chip design complexity. Furthermore, because the two asynchronous bridge modules reset in tandem, any glitches that may occur during the reset process are masked by the reset state, preventing these glitches from being identified as valid peripheral chip select signals by the non-reset asynchronous bridge modules and triggering abnormal access.
[0072] In some embodiments, the first hardware domain is a host domain, the second hardware domain is a slave domain, and a delay unit is provided between the input terminal of the first reset sub-circuit and the output terminal of the first reset generator; the delay unit is used to delay the transmission of the first reset signal to the first reset sub-circuit.
[0073] The delay unit can be understood as a delay device or delay circuit located between the first reset generator and the first reset sub-circuit, used to delay the transmission of the first reset signal to the first reset sub-circuit.
[0074] For example, the delay unit is configured with an adjustable delay parameter, which is related to the delay time of the delay unit. By introducing the delay parameter, the first reset signal can be controlled to be transmitted to the first reset sub-circuit according to a preset delay time, so that the second asynchronous bridge module resets before the first asynchronous bridge module. For example, the delay unit can be implemented by a buffer BUF, an inverter chain, or a delay cell wrapper, and its delay parameter can be configured by the back-end during the physical implementation stage by adjusting the specifications or number of stages of the selected delay device.
[0075] For example, by adjusting the delay parameter, the first moment when the second asynchronous bridging module resets the PSEL signal via the bridging reset signal is earlier than the second moment when the second asynchronous bridging module receives the target reset signal. The transmission path of the target reset signal is as follows: the first asynchronous bridging module generates the target reset signal when or after receiving the bridging reset signal; the target reset signal is transmitted to the output of the second asynchronous bridging module via the output of the D flip-flop. In other words, when a reset occurs, the PSEL signal output by the second asynchronous bridging module must first be reset to 0 before the corresponding address paddr signal / data pwdata signal of the first asynchronous bridging module is allowed to change. Through the design of the delay unit, it can be ensured that the PSEL signal completes the reset before the address / data signal, fundamentally avoiding timing conflicts. For example, the delay time of the delay unit can be set to be no less than the time difference between the first and second moments without a delay unit, plus the timing margin required in the physical implementation stage. In the physical implementation stage, a dedicated timing check for the above two paths can be performed to verify whether the first moment is earlier than the second moment; if not, the delay parameter is increased.
[0076] In one exemplary embodiment, such as Figure 4 As shown, an on-chip system is provided, including:
[0077] The first hardware domain includes a first reset generator and a first asynchronous bridge module.
[0078] The second hardware domain includes a second reset generator and a second asynchronous bridge module. The first asynchronous bridge module and the second asynchronous bridge module are connected for cross-domain communication.
[0079] A reset circuit, the input of which is connected to the output of the first reset generator and the output of the second reset generator; the output of the reset circuit is connected to the target asynchronous bridge module, which is the first asynchronous bridge module and / or the second asynchronous bridge module.
[0080] The reset circuit is configured as follows:
[0081] Receives a first reset signal output from a first reset generator and a second reset signal output from a second reset generator;
[0082] If at least one of the first reset signal and the second reset signal is valid, a bridging reset signal is sent to the target asynchronous bridging module. The bridging reset signal is used to trigger the target asynchronous bridging module to reset.
[0083] In some embodiments, the reset circuit is a logic circuit; the reset circuit is configured to: perform logical operations on a first reset signal and a second reset signal; and, if at least one of the first reset signal and the second reset signal is valid, generate a valid bridged reset signal; and if both the first reset signal and the second reset signal are invalid, generate an invalid bridged reset signal.
[0084] In some embodiments, the reset circuit includes: a first reset sub-circuit and a second reset sub-circuit. The first reset sub-circuit is disposed in a first hardware domain, its input terminal is connected to the output terminals of a first reset generator and a second reset generator, and its output terminal is connected to a first asynchronous bridge module. The first reset sub-circuit is used to send a bridged reset signal to the first asynchronous bridge module when at least one of the first reset signal and the second reset signal is valid. The second reset sub-circuit is disposed in a second hardware domain, its input terminal is connected to the output terminals of the first reset generator and the second reset generator, and its output terminal is connected to a second asynchronous bridge module. The second reset sub-circuit is used to send a bridged reset signal to the second asynchronous bridge module when at least one of the first reset signal and the second reset signal is valid.
[0085] In some embodiments, the first hardware domain is a host domain, the second hardware domain is a slave domain, and a delay unit is provided between the input terminal of the first reset sub-circuit and the output terminal of the first reset generator. The delay unit is used to delay the transmission of the first reset signal to the first reset sub-circuit.
[0086] In some embodiments, the first asynchronous bridging module is configured to: send a target reset signal to the second asynchronous bridging module when the first asynchronous bridging module receives a bridging reset signal, the target reset signal being used to trigger the second asynchronous bridging module to reset; and send a peripheral chip select (PSEL) control signal to the second asynchronous bridging module, the PSEL control signal being used to enable the second asynchronous bridging module to generate a PSEL signal.
[0087] In some embodiments, the second asynchronous bridging module resets the PSEL signal at a first moment via the bridging reset signal, earlier than the second asynchronous bridging module receives the target reset signal at a second moment.
[0088] Figure 4 The example illustrates a first hardware domain denoted as domainA, a first reset generator denoted as rst_gen_a, and a first asynchronous bridge module denoted as AAPB MST; a second hardware domain denoted as domainB, a first reset generator denoted as rst_gen_b, and a first asynchronous bridge module denoted as AAPB SLV; domainA is the master domain, and domainB is the slave domain.
[0089] The first reset generator rst_gen_a outputs the first reset signal rst_a_b. rst_a_b enters the first reset sub-circuit in domain A through the delay unit BUF (as shown in the dashed box in domain A), and enters the second reset sub-circuit in domain B without passing through the delay unit (as shown in the dashed box in domain B).
[0090] The second reset generator rst_gen_b outputs the second reset signal rst_b_b, which enters the second reset sub-circuit in domain B and the first reset sub-circuit in domain A.
[0091] For example, the first reset signal, the second reset signal, and the bridged reset signal can all be active low; correspondingly, the first reset sub-circuit and the second reset sub-circuit can be implemented by AND gates.
[0092] If at least one of rst_a_b and rst_b_b is valid, the first reset sub-circuit generates a bridged reset signal merge_rst_b and sends the bridged reset signal to the rst pin of the AAPB MST. The AAPB MST is then reset by the reset synchronizer rst_sync in the AAPB MST.
[0093] If at least one of rst_a_b and rst_b_b is valid, the second reset sub-circuit generates a bridged reset signal merge_rst_b and sends the bridged reset signal to the rst pin of the AAPB SLV. The AAPB SLV is then reset by the reset synchronizer rst_sync in the AAPB SLV.
[0094] Based on the above process, it can be seen that when any asynchronous bridge module in AAPB MST and AAPB SLV is reset, the other asynchronous bridge module will be reset in conjunction. Simultaneously, by introducing a delay unit (BUF), the first reset signal is delayed in its transmission to the first reset sub-circuit. This prevents glitches that may occur when AAPB MST in the host domain is reset from being responded to by AAPB SLV in the slave domain, thus avoiding abnormal access due to untimely reset of the second asynchronous bridge module. Since AAPB MST is located in the host domain and outputs PSEL control signals, address signals, and data signals to the slave domain, a delay unit is set on the transmission path of the first reset signal. When domainB initiates a reset, the second reset signal rst_b_b arrives at both the first and second reset sub-circuits simultaneously. AAPB SLV resets its output PSEL signal to an invalid level while resetting itself, eliminating the aforementioned timing conflict. Therefore, a delay unit is not required on the transmission path of the second reset signal. The PSEL signal is the switch for peripheral access in the APB (Advanced Peripheral Bus) protocol, and its stability directly affects the reliability of the system. By employing two main mechanisms—cross-domain bridging module linkage reset and precise timing control of the reset signal—the stability and correctness of the Psel signal during the reset process are ensured.
[0095] Continue to refer to Figure 4 AAPB MST can send requests or payloads to AAPB SLV; AAPB SLV can respond to AAPB MST with acks or return the required payloads.
[0096] Optionally, the AAPB MST can send the PSEL control signal to the AAPB SLV via the D flip-flop (DFF). The AAPB SLV can process the PSEL control signal via double sync, generate the PSEL signal locally, and send the PSEL signal to the IP module.
[0097] Optionally, the AAPB MST can send a target reset signal to the AAPB SLV upon or after receiving the bridge reset signal. Specifically, the first moment when the second asynchronous bridge module resets the PSEL signal via the bridge reset signal is earlier than the second moment when the second asynchronous bridge module receives the target reset signal.
[0098] For example, the first reset generator rst_gen_a can also output a first clock disable signal clk_dis_a, which is sent to the clock gating unit CG in domainA after logic processing. The CG in domainA sends a first gated clock to the AAPB MST according to the first local clock clk_a and clk_dis_a. The second reset generator rst_gen_b can also output a second clock disable signal clk_dis_b, which is sent to the clock gating unit CG in domainB after logic processing. The CG in domainB sends a second gated clock to the AAPB SLV according to the second local clock clk_b and clk_dis_b.
[0099] For example, when the clock disable signal clk_dis is invalid, the CG outputs a normal clock; when the clock disable signal clk_dis is valid, the CG outputs a constant low level. Since the reset synchronizer in the asynchronous bridge module adopts the mode of asynchronous set and synchronous release, the reset release process requires the participation of the local clock. Therefore, before the bridge reset signal is de-asserted, the clock disable signal clk_dis can be de-asserted first to restore the local clock, ensuring that the asynchronous bridge module can exit the reset state normally.
[0100] It should be noted that the embodiments of the present application are not limited to the scenario with two hardware domains. For example, for a system-on-chip including three or more hardware domains, any two hardware domains with cross-domain communication connection can be provided with reset subcircuits in the above manner, that is, the input end of the reset subcircuit in each hardware domain receives the reset signal of the local hardware domain and the reset signals of each hardware domain that has cross-domain communication connection with the local hardware domain, and outputs a bridge reset signal to the asynchronous bridge module of the local hardware domain when at least one of the reset signals is valid. In this way, in scenarios such as multi-domain nested reset and emergency power-off reset, it is not necessary to separately design clamp circuits or isolation logic for different scenarios, and the linkage protection for cross-domain reset can be realized.
[0101] In addition, during the above reset process, only the asynchronous bridge modules with cross-domain communication connection are linked and reset, and other hardware resources such as processor cores and memories in the unreleased hardware domain are not affected and can continue to operate, thus ensuring the continuity of the core functions of the unreleased hardware domain while realizing cross-domain reset protection. A reset method is provided based on the above embodiment, which is applied to the above reset circuit, as Figure 5 shown, the method includes:
[0102] S501, receiving a first reset signal output by a first reset generator and a second reset signal output by a second reset generator;
[0103] S502, if at least one of the first reset signal and the second reset signal is valid, a bridging reset signal is sent to the target asynchronous bridging module. The bridging reset signal is used to trigger the target asynchronous bridging module to reset.
[0104] In some embodiments, logical operations can be performed on the first reset signal and the second reset signal; and, if at least one of the first reset signal and the second reset signal is valid, a valid bridged reset signal is generated; if both the first reset signal and the second reset signal are invalid, an invalid bridged reset signal is generated. The relevant details regarding the reset circuit and the on-chip system have been described above and will not be repeated here.
[0105] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0106] Based on the same inventive concept, this application also provides a reset device for implementing the reset method described above. The solution provided by this device is similar to the solution described in the above method; therefore, the specific limitations in one or more reset device embodiments provided below can be found in the limitations of the reset method described above, and will not be repeated here.
[0107] In one exemplary embodiment, such as Figure 6 As shown, a reset device is provided, comprising: a receiving module 601 and a transmitting module 602, wherein:
[0108] The receiving module 601 is used to receive the first reset signal output by the first reset generator and the second reset signal output by the second reset generator.
[0109] The sending module 602 is used to send a bridging reset signal to the target asynchronous bridging module when at least one of the first reset signal and the second reset signal is valid. The bridging reset signal is used to trigger the target asynchronous bridging module to reset.
[0110] In some embodiments, the sending module is specifically configured to perform logical operations on the first reset signal and the second reset signal; and, if at least one of the first reset signal and the second reset signal is valid, generate a valid bridged reset signal; and if both the first reset signal and the second reset signal are invalid, generate an invalid bridged reset signal.
[0111] Each module in the aforementioned reset device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.
[0112] In one exemplary embodiment, a chip is provided that includes the reset circuit or the system-on-a-chip described above.
[0113] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.
[0114] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.
[0115] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A reset circuit, characterized in that, The reset circuit is applied to a system-on-a-chip, which includes a first hardware domain and a second hardware domain associated with the first hardware domain. The first hardware domain is provided with a first reset generator and a first asynchronous bridge module, and the second hardware domain is provided with a second reset generator and a second asynchronous bridge module. The first asynchronous bridge module and the second asynchronous bridge module are connected in cross-domain communication. The input terminal of the reset circuit is connected to the output terminal of the first reset generator and the output terminal of the second reset generator; The output terminal of the reset circuit is connected to the target asynchronous bridge module, which is the first asynchronous bridge module and / or the second asynchronous bridge module. The reset circuit is configured as follows: Receives a first reset signal output by the first reset generator and a second reset signal output by the second reset generator; If at least one of the first reset signal and the second reset signal is valid, a bridging reset signal is sent to the target asynchronous bridging module, the bridging reset signal being used to trigger the target asynchronous bridging module to reset.
2. The reset circuit according to claim 1, characterized in that, The reset circuit is a logic circuit; when the reset circuit sends a bridged reset signal to the target asynchronous bridge module in the event that at least one of the first reset signal and the second reset signal is valid, it is configured as follows: Perform logical operations on the first reset signal and the second reset signal; and, A valid bridged reset signal is generated when at least one of the first reset signal and the second reset signal is valid; If both the first reset signal and the second reset signal are invalid, an invalid bridged reset signal is generated.
3. The reset circuit according to claim 1 or 2, characterized in that, The reset circuit includes: A first reset sub-circuit is disposed in the first hardware domain. The input terminal of the first reset sub-circuit is connected to the output terminal of the first reset generator and the output terminal of the second reset generator. The output terminal of the first reset sub-circuit is connected to the first asynchronous bridge module. The first reset sub-circuit is used to send a bridged reset signal to the first asynchronous bridge module when at least one of the first reset signal and the second reset signal is valid. The second reset sub-circuit is located in the second hardware domain. The input terminal of the second reset sub-circuit is connected to the output terminal of the first reset generator and the output terminal of the second reset generator. The output terminal of the second reset sub-circuit is connected to the second asynchronous bridge module. The second reset sub-circuit is used to send a bridged reset signal to the second asynchronous bridge module when at least one of the first reset signal and the second reset signal is valid.
4. The reset circuit according to claim 3, characterized in that, The first hardware domain is the host domain, the second hardware domain is the slave domain, and a delay unit is provided between the input terminal of the first reset sub-circuit and the output terminal of the first reset generator; The delay unit is used to delay the transmission of the first reset signal to the first reset sub-circuit.
5. The reset circuit according to claim 3, characterized in that, The first asynchronous bridge module is configured to be at least one of the following: When the first asynchronous bridging module receives the bridging reset signal, it sends a target reset signal to the second asynchronous bridging module. The target reset signal is used to trigger the second asynchronous bridging module to reset. A peripheral chip select (PSEL) control signal is sent to the second asynchronous bridge module. The PSEL control signal is used to generate a PSEL signal by the second asynchronous bridge module.
6. The reset circuit according to claim 5, characterized in that, The second asynchronous bridging module resets the PSEL signal at a first moment earlier than the second asynchronous bridging module receives the target reset signal at a second moment.
7. A system-on-a-chip, characterized in that, The on-chip system includes: A first hardware domain, wherein a first reset generator and a first asynchronous bridge module are provided; The second hardware domain includes a second reset generator and a second asynchronous bridge module, and the first asynchronous bridge module and the second asynchronous bridge module are connected in a cross-domain communication connection. A reset circuit, wherein the input terminal of the reset circuit is connected to the output terminal of the first reset generator and the output terminal of the second reset generator; the output terminal of the reset circuit is connected to a target asynchronous bridge module, wherein the target asynchronous bridge module is the first asynchronous bridge module and / or the second asynchronous bridge module; The reset circuit is configured as follows: Receives a first reset signal output by the first reset generator and a second reset signal output by the second reset generator; If at least one of the first reset signal and the second reset signal is valid, a bridging reset signal is sent to the target asynchronous bridging module, the bridging reset signal being used to trigger the target asynchronous bridging module to reset.
8. A reset method, characterized in that, The method, applied to the reset circuit according to any one of claims 1-6, comprises: Receives a first reset signal output by the first reset generator and a second reset signal output by the second reset generator; If at least one of the first reset signal and the second reset signal is valid, a bridging reset signal is sent to the target asynchronous bridging module, the bridging reset signal being used to trigger the target asynchronous bridging module to reset.
9. A reset device, characterized in that, The reset circuit configured according to any one of claims 1-6, the means comprising: The receiving module is used to receive the first reset signal output by the first reset generator and the second reset signal output by the second reset generator; The sending module is configured to send a bridging reset signal to the target asynchronous bridging module when at least one of the first reset signal and the second reset signal is valid, the bridging reset signal being used to trigger a reset of the target asynchronous bridging module.
10. A chip, characterized in that, The chip includes the reset circuit as described in any one of claims 1-6.