Dynamic division method, device and equipment of storage control chip power domain and medium

Abstract

The application provides a kind of dynamic partitioning method, device, equipment and medium of storage control chip power domain, comprising acquisition window memory access instruction, extraction block address, instruction type, time stamp, by address difference value dispersion and average jump distance index jointly represent spatial locality, by instruction interval construct time intensity vector, fusion multiple parameters to obtain load characteristic fingerprint, based on time intensity vector weighted benchmark transition matrix to obtain instantaneous transition matrix, combine current fingerprint to predict next window maximum probability load fingerprint;Look-up table obtains unit active state, according to dispersion and average jump distance index scale benchmark activity level, when dispersion and average jump distance index meet the locality condition, improve cache activity, inhibit main memory controller power consumption, combine energy consumption mapping coefficient to calculate energy efficiency gain, based on gain, fingerprint probability and switching energy consumption determine whether to output power supply switching scheme, realize power domain partition control and energy consumption optimization.

Description

Technical Field

[0001] This application belongs to the field of dynamic partitioning, and in particular relates to a method, apparatus, device and medium for dynamic partitioning of the power domain of a storage control chip. Background Technology

[0002] As the core hub connecting the host and the underlying storage medium, the operational efficiency and power consumption control capabilities of storage controller chips are becoming increasingly important. To meet the demands of high-speed data transmission and real-time data processing, modern storage controller chips typically integrate multiple functional modules, including cache controllers, main memory controllers, high-speed data channels, and various coprocessor units. In practical applications, the workloads carried by storage devices are significantly dynamic and complex. Access requests generated by different applications vary significantly in terms of instruction type, arrival frequency, and spatial address distribution, and these characteristics fluctuate continuously as the business operation phase changes. Faced with dynamically alternating complex loads, if the storage controller chip always maintains a uniform high-power operating mode, or only adopts a fixed and rigid power domain partitioning strategy, a large number of functional units may continue to consume power in idle or low-load states, resulting in energy waste and chip heat accumulation.

[0003] Currently, most common power management solutions rely on coarse-grained system utilization metrics or simple idle timeout mechanisms for passive power state adjustments. These methods typically only provide a lagging response to surface-level load changes, failing to delve into the spatiotemporal locality patterns inherent in memory access commands and lacking effective predictive capabilities for subsequent load trends. Due to the inability to accurately perceive and predict load characteristic changes, existing technologies often struggle to promptly define the actual activity requirements of different functional modules when faced with rapid switching or sudden read / write requests. This lack of perception and prediction capabilities not only causes chips to miss appropriate opportunities for refined power degradation but also easily leads to frequent power state switching due to short-sighted decisions. Frequent and disordered power switching incurs additional hardware switching energy consumption and may impact system performance, making it difficult to achieve substantial improvements in overall energy efficiency. Therefore, there is an urgent need in this field for an intelligent power management solution capable of extracting and predicting the deep behavioral characteristics of memory load in real time. Based on a comprehensive assessment of expected energy efficiency gains and switching overhead, it can achieve dynamic partitioning and refined control of the chip's internal power domain, thereby improving overall system energy efficiency while ensuring memory processing performance. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a method, apparatus, device, and medium for dynamically partitioning the power domain of a storage control chip, thereby resolving the technical issues in the prior art.

[0005] In a first aspect, the present invention provides the following technical solution: a method for dynamically partitioning the power domain of a storage control chip, comprising the following steps: The system acquires the sequence of storage access instructions within a time window, extracts the logical block address, instruction type, and arrival timestamp, calculates the dispersion of the logical block address difference between consecutive instructions, and calculates the mean of the absolute values ​​of the logical block address differences as the average hop distance index. The system quantifies spatial locality by combining the dispersion and the average hop distance index, calculates the instruction time interval distribution to generate a time intensity vector, and fuses the dispersion, the average hop distance index, the time intensity vector, and the instruction type ratio to generate the current load feature fingerprint. The instantaneous transition matrix is ​​generated by asymmetric weighting of the baseline transition probability matrix using the time intensity vector. Combined with the discrete load category index corresponding to the current load feature fingerprint, the probability distribution of the next window fingerprint is determined. The fingerprint corresponding to the highest probability is selected as the predictive load fingerprint. The baseline activity level corresponding to the current load and the predicted load is queried. The baseline activity level is scaled using the dispersion and the average hop distance index to calculate the expected activity level. When the spatial locality condition is met, the activity level of the cache unit is enhanced and the activity level of the main memory controller is suppressed. The expected energy efficiency gain is calculated based on the energy consumption difference between the current activity level and the expected activity level. Based on the expected energy efficiency gain, the probability of the predictive load fingerprint, and the switching energy consumption model decision, when the expected energy efficiency gain exceeds the threshold determined by the probability and switching overhead, a power configuration scheme for switching the power supply state of the functional unit is generated.

[0006] Preferably, the calculation of the dispersion and average jump distance indices of consecutive instruction logic block address differences to jointly quantify spatial locality includes: Calculate the difference sequence of adjacent instruction logic block addresses in the instruction sequence, and obtain the mean of the difference sequence; The variance median is obtained by calculating the square of the difference between each difference in the difference sequence and the mean, summing all the squares and dividing by the length of the difference sequence; the variance median is then calculated by taking the square root of the variance median. Take the absolute value of each difference in the difference sequence, sum all the absolute values ​​and divide by the length of the difference sequence to obtain the average jump distance index, and determine the strength of spatial locality based on the dispersion and the average jump distance index.

[0007] Preferably, the calculation of the instruction time interval distribution to generate a time intensity vector includes: Calculate the arrival timestamp difference between adjacent instructions in the instruction sequence to obtain the time interval sequence; The time interval is divided into multiple preset time intervals, and the frequency of the time interval sequence in each time interval is counted. Divide the frequency of each time interval by the total number of time interval sequences to obtain the time interval percentage value corresponding to each time interval; arrange the time interval percentage values ​​according to the order of the multiple preset time intervals to generate a time intensity vector.

[0008] Preferably, the step of generating the instantaneous transition matrix by performing asymmetric weighting on the reference transition probability matrix using the time intensity vector includes: Extract the short time interval proportion component and the long time interval proportion component from the time intensity vector; The result of multiplying the baseline probability that the state remains unchanged by the short time interval proportion component is used as the instantaneous weight value of the updated diagonal element to update the diagonal elements in the baseline transition probability matrix. The result of multiplying the baseline probability of state transition by the long time interval proportion component is used as the instantaneous weight value of the updated off-diagonal element to update the off-diagonal elements in the baseline transition probability matrix. The updated matrix is ​​normalized row by row so that the sum of the elements in each row is 1, thus generating the instantaneous transition matrix.

[0009] Preferably, the step of combining the current load feature fingerprint to determine the fingerprint probability distribution of the next window and selecting the fingerprint corresponding to the highest probability as the predictive load fingerprint includes: The current load feature fingerprint is mapped to a discrete load category index by a preset load category mapper, and an initial state vector is generated based on the discrete load category index, wherein the category probability corresponding to the discrete load category index is 1, and the probability of the other categories is 0. Multiply the initial state vector by the instantaneous transition matrix to calculate the next window fingerprint probability distribution vector; The load feature fingerprint corresponding to the element with the highest probability value in the next window fingerprint probability distribution vector is selected as the predictive load fingerprint.

[0010] Preferably, the step of calculating the expected energy efficiency gain based on the energy consumption difference between the current activity level and the expected activity level, and making decisions based on the expected energy efficiency gain, the probability of the predictive load fingerprint, and the switching energy consumption model, generates a power configuration scheme for the switching functional unit's power supply state when the expected energy efficiency gain exceeds a threshold determined by the probability and switching overhead, including: The window equivalent energy consumption corresponding to the current activity level and the window equivalent energy consumption corresponding to the expected activity level are calculated using a preset energy consumption mapping coefficient. The window equivalent energy consumption corresponding to the current activity level is subtracted from the window equivalent energy consumption corresponding to the expected activity level to obtain the energy saving amount. When the energy saving amount is positive, it is used as the expected energy efficiency gain. The state switching energy consumption cost of the functional unit to be switched is multiplied by a first conversion coefficient to obtain a first product. The topology delay cost of the functional unit to be switched is multiplied by a second conversion coefficient to obtain a second product. The first product and the second product are added to obtain the total cost of each functional unit. The total cost of all the functional units to be switched is accumulated and then divided by the maximum value between the probability of the predictive load fingerprint and the preset minimum probability lower limit to calculate the dynamic threshold. The first conversion coefficient and the second conversion coefficient are used to convert the energy consumption cost and delay cost into a dimension consistent with the expected energy efficiency gain. If the expected energy efficiency gain is greater than the dynamic threshold, a control signal to change the power supply state is generated to switch the power domain of the functional unit; otherwise, the current power supply state remains unchanged.

[0011] Secondly, the present invention provides the following technical solution: a dynamic partitioning device for the power domain of a storage control chip, comprising the following modules: The calculation module is used to acquire the memory access instruction sequence within a time window, extract the logical block address, instruction type and arrival timestamp, calculate the dispersion of the logical block address difference of consecutive instructions, and calculate the mean of the absolute value of the logical block address difference as the average hop distance index. The dispersion and the average hop distance index are used to quantify spatial locality, calculate the instruction time interval distribution to generate a time intensity vector, and fuse the dispersion, the average hop distance index, the time intensity vector and the instruction type ratio to generate the current load feature fingerprint. The selection module is used to generate an instantaneous transition matrix by performing asymmetric weighting on the baseline transition probability matrix using the time intensity vector, and to determine the next window fingerprint probability distribution by combining the discrete load category index corresponding to the current load feature fingerprint. The fingerprint corresponding to the highest probability is selected as the predictive load fingerprint. The baseline activity level corresponding to the current load and the predicted load is queried. The baseline activity level is scaled using the dispersion and the average hop distance index to calculate the expected activity level. When the spatial locality condition is met, the activity level of the cache unit is enhanced and the activity level of the main memory controller is suppressed. The generation module is used to calculate the expected energy efficiency gain based on the energy consumption difference between the current activity level and the expected activity level. Based on the expected energy efficiency gain, the probability of the predictive load fingerprint, and the switching energy consumption model decision, when the expected energy efficiency gain exceeds the threshold determined by the probability and switching overhead, a power configuration scheme for switching the power supply state of the functional unit is generated.

[0012] Furthermore, the calculation of the dispersion and average jump distance indices of consecutive instruction logic block address differences to jointly quantify spatial locality includes: Calculate the difference sequence of adjacent instruction logic block addresses in the instruction sequence, and obtain the mean of the difference sequence; The variance median is obtained by calculating the square of the difference between each difference in the difference sequence and the mean, summing all the squares and dividing by the length of the difference sequence; the variance median is then calculated by taking the square root of the variance median. Take the absolute value of each difference in the difference sequence, sum all the absolute values ​​and divide by the length of the difference sequence to obtain the average jump distance index, and determine the strength of spatial locality based on the dispersion and the average jump distance index.

[0013] Further, the calculation instruction time interval distribution generates a time intensity vector, including: Calculate the arrival timestamp difference between adjacent instructions in the instruction sequence to obtain the time interval sequence; The time interval is divided into multiple preset time intervals, and the frequency of the time interval sequence in each time interval is counted. Divide the frequency of each time interval by the total number of time interval sequences to obtain the time interval percentage value corresponding to each time interval; arrange the time interval percentage values ​​according to the order of the multiple preset time intervals to generate a time intensity vector.

[0014] Further, the step of generating the instantaneous transition matrix by performing asymmetric weighting on the reference transition probability matrix using the time intensity vector includes: Extract the short time interval proportion component and the long time interval proportion component from the time intensity vector; The result of multiplying the baseline probability that the state remains unchanged by the short time interval proportion component is used as the instantaneous weight value of the updated diagonal element to update the diagonal elements in the baseline transition probability matrix. The result of multiplying the baseline probability of state transition by the long time interval proportion component is used as the instantaneous weight value of the updated off-diagonal element to update the off-diagonal elements in the baseline transition probability matrix. The updated matrix is ​​normalized row by row so that the sum of the elements in each row is 1, thus generating the instantaneous transition matrix.

[0015] Further, the step of combining the current load feature fingerprint to determine the fingerprint probability distribution of the next window and selecting the fingerprint corresponding to the highest probability as the predictive load fingerprint includes: The current load feature fingerprint is mapped to a discrete load category index by a preset load category mapper, and an initial state vector is generated based on the discrete load category index, wherein the category probability corresponding to the discrete load category index is 1, and the probability of the other categories is 0. Multiply the initial state vector by the instantaneous transition matrix to calculate the next window fingerprint probability distribution vector; The load feature fingerprint corresponding to the element with the highest probability value in the next window fingerprint probability distribution vector is selected as the predictive load fingerprint.

[0016] Further, the step of calculating the expected energy efficiency gain based on the energy consumption difference between the current activity level and the expected activity level, and making decisions based on the expected energy efficiency gain, the probability of the predictive load fingerprint, and the switching energy consumption model, generates a power configuration scheme for the switching functional unit's power supply state when the expected energy efficiency gain exceeds a threshold determined by the probability and switching overhead, including: The window equivalent energy consumption corresponding to the current activity level and the window equivalent energy consumption corresponding to the expected activity level are calculated using a preset energy consumption mapping coefficient. The window equivalent energy consumption corresponding to the current activity level is subtracted from the window equivalent energy consumption corresponding to the expected activity level to obtain the energy saving amount. When the energy saving amount is positive, it is used as the expected energy efficiency gain. The state switching energy consumption cost of the functional unit to be switched is multiplied by a first conversion coefficient to obtain a first product. The topology delay cost of the functional unit to be switched is multiplied by a second conversion coefficient to obtain a second product. The first product and the second product are added to obtain the total cost of each functional unit. The total cost of all the functional units to be switched is accumulated and then divided by the maximum value between the probability of the predictive load fingerprint and the preset minimum probability lower limit to calculate the dynamic threshold. The first conversion coefficient and the second conversion coefficient are used to convert the energy consumption cost and delay cost into a dimension consistent with the expected energy efficiency gain. If the expected energy efficiency gain is greater than the dynamic threshold, a control signal to change the power supply state is generated to switch the power domain of the functional unit; otherwise, the current power supply state remains unchanged.

[0017] This invention extracts feature parameters from storage access instruction sequences and calculates dispersion, average hop distance, and time intensity vectors to generate a load feature fingerprint. This fingerprint accurately represents the spatial locality and temporal distribution characteristics of storage accesses, avoiding misjudgments of strong spatial locality due to small fluctuations in the difference between fixed large step sizes, thus improving the accuracy of load identification. The invention uses the time intensity vector to generate an instantaneous transition matrix to predict future load fingerprints and calculates the expected activity level based on dispersion and average hop distance, establishing a mapping between load characteristics and the activity states of different storage components, enabling proactive prediction of future system load changes. The difference in activity levels is converted into expected energy efficiency gains, and threshold judgments are made using predicted probabilities and switching energy consumption models. The power supply state of functional units is adjusted only when the benefit is confirmed to outweigh the switching overhead. This reduces ineffective or frequent power state switching, ensuring storage processing performance while reducing the overall energy consumption of the storage control chip, improving the granularity of system power management and overall operating energy efficiency. Attached Figure Description

[0018] Figure 1 A flowchart illustrating a method for dynamically partitioning the power domain of a storage control chip; Figure 2 A schematic diagram illustrating the dispersion under different loads; Figure 3 This is a schematic diagram of the probability distribution of the feature fingerprint in the next window; Figure 4 This is a schematic diagram showing the relationship between the decision threshold and energy consumption revenue. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] In this application, reference is made to Figure 1 As shown, a method for dynamically partitioning the power domain of a storage control chip includes the following steps: S1. Obtain the storage access instruction sequence within the time window, extract the logical block address, instruction type, and arrival timestamp, calculate the dispersion of the logical block address difference of consecutive instructions, and calculate the mean of the absolute values ​​of the logical block address differences as the average hop distance index. Quantify spatial locality by combining the dispersion and the average hop distance index, calculate the instruction time interval distribution to generate a time intensity vector, and fuse the dispersion, the average hop distance index, the time intensity vector, and the instruction type ratio to generate the current load feature fingerprint.

[0021] The system reads and parses the input / output request sequence sent by the host through a high-speed interconnect bus monitoring module or a non-volatile memory interface protocol parser. A time window of 1ms to 10ms is set, and the instructions within this window are traversed. The header of each input / output command packet is parsed, extracting the logical block address field, read / write flag field (i.e., instruction type), and arrival timestamp corresponding to the high-precision system clock. The signed difference between the logical block addresses of two adjacent access instructions is calculated to form a difference sequence. The standard deviation of this difference sequence is calculated as the dispersion. Simultaneously, the mean absolute value of the difference sequence is calculated as the average jump distance index. The dispersion represents the fluctuation of continuous address jump amplitude, and the average jump distance index represents the size of the address jump amplitude itself. When both the dispersion and the average jump distance index are below a preset dispersion threshold, strong spatial locality is determined. When the dispersion is low but the average jump distance index is high, it is determined to be a fixed large-step access, and not directly judged as strong spatial locality. This avoids misjudging fixed large-span jumps as local accesses based solely on the standard deviation.

[0022] The time interval sequence is obtained by calculating the difference in arrival timestamps of adjacent instructions. Using a histogram function or a histogram statistical unit composed of an on-chip comparator and a frequency register, the time interval is divided into multiple fixed logarithmic intervals. The frequency within each interval is counted and normalized to generate a time intensity vector composed of the frequencies of each interval. The ratio of read and write instructions to the total number of instructions within the statistical window yields the instruction type ratio. The discreteness, average hop distance index, elements of the time intensity vector, and the read / write instruction type ratio are concatenated into a one-dimensional real number array. This array is then linearly normalized and scaled according to pre-determined scaling parameters based on the maximum and minimum values ​​of historical training samples. The normalized array is then feature-encoded using a multilayer perceptron network or support vector machine classifier to obtain a low-dimensional continuous feature vector. This low-dimensional continuous feature vector is then mapped to discrete load category indices using a pre-defined load category mapper. The load category mapper can be implemented using nearest neighbor matching of cluster centers, support vector machine classification output categories, or multilayer perceptron output of the highest probability category. In this paper, the current load feature fingerprint can be represented as a low-dimensional continuous feature vector when participating in feature fusion, and as the discrete load category index or its corresponding One-Hot state vector when participating in Markov transition calculation. The dispersion of different loads is illustrated as follows: Figure 2 As shown.

[0023] In some embodiments, the calculation of the dispersion and average jump distance metrics of consecutive instruction logic block address differences to jointly quantify spatial locality includes: Calculate the difference sequence of adjacent instruction logic block addresses in the instruction sequence, and obtain the mean of the difference sequence; The variance median is obtained by calculating the square of the difference between each difference in the difference sequence and the mean, summing all the squares and dividing by the length of the difference sequence; the variance median is then calculated by taking the square root of the variance median. Take the absolute value of each difference in the difference sequence, sum all the absolute values ​​and divide by the length of the difference sequence to obtain the average jump distance index, and determine the strength of spatial locality based on the dispersion and the average jump distance index.

[0024] In the firmware queue of the front-end interface of the storage controller chip, extract the current time window, such as 1ms to 5ms, preferably 2ms, containing N instructions accumulated within that time window. Typically, N ranges from 128 to 1024, for example, N=256. Assume the extracted logical block address LBA sequence is... , ,..., Subtracting each element sequentially generates a difference sequence D containing 255 elements, where the i-th difference is... To represent address jumps, the arithmetic mean of the difference sequence will be calculated. That is, all The sum is divided by 255. For example, if the sequence has local sequential reads, a large number of... A value of 1 indicates a continuous 4KB logic block, while a few instances of large-scale random jumps occur; the calculated average value... It could be 150. Perform the standard deviation calculation logic: for each difference... Subtract the mean The deviations are obtained, and the sum of squares of all deviations is calculated using a DSP multiplier-accumulator. The quotient V is obtained by dividing the sum of squares by the length of the difference sequence, 255.

[0025] To reduce subsequent hardware resource consumption, a lookup table method or a Newton-Raphson iteration hardware accelerator is used to perform a square root operation on the quotient V to obtain the dispersion. Furthermore, the average jump distance index was calculated. The method inputs both σ and M into the spatial locality discrimination logic. If σ is less than a preset dispersion threshold (e.g., 32) and M is less than a preset average hop distance threshold (e.g., 64 logic blocks), the load within the time window is determined to exhibit highly concentrated spatial locality. If σ is small but M is much larger than the preset average hop distance threshold, it indicates that adjacent accesses may exhibit fixed large step lengths, which is not considered a strong basis for cache locality. For example, in reading a video stream, σ is calculated to be 1.5, and the average hop distance M is close to 1, indicating extremely strong local order characteristics. However, in a random database retrieval load, σ may increase to 4096, or the average hop distance M may be significantly higher than the preset average hop distance threshold. This method reduces the error of traditional simple hit rate judgments with absolutely specific numerical statistics and can achieve parallelism of processing at least 8 deviation operations in a single clock cycle through hardware computing units, improving the real-time performance of chip I / O feature recognition.

[0026] In some embodiments, the calculation of the instruction time interval distribution to generate a time intensity vector includes: Calculate the arrival timestamp difference between adjacent instructions in the instruction sequence to obtain the time interval sequence; The time interval is divided into multiple preset time intervals, and the frequency of the time interval sequence in each time interval is counted. Divide the frequency of each time interval by the total number of time interval sequences to obtain the time interval percentage value corresponding to each time interval; arrange the time interval percentage values ​​according to the order of the multiple preset time intervals to generate a time intensity vector.

[0027] The controller's clock timer timestamps each enqueued memory instruction with a timestamp in nanoseconds. For N commands within the window, N-1 time intervals are calculated. This forms a time interval sequence. Five time intervals, defined by four register boundaries, are pre-defined within the chip, preferably divided into the following ranges: [0, 100ns), [100ns, 500ns), [500ns, 2μs), [2μs, 10μs), [10μs, +∞). The hardware monitoring unit is equipped with a set of parallel comparators and five frequency accumulation registers C1 to C5. When each... After the calculation is completed, the parallel comparator determines... The range it belongs to will be incremented by 1, driving the corresponding register value to increment by 1. For example, if a If the accumulator value is 350ns, then the value of accumulator C2 will increment by 1.

[0028] At the end of the time window, assuming the total number of time intervals is N-1, such as 255, the division logic in the chip divides the values ​​of each frequency register C1 to C5 by 255. Assuming a burst write load, the frequencies of C1 to C5 are 200, 30, 15, 10, and 0 respectively, the division operation will yield five percentage quotients: [0.78, 0.12, 0.06, 0.04, 0.00]. These five quotients are concatenated sequentially in the registers to form a 40-bit time intensity vector, with each quotient represented by an 8-bit fixed-point decimal. The generation process of this vector seamlessly incorporates the quantization of load time-domain density. A large proportion of short intervals clearly indicates sudden and dense high-intensity access, serving as a benchmark for subsequent probability transitions in calculations. This ensures the hardware can make timely decisions regarding state maintenance or power supply adjustments during periods of high intensity. It's important to note that the time intensity vector itself is a frequency histogram composed of the proportions of each time interval; it does not directly store the value of each specific time interval. Subsequent weighted transition matrices prioritize the use of the short and long time interval proportions. If an average time interval needs to be estimated, the estimate is obtained by weighted summation of the representative time values ​​of each time interval and their corresponding proportions, rather than directly extracting the inverse of the precise average time interval from the time intensity vector.

[0029] S2, using the time intensity vector to perform asymmetric weighting on the baseline transition probability matrix to generate an instantaneous transition matrix, combining the discrete load category index corresponding to the current load feature fingerprint to determine the next window fingerprint probability distribution, selecting the fingerprint corresponding to the highest probability as the predictive load fingerprint, querying the baseline activity level corresponding to the current load and the predicted load, scaling the baseline activity level using the dispersion and the average hop distance index to calculate the expected activity level, and enhancing the cache unit activity level and suppressing the main memory controller activity level when the spatial locality condition is met.

[0030] A baseline transition probability matrix for the Markov state transition model is pre-trained based on historical workloads. This matrix represents the fixed switching probabilities between different workload fingerprints. The low-dimensional continuous feature vector obtained in S1 is first input into the workload category mapper to obtain the current workload category index, which is then used as the discrete state index of the Markov model. The proportions of short and long time intervals in the time intensity vector are extracted, instead of directly extracting the reciprocal of the average time interval from the frequency histogram as a weighting factor. When the proportion of short time intervals is high, the state-keeping weights corresponding to the diagonal elements in the baseline transition probability matrix are increased; when the proportion of long time intervals is high, the state transition weights corresponding to the off-diagonal elements are increased. After weighting, normalization is performed by summing and dividing by rows, ensuring the sum of each row's elements is 1, generating the instantaneous transition matrix. Combining Markov state transition calculation, the One-Hot state vector corresponding to the current load category index is used as the initial state input. A matrix multiplication operation is performed with the instantaneous transition matrix to output the probability distribution vectors of each state index in the next window. The maximum index in the probability distribution vector is found using the numpy.argmax function, and the load feature fingerprint corresponding to this maximum index is determined as the predictive load fingerprint. The probability distribution of the feature fingerprint in the next window is illustrated below. Figure 3 As shown.

[0031] A two-dimensional hash table reflecting the utilization rate of each hardware unit by different discrete load category indices is pre-defined as the activation matrix. Key-value matching is performed in the activation matrix using the current discrete load category index and the predicted discrete load category index to find the corresponding baseline activity level vector. Specifically, the current activity level vector corresponding to the current discrete load category index is used as the current baseline for subsequent energy consumption difference calculations; the predicted baseline activity level vector corresponding to the predicted discrete load category index is used as the basis for subsequent dispersion scaling. The previously calculated dispersion and average hop distance index are input into an inverse proportional mapping function. When the dispersion is lower than a preset dispersion threshold and the average hop distance index is lower than a preset average hop distance threshold, a cache unit amplification factor greater than 1 and a main memory controller shrinkage factor less than 1 are output. The cache unit base activity in the predicted baseline activity level vector is multiplied by the cache unit amplification factor, and the main memory controller base activity is multiplied by the main memory controller shrinkage factor to obtain the expected activity level. If the average hop distance index does not satisfy the locality condition, the cache enhancement and main memory controller suppression mapping corresponding to low dispersion are not executed. This mapping strategy matches the high probability of cache hits during consecutive address accesses by reducing the activity level of the main memory controller and increasing the activity level of cache units.

[0032] In some embodiments, generating an instantaneous transition matrix by performing asymmetric weighting on the reference transition probability matrix using the time intensity vector includes: Extract the short time interval proportion component and the long time interval proportion component from the time intensity vector; The result of multiplying the baseline probability that the state remains unchanged by the short time interval proportion component is used as the instantaneous weight value of the updated diagonal element to update the diagonal elements in the baseline transition probability matrix. The result of multiplying the baseline probability of state transition by the long time interval proportion component is used as the instantaneous weight value of the updated off-diagonal element to update the off-diagonal elements in the baseline transition probability matrix. The updated matrix is ​​normalized row by row so that the sum of the elements in each row is 1, thus generating the instantaneous transition matrix.

[0033] The chip firmware stores a K×K dimensional baseline transition probability matrix P. For example, when K=8, it corresponds to 8 basic load modes. The element P(i,j) represents the historical baseline probability of transitioning from load mode i to load mode j. The proportion of the [0,100ns) interval is extracted from the time intensity vector as the short time interval proportion component. ,extract Interval proportion as a component of long time interval proportion In this embodiment, "the probability" refers to the baseline probability P(i,j) at the corresponding position in the baseline transition probability matrix, not the next window state probability or the predictive load fingerprint probability. During the update process, for the diagonal elements P(i,i) of the matrix, i.e., the probability that the state remains unchanged, the following steps are performed: The calculation. For example, the original baseline diagonal probability is 0.6, and the current... If the value is as high as 0.8, the updated weight value increases to 1.08. For the off-diagonal elements P(i,j) of the matrix, where i is not equal to j, execute... The operation. If If the value is 0.5, the probability of being off-diagonal increases, and it is expected that the system may enter other load or sleep states.

[0034] After asymmetric weighting, the sum of each row of the matrix may no longer be 1. Therefore, a hardware accumulator is used to calculate the sum of all elements in each row of the updated matrix. The new value of each row element is calculated using hardware division logic. This is used to complete the normalization. For example, the sum of the i-th row above... If the value reaches 1.5, then the original updated value of 1.08 is normalized to 0.72. This row-wise normalization method ensures that the sum of the transition probabilities in each row is 1, unlike norm normalization; norm normalization can only restrict the vector norm and cannot guarantee that the sum of the probabilities in each row is 1. Extremely dense, short-interval instructions can solidify the current state exponentially, preventing invalid power domain switching caused by minor perturbations, while lengthy time intervals can enhance the sensitivity of state transitions, giving the transition matrix adjustment capabilities.

[0035] In some embodiments, determining the fingerprint probability distribution of the next window by combining the current load feature fingerprint and selecting the fingerprint corresponding to the highest probability as the predictive load fingerprint includes: The current load feature fingerprint is mapped to a discrete load category index by a preset load category mapper, and an initial state vector is generated based on the discrete load category index, wherein the category probability corresponding to the discrete load category index is 1, and the probability of the other categories is 0. Multiply the initial state vector by the instantaneous transition matrix to calculate the next window fingerprint probability distribution vector; The load feature fingerprint corresponding to the element with the highest probability value in the next window fingerprint probability distribution vector is selected as the predictive load fingerprint.

[0036] Within the state machine module of the memory chip, the low-dimensional continuous feature vector of the current load is first mapped to a discrete load category index, such as the third type of load, which represents the random read mode, and encoded as a 1×K-dimensional initial state vector of One-Hot form. Assuming there are 8 load patterns K=8, then Specifically, it is represented as [0,0,1,0,0,0,0,0]. This initial state vector is obtained through an on-chip multiply-accumulate array. The 8×8 instantaneous transition matrix generated in the previous step Perform vector-matrix multiplication. Because... With only the third element being 1, this multiplication can be simplified in hardware circuitry to addressing and extracting the third row of the instantaneous transition matrix, saving clock cycles. The extracted row vector is the fingerprint probability distribution vector for the next window. .

[0037] Assuming the extracted distribution vector The vector [0.05, 0.10, 0.45, 0.30, 0.02, 0.05, 0.03, 0.00] represents the estimated probability of entering each mode in the next time window. The distribution vector... A parallel multi-path comparison tree is fed in. The comparison tree consists of seven hardware comparators, which can find the maximum value (0.45) and its index (2) within one clock cycle from the eight fixed-point decimals. Therefore, the extracted predictive load fingerprint remains a type 3 load. This mechanism reduces the complexity of neural network inference, achieving microsecond-level load determination by combining a simplified Markov chain concept with pure hardware parallel comparison.

[0038] S3. Calculate the expected energy efficiency gain based on the energy consumption difference between the current activity level and the expected activity level. Based on the expected energy efficiency gain, the probability of the predictive load fingerprint, and the switching energy consumption model decision, when the expected energy efficiency gain exceeds the threshold determined by the probability and switching overhead, generate a power configuration scheme for switching the power supply state of the functional unit.

[0039] The dynamic and static power consumption indicators of each hardware functional module under different operating frequencies and sleep states are measured and calibrated in advance using a power analysis instrument. A linear mapping coefficient table of energy consumption values ​​from the activity level of each hardware unit to the time window is constructed, which is the preset energy consumption mapping coefficient. If the calibration table is in power, the power coefficient is first multiplied by the current time window length to convert it into the equivalent energy consumption coefficient within the time window, so that it is consistent with the switching energy consumption overhead in terms of dimension. Subsequently, the expected energy efficiency gain, state switching energy consumption overhead, topology delay equivalent overhead, and dynamic threshold are all calculated and compared using the window equivalent energy consumption dimension. Through vector subtraction, the window energy consumption corresponding to the expected activity level is subtracted from the window energy consumption corresponding to the current activity level to obtain the energy saving amount. When the energy saving amount is positive, it is taken as the expected energy efficiency gain. If the calculation result is zero or negative, it means that the target configuration cannot bring energy saving benefits and does not trigger energy-saving power domain switching.

[0040] The microcontroller's built-in switching energy consumption model evaluation function is invoked to calculate the Joule-level switching overhead energy required to switch from the current power supply state to the target state, based on the wake-up time, shutdown time, and power supply switching transient current given in the chip hardware specifications. The switching overhead energy is added to the equivalent energy consumption after conversion to delay overhead to obtain the total overhead of the functional unit to be switched. This total overhead is then divided by the larger of the maximum probability value of the predictive load fingerprint and the preset minimum probability lower limit, plus a preset safety margin tolerance, to generate a decision threshold. Here, topology delay overhead represents the state switching delay cost of the functional unit to be switched due to power supply paths, clock trees, wake-up timing, or upstream and downstream dependencies. The higher the predictive load fingerprint probability, the lower the dynamic threshold; the lower the predictive load fingerprint probability, the higher the dynamic threshold. A hardware comparator or logical decision branch instruction is invoked to compare the expected energy efficiency gain with the decision threshold. If the expected energy efficiency gain is positive and greater than the threshold, it indicates that the long-term energy consumption benefit from performing the state switch exceeds the transient switching loss. In this case, a planning algorithm is used to search for and select the lowest combination of supply voltage and lowest clock frequency that meets the expected activity level. The system modifies the register configuration sequence on the control bus based on the selected combination, thereby generating a power configuration scheme. This scheme is then sent to the power management integrated circuit and the voltage and frequency adjustment controller to change the power supply and clock states of each power domain of the chip. If the expected energy efficiency gain is negative, meaning the target power supply state will increase window power consumption, the system will not trigger a switch based on the energy efficiency benefit criterion, thus preventing scenarios with increased power consumption from being mistakenly identified as energy-saving gains.

[0041] In some embodiments, the step of calculating the expected energy efficiency gain based on the energy consumption difference between the current activity level and the expected activity level, and making decisions based on the expected energy efficiency gain, the probability of the predictive load fingerprint, and the switching energy consumption model, and generating a power configuration scheme for the switching functional unit's power supply state when the expected energy efficiency gain exceeds a threshold determined by the probability and switching overhead, includes: The window equivalent energy consumption corresponding to the current activity level and the window equivalent energy consumption corresponding to the expected activity level are calculated using a preset energy consumption mapping coefficient. The window equivalent energy consumption corresponding to the current activity level is subtracted from the window equivalent energy consumption corresponding to the expected activity level to obtain the energy saving amount. When the energy saving amount is positive, it is used as the expected energy efficiency gain. The state switching energy consumption cost of the functional unit to be switched is multiplied by a first conversion coefficient to obtain a first product. The topology delay cost of the functional unit to be switched is multiplied by a second conversion coefficient to obtain a second product. The first product and the second product are added to obtain the total cost of each functional unit. The total cost of all the functional units to be switched is accumulated and then divided by the maximum value between the probability of the predictive load fingerprint and the preset minimum probability lower limit to calculate the dynamic threshold. The first conversion coefficient and the second conversion coefficient are used to convert the energy consumption cost and delay cost into a dimension consistent with the expected energy efficiency gain. If the expected energy efficiency gain is greater than the dynamic threshold, a control signal to change the power supply state is generated to switch the power domain of the functional unit; otherwise, the current power supply state remains unchanged.

[0042] During the power management module's decision-making phase, the current activity level is obtained, such as 85%, indicating that the corresponding module is in a high-activity state; the expected activity level, such as 15%, indicates that the corresponding module is predicted to reduce to low-power operation in the next window. The difference between the two expected reductions in activity level is 70%. The chip has a built-in energy consumption mapping coefficient. The optimal setting is the equivalent energy consumption per unit activity level within a single time window, for example, 2.5 pJ / %. If the original measurement result is a power coefficient, it is converted into the window equivalent energy consumption according to the relationship E=P×T combined with the time window length, and then written into the equivalent energy consumption coefficient table. The difference between the current activity level and the expected activity level is used to obtain the difference in activity level that can be reduced, and combined with the window equivalent energy consumption coefficient, the expected energy efficiency gain is obtained. For example, when using 2.5 pJ / %, a 70% reduction in activity level corresponds to an expected energy efficiency gain of 175 pJ. If the activity level increases from 15% to 85%, it indicates an increase in window energy consumption, and the calculation result is not considered as a positive expected energy efficiency gain.

[0043] Calculating the switching penalty overhead: For functional units such as flash channel controllers, there is an inherent state switching energy consumption overhead when switching from Active state to low-power state. Such as 45pJ and topology delay overhead For example, 1.2 μs. Multiply by the first conversion coefficient α and the second conversion coefficient β stored in the control register to unify the unit of pJ. For instance, if α is 1 and β is 52.5 pJ / μs, then the state switching energy consumption of 45 pJ corresponds to the first product of 45 pJ, the topology delay of 1.2 μs corresponds to the second product of 63 pJ, and the total overhead of a single module is 108 pJ. If multiple modules are involved in linkage, the overhead of all single modules is accumulated, assuming a total of 135 pJ.

[0044] The determination of the dynamic threshold is influenced by the predictive load fingerprint probability. The total accumulated overhead of 135pJ is divided by the larger of the predictive load fingerprint probability and the preset minimum probability lower limit. Assuming this probability is 0.75 and greater than the preset minimum probability lower limit, the actual dynamic threshold of 180pJ is obtained. At this point, the hardware logic uses a digital comparator to make a decision. Since the calculated expected energy efficiency gain of 175pJ is less than the dynamic threshold of 180pJ, it indicates that implementing a power state switch under the current uncertain probability is not worthwhile, and the current power supply state is maintained to avoid energy waste. Conversely, if the predicted probability is extremely high, such as 0.95, causing the threshold to drop to approximately 142pJ, and the expected energy efficiency gain of 175pJ exceeds the threshold, the power domain controller will reduce the operating voltage of the corresponding functional module, shut down or reduce the gate clock, and issue a low-power state switching command, completing a predictive chip power allocation. The relationship curve between the decision threshold and energy consumption gain is illustrated in the figure below. Figure 4 As shown.

[0045] Based on the above-described method for dynamically partitioning the power domain of a memory control chip, this application also provides a device for dynamically partitioning the power domain of a memory control chip, comprising the following modules: The calculation module is used to acquire the memory access instruction sequence within a time window, extract the logical block address, instruction type and arrival timestamp, calculate the dispersion of the logical block address difference of consecutive instructions, and calculate the mean of the absolute value of the logical block address difference as the average hop distance index. The dispersion and the average hop distance index are used to quantify spatial locality, calculate the instruction time interval distribution to generate a time intensity vector, and fuse the dispersion, the average hop distance index, the time intensity vector and the instruction type ratio to generate the current load feature fingerprint. The selection module is used to generate an instantaneous transition matrix by performing asymmetric weighting on the baseline transition probability matrix using the time intensity vector, and to determine the next window fingerprint probability distribution by combining the discrete load category index corresponding to the current load feature fingerprint. The fingerprint corresponding to the highest probability is selected as the predictive load fingerprint. The baseline activity level corresponding to the current load and the predicted load is queried. The baseline activity level is scaled using the dispersion and the average hop distance index to calculate the expected activity level. When the spatial locality condition is met, the activity level of the cache unit is enhanced and the activity level of the main memory controller is suppressed. The generation module is used to calculate the expected energy efficiency gain based on the energy consumption difference between the current activity level and the expected activity level. Based on the expected energy efficiency gain, the probability of the predictive load fingerprint, and the switching energy consumption model decision, when the expected energy efficiency gain exceeds the threshold determined by the probability and switching overhead, a power configuration scheme for switching the power supply state of the functional unit is generated.

[0046] In this specification, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise limited, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this document, "a," "an," "the," "the," and "its" may also include plural forms unless the context clearly indicates otherwise. "Multiple" refers to at least two, such as 2, 3, 5, or 8, etc. "And / or" includes any and all combinations of the associated listed items.

[0047] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The various embodiments can be combined as needed, and the same or similar parts can be referred to each other.

[0048] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for dynamically partitioning the power domain of a storage control chip, characterized in that, Includes the following steps: The system acquires the sequence of storage access instructions within a time window, extracts the logical block address, instruction type, and arrival timestamp, calculates the dispersion of the logical block address difference between consecutive instructions, and calculates the mean of the absolute values ​​of the logical block address differences as the average hop distance index. The system quantifies spatial locality by combining the dispersion and the average hop distance index, calculates the instruction time interval distribution to generate a time intensity vector, and fuses the dispersion, the average hop distance index, the time intensity vector, and the instruction type ratio to generate the current load feature fingerprint. The instantaneous transition matrix is ​​generated by asymmetric weighting of the baseline transition probability matrix using the time intensity vector. Combined with the discrete load category index corresponding to the current load feature fingerprint, the probability distribution of the next window fingerprint is determined. The fingerprint corresponding to the highest probability is selected as the predictive load fingerprint. The baseline activity level corresponding to the current load and the predicted load is queried. The baseline activity level is scaled using the dispersion and the average hop distance index to calculate the expected activity level. When the spatial locality condition is met, the activity level of the cache unit is enhanced and the activity level of the main memory controller is suppressed. The expected energy efficiency gain is calculated based on the energy consumption difference between the current activity level and the expected activity level. Based on the expected energy efficiency gain, the probability of the predictive load fingerprint, and the switching energy consumption model decision, when the expected energy efficiency gain exceeds the threshold determined by the probability and switching overhead, a power configuration scheme for switching the power supply state of the functional unit is generated.

2. The method according to claim 1, characterized in that, The dispersion and average jump distance metrics for calculating the address differences of consecutive instruction logic blocks are used to jointly quantify spatial locality, including: Calculate the difference sequence of adjacent instruction logic block addresses in the instruction sequence, and obtain the mean of the difference sequence; The variance median is obtained by calculating the square of the difference between each difference in the difference sequence and the mean, summing all the squares and dividing by the length of the difference sequence; the variance median is then calculated by taking the square root of the variance median. Take the absolute value of each difference in the difference sequence, sum all the absolute values ​​and divide by the length of the difference sequence to obtain the average jump distance index, and determine the strength of spatial locality based on the dispersion and the average jump distance index.

3. The method according to claim 2, characterized in that, The calculation instruction time interval distribution generates a time intensity vector, including: Calculate the arrival timestamp difference between adjacent instructions in the instruction sequence to obtain the time interval sequence; The time interval is divided into multiple preset time intervals, and the frequency of the time interval sequence in each time interval is counted. Divide the frequency of each time interval by the total number of time interval sequences to obtain the time interval percentage value corresponding to each time interval; arrange the time interval percentage values ​​according to the order of the multiple preset time intervals to generate a time intensity vector.

4. The method according to claim 1 or 2, characterized in that, The step of generating the instantaneous transition matrix by performing asymmetric weighting on the reference transition probability matrix using the time intensity vector includes: Extract the short time interval proportion component and the long time interval proportion component from the time intensity vector; The result of multiplying the baseline probability that the state remains unchanged by the short time interval proportion component is used as the instantaneous weight value of the updated diagonal element to update the diagonal elements in the baseline transition probability matrix. The result of multiplying the baseline probability of state transition by the long time interval proportion component is used as the instantaneous weight value of the updated off-diagonal element to update the off-diagonal elements in the baseline transition probability matrix. The updated matrix is ​​normalized row by row so that the sum of the elements in each row is 1, thus generating the instantaneous transition matrix.

5. The method according to claim 1, characterized in that, The step of combining the current load feature fingerprint to determine the fingerprint probability distribution of the next window and selecting the fingerprint corresponding to the highest probability as the predictive load fingerprint includes: The current load feature fingerprint is mapped to a discrete load category index by a preset load category mapper, and an initial state vector is generated based on the discrete load category index, wherein the category probability corresponding to the discrete load category index is 1, and the probability of the other categories is 0. Multiply the initial state vector by the instantaneous transition matrix to calculate the next window fingerprint probability distribution vector; The load feature fingerprint corresponding to the element with the highest probability value in the next window fingerprint probability distribution vector is selected as the predictive load fingerprint.

6. The method according to claim 1, characterized in that, The process involves calculating the expected energy efficiency gain based on the energy consumption difference between the current activity level and the expected activity level. Then, based on the expected energy efficiency gain, the probability of the predictive load fingerprint, and the switching energy consumption model, a power configuration scheme for the switching functional unit's power supply state is generated when the expected energy efficiency gain exceeds a threshold determined by probability and switching overhead. This includes: The window equivalent energy consumption corresponding to the current activity level and the window equivalent energy consumption corresponding to the expected activity level are calculated using a preset energy consumption mapping coefficient. The window equivalent energy consumption corresponding to the current activity level is subtracted from the window equivalent energy consumption corresponding to the expected activity level to obtain the energy saving amount. When the energy saving amount is positive, it is used as the expected energy efficiency gain. The state switching energy consumption cost of the functional unit to be switched is multiplied by a first conversion coefficient to obtain a first product. The topology delay cost of the functional unit to be switched is multiplied by a second conversion coefficient to obtain a second product. The first product and the second product are added to obtain the total cost of each functional unit. The total cost of all the functional units to be switched is accumulated and then divided by the maximum value between the probability of the predictive load fingerprint and the preset minimum probability lower limit to calculate the dynamic threshold. The first conversion coefficient and the second conversion coefficient are used to convert the energy consumption cost and delay cost into a dimension consistent with the expected energy efficiency gain. If the expected energy efficiency gain is greater than the dynamic threshold, a control signal to change the power supply state is generated to switch the power domain of the functional unit; otherwise, the current power supply state remains unchanged.

7. A dynamic partitioning device for the power domain of a storage control chip, characterized in that, Includes the following modules: The calculation module is used to acquire the memory access instruction sequence within a time window, extract the logical block address, instruction type and arrival timestamp, calculate the dispersion of the logical block address difference of consecutive instructions, and calculate the mean of the absolute value of the logical block address difference as the average hop distance index. The dispersion and the average hop distance index are used to quantify spatial locality, calculate the instruction time interval distribution to generate a time intensity vector, and fuse the dispersion, the average hop distance index, the time intensity vector and the instruction type ratio to generate the current load feature fingerprint. The selection module is used to generate an instantaneous transition matrix by performing asymmetric weighting on the baseline transition probability matrix using the time intensity vector, and to determine the next window fingerprint probability distribution by combining the discrete load category index corresponding to the current load feature fingerprint. The fingerprint corresponding to the highest probability is selected as the predictive load fingerprint. The baseline activity level corresponding to the current load and the predicted load is queried. The baseline activity level is scaled using the dispersion and the average hop distance index to calculate the expected activity level. When the spatial locality condition is met, the activity level of the cache unit is enhanced and the activity level of the main memory controller is suppressed. The generation module is used to calculate the expected energy efficiency gain based on the energy consumption difference between the current activity level and the expected activity level. Based on the expected energy efficiency gain, the probability of the predictive load fingerprint, and the switching energy consumption model decision, when the expected energy efficiency gain exceeds the threshold determined by the probability and switching overhead, a power configuration scheme for switching the power supply state of the functional unit is generated.

8. The apparatus according to claim 7, characterized in that, The dispersion and average jump distance metrics for calculating the address differences of consecutive instruction logic blocks are used to jointly quantify spatial locality, including: Calculate the difference sequence of adjacent instruction logic block addresses in the instruction sequence, and obtain the mean of the difference sequence; The variance median is obtained by calculating the square of the difference between each difference in the difference sequence and the mean, summing all the squares and dividing by the length of the difference sequence; the variance median is then calculated by taking the square root of the variance median. Take the absolute value of each difference in the difference sequence, sum all the absolute values ​​and divide by the length of the difference sequence to obtain the average jump distance index, and determine the strength of spatial locality based on the dispersion and the average jump distance index.

9. A dynamic partitioning device for the power domain of a storage control chip, the device comprising a memory and a processor, characterized in that, The memory stores a computer program, which, when executed by a processor, implements the method as described in any one of claims 1-6.

10. A computer-readable storage medium storing a computer program thereon, characterized in that, The computer program, when executed by a processor, implements the method as described in any one of claims 1-6.

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