IO extension storage control system and method using a mixed medium of pcm and nand

Abstract

The application discloses an IO expansion storage control system and method using a PCM and NAND mixed medium, and belongs to the technical field of storage control. The system comprises a controller, which is connected to a file system upwards and connected to a NAND storage module and a PCM storage module downwards. The controller is internally provided with a customized RTL IP module and a firmware scheduling module. The customized RTL IP module judges whether an IO request is continuous or random through a pure hardware logic circuit. If the IO request is continuous, data is routed to the NAND storage module, and if the IO request is random, data is routed to the PCM storage module. The firmware scheduling module performs data migration based on space correlation prediction and cold and hot combination on data entering the PCM storage module, and sequentially writes qualified data from the PCM to the NAND in batches. Through hardware-level IO shunting and data migration, the application can reduce the write amplification influence of random IO on the NAND and improve system throughput performance.

Description

Technical Field

[0001] This invention relates to the field of storage control technology, and specifically to an I / O extended storage control system and method utilizing a hybrid PCM and NAND medium. Background Technology

[0002] In large-scale data storage systems, NAND flash memory is widely used due to its large capacity and low unit cost. However, NAND flash memory has physical characteristics such as large read / write granularity and no support for in-situ updates. When processing small random I / O blocks, frequent erase and garbage collection operations are required, which can easily lead to write amplification, resulting in a decrease in the I / O performance of the storage system and accelerated device wear.

[0003] Existing hybrid storage solutions often identify I / O patterns at the file system layer through software caching or filtering, temporarily storing some random data in a newer, higher-performance non-volatile storage medium before flushing it to NAND. While this approach alleviates the pressure of random writes on NAND to some extent, the software-interventional discrimination and routing path is relatively long, resulting in higher latency and host CPU overhead. It is prone to becoming a bottleneck when facing high-concurrency random I / O, and the degree of isolation for random I / O is limited by the software's responsiveness, making it difficult to fully protect NAND devices from the effects of random fragmented writes.

[0004] Therefore, it is essential to design an I / O extended storage control system and method that utilizes a hybrid PCM and NAND medium. Summary of the Invention

[0005] The purpose of this invention is to provide an I / O extended storage control system and method that utilizes a hybrid PCM and NAND medium. Through hardware-level I / O offloading and data migration, the impact of random I / O on NAND write amplification can be reduced, thereby improving system throughput performance.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: An IO extended storage control system utilizing a hybrid PCM and NAND medium includes: a file system, a controller, a NAND storage module, and a PCM storage module. The file system is connected to the controller, the controller is connected to the NAND storage module and the PCM storage, and the PCM storage module is connected to the NAND storage module. The file system sends I / O requests to the controller; The controller is used to identify the IO request and determine whether to send the data stream to the NAND storage module or PCM storage. If it is stored in PCM storage, then perform data migration based on spatial correlation prediction and hot / cold combination.

[0007] Furthermore, the controller is pre-configured with a custom RTL IP module and a firmware scheduling module. The custom RTL IP module is used to determine whether to send the data stream storage to the NAND storage module or the PCM storage, and the firmware scheduling module is used to perform data migration based on spatial correlation prediction and a combination of hot and cold data.

[0008] This invention also provides an IO extended memory control method utilizing a hybrid PCM and NAND medium, applied to the aforementioned IO extended memory control system utilizing a hybrid PCM and NAND medium, comprising: Step 1: The file system sends an I / O request to the controller; Step 2: Customize the RTL IP module to determine whether an I / O request is a continuous I / O request or a random I / O request; Step 3: If it is a continuous IO request, the controller will directly route the corresponding data stream and send it to the NAND storage module. If it is a random IO request, the controller will route the data stream and send it to the PCM storage module. Step 4: If stored in PCM storage, the firmware scheduling module performs data migration based on spatial correlation prediction and a combination of hot and cold storage.

[0009] Furthermore, in step 4, the firmware scheduling module performs data migration based on spatial correlation prediction and a combination of hot and cold data, specifically as follows: The firmware scheduling module constructs a spatial adjacency graph based on the historical access sequence of random IO requests flowing into the PCM storage module, with logical block addresses as nodes, access order as directed edges, and co-occurrence strength as edge weights. Using a pre-trained spatiotemporal convolutional graph neural network model deployed in the firmware scheduling module, forward reasoning is performed on the current written logical block address, outputting a set of adjacent addresses with high spatial correlation and the confidence level of each adjacent address.

[0010] Furthermore, the spatiotemporal convolutional graph neural network model includes a graph attention encoding layer, a spatial grid mapping layer, and a convolutional prediction output layer. The graph attention encoding layer aggregates the outgoing neighbor features of the current node through a multi-head attention mechanism to generate a node embedding representation. The spatial grid mapping layer performs max pooling mapping on the node embedding representation according to the logical address spatial grid to generate a multi-dimensional feature map. The convolutional prediction output layer performs multi-layer convolution processing on the feature map and then combines it with the deep embedding representation of the current node to output the probability of each candidate address being visited.

[0011] Furthermore, step 4 also includes: The firmware scheduling module filters out addresses with a confidence level higher than a preset threshold from the set of adjacent addresses; In the PCM storage module, a contiguous physical page cluster is allocated. The length of this page cluster is the number of pages required for the current data write plus the number of reserved pages corresponding to the number of filtered addresses. Write the data corresponding to the current random I / O request to the first physical page of the page cluster, and mark the remaining physical pages as addresses reserved for the selected addresses; When the logical block address of a subsequent random I / O request hits a reserved page, the corresponding data is directly written to that reserved page to achieve in-place sequential appending.

[0012] Furthermore, step 4 also includes: The firmware scheduling module counts the number of accesses to each physical page in the PCM storage module according to a preset monitoring cycle and calculates the access frequency. Data pages whose access frequency is lower than the cold data frequency threshold and which are not any reserved pages are identified as cold data. For physical page clusters written through pre-assembly, the assembly of the page cluster is considered complete when all its reserved pages are filled with valid data and the cumulative data amount reaches the size of a single physical block of the NAND storage module. Add cold data pages and assembled page clusters to the migration queue.

[0013] Furthermore, step 4 also includes: When a reserved page is not hit within a preset waiting time window or the current free space ratio of the PCM storage module drops below a preset space threshold, the firmware scheduling module reclaims the physical space corresponding to the reserved page and clears the record of the reserved page from the address mapping temporary storage area.

[0014] In summary, the present invention has at least one of the following beneficial technical effects: 1. By using the controller's custom RTL IP module to directly determine the access mode of IO requests at the hardware level, the latency caused by software stack involvement is reduced. This enables rapid separation of continuous IO and random IO with lower overhead, which helps improve the overall IO throughput performance of the system.

[0015] 2. Prioritizing the distribution of a large number of random I / O requests to PCM storage modules that support in-situ updates and small write granularity can effectively absorb fragmented data and avoid frequent small-block random writes to NAND, thereby reducing the write amplification effect of NAND and playing a positive role in extending the lifespan of NAND devices.

[0016] 3. By performing data migration based on spatial correlation prediction and a combination of hot and cold data through the firmware scheduling module, random data in PCM can be aggregated into contiguous blocks and then sequentially written to NAND. This ensures that the cache space of PCM can be reused and makes the data written to NAND more sequential, further reducing unnecessary erase operations on NAND.

[0017] 4. By fully utilizing the high performance of PCM and the large capacity and low cost of NAND, the system can balance the high random I / O processing capability of the storage system with the need for persistent storage of massive amounts of data without significantly increasing the system hardware cost, thus achieving a better balance between capacity and performance. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the system structure of the present invention; Figure 2 This is a schematic diagram of the method flow of the present invention; Figure 3 This is a bar chart comparing IOPS under different random IO ratios for different schemes in Example 1; Figure 4 This is a graph showing the pre-assembly hit rate variation under different adjacent address set sizes in Example 2; Figure 5 This is a graph showing the changes in PCM occupancy rate and cumulative migration data volume over runtime for Example 3. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0020] like Figure 1 As shown, this embodiment of the invention provides an IO extended storage control system utilizing a hybrid PCM and NAND medium. The system includes a file system, a controller, a NAND storage module, and a PCM storage module. The file system, located on the host side, acts as the top-level data initiator, responsible for sending IO requests to the controller. The controller connects upwards to the file system and downwards to both the NAND storage module and the PCM storage module via a high-speed bus. The controller internally includes a custom RTL IP module and a firmware scheduling module. The custom RTL IP module uses pure hardware logic to determine the access mode of the IO request, while the firmware scheduling module performs data migration based on spatial correlation prediction and a combination of hot and cold data. The PCM storage module and the NAND storage module are connected via the controller's internal data bus. Data in the PCM storage module that needs to be migrated can be sequentially written to the NAND storage module in batches in a unidirectional manner.

[0021] Based on the above system, embodiments of the present invention also provide an IO extended storage control method utilizing a hybrid PCM and NAND medium, such as... Figure 2The workflow shown includes the following methods: Step 1: The file system sends an I / O request to the controller; Step 2: The controller's customized RTL IP module receives the I / O request and parses it using pure hardware logic circuitry to determine whether it is a continuous or random I / O request. Specifically, it checks whether the logical block addresses of adjacent I / O requests are consecutively increasing and whether the total data block length exceeds a preset stripe size threshold. If so, it is determined to be a continuous I / O request; otherwise, it is determined to be a random I / O request. This determination, performed using hardware circuitry, can be completed at the nanosecond level, significantly reducing latency caused by software intervention. Step 3: When the customized RTL IP module determines that the current IO request is a continuous IO request, the controller directly routes and sends the corresponding data stream to the NAND storage module through the DMA engine; when it is determined to be a random IO request, the controller routes and sends the data stream to the PCM storage module. Due to its large capacity, the NAND storage module is suitable for handling large-granularity sequential writes; the PCM storage module, due to its low write granularity and support for in-place updates, can efficiently absorb fragmented random write data. Step 4: After the data stream of random I / O requests is routed to the PCM storage module, the firmware scheduling module performs data migration based on spatial correlation prediction and a combination of hot and cold data. This step includes three sub-steps: spatial correlation prediction, pre-assembly placement, and hot / cold data determination and migration, which are described in detail below: 1. Construction and Online Inference of Spatial Association Prediction Model The firmware scheduling module deploys a pre-trained and quantized spatiotemporal convolutional graph neural network model. This model is used to predict the set of adjacent addresses spatially related to the current write logical block address based on historical access relationships when each random I / O request arrives, thereby guiding the pre-assembly placement of data in the PCM.

[0022] The input to the model is the address of the currently written logic block. And a spatial adjacency graph constructed centered on this address. The spatial adjacency graph uses the addresses of each logical block as nodes, and if within a preset time window... Memory from address To address The successive visits establish a path from point to Directed edge edge weight The frequency of co-occurrence in this order is determined by the number of nodes. Maintain an initial feature vector Its dimensions The components are: normalized access frequency. Recent access time decay factor ,in For nodes The time interval between the most recent access time and the current time. The time constant is the logical offset relative to the predecessor address. and data block size levels .

[0023] The spatiotemporal convolutional graph neural network model consists of a graph attention encoding layer, a spatial grid mapping layer, and a grid score prediction output layer connected in sequence.

[0024] The graph attention encoding layer contains two multi-head graph attention sublayers. The first sublayer is for node-specific attention. Aggregate the initial features, using Each head has an output that is spliced ​​together to obtain the desired result. The calculation formula is: ; in For nodes The set of outgoing neighbors, For the first Learnable transformation matrix for each attention head , For ELU activation function. Attention coefficients. The calculation takes into account node feature similarity and edge weights. The formula is: ; in For attention vectors, This indicates vector concatenation.

[0025] The second-order graph attention sublayer For input, also use Each attention head has an average output, but the average of the outputs from each head is used as the final node embedding. Dimension : ; in This is the second-order transformation matrix. This corresponds to the attention vector.

[0026] The space grid mapping layer divides the entire logical block address space into The grid, with preferred values , Each grid cell covers A contiguous logical block address. For each grid cell The embedding vectors of all active nodes within this unit Perform max pooling to obtain the eigenvalues ​​of the unit: ; If a grid cell contains no active nodes, its corresponding eigenvalue is set to zero. This results in a grid cell with a size of... Feature map .

[0027] Grid score prediction output layer on feature map Perform three layers of convolution. The first layer uses... The convolutional kernel has a stride of 1, padding of 1, 64 input channels, and 128 output channels, followed by batch normalization and ReLU activation; the second layer uses... The convolutional kernel has a stride of 1, padding of 1, 128 input channels, and 256 output channels, followed by batch normalization and ReLU activation; the third layer uses... The convolutional kernel has a stride of 1 and padding of 1, with 256 input channels and 128 output channels, followed by batch normalization and ReLU activation. Global average pooling is then performed to obtain a 128-dimensional global feature vector. At the same time, retrieve the current query node. Deep embedding representation The dimension is reduced to 128 through a fully connected layer to obtain the query vector. .Will and The joint feature vector is obtained by concatenation. .

[0028] The grid score prediction output layer uses a convolutional layer to combine the feature maps. The spatial dimension is compressed and fused with the joint feature vector, ultimately outputting a vector of size [size missing]. Grid spatial correlation score map Each element on the score chart Indicated by grid The central region and the current query node The degree of correlation in spatial access. The output layer is specifically implemented as follows: first, ... Through a Convolution reduces dimensionality to a single channel, then combines with... Generated by full connection The adjusted graph is multiplied element by element to obtain the final score graph. .

[0029] During online inference, for the current query node The firmware scheduling module first... The graph is added to the active graph, and the relevant node features and edge weights are updated. Then, the forward propagation of the above model is performed to obtain the grid score graph. Select the highest score. Each of the given grids contains a set of active nodes, from which nodes are selected for embedding and... The node with the highest cosine similarity is used to form the set of adjacent addresses. The corresponding similarity value is then used as the confidence level. (Preferred) One node is selected from each grid, resulting in a final adjacency set size of 4. If a grid has no active nodes, it is ignored, and the final set size may be smaller than 4. .

[0030] 2. Offline training of the model The training data is constructed from historical I / O access traces. Each training sample is constructed by randomly selecting an access address at a given time as the query node. Looking back The access sequence within the time window is used to construct a spatial adjacency graph, and subsequent access sequences are recorded. Within the time window, the addresses of logical blocks actually accessed are considered positive samples, and their corresponding grids are designated as positive sample grids. An equal number of addresses are randomly sampled from the remaining unaccessed addresses as negative samples, and their corresponding grids are used as negative sample grids during training. All positive sample grids are labeled 1, and negative sample grids are labeled 0. Grids not involved in sampling are ignored in the loss calculation. The loss function uses binary cross-entropy loss, calculated as follows: ; in The number of samples in a training batch. For the first The set of grids used in loss calculation for each sample. This represents the total number of grid cells involved in the calculation for this batch. For grid labels, The value of the grid score output by the model after applying the Sigmoid function.

[0031] Training uses the Adam optimizer, with an initial learning rate of [value missing]. The weights were reduced to 0.1 times their original value in rounds 30 and 45, respectively, for a total of 60 rounds of training with a batch size of 256. After training, the model weights were quantized into 8-bit integers and burned into the controller's firmware storage chip for online inference.

[0032] 3. Pre-assembled placement and in-situ sequential addition Obtain the set of adjacent addresses After determining the confidence level, the firmware scheduling module filters out entries with a confidence level higher than a preset threshold. The addresses constitute a high-confidence subset. The firmware scheduling module queries the PCM storage module's free physical page manager and attempts to allocate a contiguous cluster of physical pages in the PCM. The length of this cluster is 1 (for the currently written data) plus... The number of elements. If a contiguous region meeting the requirements exists in the PCM free space, it is allocated. The first physical page is used to store the data of the current random I / O request, and subsequent physical pages are marked as reserved pages, with the corresponding logical block addresses pre-recorded in the address mapping temporary storage area.

[0033] When a new random I / O request is routed to the PCM, the customized RTL IP module passes its logical block address to the firmware scheduling module. If this logical block address matches an existing reserved page record, the requested data is directly written to the corresponding PCM reserved physical page without requiring new address allocation and addressing, thus achieving in-place sequential append writing. This mechanism allows the originally scattered random I / O data to be gradually aggregated into a continuous sequence in the PCM, laying the foundation for efficient migration to NAND later.

[0034] If a reserved page is within the preset waiting time window If the memory is not hit, or the current free space percentage of the PCM storage module drops to a preset space threshold. Next, the firmware scheduling module will trigger a reserved page reclamation task, mark the reserved page as invalid, reclaim its physical space, and clear the corresponding record from the address mapping temporary storage area to prevent invalid reservations from wasting PCM capacity.

[0035] 4. Determination and migration of hot and cold data The firmware scheduling module continuously monitors the access status of each physical page in the PCM storage module in the background, according to a preset monitoring period. Based on this, count the number of times each physical page was accessed in the last two periods. and Calculate access frequency When the access frequency is lower than the cold data frequency threshold If the page is not part of any reserved page, mark the logical block corresponding to the page as cold data. It can be dynamically adjusted according to the workload, with the initial value set to 0.01 times / second.

[0036] Meanwhile, for physical page clusters generated through the pre-assembly placement mechanism, the firmware scheduling module tracks the number of pages that have been filled with valid data. When all reserved pages in a page cluster have been filled with valid data, and the cumulative data volume reaches the size of one physical block of the NAND storage module... At that time, the page cluster is determined to be assembled successfully.

[0037] Physical pages identified as cold data and assembled page clusters are added to the migration queue. The controller maintains a low-priority background migration thread that retrieves tasks from the migration queue, reads the data from the corresponding physical page from the PCM storage module using DMA, and writes it directly to the NAND storage module via the controller's internal bus in a sequential write manner. After the write is complete, the logical-physical address mapping master table is updated, and the corresponding physical space in the PCM is reclaimed. If the migration queue is empty or the NAND write channel is busy, the migration thread is automatically suspended to avoid impacting front-end I / O performance.

[0038] Through the aforementioned spatial correlation prediction and hot / cold data migration, random fragmented data in the PCM storage module is continuously organized into continuous large blocks and sequentially brushed into the NAND storage module, which significantly reduces the write amplification effect of NAND, extends device life, and ensures the throughput performance of the system under high random IO load.

[0039] The above system and method will be further illustrated by the following examples: Example 1: System I / O Performance Comparison Test This embodiment compares the IO performance of the PCM and NAND hybrid storage control system (hereinafter referred to as the present invention) with that of a traditional hybrid storage solution based on file system software filtering (hereinafter referred to as the traditional solution). The test environment configuration is as follows: the host CPU is an Intel Xeon Gold 6248R, the memory is 256GB DDR4, the NAND storage module is a 4TB enterprise-grade NVMe SSD, the PCM storage module is a 512GB Optane DC Persistent Memory, FIO is used to simulate the load, the block size is 4KB, the random read / write ratio is 70 / 30, and the concurrent queue depth is 32. The stable throughput (IOPS) and average latency achieved by the system under different random IO request ratios are tested.

[0040] The test results are shown in Table 1. Figure 3 This is a bar chart comparing the corresponding IOPS.

[0041] Table 1. Performance comparison of different schemes under different random I / O ratios

[0042] As shown in Table 1, the performance of traditional solutions degrades sharply with the increase in the proportion of random I / O, while the solution of this invention, by utilizing PCM to absorb random fragmentation and orderly migrate hot and cold data to NAND, exhibits a gradual decrease in throughput, maintaining a consistently high level. In pure random I / O scenarios, the IOPS of the solution of this invention is approximately 6 times that of the traditional solution, and the average latency is only 15% of the latter.

[0043] Example 2: Validation of the Spatial Association Prediction Model This embodiment is used to evaluate the pre-assembly placement hit rate of the spatiotemporal convolutional graph neural network model described in step 4. Real-world business trace replays were used, containing approximately 2 million random I / O requests, which were input into the model online in chronological order. A time window was set. Grid division , Size of the adjacency address set Compare values ​​of 2, 4, 6, and 8 respectively. Hit rate is defined as: after pushing to the adjacent address set, The proportion of logical block addresses that actually appeared within the adjacent address set during the time period (if the actual address happens to fall into a reserved page, it is counted as a hit). The results are shown in Table 2. Figure 4 This is the corresponding hit rate change curve.

[0044] Table 2 Pre-assembly hit rate under different adjacent address set sizes

[0045] As shown in Table 2, the hit rate gradually increases with the increase of the adjacent address set, but the growth rate slows down. Considering the contiguous space allocation overhead of PCM, [the following is selected]. A balance can be struck between hit rate and space efficiency, with a hit rate of 78.3%, which can effectively cluster most random writes into contiguous blocks.

[0046] Example 3: The effect of hot and cold data migration on PCM space release This embodiment demonstrates the impact of the cold and hot data migration mechanism of this invention on the space utilization of the PCM storage module and the amount of NAND writes under long-term operation. The experimental setup is the same as in Embodiment 1, running continuously for 4 hours with a constant 70% random I / O load. The used space ratio of the PCM and the cumulative amount of data migrated to NAND are monitored. The PCM occupancy rate change is also compared with that without the migration mechanism (i.e., forcibly swapping out the oldest data after the PCM is full). The results are shown in Table 3 and... Figure 5 As shown, where, Figure 5 This is a curve showing the PCM occupancy rate and the cumulative amount of migrated data over time.

[0047] Table 3 PCM space usage and cumulative migration data volume at different time points

[0048] As shown in Table 3, the proposed solution maintains PCM occupancy at around 50% through predictive pre-assembly and hot / cold data determination, and promptly reclaims space after writing to NAND, avoiding a sharp performance drop caused by PCM filling up. Without the migration solution, PCM quickly fills up, necessitating frequent forced data evictions, severely impacting foreground I / O performance. The amount of data migrated to NAND increases linearly over time, indicating that the background migration thread is efficient and orderly.

[0049] The above embodiments and experimental results fully verify the significant advantages of the technical solution of the present invention in random I / O absorption, data space aggregation and system performance maintenance. Moreover, the parameters and thresholds of each model can be flexibly adjusted according to the actual workload, and it has good engineering feasibility and industrial practical value.

[0050] Embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0051] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0052] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0053] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0054] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.

Claims

1. An I / O extended storage control system utilizing a hybrid PCM and NAND medium, characterized in that, include: The system includes a file system, a controller, a NAND storage module, and a PCM storage module. The file system is connected to the controller, the controller is connected to the NAND storage module and the PCM storage module, and the PCM storage module is connected to the NAND storage module. The file system sends I / O requests to the controller; The controller is used to identify the IO request and determine whether to send the data stream to the NAND storage module or PCM storage. If it is stored in PCM storage, then perform data migration based on spatial correlation prediction and hot / cold combination.

2. The I / O extended storage control system utilizing a hybrid PCM and NAND medium according to claim 1, characterized in that, The controller is pre-configured with a custom RTL IP module and a firmware scheduling module. The custom RTL IP module is used to determine whether to store and send the data stream to the NAND storage module or the PCM storage. The firmware scheduling module is used to perform data migration based on spatial correlation prediction and a combination of hot and cold data.

3. A method for controlling IO extended storage using a hybrid PCM and NAND medium, applied to the IO extended storage control system using a hybrid PCM and NAND medium as described in any one of claims 1-2, characterized in that, include: Step 1: The file system sends an I / O request to the controller; Step 2: Customize the RTL IP module to determine whether an I / O request is a continuous I / O request or a random I / O request; Step 3: If it is a continuous IO request, the controller will directly route the corresponding data stream and send it to the NAND storage module. If it is a random IO request, the controller will route the data stream and send it to the PCM storage module. Step 4: If stored in PCM storage, the firmware scheduling module performs data migration based on spatial correlation prediction and a combination of hot and cold storage.

4. The I / O extended storage control method using a hybrid PCM and NAND medium according to claim 3, characterized in that, In step 4, the firmware scheduling module performs data migration based on spatial correlation prediction and a combination of hot and cold data, specifically as follows: The firmware scheduling module constructs a spatial adjacency graph based on the historical access sequence of random IO requests flowing into the PCM storage module, with logical block addresses as nodes, access order as directed edges, and co-occurrence strength as edge weights. Using a pre-trained spatiotemporal convolutional graph neural network model deployed in the firmware scheduling module, forward reasoning is performed on the current written logical block address, outputting a set of adjacent addresses with high spatial correlation and the confidence level of each adjacent address.

5. The I / O extended storage control method using a hybrid PCM and NAND medium according to claim 4, characterized in that, The spatiotemporal convolutional graph neural network model includes a graph attention encoding layer, a spatial grid mapping layer, and a convolutional prediction output layer. The graph attention encoding layer aggregates the outgoing neighbor features of the current node through a multi-head attention mechanism to generate a node embedding representation. The spatial grid mapping layer performs max pooling mapping on the node embedding representation according to the logical address spatial grid to generate a multi-dimensional feature map. The convolutional prediction output layer performs multi-layer convolution processing on the feature map and then combines it with the deep embedding representation of the current node to output the probability of each candidate address being visited.

6. The I / O extended storage control method using a hybrid PCM and NAND medium according to claim 5, characterized in that, Step 4 also includes: The firmware scheduling module filters out addresses with a confidence level higher than a preset threshold from the set of adjacent addresses; In the PCM storage module, a contiguous physical page cluster is allocated. The length of this page cluster is the number of pages required for the current data write plus the number of reserved pages corresponding to the number of filtered addresses. Write the data corresponding to the current random I / O request to the first physical page of the page cluster, and mark the remaining physical pages as addresses reserved for the selected addresses; When the logical block address of a subsequent random I / O request hits a reserved page, the corresponding data is directly written to that reserved page to achieve in-place sequential appending.

7. The I / O extended storage control method using a hybrid PCM and NAND medium according to claim 6, characterized in that, Step 4 also includes: The firmware scheduling module counts the number of accesses to each physical page in the PCM storage module according to a preset monitoring cycle and calculates the access frequency. Data pages whose access frequency is lower than the cold data frequency threshold and which are not any reserved pages are identified as cold data. For physical page clusters written through pre-assembly, the assembly of the page cluster is considered complete when all its reserved pages are filled with valid data and the cumulative data amount reaches the size of a single physical block of the NAND storage module. Add cold data pages and assembled page clusters to the migration queue.

8. The I / O extended storage control method using a hybrid PCM and NAND medium according to claim 7, characterized in that, Step 4 also includes: When a reserved page is not hit within a preset waiting time window or the current free space ratio of the PCM storage module drops below a preset space threshold, the firmware scheduling module reclaims the physical space corresponding to the reserved page and clears the record of the reserved page from the address mapping temporary storage area.

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