A data processing method and system for bypassing a flash translation layer and a computational storage device

Abstract

The application discloses a data processing method and system for bypassing a flash translation layer and a computing storage device, and belongs to the technical field of computer storage and artificial intelligence reasoning acceleration. The method comprises the following steps: analyzing a host or accelerator request, and obtaining a calculation primitive and a data type of required data in the request; obtaining a base address, a length and a cross-channel strip layout of a physical section in a storage medium according to metadata of the required data, to generate a read instruction, and performing multi-channel concurrent reading on the storage medium according to the read instruction to obtain a bypass reading result; and inputting the bypass reading result into an embedded computing engine for near-storage calculation according to the calculation primitive, or sending the bypass reading result to an accelerator through P2P DMA. The application can realize low-jitter high-bandwidth reading, reduce bus traffic and video memory pressure, and improve hardware utilization.

Description

Technical Field

[0001] This invention belongs to the field of computer storage and artificial intelligence technology, specifically relating to a data processing method, system, and computing storage device for a bypass flash conversion layer. Background Technology

[0002] Large Language Models (LLMs) have been widely deployed as cloud-based inference services. With the continuous growth of model size, context length, and the number of concurrent tenants, the massive amounts of data generated during inference far exceed the capacity of a single accelerator's video memory (HBM). This type of data includes at least four categories: First, model weights often cannot all reside in video memory in multi-tenant, multi-model mixed deployment scenarios; second, key-value caches can reach several times the size of the model itself under long contexts and large-scale offline inference conditions; third, activation checkpoints and intermediate tensors often spill into secondary storage under inter-layer pipelining and recomputation strategies; fourth, in cryptographic inference scenarios, the evaluation keys for fully homomorphic encryption (FHE) (such as key switching key families and bootstrap keys) can reach several gigabytes per parameter variant, and can reach more than ten gigabytes when multiple functions and precision variants are configured in the same tenant, far exceeding the capacity of high video memory after aggregation among multiple tenants.

[0003] All or part of the aforementioned data types exhibit characteristics such as fixed physical layout, read-only access, and repeated reading in a predictable order within the corresponding service cycle. This application collectively refers to data satisfying these characteristics as target data. Once the working set of target data exceeds the video memory capacity, it must be spilled to secondary storage media such as host memory or solid-state drives (SSDs). However, the external access path of SSDs suffers from structural bottlenecks. SSDs are connected to the host or accelerator via the PCIe bus, and the external interface bandwidth is typically only on the order of several GB per second, far lower than the original bandwidth (up to tens of GB / s) of its internal multiple flash memory channels aggregated. The movement of target data between host memory or SSDs and video memory is entirely dominated by PCIe, which has become the main source of end-to-end inference latency.

[0004] More importantly, the Flash Translation Layer (FTL) inside a general-purpose solid-state drive is designed for general read / write workloads, providing mechanisms such as dynamic address mapping, wear leveling, and garbage collection. For static, sequential, read-only target data streams, the FTL's page-by-page address translation and background block management activities such as wear leveling and garbage collection generate additional overhead and interference, increasing single-access latency and introducing latency jitter, making it difficult for the device to stably utilize its internal flash bandwidth.

[0005] To address the aforementioned challenges, existing technologies have been explored primarily from two directions.

[0006] The first approach employs data temporary storage and offloading schemes based on solid-state drives (SSDs) or host memory. Representative works can be divided into two categories. The first category, represented by systems such as FlexGen, offloads key-value caches or other target data to host memory or SSDs: the key-value cache is first loaded from the SSD to host memory, then transferred to video memory via PCIe before participating in computation. The pre-filling stage computation is completed in video memory, while the decoding stage frequently retrieves the key-value cache via PCIe. The second category, represented by InstAttention (HPCA 2025), offloads the attention computation and key-value cache in the decoding stage to compute-grade storage devices. It utilizes the aggregated bandwidth within flash memory and proposes an FTL design and dual-address mapping mechanism for key-value caches, placing the entire attention operator coarsely within the storage device for execution.

[0007] Although the above solutions have achieved some effect in alleviating memory pressure, they still have the following significant shortcomings: 1) External bandwidth bottleneck remains unresolved: Large-scale data transfer is still dominated by PCIe. Taking FlexGen-like solutions as an example, during the decoding phase of batch inference, the vast majority of latency is consumed by the loading operation of key-value caches via PCIe. 2) Generic FTL incurs additional overhead on the target data stream. The page-by-page address translation of generic FTL, as well as block management activities such as background wear leveling and garbage collection, will incur additional overhead and interference on static, sequential, read-only target data streams, increasing latency and introducing jitter; 3) The modified FTL still retains the page-level management path. InstAttention introduces a dual-address mapping for key-value caching within the FTL framework, still requiring page-level address and block management via FTL; this invention, however, for target data with a fixed physical layout, moves reserved physical segments out of the runtime address management of FTL. This constitutes one of the key aspects that distinguishes this invention from InstAttention; 4) Coarse-grained operator offloading is limited by lightweight computing cores: Placing the complete attention operator on a compute-intensive storage device requires it to bear a high computational load, making it difficult to fully utilize the advantages of both the accelerator and the compute-intensive storage device. 5) Streaming scenarios that do not cover cryptographic evaluation keys: Focusing on plaintext key-value caching, it has not yet addressed the deterministic supply of evaluation key streams, which are larger in volume and more sequential in cryptographic inference.

[0008] The aforementioned shortcomings indicate that there is still significant room for improvement in this area regarding deterministic high-volume data supply, bandwidth guarantees for near-storage execution, and fine-grained heterogeneous collaboration.

[0009] The second approach, such as the hybrid memory management of non-volatile memory devices used with recurrent neural networks disclosed in Chinese patent application CN117730306A, involves partitioning a dedicated storage region within a non-volatile memory array, accessible by an independent neural Turing machine controller. This region is assigned physical memory addresses, and the controller is allowed to bypass certain non-volatile memory management operations of the solid-state drive controller (including flash memory translation layer operations related to reads). Furthermore, it mentions setting on-chip computing units within the non-volatile memory array.

[0010] Based on the publicly available information in this document, it still has the following limitations: 1) There is a lack of a complete deployment layout mechanism for static, sequential, read-only target data. The publicly available information does not mention establishing a static metadata table that simultaneously records the physical segment base address, length, and cross-flash channel stripe layout, nor does it mention excluding the target data reservation area from the FTL free pool, wear leveling, and garbage collection scope. 2) Lack of a deterministic data supply mechanism across flash memory channels. The publicly available information does not reveal a technical solution for continuously concurrently reading data across multiple flash memory channels based on a static stripe layout during deployment, and for directly supplying bypass data streams to the embedded computing engine or external accelerators via backpressure buffering. 3) Lack of fine-grained cooperation mechanisms for heterogeneous accelerators. The published content does not provide any teachings on dividing operators according to bandwidth-constrained and computationally-constrained characteristics, exchanging only compact intermediate results through direct memory access between devices, or using a unified finite state machine and multi-context operation to maintain issuance and reduce cooperation overhead.

[0011] In summary, existing technologies have not fully addressed the issue of deterministic and efficient supply of large-volume, static, sequential, and read-only target data across storage layers in LLM inference scenarios. In particular, there are significant gaps in areas such as deployment layout, cross-channel concurrent reading, and fine-grained heterogeneous collaboration. A new technical solution is urgently needed to overcome these bottlenecks. Summary of the Invention

[0012] This invention discloses a data processing method, system, and computing storage device for a bypass flash conversion layer. Through near-memory computing and architecture optimization, it achieves low jitter and high bandwidth reading, reduces bus traffic and memory pressure, and improves hardware utilization.

[0013] To achieve the above objectives, the technical solution of the present invention includes the following:

[0014] A data processing method for bypassing a flash conversion layer, the method comprising: Parse the host or accelerator request to obtain the data type of the computation primitives and required data in the request; the data type includes target data, which is data that remains static and is repeatedly read in a predictable order within a predetermined service period. Based on the metadata of the required data, the base address, length and cross-channel stripe layout of the physical segment in the storage medium are obtained to generate a read instruction, and the storage medium is read concurrently through multiple channels according to the read instruction to obtain the bypass read result; wherein, the target data is stored in a reserved area, which is partitioned from the flash memory and is excluded from the FTL free pool, wear leveling and garbage collection. According to the computation primitives, the bypass read results are input into the embedded computing engine for near-memory computation, or sent to the accelerator via P2P DMA.

[0015] Furthermore, the step of reading data from the storage medium based on the base address, length, and cross-channel stripe layout of the physical segment to obtain the bypass read result includes: Construct a static metadata table, which records the segment base address, length, and strip layout of each target data asset; The table is looked up based on the static metadata table to obtain the metadata of the physical segment of the required data in the storage medium, obtain the base address, length and cross-channel stripe layout of the physical segment in the flash memory, and generate a read instruction. The read command is sent to the flash memory controller; The flash memory controller reads target data from the reserved area according to the read instruction and corrects errors in the read target data.

[0016] Furthermore, according to the computational primitives, the bypass read results are input into the embedded computing engine for near-memory computation, or sent to the accelerator via P2P DMA, including: When the computation primitive is a bandwidth-limited primitive, the bypass read result is sent to the embedded computing engine for near-memory computation, and the computation result is returned to the host or accelerator. When the computational primitive is a computationally restricted primitive executed by the accelerator, or when it does not require near-memory processing, the bypass read result is returned to the accelerator via P2P DMA. Furthermore, the embedded computing engine uses a single finite state machine to organize multiple computational primitive patterns and maintains multiple execution contexts; when one execution context waits for the accelerator to return a result, another ready execution context is launched.

[0017] Furthermore, the data type also includes general data, which is data other than the target data that is allowed to be written, updated, or remapped during runtime, and therefore requires dynamic address mapping, wear leveling, and garbage collection management. When the data type includes general data, the general data read result in the storage medium is obtained through the general data path; wherein, the general data path includes an NVMe controller, a flash translation layer and a flash controller, the flash translation layer uses an L2P table and an L2P lookup module to complete the conversion from logical address to physical address, performs garbage collection and wear leveling, and uses DRAM cache to map metadata.

[0018] A data processing system with a bypass flash conversion layer, the system comprising: The request parsing module is used to parse host or accelerator requests and obtain the data types of computation primitives and required data in the request; the data types include target data and general data, wherein the target data is data that remains static within a predetermined service period and is repeatedly read in a predictable order; The bypass read path is used to obtain the base address, length and cross-channel stripe layout of the physical segment in the storage medium based on the metadata of the required data, so as to generate a read instruction, and perform multi-channel concurrent read on the storage medium according to the read instruction to obtain the bypass read result; according to the computation primitive, the bypass read result is input into the embedded computing engine for near-memory computing, or sent to the accelerator via P2P DMA; A reserved area is allocated from the flash memory to store the target data; this reserved area is excluded from the FTL's free pool, wear leveling, and garbage collection.

[0019] A computing storage device with a bypass flash conversion layer, the computing storage device comprising: The request parsing module is used to parse host or accelerator requests and obtain the data types of computation primitives and required data in the request. The data types include target data and general data. The target data is data that remains static during a predetermined service cycle and is repeatedly read in a predictable order. The general data is data other than the target data that is allowed to be written, updated, or remapped during operation, and therefore requires dynamic address mapping, wear leveling, and garbage collection management. The bypass read path is used to obtain the base address, length and cross-channel stripe layout of the physical segment in the storage medium based on the metadata of the required data, so as to generate a read instruction, and perform multi-channel concurrent read on the storage medium according to the read instruction to obtain the bypass read result; according to the computation primitive, the bypass read result is input into the embedded computing engine for near-memory computing, or sent to the accelerator via P2P DMA; A general data path is used to obtain the general data read results in the flash memory based on the general data path, and return the general data read results to the host or accelerator; Flash memory is used for general data and target data; wherein the target data is stored in a reserved area, which is partitioned from the flash memory and excluded from the FTL's free pool, wear leveling, and garbage collection.

[0020] Furthermore, the computing storage device also includes a monitoring module; the monitoring module is used for: The relationship between the target data working set and the available capacity is monitored; wherein, the target data working set is the total amount of target data that currently accepted tenants need to reside or access under the corresponding operators and precision variants, and the available capacity is the video memory capacity allocated to the target data after deducting the corresponding overhead, the corresponding overhead including accelerator running overhead and model resident part running overhead; When the working set is no larger than the available capacity, the target data resides in the accelerator memory and the corresponding computation primitives are executed directly by the accelerator, while general data is read through the general data path. When the working set is larger than the available capacity, the general data read result in the storage medium is obtained based on the general data path, and the general data read result is returned to the host or accelerator; the bypass read result corresponding to the target data is obtained based on the bypass read path, and according to the computation primitive, the bypass read result is input into the embedded computing engine for near-memory computation, or sent to the accelerator via P2P DMA.

[0021] A computer device includes: a processor and a memory storing computer program instructions; the processor, when executing the computer program instructions, implements the data processing method of the bypass flash conversion layer described above.

[0022] A computer-readable storage medium storing computer program instructions, which, when executed by a processor, implement the data processing method of the bypass flash conversion layer described in any of the preceding claims.

[0023] Compared with the prior art, the present invention has at least the following beneficial effects.

[0024] This invention combines static segment metadata during deployment, cross-channel stripe layout, and reserved area isolation to enable runtime reading of target data to skip page-by-page address translation and reduce background block management interference, achieving data supply with near-original flash bandwidth and low jitter. By dividing the tasks of compute-intensive storage devices and accelerators at the primitive granularity according to arithmetic strength, large volumes of target data are consumed near the storage end, with only kilobyte-level intermediate results transmitted across devices, thereby reducing external bus traffic and alleviating pressure on GPU memory capacity. Furthermore, by using a unified finite state machine and multi-context operation to maintain issuance, it reduces shared resource arbitration and pipeline bubbling during multi-mode switching, improving the continuous utilization of flash channels, data paths, and direct memory access interfaces between devices. Attached Figure Description

[0025] Figure 1 This is the overall system architecture diagram of the present invention.

[0026] Figure 2 This is a flowchart of the data processing method.

[0027] Figure 3 This is a comparative structural diagram of reading general data through the flash memory conversion layer and reading target data through the bypass reading path in this invention. Detailed Implementation

[0028] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, and to make the objectives, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0029] This invention is used in large-model inference service systems. For example... Figure 1 As shown, the system includes a host, at least one accelerator (such as a GPU), and at least one computational storage device as described in this invention, all interconnected via PCIe. The accelerator's video memory holds a compact subset of the target data (e.g., the bootstrap key BSK in the embodiment, or a hot weight / hot key value cache). The computational storage device carries the spilled target data body and executes bandwidth-constrained operators near the flash memory. A runtime orchestrator is deployed on the host side, responsible for task splitting, descriptor generation, and doorbell distribution.

[0030] The data processing method of this invention is organized according to the deployment phase and the operation phase, such as Figure 2 As shown, it includes the following steps.

[0031] S1 Target data identification.

[0032] Identify the required data requested by the host / accelerator. The data types of the required data include target data, which is data with a fixed physical layout, kept read-only, and repeatedly read in a predictable order within a predetermined service cycle, including at least one of model weights, encapsulated key-value cache data segments, active checkpoints, and encrypted evaluation keys; the general data is data other than target data that is allowed to be written, updated, or remapped during operation, and therefore requires dynamic address mapping, wear leveling, and garbage collection management.

[0033] S2 deployment provisioning.

[0034] This application first divides the flash memory into a reserved area, which is a page-aligned and physically contiguous segment allocated for the target data. This reserved area is excluded from the FTL's free pool, wear leveling, and garbage collection, so that it will not be moved or reclaimed throughout the entire deployment lifecycle. The ordinary physical area outside the reserved area is still managed by the FTL according to the general path.

[0035] In addition, this application also establishes a static metadata table to record the segment base address, length and strip layout of each target data asset.

[0036] S3 runtime bypass read.

[0037] like Figure 3 As shown, the compute-grade storage device internally has a general data path and a bypass read path configured in parallel. For general data, the host or accelerator request 201 enters the flash translation layer 203 via the NVMe controller 202; the flash translation layer 203 uses the L2P table 204 and the L2P lookup module 205 to complete the translation from logical address to physical address, performs garbage collection and wear leveling, and uses DRAM 207 to cache mapped metadata, which is then read by the flash controller 208 from the NAND flash chip 209.

[0038] For the target data, runtime read requests do not enter the flash translation layer 203. Instead, they first access the static metadata table 210 established during the deployment phase to obtain the base address, length, and cross-channel striping layout of the corresponding reserved physical segment in the flash memory in a single lookup. This allows direct identification of the physical segment containing the target data, skipping the page-by-page address translation of the FTL, thus solving the deterministic physical supply problem for large-volume static read-only data streams. The segment direct addressing module 211 generates the physical read address accordingly. The cross-channel striping module 212 initiates concurrent reads on multiple flash channels in a polling manner according to the metadata declaration order, maintaining continuous channel occupancy. The reserved area isolation module 213 is located in the flash memory. The configuration of this module ensures that the relevant physical blocks are not moved by the flash translation layer's free block allocation, wear leveling, or garbage collection mechanisms. Subsequently, the flash controller 214 retrieves the data from the NAND flash memory chip 209 (reserved area isolation module) and completes error correction.

[0039] Among them, general data outside the reserved physical segment still goes through the general data path via the flash conversion layer 203. Therefore, the bypass read path does not cancel the flash conversion layer, but removes it from the runtime read path of the target data.

[0040] In the fully homomorphic encryption embodiment, the key switching key family is supplied to the key switching and private key switching primitives on the computing storage device side, respectively. The bootstrap key resides in the accelerator memory and is supplied to the blind rotation, fast Fourier transform and conditional multiplexing primitives. Only compact intermediate ciphertext is exchanged between the two devices.

[0041] S4 Near-memory operator execution.

[0042] The embedded computing engine (including a multiply-accumulate array) executes bandwidth-constrained operators near the flash memory. The target data required by the operator is already inside the storage device and does not need to cross an external bus.

[0043] Specifically, the bypass read result is output through a backpressured first-in-first-out buffer. When the current primitive is a bandwidth-constrained primitive executed by a computational storage device, the read result is sent to the embedded computing engine 215 for near-memory processing. This solves the deterministic bandwidth supply problem of near-memory execution, i.e., how to provide a predictable, low-jitter data path for bandwidth-constrained operators so that they can be stably executed near the storage end.

[0044] S5 compact P2P exchange of intermediate results.

[0045] After execution, the operator produces only compact intermediate results (in this example, on the order of kilobytes), which are directly exchanged between the computational storage device and the accelerator via P2P DMA, without passing through the host memory. Based on this, the accelerator completes the computationally restricted portion and sends back the results.

[0046] In one embodiment, when the read data will be consumed by a computationally constrained primitive performed by the accelerator, or when no near-end processing at storage is required, the read result is sent directly to the accelerator 216 via P2P DMA.

[0047] S6 Multi-tenant Capacity Detection and Working Mode Switching.

[0048] In an optional embodiment, the invention also monitors the relationship between the target data working set and the available capacity during runtime. The available capacity is the GPU memory capacity that can be allocated to the target data after deducting accelerator runtime, model resident portions, and other reservation overhead; the working set is the total amount of target data that currently accepted tenants need to reside or access under the corresponding operator and precision variant. When the working set is no larger than the available capacity and all target data can reside in GPU memory, the system operates in resident mode, i.e., Regime A. In this mode, the accelerator directly completes the relevant primitives, and the bypass read path does not need to participate in target data provisioning. When the working set is larger than the available capacity and at least a portion of the target data must overflow to secondary storage, the system operates in over-memory mode, i.e., Regime B. In this mode, the main body of the target data is placed in the reserved area of ​​the compute-intensive storage device, and only a compact subset required by compute-constrained primitives is reserved in GPU memory. Bypass reads, near-memory execution, and P2P DMA compact swapping are enabled. In the fully homomorphic encryption implementation, Regime A indicates that all evaluation keys reside in GPU memory; Regime B indicates that a smaller bootstrap key resides in GPU memory, while the key switching key, private key switching key, and lookup table are stored in compute storage. Multi-tenant admission control and task assignment are performed at runtime based on this.

[0049] In summary, this invention combines static segment metadata during deployment, full lifecycle isolation of reserved areas, and cross-channel striping direct read during runtime to form a deterministic bypass supply for static, sequential, read-only target data. Based on these technical features, this invention enables target data to be read at near-original flash memory bandwidth with more stable latency and lower jitter. Compared to the performance of the same device under a general FTL path, the latency of a single key switch is reduced from approximately 20 milliseconds to approximately 9 milliseconds (approximately 2.2 times), and the latency of a single private key switch is reduced from approximately 39 milliseconds to approximately 16 milliseconds (approximately 2.4 times). This is because direct segment addressing replaces page-by-page translation with a single static table lookup, cross-channel striping maintains full channel openness, and reserved area isolation reduces the interference of wear leveling and garbage collection on the target data area.

[0050] This invention enables near-memory execution of bandwidth-constrained operators and compact P2P DMA switching between devices, reducing the amount of data transferred across devices by more than three orders of magnitude. In this embodiment, a single key switch that originally required transporting approximately 86 megabytes of keys across an external bus is reduced to 2 to 16 kilobytes after this invention, a reduction of more than 5000 times. Furthermore, since the video memory only needs to retain a compact subset of the target data (bootstrapping key BSK), the number of variants that can be effectively accommodated is expanded from approximately 15 complete key sets to more than 200 BSK-only variants, significantly improving multi-tenant capacity.

[0051] This invention discloses a unified zero-arbitration kernel, which integrates multiple operator modes into a single finite state machine, sharing a data path. This unified zero-arbitration kernel reduces shared resource arbitration and pipeline bubbling during mode switching in the operator chain. In a high-precision evaluation chain of this embodiment, there are approximately 142 primitive-level execution and handover points. Traditional multi-engine architectures require arbitration and state switching between shared flash channels, DMA, and register files. This invention encodes the complete primitive sequence with a single finite state machine, advancing only state branches across primitive boundaries without interrupting the data path. This mechanism reduces the steady-state latency of the circuit bootstrapping stage from approximately 90 milliseconds to approximately 74 milliseconds.

[0052] This invention achieves multi-context working sustaining launch, hiding peer waiting. When an active context enters a peer waiting state, the next ready context is immediately launched to the shared data path, keeping the flash channel occupied across evaluation boundaries and hiding peer waiting under concurrent execution. In the encrypted LLM inference implementation, compared to the baseline of spilling target data to a solid-state drive and reading it via a general FTL path, this invention reduces the latency of high-precision encrypted nonlinear computations (such as Softmax, GELU) by up to 16 times. The latency improvement of the hybrid GPT-2 Transformer module is 3.7 to 4.3 times. Softmax is approximately 1.78 times faster than the GPU-spill baseline and approximately 10 times faster than the CPU baseline. GELU is approximately 15.9 times faster than the GPU-spill baseline.

[0053] Although the present invention has been described through the above preferred embodiments, those skilled in the art will understand that various modifications in form and detail can be made therein without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A data processing method for bypassing a flash memory conversion layer, characterized in that, The method includes: Parse the host or accelerator request to obtain the data type of the computation primitives and required data in the request; the data type includes target data, which is data that remains static and is repeatedly read in a predictable order within a predetermined service period. Based on the metadata of the required data, the base address, length and cross-channel stripe layout of the physical segment in the storage medium are obtained to generate a read instruction, and the storage medium is read concurrently through multiple channels according to the read instruction to obtain the bypass read result; wherein, the target data is stored in a reserved area, which is partitioned from the flash memory and is excluded from the FTL free pool, wear leveling and garbage collection. According to the computation primitives, the bypass read results are input into the embedded computing engine for near-memory computation, or sent to the accelerator via P2P DMA.

2. The method according to claim 1, characterized in that, The process of reading data from the storage medium based on the base address, length, and cross-channel stripe layout of the physical segment to obtain bypass read results includes: Construct a static metadata table, which records the segment base address, length, and strip layout of each target data asset; The table is looked up based on the static metadata table to obtain the metadata of the physical segment of the required data in the storage medium, obtain the base address, length and cross-channel stripe layout of the physical segment in the flash memory, and generate a read instruction. The read command is sent to the flash memory controller; The flash memory controller reads target data from the reserved area according to the read instruction and corrects errors in the read target data.

3. The method according to claim 1, characterized in that, According to the computational primitives, the bypass read results are input into the embedded computing engine for near-memory computation, or sent to the accelerator via P2P DMA, including: When the computation primitive is a bandwidth-limited primitive, the bypass read result is sent to the embedded computing engine for near-memory computation, and the computation result is returned to the host or accelerator. When the computation primitive is a computationally restricted primitive that is executed by the accelerator, or when it does not require processing near the memory, the bypass read result is returned to the accelerator via P2PDMA.

4. The method according to claim 1, characterized in that, The embedded computing engine uses a single finite state machine to organize multiple computing primitive patterns and maintains multiple execution contexts; when one execution context is waiting for the accelerator to return a result, another ready execution context is launched.

5. The method according to any one of claims 1 to 4, characterized in that, The data types also include general data, which is data other than target data that is allowed to be written, updated or remapped during runtime, and therefore requires dynamic address mapping, wear leveling and garbage collection management. When the data type includes general data, the general data read result in the storage medium is obtained through the general data path; wherein, the general data path includes an NVMe controller, a flash translation layer and a flash controller, the flash translation layer uses an L2P table and an L2P lookup module to complete the conversion from logical address to physical address, performs garbage collection and wear leveling, and uses DRAM cache to map metadata.

6. A data processing system with a bypass flash memory conversion layer, characterized in that, The system includes: The request parsing module is used to parse host or accelerator requests and obtain the data types of computation primitives and required data in the request; the data types include target data and general data, wherein the target data is data that remains static within a predetermined service period and is repeatedly read in a predictable order; The bypass read path is used to obtain the base address, length and cross-channel stripe layout of the physical segment in the storage medium based on the metadata of the required data, so as to generate a read instruction, and perform multi-channel concurrent read on the storage medium according to the read instruction to obtain the bypass read result; according to the computation primitive, the bypass read result is input into the embedded computing engine for near-memory computing, or sent to the accelerator via P2P DMA; A reserved area is allocated from the flash memory to store the target data; this reserved area is excluded from the FTL's free pool, wear leveling, and garbage collection.

7. A computing storage device with a bypass flash conversion layer, characterized in that, The computing storage device includes: The request parsing module is used to parse host or accelerator requests and obtain the data types of computation primitives and required data in the request. The data types include target data and general data. The target data is data that remains static during a predetermined service cycle and is repeatedly read in a predictable order. The general data is data other than the target data that is allowed to be written, updated, or remapped during operation, and therefore requires dynamic address mapping, wear leveling, and garbage collection management. The bypass read path is used to obtain the base address, length and cross-channel stripe layout of the physical segment in the storage medium based on the metadata of the required data, so as to generate a read instruction, and perform multi-channel concurrent read on the storage medium according to the read instruction to obtain the bypass read result; according to the computation primitive, the bypass read result is input into the embedded computing engine for near-memory computing, or sent to the accelerator via P2P DMA; A general data path is used to obtain the general data read results in the flash memory based on the general data path, and return the general data read results to the host or accelerator; Flash memory is used for general data and target data; wherein the target data is stored in a reserved area, which is partitioned from the flash memory and excluded from the FTL's free pool, wear leveling, and garbage collection.

8. The computing storage device according to claim 7, characterized in that, The computing storage device further includes a monitoring module; the monitoring module is used for: The relationship between the target data working set and the available capacity is monitored; wherein, the target data working set is the total amount of target data that currently accepted tenants need to reside or access under the corresponding operators and precision variants, and the available capacity is the video memory capacity allocated to the target data after deducting the corresponding overhead, the corresponding overhead including accelerator running overhead and model resident part running overhead; When the working set is no larger than the available capacity, the target data resides in the accelerator memory and the corresponding computation primitives are executed directly by the accelerator, while general data is read through the general data path. When the working set is larger than the available capacity, the general data read result in the storage medium is obtained based on the general data path, and the general data read result is returned to the host or accelerator; the bypass read result corresponding to the target data is obtained based on the bypass read path, and according to the computation primitive, the bypass read result is input into the embedded computing engine for near-memory computation, or sent to the accelerator via P2P DMA.

9. A computer device, characterized in that, The computer device includes: a processor and a memory storing computer program instructions; when the processor executes the computer program instructions, it implements the data processing method of the bypass flash conversion layer as described in any one of claims 1-5.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions, which, when executed by a processor, implement the data processing method of the bypass flash conversion layer as described in any one of claims 1-5.

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