A mode configuration circuit based on I2S signal connection method sequential self-recognition

Abstract

The application relates to the technical field of integrated circuits, and discloses a mode configuration circuit based on I2S signal connection method sequence self-recognition, which comprises three IO circuits for receiving external Pad_A, Pad_B and Pad_C signals and outputting Ain signals, Bin signals and Cin signals; a frequency detection and anchor point determination module performs frequency counting on the three signals in a detection time window, and determines the pin with the largest counting value as an SCLK anchor point, so that line sequence recognition is independent of SDIN flip characteristics; a line sequence determination and coding multiplexing module generates path mapping control signals according to the SCLK anchor point and a cyclic shift topology rule; and finally, through a three-way cross switch matrix, the Ain, Bin and Cin are redirected to sclk, lrck and sdin, so that integrated processing of I2S line sequence recognition, path reconstruction and mode configuration is realized.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to a mode configuration circuit based on self-identification of I2S signal connection sequence. Background Technology

[0002] Digital audio interface circuits are commonly used for serial signal transmission between audio chips and external audio devices. These circuits are constrained by the number of package pins, initialization delay, internal configuration resources, and interface compatibility. Existing technologies typically use additional configuration ports, external configuration channels, local feature determination, signal relationship comparison, and time window filtering to complete interface connection identification and working mode configuration. This approach is usually suitable for application scenarios with sufficient configuration resources, stable input signal states, and clear data flipping relationships.

[0003] In the actual access process of digital audio interfaces, the serial data signal will be stationary or in a low-frequency flip state as the audio content changes. The power-on detection stage will also be affected by the change in the initial state of the input data. The above factors will weaken the line sequence determination method that relies on the flip characteristics of the serial data signal, making it difficult to keep the interface signal connection relationship, internal receiving path and working mode configuration consistent. Therefore, the technical problem that needs to be solved is how to achieve I2S line sequence recognition, path reconstruction and mode configuration without relying on the SDIN flip characteristics.

[0004] In view of this, the present invention proposes a mode configuration circuit based on I2S signal connection sequence self-identification to solve the above problems. Summary of the Invention

[0005] To overcome the above-mentioned defects of the prior art, the present invention provides a mode configuration circuit based on I2S signal connection sequence self-identification.

[0006] To achieve the above objectives, the present invention provides the following technical solution: Firstly, a mode configuration circuit based on I2S signal connection sequence self-identification is provided, including: The three I / O circuits receive external Pad_A, Pad_B and Pad_C signals respectively, and output Ain, Bin and Cin signals respectively. The frequency detection and anchor point determination module is connected to three IO circuits. It is used to count the frequencies of the Ain, Bin and Cin signals respectively during the valid signal detection time window, and determine the pin index with the largest count value as the SCLK anchor point. The line sequence determination and encoding multiplexing module is connected to the frequency detection and anchor point determination module, and is used to output the path mapping control signal according to the SCLK anchor point and the preset cyclic shift topology rules. A 3-way cross switch matrix connects 3 I / O circuits and a line sequence determination and encoding multiplexing module, used to redirect Ain, Bin and Cin signals into sclk, lrck and sdin signals according to the path mapping control signal.

[0007] In some embodiments, the frequency detection and anchor point determination module includes three parallel frequency counters and a maximum value comparator. The three parallel frequency counters receive Ain signal, Bin signal and Cin signal respectively. The maximum value comparator is connected to the three parallel frequency counters and outputs the index of the counter with the largest count value.

[0008] In some embodiments, the three-channel parallel frequency counters are used to count using the Ain, Bin, and Cin signals as clocks, respectively, during the period when the detection time window signal is high.

[0009] In some embodiments, the maximum value comparator is used to compare the count values ​​of the three parallel frequency counters and filter out the counter index with the largest value.

[0010] In some embodiments, the line sequence determination and encoding multiplexing module is used to complete line sequence determination and latching according to the SCLK anchor point and the preset cyclic shift topology rules when the detection time window signal ends.

[0011] In some embodiments, the preset cyclic shift topology rules include a first line sequence, a second line sequence, and a third line sequence. The first line sequence is that the SCLK signal, LRCK signal, and SDIN signal correspond to the Pad_A signal, Pad_B signal, and Pad_C signal, respectively. The second line sequence is that the SDIN signal, SCLK signal, and LRCK signal correspond to the Pad_A signal, Pad_B signal, and Pad_C signal, respectively. The third line sequence is that the LRCK signal, SDIN signal, and SCLK signal correspond to the Pad_A signal, Pad_B signal, and Pad_C signal, respectively.

[0012] In some embodiments, when the SCLK anchor point is Pad_A, the path mapping control signal redirects the Ain signal to the sclk signal, the Bin signal to the lrck signal, and the Cin signal to the sdin signal.

[0013] In some embodiments, when the SCLK anchor point is Pad_B, the path mapping control signal redirects the Bin signal to the sclk signal, the Cin signal to the lrck signal, and the Ain signal to the sdin signal.

[0014] In some embodiments, when the SCLK anchor point is Pad_C, the path mapping control signal redirects the Cin signal to the sclk signal, the Ain signal to the lrck signal, and the Bin signal to the sdin signal.

[0015] In some embodiments, the 3-way cross switch matrix consists of 3 groups of 3-to-1 multiplexers, and the selection signal of each group of 3-to-1 multiplexers is controlled by the 3-bit hot code corresponding to the SCLK anchor point.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention receives external Pad_A, Pad_B, and Pad_C signals via three I / O circuits and outputs Ain, Bin, and Cin signals respectively, enabling the three externally inputted I2S related signals to form a unified input basis within the chip. During the valid signal period of the detection time window, the frequency detection and anchor point determination module counts the frequencies of the Ain, Bin, and Cin signals respectively, and determines the pin index with the highest count value as the SCLK anchor point. Since the SCLK signal has a higher toggle frequency than the lrck and sdin signals, line sequence identification no longer depends on the obviousness of the SDIN toggle feature, but instead uses the input with the highest frequency as a stable anchor point to establish the identification starting point, thereby avoiding determination failure caused by the serial data signal being in a static or low-frequency toggle state. In the line sequence determination and encoding multiplexing module, a path mapping control signal is output based on the SCLK anchor point and a preset cyclic shift topology rule, enabling the remaining two inputs to... The relative positional relationship with the SCLK anchor point is further determined, thereby converting the interface signal connection relationship into a control result that can directly drive internal path reconstruction. Subsequently, the 3-way cross switch matrix redirects the Ain, Bin, and Cin signals into sclk, lrck, and sdin signals according to the path mapping control signal. This allows the connection order of external Pad_A, Pad_B, and Pad_C to be automatically reconstructed into the correct I2S signal path within the chip. After the path reconstruction is completed, the corresponding working mode configuration is directly formed. Thus, this invention, through the processing link of "frequency detection and anchor point determination - cyclic shift topology determination - cross switch matrix redirection", achieves I2S line sequence identification, path reconstruction, and mode configuration without relying on the SDIN flip-flop feature. It also keeps the interface signal connection relationship, internal receiving path, and working mode configuration consistent, thereby improving the reliability of digital audio interface connection sequence identification and the stability of mode configuration. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall circuit architecture of a mode configuration circuit based on I2S signal connection sequence self-identification according to the present invention. Figure 2This is a schematic diagram of the structure of a frequency detection and anchor point determination module according to the present invention; Figure 3 This is a schematic diagram of the structure of the 3-way cross switch matrix in this invention; Figure 4 This is a timing characteristic diagram of the I2S signal under silent and special data conditions in this invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and the accompanying drawings. In the following detailed description, many specific details are set forth to provide a thorough understanding of the exemplary embodiments described. However, it will be apparent to those skilled in the art that the described embodiments may be practiced without some or all of these specific details. In other exemplary embodiments, well-known structures have not been described in detail to avoid unnecessarily obscuring the concepts of this disclosure. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention. Furthermore, the various aspects described in the embodiments may be combined arbitrarily without conflict.

[0019] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0020] Figure 1 This diagram illustrates the overall circuit architecture of a mode configuration circuit based on I2S signal connection sequence self-identification, according to at least one embodiment of this disclosure. Figure 2 This diagram illustrates the structure of a frequency detection and anchor point determination module provided in at least one embodiment of the present disclosure. Figure 3 This diagram illustrates the structure of a 3-way cross switch matrix provided in at least one embodiment of the present disclosure. Figure 4 The timing characteristics of the I2S signal under silent and special data conditions are shown in the diagram. (Refer to...) Figures 1 to 4 This mode configuration circuit can be applied to audio chips, digital audio interface chips, and other integrated circuits that need to receive external I2S bus signals. This mode configuration circuit is used to identify the connection sequence between the external I2S bus signals and the chip's physical pins during the chip power-on or initialization phase, and to complete the internal I2S signal path reconstruction and working mode configuration based on the identification result.

[0021] Reference Figure 1The configuration circuit includes a 3-channel I / O circuit 110, a frequency detection and anchor point determination module 120, a 3-channel crossbar switch matrix 130, an internal configuration register 140, and an I2S receiving circuit 150. The 3-channel I / O circuit 110 receives external Pad_A, Pad_B, and Pad_C signals respectively and outputs Ain, Bin, and Cin signals. The frequency detection and anchor point determination module 120 is connected to the 3-channel I / O circuit 110 and is used to count the frequencies of the Ain, Bin, and Cin signals respectively during the valid period of the detection time window, and determine the pin index with the largest count value as the SCLK anchor point. The 3-channel crossbar switch matrix 130 is connected to the 3-channel I / O circuit 110 and the frequency detection and anchor point determination module 120 and is used to redirect the Ain, Bin, and Cin signals to sclk, lrck, and sdin signals according to the path mapping control signal. The internal configuration register 140 is used to store mode parameters. The I2S receiving circuit 150 is used to process the remapped standard I2S signal according to the configuration mode.

[0022] In this embodiment, Pad_A, Pad_B, and Pad_C refer to the three physical ports of the chip used to receive external I2S bus signals. The Ain, Bin, and Cin signals refer to the signals input to the internal digital circuit after the external Pad_A, Pad_B, and Pad_C signals pass through the three I / O circuits 110. The three I / O circuits 110 can be ordinary digital I / O circuits, whose main function is to realize the connection between the external pins and the internal digital circuit. The sclk, lrck, and sdin signals correspond to the serial clock logic input, word selection clock logic input, and serial data logic input output from the three crossbar switch matrix 130 to the I2S receiving circuit 150, respectively. By distinguishing the above physical port signals and internal logic input signals, those skilled in the art can clearly identify the external connection objects as Pad_A, Pad_B, and Pad_C, and the internal receiving objects as the sclk, lrck, and sdin signals.

[0023] It should be noted that the SCLK anchor point refers to the pin index corresponding to the highest frequency signal identified from the Ain, Bin, and Cin signals by frequency counting during the valid signal detection time window. Since the LRCK frequency in a normal I2S audio signal can range from 8kHz to 192kHz, and SCLK is greater than or equal to 32 times LRCK, while SDIN is less than or equal to half of SCLK, SCLK has the highest physical frequency among the three I2S signals. Figure 4The timing characteristics of the I2S signal under mute and special data conditions shown indicate that when the audio source is in a mute state, SDIN may exhibit a continuous low level. When playing specific low-frequency audio or test signals, the flip frequency of SDIN may be lower, or even close to the frequency or phase of LRCK. Therefore, this embodiment does not rely on the flip characteristics of SDIN to distinguish between LRCK and SDIN, but only determines the SCLK anchor point through the high-frequency characteristics of SCLK, and then infers the physical positions of LRCK and SDIN according to the preset cyclic shift topology rules.

[0024] By using the SCLK anchor point as the sole frequency determination object for line sequence identification, this embodiment does not require complete protocol decoding of the LRCK and SDIN signals separately, nor does it rely on the SDIN signal to generate stable flips within the detection window. Under silent data, low-frequency data, or special test data, even if the SDIN signal exhibits a continuous low level, low-frequency flips, or a frequency relationship close to that of the LRCK signal, the frequency detection and anchor point determination module 120 can still complete the anchor point determination based on the physical characteristic of the highest frequency of the SCLK signal. This provides a clear starting basis for subsequent line sequence inference, thereby reducing the impact of audio data content on the I2S line sequence identification process and improving the identification stability and startup robustness during the chip power-on initialization phase.

[0025] Reference Figure 2 The frequency detection and anchor point determination module 120 includes a 3-channel parallel frequency counter 121, a maximum value comparator 122, and a line sequence determination and encoding multiplexing module 123. The 3-channel parallel frequency counter 121 includes a Pad_a frequency counter, a Pad_b frequency counter, and a Pad_c frequency counter. The Pad_a frequency counter receives the Ain signal, the Pad_b frequency counter receives the Bin signal, and the Pad_c frequency counter receives the Cin signal. The maximum value comparator 122 is connected to the 3-channel parallel frequency counter 121 and receives the three count values ​​output by the 3-channel parallel frequency counter 121. The line sequence determination and encoding multiplexing module 123 is connected to the maximum value comparator 122 and is used to complete the line sequence determination and latching according to the counter index with the largest count value output by the maximum value comparator 122 and the preset cyclic shift topology rule, and output the cross switch matrix control signal and the mode configuration signal.

[0026] In this embodiment, the detection time window signal is a control signal used to limit the I2S line sequence detection time range. During the period when the detection time window signal is high, the three parallel frequency counters 121 count using the Ain signal, Bin signal, and Cin signal as clocks, respectively. That is, the Pad_a frequency counter counts according to the transition of the Ain signal, the Pad_b frequency counter counts according to the transition of the Bin signal, and the Pad_c frequency counter counts according to the transition of the Cin signal. The counting method can be counting the rising edge of the input signal or counting the falling edge of the input signal. The purpose is to obtain the number of toggles of the input signal corresponding to the three physical ports within the detection time window, so that the frequency detection and anchor point determination module 120 can use the hardware counting result rather than the audio data content as the determination basis.

[0027] For example, the detection time window can be 50µs, and the counter width can be 10 bits. Considering clock fluctuations, the effective frequency range of LRCK can be considered to be 5kHz to 200kHz. When LRCK is 5kHz and SCLK is 32 times LRCK, the corresponding count value of SCLK is 8. When LRCK is 200kHz and SCLK is 64 times LRCK, the corresponding count value of SCLK is 640. Therefore, the 10-bit counter can cover the above counting range. Within this time window, the three counters count using the Ain signal, Bin signal, and Cin signal as clocks, respectively. After the window time is reached, the maximum value comparator 122 compares the values ​​of the three counters and determines the largest value as the counter index corresponding to SCLK. Thus, the SCLK anchor point determination can be completed within a shorter detection window.

[0028] The maximum value comparator 122 is used to compare the count values ​​of the three parallel frequency counters 121 and filter out the counter index with the largest value. Specifically, if the count value of the frequency counter Pad_a is the largest, the maximum value comparator 122 outputs the counter index corresponding to Pad_A, and the line sequence determination and encoding multiplexing module 123 determines Pad_A as the SCLK anchor point. If the count value of the frequency counter Pad_b is the largest, the maximum value comparator 122 outputs the counter index corresponding to Pad_B, and the line sequence determination and encoding multiplexing module 123 determines Pad_B as the SCLK anchor point. If the count value of the frequency counter Pad_c is the largest, the maximum value comparator 122 outputs the counter index corresponding to Pad_C, and the line sequence determination and encoding multiplexing module 123 determines Pad_C as the SCLK anchor point.

[0029] In this embodiment, the preset cyclic shift topology rule means that the system pre-defines the physical connection sequence of the external I2S bus signals on Pad_A, Pad_B, and Pad_C to only belong to three cyclic shift arrangements. Since the system pre-defines the positional relationship between LRCK, SDIN, and SCLK, the pin positions of LRCK and SDIN can be known after obtaining the index of the SCLK anchor point, without having to rely on the toggle frequency of SDIN to determine SDIN and LRCK. The purpose of this setting is to avoid unclear line sequence determination due to the unstable toggle frequency of SDIN under silent data or special low-frequency data. At the same time, it can also associate the mode configuration with the physical connection sequence, thereby reducing the use of additional mode configuration pins.

[0030] Specifically, the preset cyclic shift topology rules include a first line sequence, a second line sequence, and a third line sequence. The first line sequence is the SCLK signal, LRCK signal, and SDIN signal, which correspond to Pad_A signal, Pad_B signal, and Pad_C signal, respectively. The second line sequence is the SDIN signal, LRCK signal, and SCLK signal, which correspond to Pad_A signal, Pad_B signal, and Pad_C signal, respectively. The third line sequence is the LRCK signal, LRCK signal, SDIN signal, and SCLK signal, which correspond to Pad_A signal, Pad_B signal, and Pad_C signal, respectively. The above three line sequences constitute the preset cyclic shift arrangement set of the system. When any line sequence is connected, the system only needs to identify the position of SCLK to deduce the positions of the other two signals.

[0031] By limiting the physical connections on Pad_A, Pad_B, and Pad_C to the cyclic shift topology rules formed by the first, second, and third wiring sequences, this embodiment can deduce the physical ports corresponding to the LRCK and SDIN signals after obtaining the SCLK anchor point. It is not necessary to continue comparing the frequency, ratio, phase, or data flip state of the LRCK and SDIN signals. The wiring sequence determination and encoding multiplexing module 123 can directly complete the wiring sequence determination and latching based on the SCLK anchor point and generate a path mapping control signal. This transforms the wiring sequence identification process from full differentiation of three signals to single anchor point identification and topology inference, thereby reducing the complexity of the identification logic and lowering the risk of misjudgment caused by changes in the content of the SDIN signal.

[0032] When the SCLK anchor point is Pad_A, it indicates that the current physical connection wiring sequence is the first wiring sequence, that is, Pad_A corresponds to the SCLK signal, Pad_B corresponds to the LRCK signal, and Pad_C corresponds to the SDIN signal. At this time, the 3-bit hot code corresponding to the SCLK anchor point is 100. The path mapping control signal output by the wiring sequence determination and encoding multiplexing module 123 causes the 3-way cross switch matrix 130 to redirect the Ain signal to the sclk signal, the Bin signal to the LRCK signal, and the Cin signal to the sdin signal. The corresponding association mode is configured as Mode 0, and the encoding can be 00, corresponding to the I2S data format.

[0033] When the SCLK anchor point is Pad_B, it indicates that the current physical connection wiring sequence is the second wiring sequence, that is, Pad_A corresponds to the SDIN signal, Pad_B corresponds to the SCLK signal, and Pad_C corresponds to the LRCK signal. At this time, the 3-bit hot code corresponding to the SCLK anchor point is 010. The path mapping control signal output by the wiring sequence determination and encoding multiplexing module 123 causes the 3-way cross switch matrix 130 to redirect the Bin signal to the sclk signal, the Cin signal to the lrck signal, and the Ain signal to the sdin signal. The corresponding association mode is configured as Mode 1, and the encoding can be 01, corresponding to the left data format.

[0034] When the SCLK anchor point is Pad_C, it indicates that the current physical connection wiring sequence is the third wiring sequence, that is, Pad_A corresponds to the LRCK signal, Pad_B corresponds to the SDIN signal, and Pad_C corresponds to the SCLK signal. At this time, the 3-bit hot code corresponding to the SCLK anchor point is 001. The path mapping control signal output by the wiring sequence determination and encoding multiplexing module 123 causes the 3-way cross switch matrix 130 to redirect the Cin signal to the sclk signal, the Ain signal to the lrck signal, and the Bin signal to the sdin signal. The corresponding association mode is configured as Mode 2, and the encoding can be 1x, corresponding to the right data format.

[0035] Reference Figure 3The 3-way cross switch matrix 130 consists of three groups of 3-to-1 multiplexers. The selection signal of each group of 3-to-1 multiplexers is controlled by the 3-bit hot code corresponding to the SCLK anchor point. The first group of 3-to-1 multiplexers is used to output the sclk signal, the second group of 3-to-1 multiplexers is used to output the lrck signal, and the third group of 3-to-1 multiplexers is used to output the sdin signal. According to different 3-bit hot codes, each group of 3-to-1 multiplexers selects the corresponding signal from the Ain signal, Bin signal, and Cin signal and outputs it to the I2S receiving circuit 150. Since only one SCLK anchor point can be latched at the same time, the corresponding 3-bit hot codes are logically mutually exclusive, and there is no priority conflict of multiple anchor points controlling the 3-way cross switch matrix 130 at the same time.

[0036] It should be noted that the path mapping control signal is the cross switch matrix control signal generated by the line sequence determination and encoding multiplexing module 123 based on the SCLK anchor point position. Its function is to control the selection path of each 3-to-1 multiplexer inside the 3-way cross switch matrix 130, so that the physical connection on the external Pad_A, Pad_B and Pad_C is converted into the standard logic input order required by the I2S receiving circuit 150. In other words, no matter whether the external I2S bus signal is connected to the chip according to the first line sequence, the second line sequence or the third line sequence mentioned above, as long as it conforms to the preset cyclic shift topology rule, the 3-way cross switch matrix 130 can organize the input signal into the sclk signal, the lrck signal and the sdin signal and output them to the I2S receiving circuit 150.

[0037] By redirecting the Ain, Bin, and Cin signals according to the path mapping control signal through the 3-way cross switch matrix 130, this embodiment can still provide the I2S receiving circuit 150 with a fixed sequence of sclk, lrck, and sdin signals when Pad_A, Pad_B, and Pad_C are connected with different cyclic wiring sequences. This isolates the external physical connection changes from the internal I2S receiving logic. At the same time, the wiring sequence determination result can also be associated with mode configurations such as Mode 0, Mode 1, and Mode 2, so that the physical connection sequence can simultaneously serve as the signal path reconstruction and working mode configuration input. This reduces the occupation of chip packaging and system initialization processes by additional mode configuration pins or dedicated configuration operations.

[0038] In this embodiment, the line sequence determination and encoding multiplexing module 123 can also output a mode configuration signal. The mode configuration signal can be written into the internal configuration register 140. The internal configuration register 140 is used to store mode parameters such as data format and channel mapping. The configuration result can be latched by a D flip-flop at the falling edge of the detection time window signal. The reset condition can be the system POR. The system can also support writing operations to the internal configuration register 140 through an external I2C or SPI bus, thereby allowing software overwriting after the detection result is generated to adapt to special application scenarios.

[0039] During the switching process of the cross switch matrix 130, the switching occurs at the end of the detection time window signal. Before the detection time window signal is pulled low and the path is locked, the back-end I2S receiving circuit 150 can be in a reset or mute state. Once the path is locked, the system generates a synchronous reset pulse to the I2S receiving circuit 150, so that the clock and data stream in the I2S receiving circuit 150 start working synchronously from the starting position after remapping, thereby avoiding the transient signals generated during the switching process of the three-way cross switch matrix 130 from affecting normal audio processing.

[0040] With the above settings, in the I2S line sequence identification process, this embodiment only compares the frequency counting results of the Ain, Bin, and Cin signals, and uses the pin index corresponding to the signal with the largest count value as the SCLK anchor point. Then, the physical positions of LRCK and SDIN are inferred by the preset cyclic shift topology rules. Since SDIN may be continuously low-level, low-frequency flipped, or have a frequency relationship close to LRCK under mute or special data conditions, this embodiment does not use the SDIN flipping feature as a necessary condition for line sequence determination. Instead, it uses the stable feature of the highest SCLK frequency to complete the anchor point identification, and uses a 3-way cross switch matrix 130 to complete the dynamic redirection from the physical path to the logical path. Thus, I2S line sequence identification, path reconstruction, and mode configuration can be achieved while reducing the number of mode configuration pins.

[0041] The detailed description above, in conjunction with the accompanying drawings, describes examples but does not represent all examples that can be implemented or fall within the scope of the claims. The terms “example” and “exemplary” are used in this specification to mean “serving as an example, instance or illustration” and do not mean “superior to or better than other examples”.

[0042] Throughout this specification, the phrase "an embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. Therefore, the use of these phrases may refer to more than one embodiment. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0043] It should also be noted that these embodiments may be described as processes depicted as flowcharts, structural diagrams, or block diagrams. Although a flowchart may describe the operations as sequential processes, many of these operations can be performed in parallel or concurrently, and the order of these operations may be rearranged.

Claims

1. A mode configuration circuit based on self-identification of I2S signal connection sequence, characterized in that, include: The three I / O circuits receive external Pad_A, Pad_B and Pad_C signals respectively, and output Ain, Bin and Cin signals respectively. The frequency detection and anchor point determination module is connected to three IO circuits. It is used to count the frequencies of the Ain, Bin and Cin signals respectively during the valid signal detection time window, and determine the pin index with the largest count value as the SCLK anchor point. The line sequence determination and encoding multiplexing module is connected to the frequency detection and anchor point determination module, and is used to output the path mapping control signal according to the SCLK anchor point and the preset cyclic shift topology rules. A 3-way cross switch matrix connects 3 I / O circuits and a line sequence determination and encoding multiplexing module, used to redirect Ain, Bin and Cin signals into sclk, lrck and sdin signals according to the path mapping control signal.

2. The mode configuration circuit based on I2S signal connection sequence self-identification according to claim 1, characterized in that, The frequency detection and anchor point determination module includes three parallel frequency counters and a maximum value comparator. The three parallel frequency counters receive the Ain signal, the Bin signal, and the Cin signal, respectively. The maximum value comparator is connected to the three parallel frequency counters and outputs the index of the counter with the largest count value.

3. The mode configuration circuit based on I2S signal connection sequence self-identification according to claim 2, characterized in that, The three-channel parallel frequency counter is used to count using the Ain, Bin, and Cin signals as clocks respectively during the high-level period of the detection time window.

4. The mode configuration circuit based on I2S signal connection sequence self-identification according to claim 2, characterized in that, The maximum value comparator is used to compare the count values ​​of three parallel frequency counters and filter out the counter index with the largest value.

5. A mode configuration circuit based on I2S signal connection sequence self-identification according to claim 1, characterized in that, The line sequence determination and encoding multiplexing module is used to determine and latch the line sequence according to the SCLK anchor point and the preset cyclic shift topology rules when the detection time window signal ends.

6. The mode configuration circuit based on I2S signal connection sequence self-identification according to claim 1, characterized in that, The preset cyclic shift topology rules include a first line sequence, a second line sequence, and a third line sequence. The first line sequence is that the SCLK signal, LRCK signal, and SDIN signal correspond to the Pad_A signal, Pad_B signal, and Pad_C signal, respectively. The second line sequence is that the SDIN signal, SCLK signal, and LRCK signal correspond to the Pad_A signal, Pad_B signal, and Pad_C signal, respectively. The third line sequence is that the LRCK signal, SDIN signal, and SCLK signal correspond to the Pad_A signal, Pad_B signal, and Pad_C signal, respectively.

7. A mode configuration circuit based on I2S signal connection sequence self-identification according to claim 6, characterized in that, When the SCLK anchor point is Pad_A, the path mapping control signal redirects the Ain signal to the sclk signal, the Bin signal to the lrck signal, and the Cin signal to the sdin signal.

8. A mode configuration circuit based on I2S signal connection sequence self-identification according to claim 6, characterized in that, When the SCLK anchor point is Pad_B, the path mapping control signal redirects the Bin signal to the sclk signal, the Cin signal to the lrck signal, and the Ain signal to the sdin signal.

9. A mode configuration circuit based on I2S signal connection sequence self-identification according to claim 6, characterized in that, When the SCLK anchor point is Pad_C, the path mapping control signal redirects the Cin signal to the sclk signal, the Ain signal to the lrck signal, and the Bin signal to the sdin signal.

10. A mode configuration circuit based on I2S signal connection sequence self-identification according to claim 1, characterized in that, The 3-way cross switch matrix consists of 3 groups of 3-to-1 multiplexers. The selection signal of each group of 3-to-1 multiplexers is controlled by the 3-bit hot code corresponding to the SCLK anchor point.

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