An accelerated processor and pipelined architecture with non-binary radix arithmetic units

Abstract

The application discloses an arithmetic processing unit and pipeline architecture with custom operation base on demand, and belongs to the technical field of computer arithmetic operation. The standard binary ALU has low efficiency and high delay when processing non-standard base operation. The application realizes structured operation code decoding through bit selection logic, without storage resources such as lookup table; the combination logic is used to realize addition, subtraction and multiplication of any base in a single clock cycle; the operation result reaches the base boundary, and the boundary condition flag is automatically output; four pipeline stages of encoding, transformation, mapping and output are supported for dynamic topology switching. The circuit structure of the application can be realized with a small amount of logic resources (about 100 LUT level), without the support of high-performance process or special instruction set, and can be embedded into various processor systems as a standard IP core or deployed on a low-cost FPGA as an independent accelerator, to provide hardware-level acceleration for non-standard base operation.

Description

Technical Field

[0001] This invention relates to the fields of processor architecture and semiconductor IP technology, specifically to an accelerated processor with a non-binary radix arithmetic unit and a configurable pipeline architecture. Background Technology

[0002] The arithmetic logic unit (ALU) of current mainstream processor architectures (RISC-V, ARM, x86, etc.) all use two's complement arithmetic, with a base of 2 and a data width of 2^n (8 / 16 / 32 / 64 bits). The opcode is encoded as a compact binary assignment, and there is no structured mapping relationship between the encoded value and the operation type. The instruction decoder must rely on a lookup table or read-only memory to map the opcode to the control signal.

[0003] However, the existing solutions described above all use a 2-base arithmetic. The underlying ALUs of general-purpose processors, neural network accelerators, and FPGA IP cores are all based on standard binary arithmetic, making it impossible to support non-binary radix operations at the hardware level. Even in dedicated accelerators, binary arithmetic remains the foundation of the entire chain from single instruction to pipelined execution. Non-standard modulo operations (such as modulo-5 counting and modulo-60 coordinate transformations) must rely on frequent radix conversions at the software level, making it impossible to achieve hardware-level acceleration at the silicon level.

[0004] Specifically, the limitations include the following: (1) The opcode encoding lacks structured mapping, and the decoder must rely on the lookup table ROM, which increases the chip area and power consumption; (2) The arithmetic base is fixed at 2. For scenarios such as modulo 5 counting, modulo 60 coordinate transformation, and ternary / quinary data encoding, the base conversion needs to be performed frequently in the software layer, which increases the number of instructions and power consumption; (3) The data path width is fixed at 2^n, which is not aligned with the operands that are not in units of 2^n, resulting in wasted bit width; (4) The instruction encoding space is a single-plane decoding, and the decoder hardware cannot be reused; (5) There is a lack of hardware-level native detection flags for modulo boundary conditions. Summary of the Invention

[0005] The technical problems to be solved by this invention are: (1) There is no structured mapping between opcode encoding and operation type, and the instruction decoder must rely on lookup table or ROM; (2) The arithmetic base is fixed at 2, and non-binary modulo operation requires additional conversion overhead; (3) The data path width is limited to 2^n, which is not aligned with the natural width of the data of the modulo operation object; (4) There is a lack of hardware-level detection flags for modulo boundary conditions.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution.

[0007] The technical solution adopted in this invention is as follows: An accelerated processor with a non-binary radix arithmetic unit includes: a structured opcode decoder configured to receive an N-bit structured opcode and directly extract control signals from preset bit positions of the structured opcode via bit selection logic. The bit selection logic comprises multiple combinational logic gates, each with its input directly connected to the bit line corresponding to the preset bit position of the opcode, and its output directly connected to the control signal input of the arithmetic unit, without using a lookup table or read-only memory. The preset bit positions have a fixed mapping relationship with the arithmetic class: the highest bit is used for different arithmetic operations. The arithmetic operations are categorized into two classes: a subclass and a non-binary radix arithmetic unit, connected to the output of the structured opcode decoder, configured to perform arithmetic operations using a predetermined positive integer not a power of 2 as the base. The arithmetic operations include addition, subtraction, and multiplication, and all operations are completed within a single clock cycle through combinational logic. A status flag register, connected to the output of the non-binary radix arithmetic unit, is configured to generate a first status flag when the arithmetic operation result reaches a first preset threshold, and a second status flag when the arithmetic operation result reaches a second preset threshold.

[0008] Furthermore, the base of the non-binary radix arithmetic unit is 5, the input operands are primitive numbers ranging from 0 to 4, the addition operation follows the carry rule of carrying over when reaching five, the subtraction operation follows the borrow rule of borrowing with 5 as the borrow base, and the multiplication operation uses 5 as the operator to perform primitive number multiplication.

[0009] Furthermore, the 3-bit opcode received by the structured opcode decoder has a structured mapping relationship with the 8 basic operation types, and the bit positions of the opcode carry the encoding information of the major operation category.

[0010] Furthermore, the accelerated processor also includes a hierarchical instruction decoder, which decodes the high 3 bits and low 3 bits of the 6-bit instruction code into operation class signals and sub-operation signals, respectively, and the parity of the encoding space determines the direction of operation.

[0011] Furthermore, the accelerated processor also includes a configurable pipeline connected to the output of the non-binary radix arithmetic unit, comprising a serially connected encoding stage, transformation stage, mapping stage, and output stage, as well as a first bypass path that bypasses the transformation stage and the mapping stage and a second bypass path that bypasses the mapping stage; the first bypass path and the second bypass path are controlled to be turned on or off by a pipeline configuration register through multiple switches.

[0012] Furthermore, the data path width of the non-binary radix arithmetic unit is a non-power of 2 width of 36 bits, 24 bits, or a common factor of 6 bits.

[0013] Furthermore, the first status flag of the status flag register is activated when the arithmetic result is equal to the base minus one, and the second status flag is activated when the arithmetic result is equal to 0, which is used to detect the boundary conditions of the modulo operation of non-binary base arithmetic at the hardware level.

[0014] Furthermore, the combinational logic gate of the bit selection logic includes multiple AND gates. The first input of each AND gate is connected to the bit line of a preset bit position of the opcode, the second input is connected to the comparison reference value of that bit position, and the output of the AND gate is directly connected to the corresponding operation type control signal line.

[0015] Furthermore, the accelerated processor is packaged as a standard peripheral IP core with register mapping via the AXI4-Lite bus.

[0016] Beneficial effects: (1) The structured opcode decoder generates control signals directly from the opcode bit position through bit selection logic, eliminating the dependence on lookup tables or read-only memory, which can reduce chip area and static power consumption in ASIC implementation; (2) The non-binary radix arithmetic unit completes radix-5 addition, subtraction and multiplication operations in a single clock cycle, avoiding the format conversion and overflow handling overhead required for binary analog 5-ary arithmetic, which is expected to reduce the number of instructions executed in typical scenarios; (3) The status flag register detects the modulus boundary conditions in real time at the hardware level, and directly activates the flag when the operation result is equal to the radix minus one or zero. (4) The configurable pipeline supports three topology switching: single-stage pass-through, two-stage pipeline and four-stage pipeline. The same hardware can flexibly choose the balance point between delay and accuracy in different scenarios. (5) The data path width adopts a non-power of 2 width (36-bit, 24-bit, 6-bit), which is directly aligned with the natural bit width of the sensor output data, eliminating the data conversion overhead of bit width expansion. (6) The hierarchical instruction decoder decodes the instruction code in groups of high 3 bits and low 3 bits. The encoding space is structured and grouped according to the major operation categories. The decoder hardware has the advantage of regularity, which is conducive to timing convergence in physical design. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the architecture of the accelerated processor of the present invention. 100 is the structured opcode input; 110 is the structured opcode decoder (bit selection logic), which directly extracts the control signal from the opcode bit position; 200 is the non-binary radix arithmetic unit, which includes a radix configuration register (210), an arithmetic core (220), a carry-shift chain (230), and a status flag register (240); 300 is a configurable pipeline that supports four-stage topology switching: encoding → transformation → mapping → output; 400 is the output of the operation result.

[0018] Figure 2This is a schematic diagram of the bit selection logic of the structured opcode decoder of the present invention. 100 is the 3-bit opcode [2:0] input; 110 is the combinational logic gate array for the bit selection logic, where 111 is the bit2 decoding logic (highest bit classification), 112 is the bit1 decoding logic (subclass division), and 113 is the bit0 direction logic; 120 is the control signal output, connected to the control signal input terminal of the 200 non-binary radix arithmetic unit. The bit selection logic directly generates the control signal from the combinational logic circuit, without going through a lookup table or read-only memory.

[0019] Figure 3 This is a schematic diagram of the topology switching of the configurable pipeline of the present invention. 300 is the configurable pipeline, 310 is the encoding stage, 320 is the transformation stage, 330 is the mapping stage, and 340 is the output stage. The pipeline configuration register controls the conduction or disconnection of the bypass path through switches one to four. The three operating modes are: 350 Mode 1 (single-stage pass-through, encoding → output), 351 Mode 2 (two-stage pipeline, encoding → transformation → output), and 352 Mode 3 (four-stage pipeline, encoding → transformation → mapping → output). Detailed Implementation

[0020] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings.

[0021] Example 1: Structured Opcode Decoder This embodiment provides a mapping scheme between a 3-bit structured opcode and eight basic arithmetic operations. A structured mapping relationship is constructed between the 3-bit binary opcode and the eight basic arithmetic operations: 000 corresponds to addition (ADD), 001 to subtraction (SUB), 010 to multiplication (MUL), 011 is reserved / unused, 100 corresponds to left shift (SHL), 101 to bitwise AND, 110 to bitwise OR, and 111 to right shift (SHR). The bit positions of the opcode carry encoded information: the highest bit (bit2) distinguishes between arithmetic operations (0xx) and shift / bitwise operation operations (1xx); the second highest bit (bit1) distinguishes between basic arithmetic and extended arithmetic within the arithmetic class; and the lowest bit (bit0) distinguishes the specific operation direction within the same class.

[0022] The decoder generates control signals directly from the opcode bit positions through bit selection logic, eliminating the need for storage resources such as lookup tables. For example, the control signal for addition is generated by combinational logic of bit2=0 AND bit1=0 AND bit0=0; the shift direction signal is directly provided by bit2=1. In FPGA synthesis, this implementation consumes roughly the same resources as traditional lookup table schemes, and in ASIC standard cell implementations, it offers the advantage of structural simplicity due to the direct use of basic logic gates.

[0023] Example 2: Non-binary radix arithmetic unit This embodiment provides an arithmetic logic unit with 5 as the radix. Primitive numbers 1 to 4 (corresponding to values 1, 2, 3, 4) are defined as basic operation operands, and the carry operator 5 is used as the radix threshold. Addition follows the carry rule of carrying 1 when the sum reaches 5: result = (a + b) mod 5, carry = (a + b) >= 5. Subtraction follows the borrow rule with 5 as the borrow radix: result = (a >= b) ? (a - b) : (a - b + 5), borrow = (a < b). Multiplication performs primitive number multiplication with 5 as an operator, and uses operator 5 as a multiplication factor.

[0024] All the above non-binary radix arithmetic operations are implemented by combinational logic table lookup, and no sequential state machine or clock cycle waiting is required. The adder consists of a radix encoding lookup table and a carry comparator—the lookup table takes two primitive numbers as inputs and outputs a (result, carry_flag) pair; the carry comparator determines whether the sum of two operands reaches the radix threshold. The output of the subtracter is selected by a comparator—when a≥b, the result a-b is directly output, when a<b, the result a-b + the radix value is output and the borrow flag is set. The multiplier implements primitive number multiplication by using the radix operator. In the implementation of 6-bit data width, the operand range is 0-63, and one addition / subtraction / multiplication can be completed in a single clock cycle. When the width is extended, the carry shift chain connects the carry / borrow output of the lower unit to the addend input of the higher unit, and the length of the carry propagation path is equal to the data width (6-bit width corresponds to 6 levels of propagation).

[0025] The data path width of this embodiment adopts non-power-of-two width, including a 36-bit main data path (for full-width operations such as addition, multiplication, bitwise AND, bitwise OR, etc.), a 24-bit auxiliary data path (for operations such as subtraction, comparison, shifting, etc.) and a 6-bit minimum implementation width (a complete 36 / 24-bit data path can be formed by repeated combination). In the 6-bit width implementation, the data range is 0-63, which can accommodate all operands and operation results. The non-2^n width is directly aligned with the natural bit width of sensor output data (common 12-bit, 16-bit, 24-bit), which avoids the data conversion overhead of bit width extension.

[0026] Example 3: Status flag register This embodiment provides a modulo-digital boundary condition status flag register. A first status flag bit (high) is added, activated when the calculation result equals the base minus one (e.g., 4 in a radix-5 system); a second status flag bit (low) is added, activated when the calculation result equals 0. Both flag bits are directly generated in the calculation result bus via a comparator, requiring no additional judgment instructions. In subsequent control flow, these two flag bits can be directly used as the basis for conditional jumps, realizing hardware-level modulo-digital boundary detection.

[0027] Example 4: Configurable Production Line This embodiment provides a configurable pipeline that supports topology switching. The pipeline includes an encoding stage, a transformation stage, a mapping stage, and an output stage connected in series: the encoding stage converts the operation results of non-binary radix arithmetic units into a structured intermediate representation according to a preset encoding rule; the transformation stage performs bit-width conversion or value range scaling on the intermediate representation; the mapping stage maps the transformed data to a specified output value range space through combinational logic; and the output stage drives the mapping result to the output signal line via an output register. A first bypass path connects directly to the output stage from the output of the encoding stage, bypassing the transformation and mapping stages, and a second bypass path connects directly to the output stage from the output of the transformation stage, bypassing the mapping stage. The pipeline configuration register controls the on / off state of each bypass path through multiple switches: when the first bypass path is on and the second bypass path is off, a single-stage direct-through path (encode-output) is formed (suitable for simple data forwarding scenarios); when the first bypass path is off and the second bypass path is on, a two-stage pipeline (encode-transform-output) is formed (suitable for single-step transformation scenarios); when both the first and second bypass paths are off, a four-stage pipeline (encode-transform-map-output) is formed (suitable for complete transformation chain scenarios). The pipeline configuration signal shares the same control path with the ALU's mode signal, achieving structural coupling.

[0028] Example 5: Layered Instruction Decoder This embodiment provides a hierarchical instruction decoder. The high 3 bits of the 6-bit instruction code are decoded into one of eight major operation categories (arithmetic, logic, shift, memory access, control transfer, etc.), and the low 3 bits are decoded into one of eight sub-operations. The decoding rules are: major operation category = instruction code [5:3] → 8-to-1 decoding → major operation control signal; sub-operation = instruction code [2:0] → 8-to-1 decoding → sub-operation control signal; direction control = parity of instruction code [5:3] → left / right direction signal. The 64 encoded values ​​are divided into 8 groups according to the major operation categories, and each group of 8 encoded values ​​corresponds to 8 specific operations under the same major operation category. This hierarchical structure gives the instruction decoder a structural regularity advantage under the same functional coverage, which is beneficial to timing convergence in subsequent physical design.

[0029] Example 6: FPGA Implementation This embodiment provides an FPGA-based hardware implementation scheme. The target platform is a Gowin GW2A-LV18PG256C8 / I7 FPGA (Sipeed Tang Primer 20K development board). The toolchain uses GOWIN IDE for synthesis and placement / routing, and openFPGALoader for JTAG programming. Synthesis results show that the complete ALU module (including a structured opcode decoder, radix-5 arithmetic logic unit, and status flag register) consumes 96 LUTs, 37 ALU units, and 6 registers. Using an FPGA hardware verification platform, the results of the eight opcode operations are mapped to four onboard LEDs that blink cyclically, verifying radix-5 addition, radix-5 subtraction, radix-5 multiplication, full coverage of the eight opcodes, full coverage of 64 codes for the 6-bit decoder, and the status flag functionality. FPGA verification results show that this invention can complete synthesis, placement / routing, functional verification, and hardware operation on the Tang Primer 20K, with resource consumption within a reasonable range. The resource consumption described above indicates that the base-5 ALU of this invention can be fully deployed on entry-level FPGAs (thousands of LUTs), and is suitable for non-binary arithmetic acceleration in resource-constrained or legacy hardware environments.

[0030] The accelerated processor of this invention can be packaged as a standard register-mapped peripheral IP core via the AXI4-Lite bus interface and embedded in various processor systems (including but not limited to RISC-V, ARM, x86, etc. architectures), or deployed as a standalone accelerator on low-cost FPGAs or legacy hardware. It has low logic resource consumption (a complete ALU module has only 96 LUTs) and a low manufacturing cost threshold—mature processes such as 0.35μm and above can support it, without requiring advanced process support, providing hardware-level acceleration support for non-binary radix arithmetic. In typical scenarios of non-standard modulo-digital arithmetic, radix-5 arithmetic is performed in a single clock cycle using a dedicated hardware unit, avoiding the format conversion and overflow handling required for binary analog 5th-digit arithmetic, and is expected to reduce the number of instructions executed.

[0031] Example 7: Processing of quinary discrete symbol sequences This embodiment provides a scheme for applying a radix-5 ALU to hardware processing of pentary discrete symbol sequences. In a pentary encoding system, five symbol values ​​are used to encode information. Traditional processing maps the received symbols to binary before performing subsequent operations, introducing additional latency in the mapping process. The radix-5 ALU directly processes the five symbol values ​​in pentary form: addition corresponds to the sum of the five symbol values, subtraction corresponds to symbol offset correction, and multiplication corresponds to weighted coefficient calculation. All operations are completed within a single clock cycle, eliminating the need for a secondary mapping from symbol to binary to operation.

[0032] In this embodiment, the radix-5 ALU serves as a dedicated hardware accelerator for the pentadecimal symbol stream at the receiving end. The status flag register has preset thresholds of 4 (highest symbol value) and 0 (lowest symbol value). When the computation result exceeds the valid symbol range, a boundary flag is triggered, directly driving the gain control and symbol remapping logic. Compared to the software implementation, the hardware latency is reduced from tens of clock cycles to a single clock cycle.

[0033] This invention can be applied to the following fields: (1) IP core licensing - embedding non-standard arithmetic accelerator IP into SoC design; (2) multilevel signal processing - hardware-level arithmetic operations and boundary detection of multilevel symbol streams; (3) arithmetic acceleration - replacing software simulation with non-binary arithmetic hardware to reduce computational latency; (4) embedded coprocessors - providing low-power non-binary arithmetic support in resource-constrained devices; (5) dedicated processor design - providing hardware-level acceleration in multi-modal arithmetic scenarios.

[0034] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An accelerated processor with a non-binary radix arithmetic unit, characterized in that, include: A structured opcode decoder receives an N-bit structured opcode at its input and directly extracts control signals from preset bit positions of the structured opcode through bit selection logic. The bit selection logic includes multiple combinational logic gates, the input of each combinational logic gate being directly connected to the bit line corresponding to the preset bit position of the opcode, and the output of each combinational logic gate being directly connected to the control signal input of the arithmetic unit, without going through a lookup table or read-only memory. The preset bit positions have a fixed mapping relationship with the operation categories: the highest bit distinguishes between the arithmetic category and the bit operation category, and the second highest bit distinguishes between the subcategories within the major category. The non-binary radix arithmetic unit is connected to the output of the structured opcode decoder and performs arithmetic operations with a predetermined positive integer that is not a power of 2 as the base. The arithmetic operations include addition, subtraction and multiplication, and all operations are completed in a single clock cycle through combinational logic. A status flag register is connected to the output of the non-binary radix arithmetic unit. It generates a first status flag when the arithmetic result reaches a first preset threshold and a second status flag when the arithmetic result reaches a second preset threshold.

2. The accelerated processor according to claim 1, characterized in that, The non-binary radix arithmetic unit has a base of 5, and the input operands range from 0 to 4. The addition operation follows the carry rule of carrying over when it reaches 5, the subtraction operation follows the borrow rule of borrowing with 5 as the borrow base, and the multiplication operation uses 5 as the operator to perform radix multiplication.

3. The accelerated processor according to claim 1, characterized in that, In the structured opcode decoder, N equals 3 in the N-bit opcode received. The mapping relationship between the 3-bit opcode and the 8 basic operation types is as follows: the first code value 000 corresponds to the addition operation; the second code value 001 corresponds to the subtraction operation; the third code value 010 corresponds to the multiplication operation; the fourth code value 011 is reserved / unused; the fifth code value 100 corresponds to the left shift operation; the sixth code value 101 corresponds to the bitwise AND operation; the seventh code value 110 corresponds to the bitwise OR operation; and the eighth code value 111 corresponds to the right shift operation.

4. The accelerated processor according to claim 1, characterized in that, It also includes a configurable pipeline connected to the output of the non-binary radix arithmetic unit. The configurable pipeline includes an encoding stage, a transformation stage, a mapping stage, and an output stage connected in series. A first bypass path bypasses the transformation stage and the mapping stage to connect the output of the encoding stage to the output stage, and a second bypass path bypasses the mapping stage to connect the output of the transformation stage to the output stage. The bypass path is controlled to be turned on or off by a pipeline configuration register through multiple switches.

5. The accelerated processor according to claim 4, characterized in that, The configurable pipeline forms a single-stage direct path of encoding-output when the first bypass path is open and the second bypass path is closed; forms a two-stage pipeline of encoding-transformation-output when the first bypass path is closed and the second bypass path is open; and forms a four-stage pipeline of encoding-transformation-mapping-output when both the first and second bypass paths are closed.

6. The accelerated processor according to claim 1, characterized in that, The data path width of the non-binary radix arithmetic unit adopts a width that is not a power of 2, and is selected from 36 bits, 24 bits, or their common factor 6 bits.

7. The accelerated processor according to claim 1, characterized in that, The first status flag of the status flag register is activated when the result of the arithmetic operation is equal to the base minus one, and the second status flag is activated when the result of the arithmetic operation is equal to 0. This is used to detect the boundary conditions of the modulo operation in non-binary base arithmetic at the hardware level.

8. The accelerated processor according to claim 1, characterized in that, It also includes a host processor interface that communicates with the host processor via the AXI4-Lite bus, encapsulating the accelerator processor as a standard peripheral IP core with register mapping.

9. A method for accelerating non-binary radix arithmetic, applied to the accelerated processor according to any one of claims 1 to 8, characterized in that, include: Opcode receiving steps: Receive N-bit opcodes through a structured opcode decoder, and extract control signals directly from preset bit positions through bit selection logic; Non-binary arithmetic execution steps: Using a predetermined positive integer other than a power of 2 as the base, arithmetic operations including addition, subtraction, and multiplication are completed through combinational logic within a single clock cycle; Status flag output steps: A first status flag is generated when the arithmetic operation result reaches a first preset threshold, and a second status flag is generated when the arithmetic operation result reaches a second preset threshold.

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