Dynamic partial sum tree circuit

Abstract

The embodiment of the application discloses a dynamic local adder tree circuit, comprising: a M-to-N full-precision compressor composed of (M-N) dynamic full adders (DM-FA) through multi-stage cascading, used for generating a accumulated result based on n inputs; the first stage is composed of (M / 3) DM-FA used for accumulating M bit-weightless point results, and the second stage to the last stage are used for accumulating at least part of the sum of bits and / or carry of the previous stage; a Wallace tree circuit composed of multi-stage full adders and (s-1) half adders, used for multi-stage parallel accumulation of the a accumulated results and b one-bit point products, and outputting s-bit local multiplication and addition results. The circuit is suitable for high-performance multiplication and addition operation units, and can effectively improve the partial product compression efficiency and overall calculation speed.

Description

Technical Field

[0001] This application relates to the field of integrated circuits and memory computing technology, specifically to a dynamic local addition tree circuit. Background Technology

[0002] In Digital Compute-in-Memory (DCIM) architectures, multiply-accumulate (MAC) operations are core to achieving highly parallel computing tasks such as neural network inference. To efficiently process the large number of partial products or dot products output from the memory array, an addition tree structure is typically used to quickly compress and accumulate multiple inputs. Traditional addition trees are mostly built based on static CMOS logic, cascading full adders (FAs) and half adders (HAs) to form a Wallace tree or similar topology to achieve high bit width and full precision parallel accumulation. For example, in a 64-channel fixed-point MAC unit, a conventional design requires as many as 127 HAs and 120 FAs to complete partial product compression, resulting in a large circuit area and severely limiting the integration efficiency of high-density in-memory computing chips. Furthermore, when such static addition trees process "weightless dot products" (i.e., input items do not have uniform weight alignment) from the in-memory computation units of MRAM or SRAM, the sparse and non-full input distribution results in a large number of idle carry links and invalid intermediate node states, leading to significant logical redundancy and resource waste.

[0003] In recent years, in order to improve energy efficiency and area efficiency, the industry has proposed a variety of optimization schemes. CN114937470B proposes to integrate the transmission gate multiplier and adder tree in the SRAM array, and realize full-precision calculation through bit serial input and shift accumulation. Although it improves the parallelism, its adder tree still uses the traditional static FA / HA structure, which fails to solve the problem of low logic utilization. CN114647399B introduces an approximate compression strategy, and uses truncation and approximate 4:2 compressor in the low bit to reduce power consumption, but sacrifices the full-precision characteristics and is not suitable for application scenarios with strict requirements for computational accuracy[4]. Although CN117369767A reduces the area of ​​a single adder unit by reducing the number of transistors (10T full adder), its cascaded adder tree still has a large number of invalid carry paths when facing unaligned and unweighted inputs, and fails to optimize the data flow and compression logic from the architecture level. The CN116088792B uses a combination of Poltz coding and multi-channel adder tree to improve throughput, but its adder tree still relies on standard static logic, making it difficult to avoid static leakage and redundant switching power consumption, especially under high-frequency operation, the power consumption increases significantly.

[0004] The aforementioned existing technologies share three major drawbacks: First, they are structurally complex and have low logic utilization—when processing weightless dot products, the uneven distribution of input bit weights in static FA / HA addition trees leads to a large number of idle multi-level carry networks, resulting in invalid intermediate states. Second, they have high energy consumption and latency—static CMOS logic requires complete pull-up / pull-down networks and inverting buffers, which not only results in static leakage but also generates redundant charging and discharging power consumption during high-frequency evaluation, making it difficult to meet the real-time requirements of high-speed in-memory computing architectures such as MRAM-CIM. Third, they have large circuit area overhead—taking a 64-input system as an example, a traditional Wallace tree requires hundreds of addition units, often exceeding the area of ​​macrocells by 50%, severely limiting array density and scalability. Although some research has attempted to alleviate these problems through device-level simplification or approximate calculations, significant technical bottlenecks remain in achieving full precision, low power consumption, and high integration. A new addition tree architecture is urgently needed that can dynamically adapt to weightless input characteristics, reduce redundant logic, and utilize efficient circuits to achieve low-power, high-speed accumulation.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] To address the technical challenges of existing digital in-memory computing (DCIM) architectures, such as complex structures, low logic utilization, high energy consumption and latency, and large circuit area in addition trees, a dynamic local addition tree circuit is proposed to achieve high energy efficiency, full precision, low power consumption, and high integration of multi-channel point accumulation addition operations.

[0007] The technical solution adopted by this application to solve its technical problem is as follows: A dynamic local addition tree circuit is provided, including *a* M-to-N full-precision compressors and a Wallace tree circuit; the M-to-N full-precision compressor is composed of (MN) groups of dynamic full adders DM-FA cascaded in multiple stages, used to generate *a* accumulated results based on *n* unweighted dot product inputs; wherein, the first stage consists of (M / 3) DM-FAs used to accumulate the *M* unweighted dot product results, and the second to the last stage are respectively used to accumulate at least some of the partial sum bits and / or carry bits from the previous stage; the Wallace tree circuit is composed of multiple stages of full adders and (s-1) half adders, performing multi-level parallel accumulation of the *a* accumulated results and *b* 1-bit dot products, outputting *s*-bit local multiplication-addition results; wherein... .

[0008] Furthermore, the M-to-N full-precision compressor is organized hierarchically according to bit weights: the second stage is used to combine the parts and bits of the first stage according to bit weight 2.0 Accumulate, with partial carry-over calculated according to place value 2. 1 Accumulation is performed; Level 3 is used to combine parts and bits from Levels 1 and 2 according to their bit weights of 2. 0 Accumulate the values, and adjust the corresponding carry-over values ​​according to their place value of 2. 1 Accumulation is performed; Level 4 is used to combine the parts and bits of Level 2 according to their bit weights of 2. 1 Perform the summation, and then combine the third-level partial sum and partial carry according to the place value 2. 1 Perform accumulation; in level 5, carry over parts of levels 2 and 3, and add parts of level 4 according to place value 2. 2 The results are accumulated and finally output as an N-bit full-precision compressed result.

[0009] Furthermore, the Wallace tree circuit is specifically used to process each column of input in groups of 3 bits by calling a full adder at each level to achieve efficient parallel compression.

[0010] Furthermore, M=15, N=4, n=64, meaning the M-to-N full-precision compressor is a 15-to-4 full-precision compressor, used to receive 15 unweighted dot product inputs, and to achieve full-bit logic mapping through eleven sets of dynamic full adders DM-FA cascaded.

[0011] Furthermore, the Wallace tree circuit receives four 4-bit SUM[3:0] outputs from a 15-to-4 full-precision compressor and four 1-bit partial product inputs IN[33:30]. The 0th bit of each stage's four partial sums and its corresponding 1-bit partial product are used as inputs to two full adders to generate the first sum bit and two carry bits. The sum bit of one of the full adders and its corresponding 1-bit partial product are used as inputs to the third FA. The second sum bit generated by the third FA and the first sum bit are used as input data to the half adder of this stage. The sum bit generated by the half adder of this stage is the least significant bit of the final output data. All carry bits of this stage are used as inputs to the next stage according to their set bit weights.

[0012] Furthermore, the dynamic full adder DM-FA includes: a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, a fifth N-type transistor, a sixth N-type transistor, a seventh N-type transistor, an eighth N-type transistor, a ninth N-type transistor, a tenth N-type transistor, an eleventh N-type transistor, a twelfth N-type transistor, a thirteenth N-type transistor, and a fourteenth N-type transistor; After the first N-type transistor and the fifth N-type transistor are connected in parallel, their drains are connected to the source of the second N-type transistor, and their sources are connected to the source of the fourth N-type transistor and the drain of the thirteenth N-type transistor. The drain of the fourth N-type transistor is connected to the source of the third N-type transistor. The drain of the first P-type transistor is connected to the drain of the second N-type transistor and the drain of the third N-type transistor at node X. After the ninth, tenth, and eleventh N-type transistors are connected in parallel, their drains are connected to the source of the sixth N-type transistor, and their sources are connected to the source of the twelfth N-type transistor and the drain of the fourteenth N-type transistor. The drain of the eighth N-type transistor is connected to the source of the seventh N-type transistor, and its source is connected to the drain of the twelfth N-type transistor. The drains of the second P-type transistor, the sixth N-type transistor, and the N-type transistor N7 are connected to node Y.

[0013] Furthermore, the DM-FA employs a dynamic logic strategy based on pre-charge and evaluation.

[0014] Furthermore, during the pre-charging phase, the internal nodes X and Y of the DM-FA are charged to a high level; during the evaluation phase, the NMOS network performs logic operations.

[0015] Furthermore, during the pre-charging phase, the first P-type transistor and the second P-type transistor are turned on for pre-charging, the thirteenth N-type transistor and the fourteenth N-type transistor are turned off, nodes X and Y are kept at a high level, and the carry and sum bits are at a low level.

[0016] Furthermore, during the evaluation phase, the first P-type transistor and the second P-type transistor are turned off, while the thirteenth N-type transistor and the fourteenth N-type transistor are turned on.

[0017] The beneficial effects of this application are as follows: In the verification of a 128 kb MRAM-CIM macrostructure, compared with the traditional static CMOS adder tree (requiring 127 HAs and 120 FAs), this application only requires 57 FAs and 6 HAs, reducing the number of transistors by approximately 50% and saving 48.7% of the logic area; the dynamic logic structure eliminates static current paths and redundant inverters, reducing MAC operation power consumption by 48.7% while suppressing transient DC leakage current during switching; the 15-to-4 full-precision compressor can achieve full-bit logic utilization, avoid carry chain idleness caused by non-full-bit inputs, and reduce the number of adder stages, which is crucial. Path latency is reduced, and full-precision compression of 64-channel unweighted dot product is completed in a single cycle. A customized Wallace tree is used with precise matching of FC bit width (4-bit output × 4-way + 4-bit original dot product), which improves logic utilization and area efficiency compared to the general Wallace structure. The overall solution significantly reduces the energy consumption and area ratio of the adder tree from >50%, and has the advantages of high speed (completed in a single cycle), low power consumption (48.7% energy reduction) and high integration (48.7% area saving) in high-density, high-throughput MRAM-CIM systems.

[0018] Specific embodiments of this application are disclosed in detail with reference to the following description and accompanying drawings, indicating how the principles of this application can be adopted. It should be understood that the embodiments of this application are not limited in scope. Within the spirit and scope of the appended claims, embodiments of this application include many changes, modifications, and equivalents. Features described and / or shown for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments. Attached Figure Description

[0019] The accompanying drawings described herein are for illustrative purposes only and are not intended to limit the scope of this application in any way. Furthermore, the shapes and scales of the components in the drawings are merely illustrative to aid in understanding this application and do not specifically limit the shapes and scales of the components. Those skilled in the art, guided by the teachings of this application, can select various possible shapes and scales to implement this application according to specific circumstances.

[0020] Figure 1 This is a schematic diagram of the dynamic local addition tree circuit of the first embodiment of this application; Figure 2 This is a schematic diagram of the dynamic local addition tree circuit of the second embodiment of this application; Figure 3 This is a schematic diagram of the circuit structure of a 15-to-4 full-precision compressor according to an embodiment of this application; Figure 4This is a schematic diagram of the Wallace tree circuit in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of the dynamic full adder according to an embodiment of this application; Figure 6 This is a schematic diagram of the operation timing of the dynamic full adder according to an embodiment of this application. Detailed Implementation

[0021] The technical solutions of this application will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that these embodiments are only used to illustrate this application and are not intended to limit the scope of this application. After reading this application, any modifications of this application in various equivalent forms by those skilled in the art fall within the scope defined by the appended claims.

[0022] In the embodiments of this application, the terms "first," "second," etc., are used to distinguish different elements by name, but do not indicate the spatial arrangement or chronological order of these elements, and these elements should not be limited by these terms. The term "and / or" includes any one or more of the terms listed in association and all combinations thereof. The terms "comprising," "including," "having," etc., refer to the presence of the stated features, elements, components, or assemblies, but do not exclude the presence or addition of one or more other features, elements, components, or assemblies.

[0023] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0024] Positional relationships such as "parallel" or "perpendicular" not only include completely "parallel" or "perpendicular" positional relationships, but also positional relationships with angular deviations relative to completely "parallel" or "perpendicular" within a preset deviation range.

[0025] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0026] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linking," and "socketing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0027] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0029] In one embodiment of this application, a dynamic local addition tree circuit is provided, such as... Figure 1 As shown, the dynamic local additive tree circuit includes: a M-to-N full-precision compressor and a Wallace tree circuit.

[0030] A multi-stage cascaded M-to-N full-precision compressor, consisting of (MN) groups of dynamic full adders (DM-FA), is used to generate a cumulative result based on n inputs. The first stage consists of (M / 3) DM-FAs used to accumulate M unweighted results. The second to the final stage are used to accumulate at least a portion of the sum bits and / or carry bits from the previous stages, ultimately outputting a partial cumulative result SUM[(N-1):0]. Unlike existing hierarchical CMOS static adder trees, the FC in this application maintains full-bit logic utilization in each compression stage, meaning all input and output bits participate in effective logic mapping. This avoids idle or redundant states present in conventional carry chains or non-full-bit logic paths, significantly improving logic resource utilization efficiency and drastically reducing the number of adder stages and devices required for the same accumulation precision.

[0031] In some embodiments, the number of cascaded stages can be determined based on the total number of DM-FAs.

[0032] The Wallace tree circuit consists of multiple full adders and (s-1) half adders. It performs multi-level parallel accumulation on the a accumulated results and b 1-bit partial products, and outputs s-bit local multiply-accumulate results.

[0033] in, .

[0034] This dynamic local addition tree circuit structure can directly compress the input data, which is the result of the weightless dot product OUT=IN×W from n inputs IN and weights W, into a full-precision local multiply-accumulate result LMAC[s:0] within the array, thereby achieving high-throughput local addition operations without relying on external accumulators.

[0035] In some embodiments, M=15, N=4, and n=64. Then, a=64 / 15, taking the quotient, a=4, and b=64-(4×15)=4. For example... Figure 2 As shown, the dynamic local additive tree circuit includes: four 15-to-4 full-precision compressors and a Wallace tree circuit.

[0036] This dynamic local addition tree circuit structure can directly compress the input data from the weightless dot product OUT=IN×W of 64 inputs IN and weights W into a full-precision local multiply-accumulate result LMAC[6:0] within the array, thereby achieving high-throughput local addition operations without relying on external accumulators.

[0037] This 15-to-4 full-precision compressor consists of 11 sets of dynamic full adders (DM-FAs) cascaded in 5 stages to generate 4 accumulated results based on 64 inputs. The first stage comprises 5 DM-FAs used to accumulate 15 unweighted results. Stages 2 through 5 are used to accumulate at least a portion of the sum bits and / or carry bits from the previous stages, ultimately outputting a partial accumulated result SUM[3:0]. Unlike existing hierarchical CMOS static adder trees, the FC in this application maintains full-bit logic utilization in each compression stage, meaning all input and output bits participate in effective logic mapping. This avoids idle or redundant states present in conventional carry chains or non-full-bit logic paths, significantly improving logic resource utilization efficiency and drastically reducing the number of adder stages and devices required for the same accumulation precision.

[0038] In some embodiments, such as Figure 3 As shown, the accumulation method for levels 2 to 5 is as follows: Level 2 is to sum the part of level 1 and bit S according to the bit weight of 2. 0 When performing group accumulation, the carry-in CO is weighted at 2. 1Accumulate; Level 3 will sum the parts of Level 1 and Level 2 and bit S according to bit weight 2. 0 Perform group accumulation, taking the carry CO from levels 1 and 2 with a place value of 2. 1 Accumulate; Level 4 adds the partial sum of Level 2 (S) and Level 3 (S) with the carry (CO), according to the position weight 2. 1 The summation is performed; in level 5, the carry CO from levels 2 and 3, and the sum S from level 4, are all weighted according to position 2. 2 Accumulate.

[0039] Figure 4 This is a schematic diagram of the Wallace tree circuit in an embodiment of this application, as shown below. Figure 4 As shown, the Wallace tree circuit (also known as the Wallace adder tree) includes multiple CMOS full adders (FA) and half adders (HA). The Wallace tree circuit is used to accumulate the results of the 4-bit partial product SUM[3:0] and the four 1-bit dot product inputs IN[33:30] from the 15-to-4 full-precision compressor, and outputs the 7-bit local multiply-accumulate result LMAC[6:0].

[0040] The Wallace tree circuit achieves efficient parallel compression through multi-level parallel accumulation. Specifically, for each level, each column of input is processed by a single algorithm (FA) in groups of three bits, achieving high efficiency. In practice, the product of the 0th bit of the sum of the four parts of each level and the corresponding 1 bit is used as the input of two FAs to generate the first sum bit and two carry bits (for example, the 0th bit of the sum of the four parts of the first level and IN[31:30] are used as the input of two FAs to generate the sum bit S[1:0] and two carry bits CO). The product of the sum bit of one of the two FAs and the corresponding 1 bit is used as the input of the third FA. The second sum bit generated by the third FA and the first sum bit are used as the input data of the half-adder of this level. The sum bit generated by the half-adder of this level is used as the least significant bit of the final output data. All carry bits of this level are used as the input of the next level according to the set bit weight. This Wallace tree circuit structure has the advantages of high parallelism, low logic depth, and optimized area and power consumption, which can significantly improve the speed of local multiplication and addition operations and provide high-precision data for subsequent addition trees or global accumulation.

[0041] Figure 5 This is a schematic diagram of the structure of the dynamic full adder according to an embodiment of this application, as shown below. Figure 5 As shown, the DM-FA includes: a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1, a second N-type transistor N2, a third N-type transistor N3, a fourth N-type transistor N4, a fifth N-type transistor N5, a sixth N-type transistor N6, a seventh N-type transistor N7, an eighth N-type transistor N8, a ninth N-type transistor N9, and a tenth N-type transistor N1. 10 11th type N transistor N 11Twelfth N-type transistor N 12 Thirteenth N-type transistor N 13 and the fourteenth N-type transistor N 14 .

[0042] The first N-type transistor N1 and the fifth N-type transistor N5 are connected in parallel, with their drains connected to the source of the second N-type transistor N2, and their sources connected to the source of the fourth N-type transistor N4 and the thirteenth N-type transistor N2. 13 The drain of the fourth N-type transistor N4 is connected to the source of the third N-type transistor N3; the drain of the first P-type transistor P1 is connected to the drain of the second N-type transistor N2 and the drain of the third N-type transistor N3 at node X; the ninth N-type transistor N9 and the tenth N-type transistor N... 10 and the eleventh N-type transistor N 11 After the three are connected in parallel, the drain is connected to the source of the sixth N-type transistor N6, and the source is connected to the twelfth N-type transistor N. 12 The source and the fourteenth N-type transistor N 14 The drain of the eighth N-type transistor N8 is connected to the source of the seventh N-type transistor N7, and the source is connected to the twelfth N-type transistor N... 12 The drain of the second P-type transistor P2, the drain of the sixth N-type transistor N6, and the drain of the N-type transistor N7 are connected to the Y node.

[0043] In some embodiments, the DM-FA employs a dynamic logic strategy based on pre-charge-evaluation, which significantly improves speed and energy efficiency.

[0044] In some embodiments, during the pre-charge phase (PRE = VSS), the drains of the internal nodes X and Y of the DM-FA are charged to a high level, and the first P-type transistor P1 and the second P-type transistor P2 are turned on.

[0045] During the evaluation phase, the NMOS network performs logic operations.

[0046] Specifically, during the pre-charge phase (PRE=VSS), the first P-type transistor P1 and the second P-type transistor P2 are turned on for pre-charge, and the thirteenth N-type transistor N... 13 and the fourteenth N-type transistor N 14 When closed, internal nodes X and Y remain at a high level, while carry (CO) and sum (S) are at a low level.

[0047] During the evaluation phase (PRE = VDD), the first P-type transistor P1 and the second P-type transistor P2 are turned off, and the thirteenth N-type transistor N... 13 and the fourteenth N-type transistor N14 When opened, the internal nodes discharge according to the states of inputs A, B, and C. Specifically, as follows: Figure 5 As shown, when inputs A = B = C = 1, the level is high, and the N-type transistors N1-N... 12 When all circuits are turned on, leakage paths are formed in both the CO and S circuits. Therefore, internal nodes X and Y are pulled low during the evaluation phase, ultimately outputting logic "1" S and CO signals via inverters. When A = B = C = 0, inputs A, B, and C are all set to low level, and N-type transistors N1-N... 12 When both are turned off, the CO and S circuits are shut down, preventing the formation of a leakage path. The voltages at internal nodes X and Y remain high, ultimately resulting in S and CO signals output as logic "0" via the inverter. The corresponding timing waveforms are as follows: Figure 6 As shown.

[0048] like Figure 6 As shown, when A=B=1 and C=0, for the CO circuit section, the second N-type transistor N2 is off, and all other transistors are on. At this time, N-type transistors N3 and N4 will form a leakage path, and the voltage of the internal node X will be pulled low. Therefore, the CO circuit section outputs logic "1" through the inverter. For the S circuit section, N-type transistors N9 and N4... 12 If the circuit is closed, neither of the two circuit branches under internal node Y can conduct, and the voltage of internal node Y will remain high. Therefore, the output of the S-section circuit after the inverter will be logic "0". When A = B = C = 1, the circuit is at a high level, and the N-type transistors N1-N... 12 When all circuits are turned on, a leakage path is formed in both the CO and S circuits. Therefore, internal nodes X and Y are pulled low during the evaluation phase, and finally, the S and CO signals with logic "1" are output through the inverter.

[0049] By utilizing dynamic node flipping to generate summation and carry signals, the DM-FA effectively eliminates redundant inversion and quiescent current paths, reducing the number of transistors by nearly 50%, thereby significantly reducing power consumption and area overhead. Integrating the DM-FA into a 15-to-4 FC chain further improves energy efficiency and area utilization.

[0050] The dynamic local adder tree circuit proposed in this application can achieve parallel compression and summation of multi-channel weighted data by integrating an M-to-N (e.g., 15-to-4) full-precision compressor (FC) and a customized Wallace adder tree within the array. Each FC consists of cascaded dynamic DM-FAs, which can achieve high-speed, low-power multi-input compression while ensuring full-bit logic utilization.

[0051] The Wallace adder tree of this application can complete full-precision addition compression operations for multiple inputs in a single cycle, which significantly reduces the logic depth and transistor count compared to traditional CMOS static adder tree-based schemes.

[0052] In a typical 64-channel accumulation operation, this application reduces approximately 121 half-adders (HA) and 63 full adders (FA), resulting in a logic area saving of approximately 48.7% and a significant reduction in power consumption. Simultaneously, the dynamic addition structure effectively suppresses DC leakage current during switching transients, further improving overall energy efficiency.

[0053] Therefore, this application achieves high throughput parallel accumulation while also taking into account high speed, low power consumption and high integration, making it suitable for energy efficiency optimization and high-precision computing tasks of next-generation MRAM-CIM chips.

[0054] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0055] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A dynamic local addition tree circuit, characterized in that, include: A multi-stage cascaded M-to-N full-precision compressor, consisting of (MN) groups of dynamic full adders DM-FA, is used to generate a accumulated results based on n inputs; wherein, the first stage consists of (M / 3) DM-FAs for accumulating M unweighted point results, and the second to the last stage are used to accumulate at least a portion of the sum bits and / or carry bits from the previous stages respectively; The Wallace tree circuit consists of multiple full adders and (s-1) half adders. It performs multi-level parallel accumulation on the a accumulated results and b 1-bit partial products, and outputs s-bit local multiply-accumulate results. in, .

2. The dynamic local addition tree circuit according to claim 1, characterized in that, Level 2 is used to combine the parts and bits of Level 1 according to their place value 2. 0 Accumulation is performed, with partial carry-overs accumulated according to their place values; Level 3 is used to combine the partial sums from Level 1 and Level 2 according to their place values. 0 Accumulation is performed, with partial carry-over accumulated according to place value; the fourth level is used to combine the partial sum from the second level according to place value. 1 Line accumulation, taking the third-level partial sum and partial carry according to the position weight 2. 1 Perform accumulation; in level 5, carry over parts of levels 2 and 3, and add parts of level 4 according to their place value 2. 2 Accumulate.

3. The dynamic local addition tree circuit according to claim 1, characterized in that, For each level, the Wallace tree circuit processes each column of input in groups of 3 bits using the corresponding full adder.

4. The dynamic local addition tree circuit according to claim 1, characterized in that, M=15, N=4, n=64.

5. The dynamic local addition tree circuit according to claim 4, characterized in that, The product of the 0th bit of the sum of the four parts of each stage and the corresponding 1 bit is used as the input of two full adders to generate the first sum bit and two carry bits. The sum bit of one of the full adders and the corresponding 1 bit are used as the input of the third FA. The second sum bit generated by the third FA and the first sum bit are used as the input data of the half adder of this stage. The sum bit generated by the half adder of this stage is used as the least significant bit of the final output data. All carry bits of this stage are used as the input of the next stage according to the set bit weight.

6. The dynamic local addition tree circuit according to claim 1, characterized in that, The DM-FA includes: a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, a fifth N-type transistor, a sixth N-type transistor, a seventh N-type transistor, an eighth N-type transistor, a ninth N-type transistor, a tenth N-type transistor, an eleventh N-type transistor, a twelfth N-type transistor, a thirteenth N-type transistor, and a fourteenth N-type transistor; After the first N-type transistor and the fifth N-type transistor are connected in parallel, their drains are connected to the source of the second N-type transistor, and their sources are connected to the source of the fourth N-type transistor and the drain of the thirteenth N-type transistor. The drain of the fourth N-type transistor is connected to the source of the third N-type transistor. The drain of the first P-type transistor is connected to the drain of the second N-type transistor and the drain of the third N-type transistor at node X. After the ninth, tenth, and eleventh N-type transistors are connected in parallel, their drains are connected to the source of the sixth N-type transistor, and their sources are connected to the source of the twelfth N-type transistor and the drain of the fourteenth N-type transistor. The drain of the eighth N-type transistor is connected to the source of the seventh N-type transistor, and its source is connected to the drain of the twelfth N-type transistor. The drains of the second P-type transistor, the sixth N-type transistor, and the N-type transistor N7 are connected to node Y.

7. The dynamic local addition tree circuit according to claim 6, characterized in that, The DM-FA employs a dynamic logic strategy based on pre-charge and evaluation.

8. The dynamic local addition tree circuit according to claim 7, characterized in that, During the pre-charge phase, the drain of the internal node of the DM-FA is charged to a high level; during the evaluation phase, the NMOS network performs logic operations.

9. The dynamic local addition tree circuit according to claim 8, characterized in that, During the pre-charging phase, the first P-type transistor and the second P-type transistor are turned on for pre-charging, the thirteenth N-type transistor and the fourteenth N-type transistor are turned off, the internal node X and the internal node Y are kept at a high level, and the carry and sum bits are at a low level.

10. The dynamic local addition tree circuit according to claim 8, characterized in that, During the evaluation phase, the first P-type transistor and the second P-type transistor are turned off, while the thirteenth N-type transistor and the fourteenth N-type transistor are turned on.

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