High-robust CNTFET probabilistic bit circuit based on sampling calibration compensation and working method thereof

Abstract

This invention provides a highly robust CNTFET probabilistic bit circuit based on sampling calibration compensation and its operating method. The circuit includes a CNTFET random device, a DAC pulse driving module, an ADC sampling module, a sampling calibration control module, and a comparison and decision module. The sampling calibration control module acquires the input control quantity corresponding to the CNTFET random device to be updated and converts it into a DAC control code. The DAC pulse driving module applies an input pulse V to the CNTFET random device according to the DAC control code. in Simultaneously, a reference pulse V is inserted into the input pulse sequence according to a preset timing. ref The ADC sampling module collects the input response samples D respectively. in and reference response sample D ref The sampling calibration control module is based on D ref Generate dynamic reference value D REF And according to D in With D REF A calibration compensation decision value ΔD is generated, and the comparison decision module outputs a stable p-bit state based on ΔD. This invention reduces the impact of slow drift, zero-point offset, low-frequency disturbances, and slow-changing errors in the ADC / DAC link on the output probability, improving the circuit's cycle-to-cycle consistency and device-to-device consistency.

Description

Technical Field

[0001] This invention belongs to the technical field of probabilistic calculation circuits and carbon nanotube field-effect transistor random devices, specifically relating to a highly robust carbon nanotube field-effect transistor (CNTFET) probabilistic bit circuit based on sampling calibration compensation and its working method. Background Technology

[0002] Probabilistic computers typically consist of multiple probability bits, which output random binary states of logic "1" or logic "0" under the control of input signals. Probabilistic bits generally rely on physical random devices to generate random fluctuations, and then external circuitry converts the random analog response into a binary state. During long-term continuous operation, the output probability of the probability bits may be affected by factors such as device state drift, threshold drift, low-frequency drift, bias stress, temperature disturbances, and insufficient consistency between devices. This results in unstable probability distributions for the same probability bit across different operating cycles, and inconsistent probability responses among multiple probability bits.

[0003] Existing probabilistic bit circuits typically connect the analog output node of the random access device to one end of a comparator and apply a fixed comparison voltage V. cmp Alternatively, a fixed comparison threshold can be connected to the other end of the comparator, allowing the comparator to directly output a logic "1" or logic "0". This method has a simple structure, but requires a fixed comparison voltage V. cmp It cannot change with changes in the state of the random device itself, or with zero-point offsets or gain changes in the external readout and sampling links. Therefore, when the state of the device or the state of the external circuit changes slowly, a deviation will occur between the comparator's decision reference and the actual random response, causing the output probability corresponding to a certain input signal to shift.

[0004] For probabilistic bits based on carbon nanotube field-effect transistors (CNTFETs), the random fluctuations of the CNTFET random device can serve as a source of probabilistic sampling. By adjusting the input signal applied to the gate or control terminal of the CNTFET random device, the statistical probability of its output logic "1" can be changed. To ensure stable output of the CNTFET probabilistic bits under continuous pulse drive, long-term sampling, and multi-device array operation conditions, a method is needed that no longer relies solely on a comparator and a fixed comparison voltage V. cmp The circuit and operating method enable it to obtain the input response and reference response through ADC sampling, and then output the p-bit state after calibrating and compensating the input response based on the reference response, thereby improving the period-to-period consistency and device-to-device consistency of the CNTFET probability bits. Summary of the Invention

[0005] To address the issue that the output probability of a CNTFET probabilistic computer is susceptible to device drift and sampling link errors during continuous operation, this invention provides a highly robust CNTFET probabilistic bit circuit based on sampling calibration compensation and its operating method. The core of this solution lies in: incorporating a CNTFET random device, a DAC pulse drive module, an ADC sampling module, a sampling calibration control module, and a comparison and decision module into the highly robust CNTFET probabilistic bit circuit based on sampling calibration compensation; and designing an input pulse V... in and reference pulse V ref The driving waveform is obtained by using the ADC sampling module to acquire the input response samples D. in and reference response sample D ref The sampling calibration control module determines the reference response sample D based on the data. ref Update dynamic reference value D REF And based on the input response sample D in With dynamic reference value D REF A calibration compensation decision quantity is generated, and then the comparison decision module outputs a stable p-bit state based on the calibration compensation decision quantity.

[0006] The technical solution of the present invention is as follows:

[0007] A high-robust CNTFET probabilistic bit circuit based on sampling calibration compensation is characterized by comprising a CNTFET random device, a DAC pulse driving module, an ADC sampling module, a sampling calibration control module, and a comparison decision module; the gate or control terminal of the CNTFET random device is connected to the DAC pulse driving module, the source terminal is grounded or connected to a reference potential, and the drain or readout terminal forms a sampling node through a read resistor or a current-to-voltage conversion circuit; the input terminal of the ADC sampling module is connected to the sampling node to acquire the voltage of the sampling node, and the output terminal is connected to the sampling calibration control module, which, upon input pulse V... in After the action, the output and input response samples D in and in reference pulse V ref Output reference response sample D after action ref The sampling calibration control module is connected to the DAC pulse drive module, the ADC sampling module, and the comparison decision module. The sampling calibration control module includes a pulse control unit, a reference update unit, and a calibration compensation unit. The pulse control unit acquires the input control quantity corresponding to the CNTFET random device to be updated, generates a DAC control code based on the input control quantity, and controls the DAC pulse drive module to insert a reference pulse V into the input pulse sequence according to a preset insertion rule. ref The DAC pulse drive module applies an input pulse V to the CNTFET random device according to the DAC control code. in and the inserted reference pulse Vref The reference update unit is used to update the reference response sample D based on one or more reference response samples D. ref Generate dynamic reference value D REF The calibration compensation unit is used to adjust the input response sample D. in With dynamic reference value D REF Generate a calibration compensation decision value ΔD, where ΔD represents the input response sample D. in Relative to dynamic reference value D REF The deviation amount; the comparison decision module is used to make a decision on the calibration compensation decision amount ΔD. When ΔD is greater than the preset decision threshold θ, it outputs a p-bit state of logic "1"; otherwise, it outputs a p-bit state of logic "0".

[0008] Furthermore, the ADC sampling module and DAC pulse drive module meet the requirements of low-noise sampling and low-error pulse output, so that the ADC sampling error, DAC output error and peripheral readout link noise are lower than the effective amplitude of the random fluctuation signal of the CNTFET random device.

[0009] This invention also proposes a working method for the above-mentioned high-robust CNTFET probabilistic bit circuit based on sampling calibration compensation, which includes the following steps within a single probabilistic bit update process or a sampling window:

[0010] S1. The sampling calibration control module obtains the input control quantity corresponding to the CNTFET random device to be updated, generates the corresponding DAC control code based on the input control quantity, and controls the DAC pulse drive module to output the input pulse V. in The DAC pulse drive module will input pulse V in The reference pulse V is applied to the gate or control terminal of the CNTFET random device to be updated, and inserted into the input pulse sequence according to a preset insertion rule. ref ;CNTFET random devices at input pulse V in and reference pulse V ref Under its influence, the drain or readout end forms a corresponding sampling node response;

[0011] S2, In the input pulse V in After the action, the ADC sampling module samples the sampling node to obtain the input response sample D. in And input response sample D in Output to the sampling calibration control module;

[0012] S3, at the reference pulse V ref After the operation, the ADC sampling module samples the same sampling node to obtain the reference response sample D. ref and the reference response sample D refOutput to the sampling calibration control module;

[0013] S4, The reference update unit in the sampling calibration control module updates one or more reference response samples D ref Perform median filtering, moving average, exponential average, or low-pass filtering to generate a dynamic reference value D. REF and the dynamic reference value D REF Output to calibration compensation unit;

[0014] S5, The calibration compensation unit in the sampling calibration control module calculates the input response sample D. in With dynamic reference value D REF Generate the calibration compensation decision quantity ΔD, ΔD=D in -D REF The calibration compensation decision quantity ΔD is used to represent the input response sample D. in Relative to the current dynamic reference value D REF The direction and magnitude of the deviation;

[0015] S6. The comparison and decision module makes a decision on the calibration compensation decision amount ΔD. When ΔD is greater than the preset decision threshold θ, it outputs logic "1"; otherwise, it outputs logic "0" and uses this logic state as the p-bit state of the high robust CNTFET probability bit circuit based on sampling calibration compensation.

[0016] Furthermore, the preset decision threshold θ has a value of zero or a threshold set according to the circuit bias.

[0017] Furthermore, the step of inserting a reference pulse V into the input pulse sequence according to a preset insertion rule... ref The preset rule includes every input pulse V in Insert a reference pulse V ref Every multiple input pulses V in Insert a reference pulse V ref Alternatively, a reference pulse V can be inserted before or after a sampling window. ref .

[0018] Furthermore, the input pulse V in and reference pulse V ref Using the same or similar pulse width, edge conditions, and sampling delay, the input response sample D is made... in and reference response sample D ref Obtained under the same or similar pulse timing conditions.

[0019] Furthermore, in the input pulse V in and reference pulse V refIn the case of a negative pulse, the DAC pulse driving module inserts a positive recovery pulse V between adjacent negative pulses. rec The positive recovery pulse V rec The positive recovery pulse has the same pulse width but opposite polarity as the negative pulse and is used to release accumulated charge at the gate of the CNTFET random device and suppress drift caused by bias stress; the positive recovery pulse V rec Not participating in input response sample D in and reference response sample D ref Sampling.

[0020] Furthermore, when the robust CNTFET probabilistic bit circuit based on sampling calibration compensation is used in a probabilistic computer, multiple CNTFET random devices form a probabilistic bit array in a row-column configuration. Each CNTFET random device serves as a probabilistic bit random unit. The gate or control terminal of each CNTFET random device is connected to the DAC pulse drive module via row-column gating switches. The drain or readout terminal of each CNTFET random device is connected to the ADC sampling module via corresponding readout branches and row-column gating switches. The sampling calibration control module selects the CNTFET random device to be updated according to the update order of the probabilistic computer, provides the DAC control code and reference pulse insertion timing corresponding to the CNTFET random device to the DAC pulse drive module, and controls the ADC sampling module to acquire the input response sample D in the corresponding sampling window. in and reference response sample D ref Subsequently, the sampling calibration control module applies a dynamic reference value D to the CNTFET random device. REF The updated and calibrated compensation decision value ΔD is generated, and the corresponding p-bit state is output by the comparison decision module and provided to the probability computer for subsequent updates.

[0021] Compared with the prior art, the present invention has the following technical effects:

[0022] First, this invention no longer uses a comparator and a fixed reference voltage V. ref Instead of a direct decision-making method, a reference pulse V is inserted into the input pulse sequence. ref And the reference response sample D is acquired through the ADC sampling module. ref , so that the reference response sample D ref The first is a reference standard that reflects the response of the CNTFET random device and the ADC / DAC sampling link in the current operating state; the second is a sampling calibration control module based on the reference response sample D. ref Generate dynamic reference value D REF And based on the input response sample D in With dynamic reference value D REFA calibration-compensated decision value ΔD is generated, and the comparison decision module outputs the p-bit state based on the calibration-compensated decision value, thereby reducing the impact of slow drift of CNTFET random devices, low-frequency disturbances, and slow-changing errors in the ADC / DAC link on the output probability; third, median filtering, moving average, exponential averaging, or low-pass filtering can reduce the impact of abnormal reference response samples on the dynamic reference value D. REF The method can improve the stability of p-bit state decision-making by multiplexing ADC / DAC resources in a multi-p-bit array, which is beneficial to improving the cycle-to-cycle consistency and device-to-device consistency of the CNTFET probabilistic computer. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the module connection of a high-robust CNTFET probability bit circuit based on sampling calibration compensation in an embodiment of the present invention.

[0024] Figure 2 This is a flowchart illustrating the operation of a highly robust CNTFET probability bit circuit based on sampling calibration compensation in an embodiment of the present invention.

[0025] Figure 3 The input pulse V in this embodiment of the invention in Reference pulse V ref ADC sampling, dynamic reference value D REF Timing diagram of calibration compensation decision quantity ΔD and p-bit state output.

[0026] Figure 4 This is a verification diagram of the period-to-period consistency effect of the high-robust CNTFET probability bit circuit based on sampling calibration compensation in an embodiment of the present invention.

[0027] Figure 5 This diagram shows the device-to-device consistency performance verification of the high-robust CNTFET probability bit circuit based on sampling calibration compensation in an embodiment of the present invention. Detailed Implementation

[0028] The present invention will be further described below with reference to the accompanying drawings and embodiments. It should be noted that the following embodiments are only used to illustrate the technical concept and implementation of the present invention, and are not intended to limit the scope of protection of the present invention. Equivalent substitutions or combinations made by those skilled in the art, without departing from the concept of the present invention, regarding the specific structure of the CNTFET random access device, the bit width of the DAC pulse drive module and the ADC sampling module, the sampling frequency, the reference pulse insertion rule, the filtering method, the array size, and the control implementation, should all fall within the scope of protection of the present invention.

[0029] The core idea of ​​this invention is to change the decision process of the CNTFET probability bits from a one-time comparison under a fixed reference voltage to a decision process based on the input response sample D. in Reference response sample D ref Dynamic reference value D REF The sampling calibration compensation process is jointly completed by the calibration compensation decision quantity ΔD and the decision process for ΔD. Input pulse V in Used to drive CNTFET random devices to generate random responses related to input control quantities, with reference pulse V. ref This is used to obtain the reference response of the same CNTFET random device and its sampling link at the current moment. By updating the reference response and compensating for the input response, the impact of slow drift, zero-point offset, low-frequency disturbances, and slow-changing errors in the ADC / DAC link on the output probability can be reduced, thereby improving the period-to-period consistency and device-to-device consistency of the CNTFET probabilistic bit circuit.

[0030] This embodiment provides a highly robust CNTFET probability bit circuit based on sampling calibration compensation, such as... Figure 1 As shown, the circuit includes a CNTFET random device, a DAC pulse drive module, an ADC sampling module, a sampling calibration control module, and a comparison decision module. The gate or control terminal of the CNTFET random device is connected to the DAC pulse drive module, the source terminal is grounded or connected to a reference potential, and the drain or readout terminal forms a sampling node through a read resistor or a current-to-voltage conversion circuit. The input terminal of the ADC sampling module is connected to the sampling node to acquire the sampling node voltage, and the output terminal of the ADC sampling module is connected to the sampling calibration control module to output the input response sample D to the sampling calibration control module. in and reference response sample D ref The sampling calibration control module is connected to the DAC pulse drive module, the ADC sampling module, and the comparison decision module. The sampling calibration control module includes a pulse control unit, a reference update unit, and a calibration compensation unit. The pulse control unit is used to acquire the input control quantity corresponding to the CNTFET random device to be updated, generate a DAC control code based on the input control quantity, and control the DAC pulse drive module to insert a reference pulse V into the input pulse sequence according to a preset rule. ref The reference update unit is used to update the reference response sample D based on one or more reference response samples D. ref Generate dynamic reference value D REF The calibration compensation unit is used to adjust the input response sample D. in With dynamic reference value D REF Generate a calibration compensation decision value ΔD, where ΔD represents the input response sample D. in Relative to dynamic reference value D REFThe deviation amount; the comparison decision module is connected to the sampling calibration control module to make a decision on the calibration compensation decision amount ΔD. When ΔD is greater than the preset decision threshold θ, it outputs a logic "1" p-bit state, otherwise it outputs a logic "0" p-bit state, where θ is zero or a threshold set according to the circuit bias.

[0031] Furthermore, the ADC sampling module and DAC pulse drive module meet the requirements of low-noise sampling and low-error pulse output, so that the ADC sampling error, DAC output error and peripheral readout link noise are lower than the effective amplitude of the random fluctuation signal of the CNTFET random device, thereby avoiding the peripheral circuit error from masking the random response of the CNTFET random device.

[0032] The operation method of the high-robust CNTFET probabilistic bit circuit based on sampling calibration compensation in this invention can be completed within a single probabilistic bit update process or a sampling window, such as... Figure 2 As shown. The sampling calibration control module first obtains the input control quantity corresponding to the CNTFET random device to be updated, and converts the input control quantity into a DAC control code; the DAC pulse drive module applies an input pulse V to the gate or control terminal of the CNTFET random device according to the DAC control code. in Simultaneously, a reference pulse V is inserted into the input pulse sequence according to a preset insertion rule. ref ;CNTFET random devices at input pulse V in and reference pulse V ref Under the influence of the input pulse V, the ADC sampling module generates a corresponding sampling node response at its drain or readout end; in After the action, the voltage of the sampling node is acquired and the input response sample D is output. in In the reference pulse V ref After the action, the sampling node voltage is acquired and the reference response sample D is output. ref The reference update unit in the sampling calibration control module updates the data based on one or more reference response samples D. ref Generate dynamic reference value D REF and the dynamic reference value D REF The output is sent to the calibration and compensation unit; the calibration and compensation unit adjusts the input response sample D. in With dynamic reference value D REF Generate a calibration compensation decision value ΔD, which is used to represent the input response sample D. in Relative to the current dynamic reference value D REF The deviation direction and deviation magnitude are determined; the comparison and decision module makes a decision on the calibration compensation decision amount ΔD. When ΔD is greater than the preset decision threshold θ, it outputs logic "1"; otherwise, it outputs logic "0" and provides this p-bit state to the probability computer for the next update.

[0033] In one specific implementation, the reference pulse V ref It can be every other input pulse V in Insert once, or every multiple input pulses V in Insert once, or insert before and after a sampling window. The reference update unit can update one or more reference response samples D. ref Median filtering, moving average, exponential average, or low-pass filtering are applied to obtain the dynamic reference value D. REF When only one reference response sample D is used ref When updating, the dynamic reference value D REF It can be equal to the reference response sample D ref The calibration compensation unit calculates ΔD = D. in - D REF The comparison and decision module compares ΔD with a preset decision threshold θ; when ΔD > θ, it outputs logic "1", otherwise it outputs logic "0". Here, θ can be zero or a fixed threshold set according to the circuit bias. The above method involves sampling, calibrating, and compensating the input response based on a reference response before deciding the output p-bit state.

[0034] Figure 3 The input pulse V in this embodiment is shown. in Reference pulse V ref ADC sampling, dynamic reference value D REF The timing relationship between the calibration compensation decision quantity ΔD and the p-bit state output. Figure 3 In the diagram, the solid pulse output by the DAC pulse drive module represents the input pulse V. in Hollow pulses represent the inserted reference pulse V. ref The ADC sampling module receives the input pulse V. in The corresponding sampling time outputs D in In the reference pulse V ref The corresponding sampling time outputs D ref The sampling calibration control module obtains one or more D... ref Update D REF And in the input response sample D in Upon arrival, a corresponding ΔD is generated; the comparison and decision module compares ΔD with a preset decision threshold θ and outputs the p-bit state at the corresponding time. Reference pulse V ref The corresponding sampling results are used to update the dynamic reference value D. REF It does not directly generate p-bit state output; the p-bit state is generated by the input pulse V. in The corresponding calibration compensation decision value ΔD is generated after being decided by the comparison decision module. For example, in a specific waveform parameter, the reference pulse V... refSet to -4 V, input pulse V in The pulse width varies around -4 V and is 250 μs.

[0035] In the experimental implementation of this embodiment, the ADC sampling module and DAC pulse drive module were selected and designed with low noise and low error requirements in mind. Based on experimental tests and simulation results, the random fluctuations of CNTFET random devices are typically approximately 10% of the channel current. -3 Up to 10 -4 Therefore, the noise and error in the peripheral sampling and drive chain should be controlled within 10. -6 Below A; for a CNTFET in the on-state, this error level corresponds to approximately 10. -3 Voltage fluctuations of V or less. For example, the ADC sampling module uses a 24-bit low-noise Δ-Σ ADC ADS1255 with a high-precision ADR4525 reference source, the DAC pulse drive module uses a 16-bit DAC AD5660, the buffer uses an OPA387, and the power supply circuit uses a low-noise LDO. In supplementary experiments, the typical sampling noise of the ADS1255 at a 30 kSPS sampling rate is less than 10 μV; under 10 kSPS conditions, continuous sampling of a 1 V reference voltage shows fluctuations of less than ±110 μV; and the fluctuation of the AD5660 outputting a 1 V signal is less than ±15 μV. The noise and error of the above peripheral circuits are lower than the effective amplitude of the random fluctuation signal of the CNTFET random device, which can meet the input response sample D. in and reference response sample D ref Sampling requirements.

[0036] When the aforementioned robust CNTFET probabilistic bit circuit based on sampling calibration compensation is used in a probabilistic computer, multiple CNTFET random devices can be arranged in rows and columns to form a probabilistic bit array, where each CNTFET random device serves as a probabilistic bit random unit. The gate or control terminal of each CNTFET random device in the array is connected to the DAC pulse drive module via row and column selection switches. The drain or readout terminal of each CNTFET random device forms a sampling node via a corresponding readout resistor or current-to-voltage conversion circuit, and is connected to the ADC sampling module via row and column selection switches. The sampling calibration control module selects the CNTFET random device to be updated according to the update order of the probabilistic computer, outputs the DAC control code corresponding to that CNTFET random device to the DAC pulse drive module, and controls the input pulse V. in and reference pulse V ref The timing of the application; the ADC sampling module acquires the input response sample D of the CNTFET random device within the corresponding sampling window. in and reference response sample D refSubsequently, the reference update unit in the sampling calibration control module updates according to D. ref Generate dynamic reference value D REF The calibration compensation unit is based on D in With D REF A calibration compensation decision value ΔD is generated, and the comparison decision module outputs the corresponding p-bit state based on ΔD. Through the above row and column gating method, the DAC pulse drive module, ADC sampling module, sampling calibration control module, and comparison decision module can serve multiple CNTFET random devices, thereby reducing the number of array peripheral circuits and lowering the implementation complexity of the probabilistic computer.

[0037] The following tests demonstrate the stability of the aforementioned robust CNTFET probabilistic bit circuit based on sampling calibration compensation under long-term operation and multi-device working conditions. During testing, the circuit and operating method described in Example 1 were used, causing the CNTFET random device to operate under input pulse V. in and reference pulse V ref The sampling node response is generated under the action, and the ADC sampling module acquires the input response sample D respectively. in and reference response sample D ref The sampling calibration control module continuously updates the dynamic reference value D. REF It generates a calibration compensation decision value ΔD and compares the p-bit state output by the decision module. This is achieved by changing the input pulse V. in Alternatively, using the corresponding DAC control code, a probability response curve can be obtained showing the average probability of output logic "1" as a function of the input control quantity. In the prototype system, this probability response curve shows a good fit to the Sigmoid function, with a goodness of fit R0. 2 The accuracy rate of 99.97% indicates that the circuit can provide an adjustable random binary output suitable for probabilistic computers.

[0038] like Figure 4 As shown, cycle-to-cycle consistency verification is performed on the high-robust CNTFET probabilistic bit circuit based on sampling calibration compensation according to the present invention. During the test, in the initial state and after 10... 8 10 9 and 10 10 After each working cycle, the average probability of the output p-bit state as a function of the input pulse V is measured. in The probability response curves vary, and the differences between the probability response curves under different duty cycles are compared. Due to the reference pulse V... ref It can reflect the current reference state of CNTFET random devices and sampling links in real time during operation, and the reference update unit can update the dynamic reference value D accordingly. REF The calibration compensation unit can reduce the input response sample D inThe effects of slow drift, zero-point offset, and peripheral link errors in the process, therefore, after 10 10 After several operating cycles, the probability response curves still maintain good overlap. The results show that the maximum probability difference Δmax under different operating cycles is less than 6.14%, indicating that the present invention can improve the cycle-to-cycle consistency of the high-robust CNTFET probability bit circuit.

[0039] like Figure 5 As shown, device-to-device conformance verification is performed on multiple robust CNTFET probabilistic bit circuits based on sampling calibration compensation or multiple CNTFET random devices selected by multiplexed peripheral circuits. During the test, the same input pulse V is applied to 16 p-bit cells. in and reference pulse V ref The conditions were set, and the probability response curves were output separately. The results show that the maximum probability difference Δmax between multiple p-bit units is less than 8.49%, indicating that the present invention can reduce the impact of initial differences, slow drift and peripheral link errors between CNTFET random devices on the output probability distribution. Figure 4 and Figure 5 The circuit and its operating method are used to verify the effectiveness of period-to-period consistency and device-to-device consistency, respectively, demonstrating that the circuit and its operating method are suitable for CNTFET probabilistic computers that require long-term stable random binary flow.

Claims

1. A highly robust CNTFET probabilistic bit circuit based on sampling calibration compensation, characterized in that, The system includes a CNTFET random access device, a DAC pulse drive module, an ADC sampling module, a sampling calibration control module, and a comparison decision module. The gate or control terminal of the CNTFET random access device is connected to the DAC pulse drive module, its source terminal is grounded or connected to a reference potential, and its drain or readout terminal forms a sampling node via a read resistor or a current-to-voltage conversion circuit. The input terminal of the ADC sampling module is connected to the sampling node to acquire the sampling node voltage, and its output terminal is connected to the sampling calibration control module. The module operates on an input pulse V... in After the action, the output and input response samples D in and in reference pulse V ref Output reference response sample D after action ref The sampling calibration control module is connected to the DAC pulse drive module, the ADC sampling module, and the comparison decision module, respectively. The sampling calibration control module includes a pulse control unit, a reference update unit, and a calibration compensation unit. The pulse control unit is used to acquire the input control quantity corresponding to the CNTFET random device to be updated, generate a DAC control code based on the input control quantity, and control the DAC pulse drive module to insert a reference pulse V into the input pulse sequence according to a preset insertion rule. ref The DAC pulse drive module applies an input pulse V to the CNTFET random device according to the DAC control code. in and the inserted reference pulse V ref The reference update unit is used to update the reference response sample D based on one or more reference response samples D. ref Generate dynamic reference value D REF The calibration compensation unit is used to adjust the input response sample D. in With dynamic reference value D REF Generate a calibration compensation decision value ΔD, where ΔD represents the input response sample D. in Relative to dynamic reference value D REF The deviation amount; the comparison decision module is used to make a decision on the calibration compensation decision amount ΔD. When ΔD is greater than the preset decision threshold θ, it outputs a logic "1" p-bit state, otherwise it outputs a logic "0" p-bit state.

2. The circuit as described in claim 1, characterized in that, The ADC sampling module and DAC pulse drive module meet the requirements of low-noise sampling and low-error pulse output, so that the ADC sampling error, DAC output error and peripheral readout link noise are lower than the effective amplitude of the random fluctuation signal of the CNTFET random device.

3. The circuit as described in claim 1, characterized in that, When the robust CNTFET probabilistic bit circuit based on sampling calibration compensation is used in a probabilistic computer, multiple CNTFET random devices form a probabilistic bit array in a row-column configuration. Each CNTFET random device serves as a probabilistic bit random unit. The gate or control terminal of each CNTFET random device is connected to the DAC pulse drive module via row-column gating switches. The drain or readout terminal of each CNTFET random device is connected to the ADC sampling module via corresponding readout branches and row-column gating switches. The sampling calibration control module selects the CNTFET random device to be updated according to the update order of the probabilistic computer, provides the DAC control code and reference pulse insertion timing corresponding to the CNTFET random device to the DAC pulse drive module, and controls the ADC sampling module to acquire the input response sample D in the corresponding sampling window. in and reference response sample D ref Subsequently, the sampling calibration control module applies a dynamic reference value D to the CNTFET random device. REF The updated and calibrated compensation decision value ΔD is generated, and the corresponding p-bit state is output by the comparison decision module and provided to the probability computer for subsequent updates.

4. A method for operating a highly robust CNTFET probabilistic bit circuit based on sampling calibration compensation as described in claim 1, characterized in that, A single probability bit update process or a sampling window includes the following steps: S1. The sampling calibration control module obtains the input control quantity corresponding to the CNTFET random device to be updated, generates the corresponding DAC control code based on the input control quantity, and controls the DAC pulse drive module to output the input pulse V. in The DAC pulse drive module will input pulse V in The reference pulse V is applied to the gate or control terminal of the CNTFET random device to be updated, and inserted into the input pulse sequence according to a preset insertion rule. ref ;CNTFET random devices at input pulse V in and reference pulse V ref Under its influence, the drain or readout end forms a corresponding sampling node response; S2, at the input pulse V in After the action, the ADC sampling module samples the sampling node to obtain the input response sample D. in And input response sample D in Output to the sampling calibration control module; S3, at the reference pulse V ref After the operation, the ADC sampling module samples the same sampling node to obtain the reference response sample D. ref and the reference response sample D ref Output to the sampling calibration control module; S4, The reference update unit in the sampling calibration control module updates one or more reference response samples D ref Perform median filtering, moving average, exponential average, or low-pass filtering to generate a dynamic reference value D. REF and the dynamic reference value D REF Output to calibration compensation unit; S5, The calibration compensation unit in the sampling calibration control module calculates the input response sample D. in With dynamic reference value D REF Generate the calibration compensation decision quantity ΔD, ΔD=D in -D REF The calibration compensation decision quantity ΔD is used to represent the input response sample D. in Relative to the current dynamic reference value D REF The direction and magnitude of the deviation; S6. The comparison and decision module makes a decision on the calibration compensation decision amount ΔD. When ΔD is greater than the preset decision threshold θ, it outputs logic "1"; otherwise, it outputs logic "0" and uses this logic state as the p-bit state of the high robust CNTFET probability bit circuit based on sampling calibration compensation.

5. The method as described in claim 4, characterized in that, The preset decision threshold θ has a value of zero or a threshold set according to the circuit bias.

6. The method as described in claim 4, characterized in that, The reference pulse V is inserted into the input pulse sequence according to a preset insertion rule. ref The preset rule includes every input pulse V in Insert a reference pulse V ref Every multiple input pulses V in Insert a reference pulse V ref Alternatively, a reference pulse V can be inserted before or after a sampling window. ref .

7. The method as described in claim 4, characterized in that, The input pulse V in and reference pulse V ref Using the same or similar pulse width, edge conditions, and sampling delay, the input response sample D is made... in and reference response sample D ref Obtained under the same or similar pulse timing conditions.

8. The method as described in claim 4, characterized in that, In the input pulse V in and reference pulse V ref In the case of a negative pulse, the DAC pulse driving module inserts a positive recovery pulse V between adjacent negative pulses. rec The positive recovery pulse V rec The positive recovery pulse has the same pulse width but opposite polarity as the negative pulse and is used to release accumulated charge at the gate of the CNTFET random device and suppress drift caused by bias stress; the positive recovery pulse V rec Not participating in input response sample D in and reference response sample D ref Sampling.

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