A burner and a control method thereof

Abstract

The application discloses a burner and a control method thereof. The burner comprises a main control module, an interface module, a power supply control circuit and a bus isolation and monitoring circuit. The main control module is internally provided with a timer and a GPIO. The power supply control circuit comprises a controllable electronic switch. The bus isolation and monitoring circuit is used for sampling a Flash bus level state and feeding back to the main control module. The main control module is triggered by power-on of a target finished board, acquires bus level state feedback through the timer and the GPIO interruption, and calculates an idle time window between power-on completion of the target finished board and first initiation of Flash access of the main control module according to the level state and a preset MCU starting time sequence model. Then, the burner initiates a burning operation on the target Flash in the idle time window. Thus, through real-time monitoring of the bus level and dynamic calculation of the idle window, bus competition with the MCU module is effectively avoided, and the compatibility and safety of the burning process are improved.

Description

Technical Field

[0001] This invention relates to the field of embedded systems, and in particular to a programmer and its control method. Background Technology

[0002] NOR Flash, due to its ability to support Execute-in-Place (XIP), is widely used for firmware storage in various embedded devices. During product development and verification, mass production programming, and after-sales maintenance, it is typically necessary to write firmware or update data on external NOR Flash chips. Existing programming methods mainly fall into two categories: one is offline programming using a dedicated programming socket or jig before the Flash chip is soldered; the other is online programming using an external programmer after the chip has been soldered, through pre-reserved test points or a dedicated programming interface on the target finished product board.

[0003] However, existing technologies have significant drawbacks when performing in-circuit programming on NOR Flash chips already soldered onto finished boards. After the finished board powers on, its main control MCU (Microcontroller Unit) initializes within a very short time and actively initiates chip select and read / write operations on the Flash via buses such as SPI / QSPI to load boot code or execute applications. If an external programmer simultaneously attempts to access the Flash via the same bus, a bus contention will occur with the main control MCU, leading to programming failure, data corruption, or even Flash logic lockup. To circumvent this problem, existing solutions often employ fixed delays or forced resets of the main control MCU. However, the former is difficult to adapt to the different boot speeds of different control chips, while the latter may trigger a watchdog timer reset or cause the board to enter an abnormal state, resulting in insufficient reliability.

[0004] Therefore, there is an urgent need for a NOR Flash in-circuit programming device and method that can effectively avoid interference from the main control MCU occupying the bus. Summary of the Invention

[0005] This invention provides a programmer and its control method to solve the technical problem of programmers competing with bus MCUs for the Flash bus in the prior art.

[0006] In a first aspect, embodiments of the present invention provide a programmer, comprising: The main control module includes timers and GPIO; The interface module connects to the main control module; The power control circuit, connected to the main control module, includes a controllable electronic switch, which is used to manage the timing of power supply to the target finished board. The bus isolation and monitoring circuit is connected to the main control module and is used to sample the Flash bus level status and feed it back to the main control module. The main control module is configured as follows: In response to the power control circuit triggering the power-on of the target finished board, the Flash bus level status fed back by the bus isolation and monitoring circuit is obtained through timer and GPIO interrupt; The idle time window is calculated based on the Flash bus level state and the preset MCU startup timing model. The idle time window is the time period between the moment the target finished product board is powered on and the moment the main control module first initiates Flash access. During the idle time window, a programming operation is initiated to the target Flash, which is the NOR Flash chip on the target finished board.

[0007] Secondly, embodiments of the present invention provide a method for controlling a programmer, including: In response to the power control circuit triggering the power-on of the target finished board, the Flash bus level status fed back by the bus isolation and monitoring circuit is obtained through timer and GPIO interrupt; The idle time window is calculated based on the Flash bus level state and the preset MCU startup timing model. The idle time window is the time period between the moment the target finished product board is powered on and the moment the main control module first initiates Flash access. During the idle time window, a programming operation is initiated to the target Flash, which is the NOR Flash chip on the target finished board.

[0008] The technical solution of this invention incorporates a main control module, an interface module, a power control circuit, and a bus isolation and monitoring circuit within the programmer. The main control module includes a built-in timer and GPIO, the power control circuit includes a controllable electronic switch to manage the power supply timing of the target finished board, and the bus isolation and monitoring circuit samples the Flash bus level and feeds it back to the main control module. The programming control method is as follows: In response to the power-on trigger of the target finished board, the main control module obtains the bus level feedback through timers and GPIO interrupts. Based on this level and a preset MCU startup timing model, it calculates the idle time window from the completion of the target finished board's power-on to the main control module's first Flash access. Then, within this idle time window, it initiates a programming operation on the target Flash. Therefore, by monitoring the bus level in real time and dynamically calculating the idle window, bus contention with the MCU module is effectively avoided, improving the compatibility and security of the programming process. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of the programmer provided in an embodiment of the present invention; Figure 2 This is a flowchart of the control method for the programmer provided in an embodiment of the present invention; Figure 3 This is a hardware architecture diagram of the electronic device provided in an embodiment of the present invention; Figure 4 This is a structural diagram of the control device for the programmer provided in an embodiment of the present invention; Figure 5 This is a timing diagram for idle time window detection and programming provided in an embodiment of the present invention. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0012] Figure 1 This is a schematic diagram of the programmer provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the programmer includes a main control module 11, an interface module 12, a power control circuit 13, a bus isolation and monitoring circuit 14, and a human-machine interaction module 15.

[0013] The main control module 11 is the core control module of the programmer, including timers and GPIO, and is specifically used for programming firmware. In this embodiment of the invention, the main control module 11 controls the Flash programming timing through peripherals, and uses timers and interrupt modules to manage timeout protection and event response at each operation stage. By monitoring the bus level in real time and dynamically calculating the idle window, bus contention and driver conflicts are avoided, thus improving the compatibility and security of the programming process.

[0014] The interface module 12 is used to establish an electrical connection between the programmer and the target finished board. In this embodiment of the invention, the interface module includes a spring pin connector array.

[0015] The power control circuit 13 is used to independently and programmably manage the power-on and power-off timing of the target finished board. It includes a controllable electronic switch, which is controlled by the main control module through GPIO to turn on and off the power supply rail of the Flash chip. It supports software configuration of the power-on slope and initial delay time to adapt to different requirements and suppress the current surge and bus level conflict at the moment of power-on.

[0016] The bus isolation and monitoring circuit 14 is used to achieve electrical isolation and bus status awareness between the programmer and the target Flash, including a bidirectional level conversion chip and a high-impedance state monitoring unit. The high-impedance state monitoring unit samples the electrical state of the Flash bus in real time and feeds the sampled signal back to the main control module. The bidirectional level conversion chip performs level matching between the programmer bus and the target Flash bus, and switches the programmer bus to a high-impedance state under the control of the main control module.

[0017] The human-machine interface module 15 is connected to the main control module 11 and includes a display screen and an independent physical button group. The display screen is used to display at least one of the following: burning mode, progress, status code, and Flash parameters. The independent physical button group includes at least one of the following: reset button, USB flash drive mode button, detection button, read-back button, and write button. It is used to receive button commands from the operator and trigger the corresponding burning process. Specifically, the reset button is used to reset the main control module and clear abnormal states; the USB flash drive mode button is used to switch to the USB Mass Storage protocol, enabling the host to recognize it as a removable disk for file drag-and-drop transfer; the detection button is used to send JEDEC commands to read the Flash identification and capacity parameters; the read-back button is used to completely read the Flash content in address order and supports data export; and the write button is used to trigger a complete burning process including erasure, programming, and real-time verification.

[0018] In this embodiment of the invention, the main control module is configured to control the programmer. Figure 2 This is a flowchart of the control method for the programmer provided in an embodiment of the present invention, such as... Figure 2 As shown, it includes the following steps: Step 100: In response to the power control circuit triggering the power-on of the target finished board, the Flash bus level status fed back by the bus isolation and monitoring circuit is obtained through the timer and GPIO interrupt.

[0019] Step 200: Calculate the idle time window based on the Flash bus level state and the preset MCU startup timing model. The idle time window is the time period between the moment the target finished product board is powered on and the moment the main control module first initiates Flash access.

[0020] Step 300: During the idle time window, initiate a programming operation to the target Flash, which is the NOR Flash chip on the target finished board.

[0021] The following is a detailed explanation of each step. Regarding step 100, firstly, the main control module controls the power control circuit to trigger the power-on of the target finished board. After the power-on is triggered, the main control module obtains the Flash bus level status fed back by the bus isolation and monitoring circuit through the timer and GPIO interrupt.

[0022] Specifically, the main control module starts a timer and configures the corresponding GPIO pins to interrupt input mode. The timer is used to accurately measure the accumulated time since power-on, and the GPIO interrupt is used to capture the edge transition events of the bus level in real time. Since the main control MCU of the target finished board will actively pull low the Flash chip select CS or trigger the clock CLK signal after initialization, the high-impedance state monitoring unit in the bus isolation and monitoring circuit 14 samples the level states of bus nodes such as CS, CLK, and IO0~IO3 in real time through a bidirectional level conversion chip. When the main control module 11 detects a transition of the bus level from a high-impedance state or a stable idle state via the GPIO interrupt, it can determine that the main control MCU has started to preempt the bus. If the bus remains idle within the preset timer period, it is determined that it is currently within the usable safe window. Through the real-time sampling mechanism, the main control module 11 can dynamically identify the time node when the main control MCU of the target finished board first initiates Flash access after power-on, thereby providing electrical state basis for avoiding bus preemption conflicts in subsequent steps.

[0023] In one optional implementation, the main control module is further configured to: during the power-on phase of the target finished board, configure the initial conduction delay time and conduction slope of the controllable electronic switch so that the voltage of the target finished board slowly rises to the operating voltage at a set ramp rate.

[0024] Specifically, the main control module is connected to the control terminal of the controllable electronic switch in the power control circuit 13 via GPIO. When the target finished board is powered on, the main control module 11 does not immediately turn on the controllable electronic switch completely. Instead, according to the preset software configuration parameters, it controls the gate drive voltage of the controllable electronic switch by outputting a pulse width modulation (PWM) signal or an analog voltage ramp signal, thereby adjusting the conduction process of the controllable electronic switch.

[0025] The initial conduction delay time refers to the waiting time from when the main control module 11 receives the power-on trigger signal to when the controllable electronic switch begins to conduct. This delay time can be configured with millisecond precision via firmware. Its purpose is to ensure that all modules inside the programmer are fully stable and ready during the power-on phase before outputting power to the target board. The conduction slope refers to the rate of change of the output voltage over time during the transition from complete off to complete on of the controllable electronic switch. This can be achieved by controlling the rise time of the PWM signal's duty cycle as it gradually increases from 0% to 100%.

[0026] With the above configuration, the main control module can achieve soft-start power supply for the target finished board. Compared with the solution of directly applying a momentary full voltage to the target board by the programmer, the embodiment of the present invention effectively suppresses the surge current at the moment of power-on by controlling the slow voltage rise, avoiding damage to sensitive devices on the target board caused by large current impact, while reducing ground bounce noise on the power rail and improving the electrical quality of bus signals during programming.

[0027] Regarding step 200, after monitoring the Flash bus level, an idle time window suitable for safe operation of the programmer is calculated by combining the preset MCU startup timing model within the main control module. The preset MCU startup timing model is a set of startup parameters pre-calibrated for different target board models' main control MCUs. This parameter set includes power-on reset time, internal clock stabilization time, bootloader initialization time, and the time offset for the first Flash chip select CS pull-low or clock CLK trigger after jumping from the bootloader to the application program. The MCU startup timing model is stored in the internal memory or external memory chip of the main control module 11.

[0028] The specific operational logic is as follows: At the instant T0 when the power control circuit 13 turns on the target finished board, the main control module 11 starts the timer. Simultaneously, it continuously samples the level states of CS, CLK, and IO0~IO3 bus nodes through the bus isolation and monitoring circuit 14. If, during the timing process, a GPIO interrupt detects that CS changes from a high impedance state or a high level to a low level, or that CLK experiences its first transition edge, it is determined that the main control MCU has initiated its first Flash access, and this moment is recorded as T1. If no bus activity is detected within the preset timeout threshold, it is determined that the bus is in a long-term idle state. In this case, the main control module 11 uses the timeout threshold as the reference value for T1. Subsequently, the main control module compares and dynamically calibrates T1 with the first access reference time Tr of the corresponding main control model in the preset MCU startup timing model, and comprehensively determines the safe window start time T of this power-on cycle. start The idle time window is obtained by calculating the difference between the target board power-on stable time and the termination time Tend (i.e., the time t1 when the bus is first detected to be preempted).

[0029] This idle time window represents the available time period from when the target finished product board powers on and the Flash power supply stabilizes, to when the finished product board's main control MCU first initiates access to the Flash bus. The programmer must complete the unlocking, erasing, and writing operations on the Flash within ΔT, or at least seize bus control and place the bus under the programmer's control within ΔT. Due to its dynamic calculation characteristics, the idle time window obtained through this method is applicable to different main control MCU platforms and different startup configurations, making it more targeted. Compared to the fixed-delay scheme used in existing technologies, it significantly improves the compatibility and success rate of online programming of finished products.

[0030] In one optional implementation, the main control module 11 is also used to perform statistical analysis on the T1 value detected each time and Tr in the timing model, and dynamically correct the timing model parameters of subsequent power-on cycles, so as to achieve adaptive learning and optimization for the same type of target finished board.

[0031] Regarding step 300, after calculating the idle time window in step 200, a programming operation is initiated to the target Flash within the idle time window, wherein the target Flash is the NOR Flash chip on the target finished board.

[0032] In one alternative implementation, initiating a programming operation to the target Flash memory includes: initiating a programming operation to the target Flash memory via a spring pin connector array through a bus isolation and monitoring circuit.

[0033] During the idle time window, the main control module 11 initiates a programming operation to the target NOR Flash chip via the SPI / QSPI bus. It should be understood that NOR Flash, as a code-based flash memory chip, has the characteristic of supporting Execute-in-Place (XIP). Its read operation is similar to that of RAM, but the write operation cannot be performed directly. Instead, it needs to follow a specific command sequence specified by the chip manufacturer, and the erase and programming operations are completed by the control unit inside the chip.

[0034] Specifically, the main control module 11 sends a write enable instruction to the target NOR Flash according to the JEDEC standard command set to put the chip into a programmable state. Then, it performs an erase operation according to the programming strategy. The erase granularity depends on the Flash model and typically supports sector erase, block erase, or full-chip erase. The main control module 11 selects the smallest granularity erase operation by querying the Flash chip parameters, reducing programming time and minimizing the impact on adjacent memory areas.

[0035] After erasure, the main control module 11 performs page-by-page write operations within the idle time window. NOR Flash writing is typically done in pages. The main control module 11 sequentially sends page programming instructions, the target address, and the data to be written via the SPI / QSPI peripheral, dividing the firmware file into pages and writing them to the Flash one page at a time. During the writing process, the main control module 11 continuously monitors the bus level using the bus isolation and monitoring circuit 14. Once a bus preemption is detected by the finished board's main control MCU via a GPIO interrupt (e.g., CS being pulled low or CLK experiencing an abnormal transition), the main control module 11 immediately pauses the current programming operation, repositions the bus to a high-impedance isolation state, waits for the bus to become idle, regains control, and continues programming, thus avoiding bus conflicts with the main control MCU. If the entire programming process is successfully completed within the idle time window, the main control module 11 writes a programming completion flag to the target Flash, releases the bus back to a high-impedance state, returns bus control to the target finished board's main control MCU, and then triggers the power control circuit 13 to power down the target board according to a preset timing sequence.

[0036] In one optional implementation, the main control module is further configured to: after completing the writing of a data block, send a readback command to the target Flash via a bus isolation and monitoring circuit to read the written data; compare the written data with the source data byte by byte; if the comparison matches, continue writing the next data block; if the comparison does not match, trigger a local retry mechanism to re-execute the erase and write operation at the current position until the comparison matches or the number of triggers reaches a preset threshold. Specifically, step 300 adopts a real-time verification mechanism of writing and verifying simultaneously: after each data block (Page or Block) is written, the main control module 11 immediately initiates a readback command to read the data just written from the Flash and compare it byte by byte with the source data; if the verification passes, continue burning the next area; if the verification fails, trigger a local retry (default 3 times); if the retry threshold is exceeded, mark the area as a bad block and record the address, and finally generate a verification report for subsequent traceability. This real-time verification mechanism can detect and locate write anomalies in real time during the burning process, significantly shortening the error detection time and avoiding the problem of having to erase the entire chip and re-burn it due to partial write failure.

[0037] In an optional implementation, the main control module is further configured to: upon receiving a write instruction, send a JEDEC standard instruction to the target Flash via a bus isolation and monitoring circuit to read the target Flash's vendor ID, device ID, unique identifier, and physical capacity parameters before writing data to the target Flash; compare the size of the firmware file to be written with the physical capacity of the target Flash; if the physical capacity is greater than or equal to the firmware file size, unlock the write permission; if the physical capacity is less than the firmware file size, refuse to perform the write operation.

[0038] Specifically, after receiving a write command triggered by the write button on the human-machine interface module 15, the main control module 11 does not immediately perform Flash erasure and programming operations. Instead, it first enters the pre-write inspection stage. In this stage, the main control module 11 sends a sequence of instructions conforming to the JEDEC standard to the target Flash chip through the bidirectional level conversion chip in the bus isolation and monitoring circuit 14. This sequence of instructions specifically includes 0x9F (for reading the vendor ID and device ID), 0x4B (for reading the unique identification code), and 0x5A or 0x9F extended instructions (for reading the physical capacity parameters) to obtain the vendor ID, device ID, unique identification code, and physical capacity parameters of the target Flash. Among them, the vendor ID and device ID are used to confirm the chip model and manufacturer, the unique identification code is used to provide chip-level individual identification for traceability and anti-counterfeiting verification, and the physical capacity parameters identify the total number of storage bytes of the chip.

[0039] After obtaining the above parameters, the main control module 11 calls the firmware file management system stored in the main control module's internal memory to query the byte size of the firmware file to be written and compares the file size with the target Flash physical capacity. If the physical capacity is determined to be greater than or equal to the firmware file size, sufficient storage space is confirmed, write permission is unlocked, and subsequent erasure and programming processes are allowed. The comparison result can also be displayed on the screen as a capacity verification passed, and the percentage of the current firmware's occupied capacity to the total Flash capacity can be displayed. If the physical capacity is determined to be less than the firmware file size, the write operation is deemed to have the risk of address overflow and data truncation, and the write operation is immediately rejected. At the same time, the corresponding error code and prompt information are generated and displayed on the screen, such as "Error code E005: Firmware size exceeds Flash capacity", and the write permission remains locked.

[0040] By implementing the above settings, serious dangerous behaviors such as address overflow, data truncation, or overwriting of adjacent storage areas caused by firmware files exceeding the physical capacity of the Flash memory are prevented. Simultaneously, by leveraging the ability to read the manufacturer ID, device ID, and unique identification code, the programmer can verify whether the target Flash model matches the expected specifications before writing, improving the error prevention capabilities and traceability of mass production lines.

[0041] In one alternative implementation, the main control module is configured to simulate a large-capacity storage device via a USB OTG controller, thereby achieving an offline USB flash drive mode and a full-link file management architecture.

[0042] Specifically, the ESP32-S3 microcontroller's built-in USB OTG controller simulates a standard USB mass storage device in device mode, virtualizing a designated partition of an external SD NAND chip or internal SPI Flash as a removable disk using the FAT32 file system format. When the user presses the USB flash drive mode button, the programmer is recognized as a standard USB flash drive when connected to the PC via the USB Type-C interface. Users can directly drag and drop firmware files to the virtual disk or copy data read from the programmer to the PC without installing any drivers or dedicated software. The main control module's internal file system management module handles virtual disk mounting, file enumeration, and read / write operations, while the programming engine module handles low-level timing control such as Flash erasure, programming, and verification. The two modules interact via a message queue, enabling data exchange from file import, capacity comparison, programming, to result export.

[0043] In some embodiments, the main control module is further configured to switch the programmer bus to a high-impedance state via a bus isolation and monitoring circuit after the idle time window closes. This physically disconnects the programmer's control over the bus, ensuring that when the main control module subsequently initiates normal Flash access, there are no residual voltage levels or signal interference from the programmer on the bus, thus guaranteeing the safe and reliable normal read and write operations of the main control module on the Flash.

[0044] The embodiments of the present invention, through the above-described method, eliminate the dependence on host computer software, lower the operating threshold, and are suitable for scenarios such as batch production line operations, maintenance in offline environments, and data traceability and backup.

[0045] Through steps 100-300, this embodiment of the invention enables the power control circuit to actively trigger the programming operation of the NOR Flash chip during the initial power-on period of the target finished board and within the idle window before the main control module accesses the Flash. This avoids the risk of bus conflicts and improves the compatibility and security of the programming process without interfering with the normal startup process of the main control module, without relying on an external programmer, and without requiring hardware modifications.

[0046] Figure 5 This is a timing diagram for idle time window detection and programming provided in an embodiment of the present invention. For example... Figure 5 As shown, it includes the following stages: T0-T1: During the power-on phase, the programmer supplies power to the finished board through the power control circuit. VCC slowly rises through the RC network to suppress power-on surges and ground bounce noise.

[0047] T1-T3: Initialization phase. The main control MCU completes the reset release and bootloader initialization. Internal peripherals begin configuration, but have not yet accessed the external Flash. At this time, the Flash bus is in a high impedance state.

[0048] T3-T4: During the detection phase, the programmer's main control module samples the Flash bus level at regular intervals via GPIO.

[0049] T4-T5: The programmer pulls down the chip select CS, performs JEDEC parameter reading, write enable, sector erase, and page writing, and adopts a write-while-verify mechanism for real-time readback and comparison.

[0050] T5: The MCU initiates Flash access for the first time. The programmer must complete the programming and release the bus before this moment, or immediately stop if the MCU action is detected to avoid bus conflict.

[0051] T5-T6: The system enters normal operation and the MCU takes over the Flash bus.

[0052] like Figure 3 , Figure 4 As shown, this embodiment of the invention provides a control device for a programmer. The device embodiment can be implemented through software, hardware, or a combination of both. From a hardware perspective, as... Figure 3 The diagram shown is a hardware architecture diagram of an electronic device containing a programmer control device according to an embodiment of the present invention. (Except for...) Figure 3 In addition to the processor, memory, network interface, and non-volatile memory shown, the electronic device in the embodiment may also include other hardware, such as a forwarding chip responsible for processing packets. Taking software implementation as an example, such as... Figure 4 As shown, a device in a logical sense is formed by the CPU of the electronic device in which it is located reading the corresponding computer program from the non-volatile memory into the memory for execution.

[0053] This embodiment provides a control device for a programmer, comprising: The level state determination unit is used to respond to the power control circuit triggering the power-on of the target finished board and obtain the Flash bus level state fed back by the bus isolation and monitoring circuit through timer and GPIO interrupt; The idle time window determination unit is used to calculate the idle time window based on the Flash bus level state and the preset MCU startup timing model. The idle time window is the time period between the time when the target finished product board is powered on and the time when the main control module first initiates Flash access. The programming unit is used to initiate programming operations to the target Flash during the idle time window. The target Flash is the NOR Flash chip on the target finished board.

[0054] In some embodiments, the device is further configured to: After the idle time window is closed, the programmer bus is switched to a high impedance state through the bus isolation and monitoring circuit.

[0055] In some embodiments, the device is further configured to: During the power-on phase of the target finished board, the initial delay time and conduction slope of the controllable electronic switch are configured so that the voltage of the target finished board slowly rises to the operating voltage at a set ramp rate.

[0056] In some embodiments, the device is further configured to: After writing a data block, a readback command is sent to the target Flash to read the written data through the bus isolation and monitoring circuit. The written data is compared byte by byte with the source data. If the comparison matches, the writing of the next data block continues. If the comparison does not match, a local retry mechanism is triggered to re-execute the erase and write operation at the current position until the comparison matches or the number of triggers reaches a preset threshold.

[0057] In some embodiments, the device is further configured to: Upon receiving the write command, before writing data to the target Flash, the JEDEC standard command is sent to the target Flash via the bus isolation and monitoring circuit to read the target Flash's vendor ID, device ID, unique identifier, and physical capacity parameters. The size of the firmware file to be written is compared with the physical capacity of the target Flash. If the physical capacity is greater than or equal to the size of the firmware file, the write permission is unlocked; if the physical capacity is less than the size of the firmware file, the write operation is rejected.

[0058] It is understood that the structures illustrated in the embodiments of the present invention do not constitute a specific limitation on the control device of a programmer. In other embodiments of the present invention, a control device for a programmer may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0059] The information interaction and execution process between the modules in the above-mentioned device are based on the same concept as the method embodiment of the present invention, and the specific details can be found in the description of the method embodiment of the present invention, and will not be repeated here.

[0060] This invention also provides an electronic device, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements a microcontroller-based chip testing method according to any embodiment of this invention.

[0061] This invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform a microcontroller-based chip testing method according to any embodiment of this invention.

[0062] Specifically, a system or apparatus equipped with a storage medium may be provided, on which software program code implementing the functions of any of the embodiments described above is stored, and the computer (or CPU or MPU) of the system or apparatus may read and execute the program code stored in the storage medium.

[0063] In this case, the program code read from the storage medium can itself implement the function of any of the above embodiments, and therefore the program code and the storage medium storing the program code constitute part of the present invention.

[0064] Storage media embodiments for providing program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, program code can be downloaded from a server computer via a communication network.

[0065] Furthermore, it should be clear that not only can the program code read by the computer be executed, but also the operating system or other components operating on the computer can be instructed based on the program code to perform some or all of the actual operations, thereby realizing the function of any of the embodiments described above.

[0066] Furthermore, it is understood that the program code read from the storage medium is written to the memory set in the expansion board inserted into the computer or to the memory set in the expansion module connected to the computer. Then, based on the instructions of the program code, the CPU or other components installed on the expansion board or expansion module execute some and all of the actual operations, thereby realizing the function of any of the above embodiments.

[0067] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or electronic device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or electronic device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or electronic device that includes said element.

[0068] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various storage media that can store program code, such as ROM, RAM, magnetic disk, or optical disk.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A programmer, characterized in that, include: The main control module includes timers and GPIO; The interface module connects to the main control module; The power control circuit, connected to the main control module, includes a controllable electronic switch, which is used to manage the timing of power supply to the target finished board. The bus isolation and monitoring circuit is connected to the main control module and is used to sample the Flash bus level status and feed it back to the main control module. The main control module is configured as follows: In response to the power control circuit triggering the power-on of the target finished board, the Flash bus level status fed back by the bus isolation and monitoring circuit is obtained through timer and GPIO interrupt; The idle time window is calculated based on the Flash bus level state and the preset MCU startup timing model. The idle time window is the time period between the moment the target finished product board is powered on and the moment the main control module first initiates Flash access. During the idle time window, a programming operation is initiated to the target Flash, which is the NOR Flash chip on the target finished board.

2. The programmer according to claim 1, characterized in that, The main control module is also configured as follows: After the idle time window is closed, the programmer bus is switched to a high impedance state through the bus isolation and monitoring circuit.

3. The programmer according to claim 1 or 2, characterized in that, The bus isolation and monitoring circuit includes a bidirectional level shifting chip and a high-impedance state monitoring unit; The high-impedance monitoring unit is used to sample the electrical state of the Flash bus in real time and feed the sampled signal back to the main control module; The bidirectional level conversion chip is used to perform level matching between the programmer bus and the target Flash bus, and to switch the programmer bus to a high impedance state under the control of the main control module.

4. The programmer according to claim 1, characterized in that, Also includes: The human-computer interaction module is connected to the main control module and includes a display screen and an independent physical button group. The display screen is used to display at least one of the following: burning mode, progress, status code, and Flash parameters. The independent physical button group includes at least one of the following: reset button, USB flash drive mode button, detection button, read-back button, and write button.

5. The programmer according to claim 1, characterized in that, The interface module includes an array of spring pin connectors; Initiating a programming operation to the target Flash memory includes: The programming operation is initiated to the target Flash memory via a spring pin connector array through a bus isolation and monitoring circuit.

6. The programmer according to claim 1, characterized in that, The main control module is also configured as follows: During the power-on phase of the target finished board, the initial delay time and conduction slope of the controllable electronic switch are configured so that the voltage of the target finished board slowly rises to the operating voltage at a set ramp rate.

7. The programmer according to claim 6, characterized in that, The power control circuit also includes a high-impedance sustaining network connected between the controllable electronic switch and the spring pin connector array to suppress voltage spikes and noise during the power-on phase.

8. The programmer according to claim 1, characterized in that, The main control module is also configured to: After writing a data block, a readback command is sent to the target Flash to read the written data through the bus isolation and monitoring circuit. The written data is compared byte by byte with the source data. If the comparison matches, the writing of the next data block continues. If the comparison does not match, a local retry mechanism is triggered to re-execute the erase and write operation at the current position until the comparison matches or the number of triggers reaches a preset threshold.

9. The programmer according to claim 1, characterized in that, The main control module is also configured to: Upon receiving the write command, before writing data to the target Flash, the JEDEC standard command is sent to the target Flash via the bus isolation and monitoring circuit to read the target Flash's vendor ID, device ID, unique identifier, and physical capacity parameters. The size of the firmware file to be written is compared with the physical capacity of the target Flash. If the physical capacity is greater than or equal to the size of the firmware file, the write permission is unlocked; if the physical capacity is less than the size of the firmware file, the write operation is rejected.

10. A control method for a programmer, applied to the main control module of a programmer, characterized in that, include: In response to the power control circuit triggering the power-on of the target finished board, the Flash bus level status fed back by the bus isolation and monitoring circuit is obtained through timer and GPIO interrupt; The idle time window is calculated based on the Flash bus level state and the preset MCU startup timing model. The idle time window is the time period between the moment the target finished product board is powered on and the moment the main control module first initiates Flash access. During the idle time window, a programming operation is initiated to the target Flash, which is the NOR Flash chip on the target finished board.

Images