Processor, zero-knowledge proof system, proof state generation method and system on chip

Abstract

The application discloses a processor, a zero-knowledge proof system, a proof state generation method and a system on chip. The processor comprises: an instruction pipeline circuit, configured to execute instructions and obtain a to-be-retired instruction; a global instruction identifier circuit, connected with or integrated in the instruction pipeline circuit, configured to generate a unique and monotonically increasing global instruction identifier corresponding to the to-be-retired instruction when the to-be-retired instruction completes retirement; and an instruction state maintenance circuit, connected with the instruction pipeline circuit, configured to maintain data conversion records and identifier conversion records of the to-be-retired instruction; wherein the global instruction identifier, the data conversion records and the identifier conversion records are used to construct a proof track record. The execution witness data provided for the back-end proof is reliable, ordered and semantically consistent through the global instruction identifier, the data conversion records and the identifier conversion records.

Description

Technical Field

[0001] This application relates to the field of proof technology, and in particular to a processor, a zero-knowledge proof system, a proof state generation method, and a system-on-a-chip. Background Technology

[0002] The proof process is usually divided into two consecutive stages: trajectory generation and proof generation. The former is responsible for capturing the deterministic state of program execution, while the latter completes cryptographic verification based on the former. Therefore, the execution basis output by the trajectory generation stage must strictly meet the requirements of verifiability and timing consistency.

[0003] However, current trajectory generation schemes generally suffer from the defect of missing time-series anchor points, making it difficult to satisfy the consistency proof in the backend. For example, failure to maintain register state changes and their corresponding timestamps, and / or failure to maintain memory state changes and their corresponding timestamps, will lead to backend proof failure due to the lack of traceable time-series evidence. Summary of the Invention

[0004] To address the aforementioned issues, this application proposes a processor, a zero-knowledge proof system, a proof state generation method, and an on-chip system, which provide reliable, ordered, and semantically consistent execution witness data for backend proofs through global instruction identifiers, data conversion records, and identifier conversion records.

[0005] In a first aspect, this application provides a processor, comprising: an instruction pipeline circuit for executing instructions and obtaining instructions to be retired; a global instruction identifier circuit connected to or integrated into the instruction pipeline circuit for generating a unique and monotonically increasing global instruction identifier corresponding to the instructions to be retired when the instructions to be retired are completed; and an instruction state maintenance circuit connected to the instruction pipeline circuit for maintaining a data conversion record and an identifier conversion record of the instructions to be retired; wherein the global instruction identifier, the data conversion record, and the identifier conversion record are used to construct a proof trajectory record.

[0006] In some embodiments, the instruction pipeline circuit includes a retirement control circuit, configured to cause the instruction to retire to complete retirement when the instruction to retire meets preset retirement conditions.

[0007] In some embodiments, the global instruction identifier circuit is connected to the retirement control circuit through the instruction pipeline circuit, and the global instruction identifier circuit is used to generate the global instruction identifier when the retirement control circuit causes the instruction to be retired to complete retirement.

[0008] In some embodiments, the global instruction identifier circuit is integrated into the instruction pipeline circuit and connected to the retirement control circuit. The global instruction identifier circuit is used to generate the global instruction identifier when the retirement control circuit causes the instruction to be retired to complete retirement.

[0009] In some embodiments, the instruction status maintenance circuit is further configured to maintain the data conversion record and the identifier conversion record corresponding to the type of the retirement instruction, based on the type of the retirement instruction.

[0010] In some embodiments, the instruction state maintenance circuit is further configured to maintain the data conversion record and the identifier conversion record corresponding to the register event instruction in response to the type of the instruction to be retired being a register event instruction; or to maintain the data conversion record and the identifier conversion record corresponding to the memory event instruction in response to the type of the instruction to be retired being a memory event instruction.

[0011] In some embodiments, the processor core includes the instruction pipeline circuit and the global instruction identifier circuit; the instruction state maintenance circuit includes: a general-purpose register circuit, located in the processor core and connected to the instruction pipeline circuit, for maintaining the data conversion record corresponding to the register event instruction or the memory event instruction when the type of the instruction to be retired is the register event instruction or the memory event instruction; and a register timestamp circuit, located outside the processor core and connected to the instruction pipeline circuit, for maintaining the identifier conversion record corresponding to the register event instruction or the memory event instruction when the type of the instruction to be retired is the register event instruction or the memory event instruction.

[0012] In some embodiments, the general-purpose register circuit includes: a register file for storing register business data; a first read port for reading the value of a first source register from the register file before the retirement instruction is retired; a second read port for reading the value of a second source register from the register file before the retirement instruction is retired; a third read port for reading the old value of a destination register from the register file before the retirement instruction is retired; and a write port for writing the new value of the destination register to the register file when the retirement instruction is completed; wherein the values ​​read by the first read port and the second read port, the old value read by the third read port, and the new value written by the write port are used to form the data conversion record.

[0013] In some embodiments, the register timestamp circuit includes: a register timestamp array for storing register timestamps; a first read timestamp port for reading the timestamp of a first source register from the register timestamp array before the retirement instruction is retired; a second read timestamp port for reading the timestamp of a second source register from the register timestamp array before the retirement instruction is retired; a third read timestamp port for reading the old timestamp of a destination register from the register timestamp array before the retirement instruction is retired; and a first write timestamp port for writing the first source register to the register timestamp array when the retirement instruction is completed. A new timestamp for the register; a second write timestamp port, used to write the new timestamp of the second source register to the register timestamp array when the retirement instruction to be retired is completed; a third write timestamp port, used to write the new timestamp of the destination register to the register timestamp array when the retirement instruction to be retired is completed; wherein, the timestamps read by the first read timestamp port and the second read timestamp port, the old timestamp read by the third read timestamp port, the new timestamps written by the first write timestamp port and the second write timestamp port, and the new timestamp written by the third write timestamp port are used to form the identifier conversion record.

[0014] In some embodiments, the register timestamp circuit is further configured to arrange the new timestamp of the first source register, the new timestamp of the second source register, and the new timestamp of the destination register in ascending order according to the global instruction identifier and a preset offset rule.

[0015] In some embodiments, the register timestamp circuit is further configured to, when there are at least two identical register indices in the first source register, the second source register, and the destination register, write new timestamps to the registers corresponding to the at least two identical register indices according to a preset priority, at least two of the first write timestamp port, the second write timestamp port, and the third write timestamp port.

[0016] In some embodiments, the instruction state maintenance circuit further includes: a memory data cache circuit, located in the processor core and connected to the instruction pipeline circuit, for maintaining the data conversion record corresponding to the memory event instruction when the type of the instruction to be retired is the memory event instruction; and a memory timestamp cache circuit, located in the processor core and connected to the instruction pipeline circuit, for maintaining the identifier conversion record corresponding to the memory event instruction when the type of the instruction to be retired is the memory event instruction.

[0017] In some embodiments, the memory event instruction includes a load instruction and a store instruction; the memory data cache circuit is further configured to, in response to the load instruction, read an old memory value from the memory data address region, and the memory timestamp cache circuit is further configured to, in response to the load instruction, read an old memory timestamp from the memory timestamp address region and write a new memory timestamp into the memory timestamp address region; or the memory data cache circuit is further configured to, in response to the store instruction, read an old memory value from the memory data address region and write a new memory value into the memory data address region, and the memory timestamp cache circuit is further configured to, in response to the store instruction, read an old memory timestamp from the memory timestamp address region and write a new memory timestamp into the memory timestamp address region; wherein, the old memory value is used to form the data conversion record, and the old memory timestamp is used to form the identifier conversion record; or the old memory value and the new memory value are used to form the data conversion record, and the old memory timestamp and the new memory timestamp are used to form the identifier conversion record.

[0018] In some embodiments, the memory timestamp caching circuit is further configured to arrange the old memory timestamp and the new memory timestamp in ascending order according to the global instruction identifier and the preset offset rule.

[0019] In some embodiments, the memory timestamp caching circuit is further configured to obtain the memory timestamp address region according to a preset address mapping rule, so as to read the old memory timestamp from the memory timestamp address region and write the new memory timestamp into the memory timestamp address region.

[0020] Secondly, this application provides a zero-knowledge proof system, comprising: a host computer for providing a program, input parameters, and configuration data, wherein the program includes at least one instruction; a system-on-a-chip including the processor described in the first aspect, for acquiring the program, the input parameters, and the configuration data, and generating a proof trajectory record corresponding to the at least one instruction; and a proof circuit for acquiring the proof trajectory record, and after generating proof data corresponding to the proof trajectory record, returning the proof data to the host computer.

[0021] In some embodiments, the host is further configured to write the program, the input parameters, and the configuration data into shared memory, and perform a cache refresh operation after the writing is completed.

[0022] In some embodiments, the host is further configured to send a trajectory generation start signal to the system-on-chip; the system-on-chip is further configured to, upon receiving the trajectory generation start signal, acquire the program, the input parameters and the configuration data, and generate the proof trajectory record corresponding to the at least one instruction.

[0023] In some embodiments, the system-on-chip is further configured to send a trajectory generation end signal to the host after generating the proof trajectory record corresponding to the at least one instruction, so as to start the proof circuit through the host.

[0024] In some embodiments, the host is further configured to perform a memory barrier operation after receiving the trajectory generation end signal, and send a proof start signal to the proof circuit after performing the memory barrier operation to start the proof circuit.

[0025] In some embodiments, the proof circuit is further configured to write the proof data into shared memory after generating proof data corresponding to the proof trajectory record, and send a proof completion signal to the host.

[0026] Thirdly, this application provides a proof state generation method, comprising: executing an instruction to obtain a retirement instruction; generating a unique and monotonically increasing global instruction identifier when the retirement instruction completes retirement, and maintaining a data conversion record and an identifier conversion record of the retirement instruction; and constructing a proof trajectory record based on the global instruction identifier, the data conversion record, and the identifier conversion record.

[0027] In some embodiments, generating a unique and monotonically increasing global instruction identifier when the retirement instruction completes retirement includes: causing the retirement instruction to complete retirement when the retirement instruction meets preset retirement conditions, and generating the unique and monotonically increasing global instruction identifier.

[0028] In some embodiments, maintaining the data conversion record and identifier conversion record of the retirement instruction includes: maintaining the data conversion record and identifier conversion record corresponding to the type of the retirement instruction, based on the type of the retirement instruction.

[0029] In some embodiments, maintaining the data conversion record and the identifier conversion record corresponding to the type of the retirement instruction includes: maintaining the data conversion record and the identifier conversion record corresponding to the register event instruction in response to the retirement instruction being of type register event instruction; or maintaining the data conversion record and the identifier conversion record corresponding to the memory event instruction in response to the retirement instruction being of type memory event instruction.

[0030] In some embodiments, the step of maintaining the data conversion record and the identifier conversion record corresponding to the register event instruction in response to the retirement instruction being of the type of register event instruction includes: reading a first source register value, a second source register value, and an old value of the destination register from the register file before the retirement instruction is retired, and writing a new value of the destination register to the register file when the retirement instruction is completed, wherein the first source register value, the second source register value, the old value of the destination register, and the new value of the destination register are used to form the data conversion record; and reading a first source register timestamp, a second source register timestamp, and an old timestamp of the destination register from the register timestamp array before the retirement instruction is retired, and writing a new timestamp of the first source register, a new timestamp of the second source register, and a new timestamp of the destination register to the register timestamp array when the retirement instruction is completed, wherein the first source register timestamp, the second source register timestamp, the old timestamp of the destination register, and the new timestamp of the first source register, the new timestamp of the second source register, and the new timestamp of the destination register are used to form the identifier conversion record.

[0031] In some embodiments, the new timestamp of the first source register, the new timestamp of the second source register, and the new timestamp of the destination register are arranged in ascending order according to the global instruction identifier and the preset offset rule.

[0032] In some embodiments, when there are at least two identical register indices corresponding to the new timestamp of the first source register, the new timestamp of the second source register, and the new timestamp of the destination register, a new timestamp is written to the registers corresponding to the at least two identical register indices according to a preset priority.

[0033] In some embodiments, maintaining the data conversion record and the identifier conversion record corresponding to the memory event instruction in response to the type of the retirement instruction being a memory event instruction includes: in response to a load instruction corresponding to the memory event instruction, reading the old memory value from the memory data address region, reading the old memory timestamp from the memory timestamp address region, and writing the new memory timestamp into the memory timestamp address region; or in response to a store instruction corresponding to the memory event instruction, reading the old memory value from the memory data address region, writing the new memory value into the memory data address region, reading the old memory timestamp from the memory timestamp address region, and writing the new memory timestamp into the memory timestamp address region; wherein the old memory value is used to form the data conversion record, and the old memory timestamp and the new memory timestamp are used to form the identifier conversion record; or the old memory value and the new memory value are used to form the data conversion record, and the old memory timestamp and the new memory timestamp are used to form the identifier conversion record.

[0034] In some embodiments, the old memory timestamp and the new memory timestamp are arranged in ascending order according to the global instruction identifier and a preset offset rule.

[0035] In some embodiments, the memory timestamp address region is obtained according to a preset address mapping rule, so as to read the old memory timestamp from the memory timestamp address region and write the new memory timestamp into the memory timestamp address region.

[0036] Fourthly, this application provides a system-on-a-chip including the processor described in the first aspect above, or for implementing the method described in the third aspect above.

[0037] The beneficial effects of this application are as follows: The global instruction identifier circuit generates a unique and monotonically increasing global instruction identifier on the hardware node when the instruction to be retired completes its retirement. This binds the update of the architecture state by the instruction and the generation of the proof trajectory record into indivisible atomic events from the hardware level. This hardware-enforced atomicity mechanism completely eliminates the memory barrier or lock operation overhead introduced at the software level to ensure state consistency, guaranteeing that the proof trajectory record and the actual execution semantics of the program are completely consistent. Simultaneously, the global instruction identifier circuit directly establishes a globally unique timing benchmark through hardware logic, providing a unified timing reference for the vCPU state machine and vRAM state machine, ensuring the strong order of the trajectory and satisfying consistency proofs. Compared to traditional schemes that rely on software-layer insertion of synchronization instructions to align timestamps, this scheme, by generating explicit global instruction identifiers, avoids the occupation of the processor's front-end fetch unit and back-end execution unit by synchronization instructions, eliminating the pipeline blocking and context switching overhead caused by this. This ensures that the global order of instructions remains strictly controllable even under complex back-end proof logic, significantly improving the overall throughput and response speed of the system, meeting the urgent need for high-performance proof systems in blockchain scaling and decentralized computing. The instruction state maintenance circuit maintains data conversion records and identifier conversion records corresponding to instructions at the hardware level. It directly captures the details of register and memory state changes and corresponding timing identifiers during pipeline execution, providing complete data support for backend proofs without the need for additional software instrumentation or performance monitoring unit configuration. This solves the problem of proof failure due to a lack of traceable timing evidence, providing indispensable data support for register consistency proofs of the vCPU state machine and memory consistency proofs of the vRAM state machine. This native hardware state capture and identifier allocation mechanism significantly reduces the bandwidth pressure on trajectory data transmission between on-chip cache and off-chip storage subsystems, alleviating performance constraints caused by the memory wall. Simultaneously, the backend proof system, based on the strong ordering and complete state records guaranteed by hardware, can efficiently complete verification without complex out-of-order reordering or retries, further reducing the computational load and storage consumption of the verification stage and shortening the overall latency from instruction issuance to retirement. Therefore, the global instruction identifier, data conversion record, and identifier conversion record in the proof trajectory record provide reliable, ordered, and semantically consistent execution witness data for backend proofs, achieving hardware performance enhancement across the entire chain from instruction execution and state tracking to proof verification. Attached Figure Description

[0038] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application.

[0039] Figure 1 This is a schematic diagram of the processor structure in some embodiments of this application. Figure 1 ; Figure 2 This is a schematic diagram of the processor structure in some embodiments of this application. Figure 2 ; Figure 3 This is a schematic diagram of the processor structure in some embodiments of this application. Figure 3 ; Figure 4 This is a schematic diagram of the processor structure in some embodiments of this application. Figure 4 ; Figure 5 This is a schematic diagram of the processor structure in some embodiments of this application. Figure 5 ; Figure 6 This is a schematic diagram of the structure of a zero-knowledge proof system according to some embodiments of this application. Figure 1 ; Figure 7 This is a schematic diagram of the structure of a zero-knowledge proof system according to some embodiments of this application. Figure 2 ; Figure 8 This is a schematic diagram of the zero-knowledge proof process for some embodiments of this application. Figure 1 ; Figure 9 This is a schematic diagram of the zero-knowledge proof process for some embodiments of this application. Figure 2 ; Figure 10 This is a flowchart illustrating the proof state generation method of some embodiments of this application; Figure 11 This is a flowchart illustrating the global instruction identifier and timestamp maintenance mechanism of some embodiments of this application; Figure 12 This is a flowchart illustrating the consistency proof of the vCPU state machine and vRAM state machine in some embodiments of this application; Figure 13 This is a schematic diagram of the memory timestamp address mapping process in some embodiments of this application; Figure 14 This is a schematic diagram of the structure of a system-on-a-chip according to some embodiments of this application. Detailed Implementation

[0040] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be noted that the following embodiments are for illustrative purposes only and are not intended to limit the scope of the application. Similarly, the following embodiments are only some, not all, embodiments of the present application, and all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0041] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0042] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Additionally, the character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, "many" in this application means two or more. Moreover, the term "at least one" in this application means any combination of at least two of any one or more of a plurality of objects. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C. Furthermore, the terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0043] With the rapid implementation of scenarios such as blockchain scaling, privacy transactions, verifiable computation, and decentralized off-chain execution, the computational scale of the procedures to be proven and the amount of input data are growing exponentially. The computational overhead of the proof generation process has become a core bottleneck for system throughput. In the trajectory generation stage, the following defects are commonly found: the vCPU (Virtual Central Processing Unit) state machine and the vRAM (Virtual Random Access Memory) state machine lack a unified timing reference; the trajectory generation line order is mistakenly considered a substitute for explicit timestamps, while permutation arguments and multi-chip constraint processing can destroy or lose this implicit order; and there is a lack of traceable state transition records, making backend verification impossible.

[0044] Taking the zKVM (Zero-Knowledge Virtual Machine) scenario as an example, zero-knowledge proofs have been widely used in blockchain scaling, privacy protection, verifiable computing, decentralized computing, and off-chain execution scenarios. The performance and reliability of the proof system have become key links in the entire technology stack.

[0045] To this end, this application provides a processor, comprising: an instruction pipeline circuit for executing instructions and obtaining instructions to be retired; a global instruction identifier circuit, connected to or integrated into the instruction pipeline circuit, for generating a unique and monotonically increasing global instruction identifier when the instructions to be retired complete retirement; and an instruction state maintenance circuit, connected to the instruction pipeline circuit, for maintaining data conversion records and identifier conversion records of the instructions to be retired; wherein the global instruction identifier, data conversion records, and identifier conversion records are used to construct a proof trajectory record. This enables reliable, ordered, and semantically consistent execution witness data for backend proof through the global instruction identifier, data conversion records, and identifier conversion records.

[0046] To enable those skilled in the art to better understand the technical solution of this application, the technical solution of this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0047] Please see Figure 1 , Figure 1 This is a schematic diagram of the processor structure in some embodiments of this application. Figure 1 The processor 100 includes: an instruction pipeline circuit 110 for executing instructions and obtaining instructions to be retired; and a global instruction identifier circuit 120, connected to or integrated with the instruction pipeline circuit 110. Figure 1 (Not shown in the diagram) In the instruction pipeline circuit 110, a unique and monotonically increasing global instruction identifier is generated corresponding to the instruction to be retired when the instruction to be retired is completed; the instruction status maintenance circuit 130, connected to the instruction pipeline circuit 110, is used to maintain the data conversion record and identifier conversion record of the instruction to be retired; wherein, the global instruction identifier, data conversion record and identifier conversion record are used to construct the proof trajectory record.

[0048] The processor 100 can be an integrated circuit chip used to execute a user program and generate a proof trace record corresponding to the user program. The user program includes at least one instruction. The proof trace record can be used for zero-knowledge proofs, as well as for proofs in other cryptographic or secure computing fields.

[0049] In one implementation, the processor 100 may be a CPU (Central Processing Unit), specifically implemented based on a reduced instruction set architecture. In a specific embodiment, the processor 100 may be a RISC-V (Reduced Instruction Set Computer-Five) based processor, configured to execute user programs and generate corresponding proof trace records, wherein the user program may be an executable program conforming to the RISC-V instruction set architecture.

[0050] The instruction pipeline circuit 110 can be an integrated circuit comprising multiple functional parts. The instruction pipeline circuit 110 is the core circuit for executing instructions in the processor 100. In one embodiment, the processor 100 can be modified based on the Rocket Chip RV32IM sequential single-issue core. The instruction pipeline circuit 110 is configured to process instructions sequentially according to the RISC-V five-stage pipeline, where the five stages are instruction fetch, decode, execute, memory access, and write-back. The instructions can be from a user program, which may include at least one instruction. The instruction pipeline circuit 110 is configured to process instructions sequentially according to the five-stage pipeline. For example, if the user program includes instructions A, B, and C, the instruction pipeline circuit 110 sequentially fetches instructions A, B, and C from the user program and executes them. In one example, instructions A, B, and C are at different stages in the instruction pipeline circuit 110. Taking the instruction pipeline circuit 110 sequentially fetching instructions A, B, and C from the user program for execution as an example, instruction A is in the memory access stage, instruction B is in the execution stage, and instruction C is in the decoding stage.

[0051] Retirement instructions can be instructions that have been executed in the user program but have not yet been retired. Taking the instruction pipeline circuit 110 as a five-stage pipeline as an example, retirement instructions can be instructions that have entered the write-back stage and are waiting to be retired.

[0052] The global instruction identifier circuit 120 is used to generate global instruction identifiers, wherein the global instruction identifiers include, but are not limited to, data in a unique and monotonically increasing form such as count values, timestamps, and sequence numbers. Furthermore, the global instruction identifiers possess system-level global visibility, for example, global visibility in heterogeneous systems.

[0053] Continuing with the example of instruction pipeline circuit 110 sequentially fetching instructions A, B, and C from the user program for execution, global instruction identifier circuit 120 is used to generate a unique and monotonically increasing global instruction identifier corresponding to the instruction to be retired when the retired instruction is completed. For example, when instruction A retires, global instruction identifier id1 corresponding to instruction A is generated; when instruction B retires, global instruction identifier id2 corresponding to instruction B is generated; and when instruction C retires, global instruction identifier id3 corresponding to instruction C is generated. Here, instruction A retires before instruction B, instruction B retires before instruction C, and id1 < id2 < id3.

[0054] In one embodiment, the global instruction identifier circuit 120 is connected to the instruction pipeline circuit 110, such as... Figure 1 As shown, the global instruction identifier circuit 120 is also used to send the global instruction identifier corresponding to the instruction to be retired to the instruction pipeline circuit 110 when the instruction to be retired is retired.

[0055] In one implementation, the global instruction identifier circuit 120 is integrated into the instruction pipeline circuit 110. Figure 1 As not shown in the diagram, the global instruction identifier circuit 120 is also used to send the global instruction identifier corresponding to the instruction to be retired to the instruction pipeline circuit 110 when the instruction to be retired is completed.

[0056] The instruction status maintenance circuit 130 is used to maintain the data conversion record and identifier conversion record of the instruction to be retired. For example, the instruction status maintenance circuit 130 stores the data conversion record and identifier conversion record corresponding to the instruction to be retired.

[0057] In one implementation, the data conversion record and identifier conversion record maintained by the instruction state maintenance circuit 130 can be acquired and modified by the instruction pipeline circuit 110, for example, acquiring the data stored in the instruction state maintenance circuit 130 and writing new data to the instruction state maintenance circuit 130.

[0058] The data transformation record can include records of data transformations corresponding to an instruction generated by executing that instruction. For example, if the original data is V1, executing the instruction transforms the original data V1 into V2. The original data V1 is different from the transformed data V2; that is, the data transformation record can include both the original data V1 and the transformed data V2. In one example, the data transformation record includes register data and / or memory data. The identifier transformation record can include records of identifier transformations corresponding to an instruction generated by executing that instruction. For example, if the original identifier is D1, executing the instruction transforms the original identifier D1 into D2. The original identifier D1 is different from the transformed identifier D2; that is, the identifier transformation record can include both the original identifier D1 and the transformed identifier D2. In one example, the identifier transformation record includes register identifiers and / or memory identifiers. More specifically, the identifier transformation record can include register timestamps and / or memory timestamps.

[0059] In one embodiment, a data conversion record and an identifier conversion record correspond. For example, the data conversion record includes register data and / or memory data, and the identifier conversion record may include an identifier corresponding to the register data and / or an identifier corresponding to the memory data. In one example, the register data includes register read values ​​and register write values, and the identifier conversion record includes a timestamp corresponding to the register read value and another timestamp corresponding to the register write value. In another example, the memory data includes memory read values ​​and memory write values, and the identifier conversion record includes a timestamp corresponding to the memory read value and another timestamp corresponding to the memory write value.

[0060] Proof trace records can be a data form of instruction execution evidence structure, including a data set automatically captured and constructed from relevant data generated by the execution of instructions, used to record and prove the instruction execution process and results. In different implementations or application scenarios, proof trace records can also be called trace records, operation logs, execution summaries, verification data packets, etc.

[0061] The proof trajectory record includes, but is not limited to, global instruction identifiers, data conversion records, and identifier conversion records, which can be added according to design requirements. For example, the proof trajectory record may also include the following trajectory fields: valid, used to indicate whether this proof trajectory record is valid; pc, used to record the program counter address of the instruction; inst, used to record the opcode and operand encoding of the instruction.

[0062] In one embodiment, the instruction pipeline circuit 110 is also used to construct a proof trajectory record. For example, the instruction pipeline circuit 110 executes instruction A, obtains the global instruction identifier, data conversion record and identifier conversion record corresponding to instruction A, and encapsulates the global instruction identifier, data conversion record and identifier conversion record corresponding to instruction A into the same proof trajectory record, thereby realizing the construction of the proof trajectory record for instruction A.

[0063] In the above scheme, the global instruction identifier circuit 120 generates a unique and monotonically increasing global instruction identifier on the hardware node where the instruction to be retired completes its retirement. This binds the instruction's update of the architecture state and the generation of the proof trajectory record into indivisible atomic events at the hardware level. This hardware-enforced atomicity mechanism completely eliminates the memory barriers or lock operation overhead introduced at the software level to ensure state consistency, guaranteeing that the proof trajectory record and the actual execution semantics of the program are completely consistent. Simultaneously, the global instruction identifier circuit 120 directly establishes a globally unique timing benchmark through hardware logic, providing a unified timing reference for the vCPU state machine and vRAM state machine, ensuring the strong ordering of the trajectory and satisfying the consistency proof. Compared to traditional solutions that rely on software-level synchronization instructions to align timestamps, this solution generates explicit global instruction identifiers. This avoids the occupation of the processor's front-end fetch unit and back-end execution unit by synchronization instructions, eliminating pipeline blocking and context switching overhead. This ensures that the global order of instructions remains strictly controllable even under complex back-end proof logic, significantly improving the overall system throughput and response speed. This aligns with the urgent need for high-performance proof systems in blockchain scaling and decentralized computing. The instruction state maintenance circuit 130 maintains data conversion records and identifier conversion records corresponding to instructions at the hardware level. It directly captures the details of register and memory state changes and corresponding timing identifiers during pipeline execution. It provides complete data support for back-end proofs without the need for additional software instrumentation or performance monitoring unit configuration, solving the problem of proof failure due to a lack of traceable timing evidence. This provides indispensable data support for register consistency proofs of the vCPU state machine and memory consistency proofs of the vRAM state machine. This hardware-native state capture and identifier allocation mechanism significantly reduces the bandwidth pressure on trajectory data transmission between on-chip cache and off-chip storage subsystems, alleviating performance constraints caused by the storage wall. Simultaneously, the backend proof system, based on hardware-guaranteed strong ordering and complete state records, can efficiently complete verification without complex out-of-order reordering or retries, further reducing the computational load and storage consumption of the verification process and shortening the overall latency from instruction issuance to retirement. Thus, the global instruction identifier, data conversion record, and identifier conversion record in the proof trajectory record provide reliable, ordered, and semantically consistent execution witness data for backend proof, achieving end-to-end hardware performance enhancement from instruction execution and state tracking to proof verification.

[0064] Please see Figure 2 , Figure 2 This is a schematic diagram of the processor structure in some embodiments of this application. Figure 2 The instruction pipeline circuit 110 includes a retirement control circuit 111, which is used to retire the instruction when the instruction to be retired meets the preset retirement conditions.

[0065] The retirement control circuit 111 can be set in the preset function part of the instruction pipeline circuit 110. Taking the instruction pipeline circuit 110 as a RISC-V five-stage pipeline as an example, the retirement control circuit 111 can be set in the write-back part.

[0066] In one implementation, the preset retirement conditions are set according to the retirement semantics of the instruction pipeline circuit 110. For example, if the instruction pipeline circuit 110 is a RISC-V five-stage pipeline, the retirement control circuit 111 controls the instruction to be retired to complete retirement when the instruction to be retired meets the requirements of instruction validity, no return, and no exception.

[0067] In one implementation, the preset retirement conditions are set based on information related to the instruction. For example, it is determined whether the address of the instruction to be retired is located in a preset address region. If the instruction to be retired is located in the preset address region, the retirement control circuit 111 controls the instruction to be retired to complete the retirement. In one example, the preset address region may be a preset user program address region. The program counter address of the instruction to be retired is obtained, and it is determined whether the program counter address belongs to the preset user program address region. The size of the preset user program address region can be adjusted according to design requirements.

[0068] In one implementation, the preset retirement conditions are set based on data conversion records and / or identifier conversion records. For example, for load instructions, the instruction to be retired cannot be retired if the old value and / or timestamp corresponding to the memory access address is not read; for store instructions, the instruction to be retired cannot be retired if the old value and / or timestamp corresponding to the memory write address is not read.

[0069] In one implementation, the preset retirement conditions are set based on the consumption status of the consumer. For example, if the consumer continuously consumes proof trajectory records, and if the consumer can no longer consume a new proof trajectory record, the retirement instruction cannot be retired, and the transmission of the proof trajectory record for that retirement instruction to the consumer will stop. In one example, when the consumer can no longer consume a new proof trajectory record, it continuously sends a signal to the retirement control circuit 111 to pause the transmission of proof trajectory records, instructing the retirement control circuit 111 to pause the transmission of proof trajectory records. That is, the retirement control circuit 111 can continue to transmit proof trajectory records when it does not receive this signal, and stops transmitting proof trajectory records when it receives this signal. In one example, the consumer includes at least one of a synchronous decoupling trajectory circuit and a trajectory parsing circuit, wherein the synchronous decoupling trajectory circuit is used to accommodate complete and / or partial proof trajectory records. For example, when the proof trajectory records in the synchronous decoupling trajectory circuit are incomplete, the synchronous decoupling trajectory circuit receives asynchronously returned data and fills the proof trajectory record with the asynchronously returned data until the proof trajectory record is complete. The trajectory parsing circuit is used to parse the proof trajectory record and store the parsed proof trajectory record in the target storage area for backend proof to read. In an exemplary connection relationship, the retirement control circuit 111 is connected to the synchronous decoupling trajectory circuit, and the synchronous decoupling trajectory circuit is connected to the trajectory parsing circuit.

[0070] In one implementation, the preset retirement conditions include multi-level determinations. In one example, the preset retirement conditions include at least two of the four implementations described above, for determining whether a retirement order is valid for retirement.

[0071] The above scheme achieves deep coupling and refined control between instruction retirement and trajectory generation through multi-dimensional preset retirement conditions. Determining whether an instruction is to be retired based on retirement semantics ensures the compliance and security of the trajectory; determining whether an instruction is to be retired based on its address ensures that instructions within the legitimate user address space are allowed to retire and generate proof trajectory records, preventing illegal proofs and information leaks; determining whether an instruction is to be retired based on the data in the proof trajectory records avoids ghost instructions or incomplete trajectory issues caused by missing key data, ensuring that each output proof trajectory record has complete data support, meeting the stringent requirements of backend proof for input determinism; determining whether an instruction is to be retired based on the consumption status at the consumer end effectively prevents data overflow, packet loss, or state machine crashes caused by mismatched upstream and downstream processing rates, ensuring the continuous and stable operation of the system under long-term operation or high-load scenarios. Simultaneously, the multi-level judgment logic provides extremely high flexibility for the processor architecture, meeting diverse needs and adapting to various proof scenarios.

[0072] Please continue reading. Figure 2The global instruction identifier circuit 120 is connected to the retirement control circuit 111 through the instruction pipeline circuit 110. The global instruction identifier circuit 120 is used to generate a global instruction identifier when the retirement control circuit 111 causes the instruction to be retired to complete retirement.

[0073] like Figure 2 As shown, the global instruction identifier circuit 120 is located outside the instruction pipeline circuit 110 and is connected to the retirement control circuit 111 in the instruction pipeline circuit 110.

[0074] In one implementation, the global instruction identifier circuit 120 multiplexes a register in the processor 100 and binds the increment enable signal of the register to the instruction to be retired. For example, the processor 100 is a RISC-V based processor 100, and the global instruction identifier circuit 120 multiplexes a control status register in the processor 100 and binds the increment enable signal of the control status register to the instruction to be retired.

[0075] In specific implementation, the global instruction identifier circuit 120 can be deployed in two ways: one is internal instantiation, that is, the global instruction identifier circuit 120 internally instantiates a control status register (such as a machine mode instruction retirement counter) and connects the increment enable terminal of the control status register to the retirement valid signal of the retirement control circuit 111; the other is external connection, that is, the global instruction identifier circuit 120 is connected to the native control status register in the processor 100, the count value of the control status register is brought out through a dedicated signal line, and then the increment enable terminal is bound to the retirement valid signal.

[0076] The timing logic for the retirement of a pending instruction and the generation of a global instruction identifier is as follows: within the same clock cycle when a pending instruction completes its retirement, the global instruction identifier circuit 120 reads the current count value of the control status register as the global instruction identifier for that pending instruction. Subsequently, the increment logic of the control status register is triggered, and the updated count value is used as the global instruction identifier for the next pending instruction, ensuring that the global instruction identifier is strictly monotonically increasing and completely consistent with the instruction retirement order.

[0077] In one implementation, the processor 100 is a multi-core / multi-hardware-thread architecture, and the global instruction identifier circuit 120 is a unified global instruction identifier management circuit across cores / hardware threads, coordinating the generation and allocation of global instruction identifiers for all cores / hardware threads. Each core / hardware thread independently reuses its internal control status register, and the increment enable signal of each control status register is bound to the retirement event of the corresponding instruction to be retired on the corresponding core / hardware thread.

[0078] In a multi-core / hardware thread scenario, the global instruction identifier circuit 120 generates a system-level global instruction identifier for the instructions to be retired in each core / hardware thread according to one of the following two preset rules.

[0079] Preset rule 1: The global instruction identifier circuit 120 includes multiple sets of sub-counting units and a combination encoding unit. Each set of sub-counting units is connected to the control status register inside each core / hardware thread to obtain the count value of the control status register of that core / hardware thread in real time; the combination encoding unit combines the identifier of each core / hardware thread with the corresponding count value of that core / hardware thread for encoding (e.g., high-order bit concatenation or offset superposition) to generate the global instruction identifier for the instruction to be retired.

[0080] Preset Rule 2: The Global Instruction Identifier Circuit 120 integrates a global arbitrator, which maintains a globally unified counter. When a retired instruction completes its retirement, each core / hardware thread sends a retirement request to the global arbitrator within the Global Instruction Identifier Circuit 120. Upon responding to the request, the global arbitrator assigns a unique and incrementing global instruction identifier for each retirement event, which is then fed back to the corresponding core / hardware thread via the Global Instruction Identifier Circuit 120. This enables the Global Instruction Identifier Circuit 120 to uniformly complete the allocation and distribution of identifiers across cores / hardware threads.

[0081] In the above scheme, the global instruction identifier circuit 120 binds the global instruction identifier increment logic with the instruction retirement event, ensuring that the output global instruction identifier has inherent monotonicity and providing a global timing anchor point for the vCPU state machine and vRAM state machine. Simultaneously, the generated global instruction identifier has system-level global visibility and can be directly consumed by the backend proof system, eliminating the cumbersome timestamp alignment overhead at the software layer. This effectively supports permutation proofs and multi-Chip constraint processing, significantly improving the throughput and reliability of the proof system.

[0082] Please see Figure 3 , Figure 3 This is a schematic diagram of the processor structure in some embodiments of this application. Figure 3 The global instruction identifier circuit 120 is integrated into the instruction pipeline circuit 110 and connected to the retirement control circuit 111. The global instruction identifier circuit 120 is used to generate a global instruction identifier when the retirement control circuit 111 causes the instruction to be retired to complete retirement.

[0083] like Figure 3 As shown, the global instruction identifier circuit 120 is located in the instruction pipeline circuit 110 and is connected to the retirement control circuit 111.

[0084] In one implementation, the global instruction identifier circuit 120 is an instruction retirement counter, and the incrementing enable of the global instruction identifier circuit 120 is bound to the retirement completion of the instruction to be retired. For example, the current value of the global instruction identifier circuit 120 is used as the global instruction identifier of the instruction to be retired, and when the instruction to be retired completes its retirement, the count value of the global instruction identifier circuit 120 is incremented, and the incremented count value is used as the global instruction identifier of the next instruction to be retired. In one example, the instruction pipeline circuit 110 is a five-stage pipeline circuit, and the global instruction identifier circuit 120 is located in the write-back section of the instruction pipeline circuit 110.

[0085] In one implementation, the processor 100 is a multi-core / multi-hardware thread architecture, and the global instruction identifier circuit 120 is configured to be coupled to the commit end of the reorder buffer to generate the global instruction identifier when the reorder buffer commits instructions in program order.

[0086] Specifically, the reorder buffer is used to maintain the lifecycle of out-of-order execution instructions. During the dispatch phase, instructions are allocated reorder buffer entry indices in program order, and these indices encode the program order of the instructions at the hardware level. The global instruction identifier circuit 120 internally instantiates an instruction retirement counter and connects it to the reorder buffer's commit control logic to listen for valid instruction commit events.

[0087] When the reordering buffer commits M instructions within a clock cycle (M is the actual commit width, M≥1), the global instruction identifier circuit 120 responds to the commit event by using internal combinational logic to consecutively allocate M global instruction identifiers to these M instructions in ascending order of the reordering buffer entry index. For example, if the current instruction retirement counter value is Base, and the M consecutive instructions at the head of the reordering buffer all meet the commit condition, then the global instruction identifier circuit 120 sequentially assigns Base to the first commit instruction, Base+1 to the second, and so on, until Base+M-1 is assigned to the Mth commit instruction. Subsequently, at the end of the current clock cycle, the instruction retirement counter is incremented by M.

[0088] In the above scheme, the global instruction identifier circuit 120 is embedded in the instruction pipeline circuit 110, achieving physical-level tight coupling between instruction retirement and identifier generation. With the instruction retirement counter as the core, it ensures that the monotonicity of the global instruction identifier is completely consistent with the instruction retirement order, providing precise timing anchors for state changes in the vCPU and vRAM state machines. Specifically, in a multi-core / multi-hardware thread architecture, the global instruction identifier circuit 120 is directly coupled to the submission end of the reordering buffer. Utilizing the characteristic of the reordering buffer entry index to solidify the program order, even in scenarios where multiple instructions are submitted in a single cycle, global instruction identifiers can still be continuously allocated in index order through combinational logic. This releases the high-performance potential of out-of-order execution while mitigating the risk of out-of-order trajectory from the source. This embedded design significantly shortens the signal path from the retirement event to identifier generation, reduces the difficulty of timing convergence, and the generated global instruction identifier has system-level global visibility, allowing direct consumption by the backend proof system. This eliminates the cumbersome timestamp alignment overhead at the software layer, effectively supporting permutation proofs and multi-Chip constraint processing, and significantly improving the throughput and reliability of the proof system.

[0089] In some embodiments, the instruction status maintenance circuit 130 is further configured to maintain a data conversion record and an identifier conversion record corresponding to the type of the instruction to be retired, based on the type of the instruction to be retired.

[0090] In one implementation, the instruction pipeline circuit 110 identifies the type of retirement instruction to be implemented and maintains data conversion records and identifier conversion records corresponding to the type of retirement instruction through the instruction status maintenance circuit 130.

[0091] The data conversion record can include read values ​​and write-back values, and the identifier conversion record can include old timestamps and new timestamps. For example, read values ​​and write values ​​during instruction execution, as well as old timestamps and new timestamps during instruction execution. The timestamp corresponding to the read value can be the old timestamp, and the timestamp corresponding to the write value can be the new timestamp. In one example, the read value can be the value stored in a register or the value corresponding to a memory address; the write value can be the value that needs to be written to the register or memory address; the old timestamp can be the timestamp corresponding to the last write operation performed on the register or memory address; and the new timestamp can be the timestamp corresponding to the read or write operation on the register or memory address.

[0092] For different instruction types, the corresponding data conversion records and identifier conversion records are different. For example, for register event instructions (such as ordinary arithmetic instructions), only register read and write operations are involved, and the old timestamp and new timestamp are only related to register read and write operations. For memory event instructions (such as load instructions and store instructions), both register read operations, or read and write operations, and memory address read or write operations are involved.

[0093] In the above scheme, the instruction state maintenance circuit 130 maintains corresponding data conversion records and identifier conversion records differently according to the type of instruction to be retired, achieving accurate matching between trajectory records and instruction execution semantics, and providing accurate verification basis for state changes of vCPU state machine and vRAM state machine. Simultaneously, the structured and typed records naturally adapt to different verification logics such as backend arithmetic constraints, memory consistency constraints, and control flow constraints, eliminating the overhead of instruction parsing and field extraction in the backend software layer, and efficiently supporting the implementation of complex scenarios such as permutation proof and multi-chip parallel proof. Furthermore, this design reserves extended adaptation interfaces for instruction types, flexibly supporting the record generation needs of various standard extensions or custom instruction sets without modifying the core architecture, significantly improving the architecture compatibility and scenario adaptability of processor 100.

[0094] In some embodiments, the instruction status maintenance circuit 130 is further configured to maintain a data conversion record and an identifier conversion record corresponding to a register event instruction in response to the type of the instruction to be retired being a register event instruction; or to maintain a data conversion record and an identifier conversion record corresponding to a memory event instruction in response to the type of the instruction to be retired being a memory event instruction.

[0095] Take the register event instruction as an example, which is a normal arithmetic instruction.

[0096] When the instruction to be retired is a normal arithmetic instruction, the data conversion record corresponding to the normal arithmetic instruction should include at least the old value of source register 1, the old value of source register 2, the old value of the destination register, and the write-back value of the destination register; the identifier conversion record corresponding to the normal arithmetic instruction should include at least the old timestamp of source register 1, the old timestamp of source register 2, the old timestamp of the destination register, and the new timestamp of source register 1, the new timestamp of source register 2, and the new timestamp of the destination register. The old timestamp can be the timestamp corresponding to the last time source register 1 / source register 2 / destination register was written to, and the new timestamp can be the timestamp corresponding to the time the normal arithmetic instruction reads / writes to source register 1 / source register 2 / destination register.

[0097] Taking memory event instructions as an example, which are load and store instructions.

[0098] When the instruction to be retired is a load instruction, the data translation record corresponding to the load instruction should include at least the old value of source register 1, the read value of the memory access address, the old value of the destination register, and the write-back value. The identifier translation record corresponding to the load instruction should include at least the old timestamp of source register 1, the old timestamp of the memory access address, the old timestamp of the destination register, and the new timestamps of source register 1, the memory access address, and the destination register. The old timestamp can be the timestamp corresponding to the last time source register 1 / memory access address / destination register was written, and the new timestamp can be the timestamp corresponding to when the load instruction reads / writes to source register 1, memory access address, and destination register. In one example, source register 1 is the base address register.

[0099] When the instruction to be retired is a store instruction, the data translation record corresponding to the store instruction should include at least the old value of source register 1, the old value of source register 2, the old value of the memory write address, and the written value. The identifier translation record corresponding to the store instruction should include at least the old timestamp of source register 1, the old timestamp of source register 2, the old timestamp of the memory write address, and the new timestamps of source register 1, source register 2, and the memory write address. The old timestamp can be the timestamp corresponding to the last time source register 1 / source register 2 / memory write address was written, and the new timestamp can be the timestamp corresponding to when the store instruction reads / writes to source register 1, source register 2, and the memory write address. In one example, source register 1 is a base address register.

[0100] In the above scheme, the instruction state maintenance circuit 130 maintains the corresponding data conversion records and identifier conversion records in a refined manner according to the type of instruction to be retired. This translates the differentiated record rules into verifiable semantics on a field-by-field basis, achieving precise matching between records and the execution semantics of various instructions. This provides a complete and traceable verification basis for the state transitions of the vCPU state machine and vRAM state machine. Simultaneously, the fully structured, typed records naturally adapt to multi-dimensional verification logic such as backend register read / write dependency verification, memory consistency constraints, and control flow jump verification. This eliminates the overhead of instruction parsing, field completion, and alignment in the backend software layer, efficiently supporting low-latency implementation in complex scenarios such as permutation arguments and multi-chip parallel proofs. Furthermore, this design reserves an instruction type extension mapping interface, allowing seamless adaptation to the record generation requirements of various standard extensions or custom instruction sets without modifying the core architecture. This significantly improves the architecture compatibility and multi-scenario adaptability of the processor 100.

[0101] Please see Figure 4 , Figure 4 This is a schematic diagram of the processor structure in some embodiments of this application. Figure 4The processor 400 includes: a processor core 410, which includes an instruction pipeline circuit 411 and a global instruction identifier circuit 412; and an instruction status maintenance circuit 420, which includes: a general-purpose register circuit 421, located in the processor core 410 and connected to the instruction pipeline circuit 411, used to maintain a data conversion record corresponding to a register event instruction when the type of the instruction to be retired is a register event instruction or a memory event instruction; and a register timestamp circuit 422, located outside the processor core 410 and connected to the instruction pipeline circuit 411, used to maintain an identifier conversion record corresponding to a register event instruction when the type of the instruction to be retired is a register event instruction or a memory event instruction.

[0102] The processor 400 can be the processor 100 in the above embodiments. Similarly, the instruction pipeline circuit 411, the global instruction identifier circuit 412, and the instruction state maintenance circuit 420 can be referred to the descriptions of the instruction pipeline circuit 110, the global instruction identifier circuit 120, and the instruction state maintenance circuit 130 in the above embodiments, respectively, and will not be repeated here.

[0103] In one implementation, the processor 400 may be modified from the Rocket Chip RV32IM sequential single-issue core, and the processor core 410 is a sequential single-issue core based on the Rocket Chip RV32IM.

[0104] The general-purpose register circuit 421 may include multiple registers, each of which can be used to store data, such as instruction-related data that can be fetched and / or modified by instructions.

[0105] In one implementation, the general-purpose register circuit 421 is used to maintain a data conversion record corresponding to the register event instruction when the type of the instruction to be retired is a register event instruction. For example, when the instruction pipeline circuit 411 identifies the type of the instruction to be retired as a register event instruction, it retrieves the old value corresponding to the instruction to be retired from the registers in the general-purpose register circuit 421, and writes the new value corresponding to the instruction to be retired into the registers in the general-purpose register circuit 421. The old value retrieved from the registers and the new value to be written into the registers can be data conversion records, which are both stored in the general-purpose register circuit 421 and used to construct a proof trajectory record. The determination of which register in the general-purpose register circuit 421 to read the old value from and write the new value to is obtained during the decoding stage of the instruction to be retired. For example, the instruction pipeline circuit 411 is a five-stage pipeline circuit, and the decoding section in the instruction pipeline circuit 411 is used to parse the instruction.

[0106] The register timestamp circuit 422 may include multiple registers or storage units, each of which can be used to store a register timestamp, such as a timestamp associated with an instruction that can be retrieved and / or rewritten by the instruction.

[0107] In one implementation, the register timestamp circuit 422 is used to maintain an identifier conversion record corresponding to a register event instruction when the type of the instruction to be retired is a register event instruction. For example, when the instruction pipeline circuit 411 identifies the type of the instruction to be retired as a register event instruction, it retrieves the old timestamp corresponding to the retirement instruction from the register in the register timestamp circuit 422, and writes the new timestamp corresponding to the instruction to be retired into the register in the register timestamp circuit 422. The old timestamp retrieved from the register and the new timestamp to be written into the register can be identifier conversion records, which are both stored in the register timestamp circuit 422 and used to construct a proof trajectory record. The determination of which register in the register timestamp circuit 422 to read the old timestamp from and which register in the register timestamp circuit 422 to write the new timestamp is obtained during the decoding stage of the instruction to be retired. For example, the instruction pipeline circuit 411 is a five-stage pipeline circuit, and the decoding portion of the instruction pipeline circuit 411 is used to parse the instruction.

[0108] In one implementation, the general-purpose register circuit 421 and the register timestamp circuit 422 correspond to each other. For example, the general-purpose register circuit 421 and the register timestamp circuit 422 include multiple registers with the same index. In one example, the indices of registers r1, r2, and r3 in the general-purpose register circuit 421 are index1, index2, and index3, respectively, and the indices of registers r4, r5, and r6 in the register timestamp circuit 422 are also index1, index2, and index3, respectively. Furthermore, in the aforementioned example, the correspondence between the general-purpose register circuit 421 and the register timestamp circuit 422 is also reflected in the fact that when retrieving an old value from register r1, the old timestamp can be retrieved from register r4; and when writing a new value to register r3, the new timestamp can be written to register r6.

[0109] The general-purpose register circuit 421 and the register timestamp circuit 422 are also used to maintain corresponding data conversion records and identifier conversion records when the type of the instruction to be retired is a memory event instruction. For example, when the memory event instruction involves reading and writing to the general-purpose register circuit 421, the general-purpose register circuit 421 maintains the corresponding data conversion records, and the register timestamp circuit 422 can maintain the corresponding identifier conversion records according to the correspondence with the general-purpose register circuit 421.

[0110] In the above scheme, the general-purpose register circuit 421 is used to maintain data conversion records, and the register timestamp circuit 422 is used to maintain identifier conversion records, generating state transition records that can be proven by the vCPU state machine and vRAM state machine at the hardware level. Furthermore, the general-purpose register circuit 421 and the register timestamp circuit 422 correspond to each other, ensuring that the data conversion records and identifier conversion records correspond to the same instruction, avoiding mismatches in the proof trajectory records, and providing accurate register state transition evidence for backend proof.

[0111] Please see Figure 5 , Figure 5 This is a schematic diagram of the processor structure in some embodiments of this application. Figure 5 The general-purpose register circuit 421 includes: a register file 4211 for storing register business data; a first read port 421a for reading the value of a first source register from the register file 4211 before the retirement of the instruction to be retired; a second read port 421b for reading the value of a second source register from the register file 4211 before the retirement of the instruction to be retired; a third read port 421c for reading the old value of a destination register from the register file 4211 before the retirement of the instruction to be retired; and a write port 421d for writing the new value of the destination register to the register file 4211 when the instruction to be retired is completed; wherein the values ​​read by the first read port 421a and the second read port 421b, the old value read by the third read port 421c, and the new value written by the write port 421d are used to form a data conversion record.

[0112] The register file 4211 may include multiple registers, for example, 32 registers. Each register stores register business data, such as instruction-related data that can be fetched and / or modified by instructions.

[0113] In one implementation, the register file 4211 is configured with three read ports and one write port for updating the register file 4211 while maintaining data conversion records. Taking 32 registers (x0 to x31) as an example, the first read port 421a reads the value of the first source register from a register (e.g., register x1) in registers x0 to x31 before the retirement of the instruction to be retired. The second read port 421b reads the value of the second source register from a register (e.g., register x2) in registers x0 to x31 before the retirement of the instruction to be retired. The third read port 421c reads the old value of the destination register from a register (e.g., register x3) in registers x0 to x31 before the retirement of the instruction to be retired. The write port 421d writes the new value (e.g., the value calculated based on the value of register x1 and register x2) to a register (e.g., register x3) in registers x0 to x31 when the retirement of the instruction to be retired is completed.

[0114] The values ​​read or written by the first read port 421a, the second read port 421b, the third read port 421c, and the write port 421d are used to form a data conversion record. Taking the instruction pipeline circuit 411 as a five-stage pipeline circuit as an example, the first read port 421a and the second read port 421b are connected to the execution part of the instruction pipeline circuit 411, that is, the execution part obtains the values ​​read by the first read port 421a and the second read port 421b; the third read port 421c is connected to the instruction pipeline circuit 411. The write-back section of path 411 is connected, that is, the write-back section obtains the value read from the third read port 421c; the write port 421d is connected to the write-back section of the instruction pipeline circuit 411, that is, the write-back section writes the calculated value to be written into the register file 4211. In other words, the instruction pipeline circuit 411 can use the three read values ​​and one write value obtained by the execution section and the write-back section to form a data conversion record, and write the write value into the register file 4211 to complete the data update of the register file 4211.

[0115] In one example, write-value port 421d is connected to the instruction retirement control logic. For example, the write-back section includes retirement control circuit 4111. When retirement control circuit 4111 controls the instruction to be retired to complete retirement, instruction pipeline circuit 411 updates the data in register file 4211 through write-value port 421d. Retirement control circuit 4111 can be retirement control circuit 111 in the above embodiments.

[0116] In the above scheme, the general-purpose register circuit 421 is configured with a ported architecture of three read ports and one write port, realizing hardware-level parallelism of register business data access and trajectory data capture. While supporting the efficient execution of native instructions, it provides atomic state transition evidence for the vCPU state machine. Specifically, the three read ports read the old value in the register file 4211 before the instruction to be retired retires, and the write port writes the new value to the register file 4211 when the instruction to be retired completes its retirement. This aligns the lifecycle data of the instruction with the instruction retirement event, ensuring the integrity of the data conversion record. At the same time, this design avoids supplementing the data required for proof through additional microinstructions, software scanning, or multi-cycle register supplementary reads while ensuring instruction execution efficiency. It provides accurate, complete, and time-consistent register state transition evidence for back-end proof with extremely low intrusion, effectively supporting the efficient implementation of register dependency verification and multi-chip parallel proof.

[0117] Please continue reading. Figure 5The register timestamp circuit 422 includes: a register timestamp array 4221 for storing register timestamps; a first read timestamp port 422a for reading the timestamp of a first source register from the register timestamp array 4221 before the retirement of the instruction to be retired; a second read timestamp port 422b for reading the timestamp of a second source register from the register timestamp array 4221 before the retirement of the instruction to be retired; a third read timestamp port 422c for reading the old timestamp of the destination register from the register timestamp array 4221 before the retirement of the instruction to be retired; and a first write timestamp port 422d for writing the first source register to the register timestamp array 4221 when the instruction to be retired completes its retirement. The new timestamp of the register; the second write timestamp port 422e, used to write the new timestamp of the second source register to the register timestamp array 4221 when the retirement instruction is completed; the third write timestamp port 422f, used to write the new timestamp of the destination register to the register timestamp array 4221 when the retirement instruction is completed; wherein, the timestamps read by the first read timestamp port 422a and the second read timestamp port 422b, the old timestamp read by the third read timestamp port 422c, the new timestamps written by the first write timestamp port 422d and the second write timestamp port 422e, and the new timestamps written by the third write timestamp port 422f are used to form an identifier conversion record.

[0118] The register timestamp array 4221 may include multiple registers or storage units, for example, 32 registers. Each register can be used to store a register timestamp, for example, an instruction-related timestamp that can be fetched and / or rewritten by an instruction. Furthermore, each register may correspond to a register in the general-purpose register circuit 421; for example, the 32 registers in the register timestamp array 4221 may each correspond to a register in the general-purpose register circuit 421.

[0119] In one implementation, the register timestamp array 4221 is configured with three read timestamp ports and three write timestamp ports to update the register timestamp array 4221 while maintaining identifier conversion records. Taking registers x32~x63 as an example, the first read timestamp port 422a reads the timestamp of the first source register from a register (such as register x33) in the register timestamp array 4221 before the retirement of the instruction to be retired; the second read timestamp port 422b reads the timestamp of the second source register from a register (such as register x34) in the register timestamp array 4221 before the retirement of the instruction to be retired; the third read timestamp port 422c reads the timestamp of the second source register from a register (such as register x63) in the register timestamp array 4221 before the retirement of the instruction to be retired. 35) Read the old timestamp of the destination register; the first write timestamp port 422d writes the new timestamp (such as the timestamp corresponding to the value of the first source register) to the first source register when the retirement instruction is completed; the second write timestamp port 422e writes the new timestamp (such as the timestamp corresponding to the value of the second source register) to the second source register when the retirement instruction is completed; the third write timestamp port 422f writes the new timestamp (such as the timestamp corresponding to the new value written to the destination register) to the destination register when the retirement instruction is completed.

[0120] The timestamps read or written by the first read timestamp port 422a, the second read timestamp port 422b, the third read timestamp port 422c, the first write timestamp port 422d, the second write timestamp port 422e, and the third write timestamp port 422f are used to construct the identifier conversion record. Taking the instruction pipeline circuit 411 as a five-stage pipeline circuit as an example, the first read timestamp port 422a, the second read timestamp port 422b, the third read timestamp port 422c, the first write timestamp port 422d, the second write timestamp port 422e, and the third write timestamp port 422f are connected to the write-back part of the instruction pipeline circuit 411. The write-back part obtains the read timestamp and calculates the new timestamp to construct the identifier conversion record, and uses the new timestamp to update the timestamp of the register timestamp array 4221. Continuing with the example of a five-stage pipeline circuit 411, the processor 400 includes a synchronous decoupling trajectory circuit (not shown in the figure) outside the processor core 410. This synchronous decoupling trajectory circuit can be used for asynchronous backfilling of proof trajectory records. For example, it receives incomplete data conversion records and identifier conversion records, fills in the data required for these records, and outputs a complete proof trajectory record after all required data is available. In one example, a register timestamp circuit 422 is connected between the instruction pipeline circuit 411 and the synchronous decoupling trajectory circuit. The write-back portion of the instruction pipeline circuit 411 writes a new timestamp to the register timestamp array 4221 through the first write timestamp port 422d, the second write timestamp port 422e, and the third write timestamp port 422f. The synchronous decoupling trajectory circuit reads the timestamp through the first read timestamp port 422a, the second read timestamp port 422b, and the third read timestamp port 422c, and forms an identifier conversion record in the synchronous decoupling trajectory circuit.

[0121] In one example, the first write timestamp port 422d, the second write timestamp port 422e, and the third write timestamp port 422f are connected to the instruction retirement control logic. For example, the write-back section includes a retirement control circuit 4111. When the retirement control circuit 4111 controls the instruction to be retired to complete its retirement, the instruction pipeline circuit 411 updates the timestamps of the register timestamp array 4221 through the first write timestamp port 422d, the second write timestamp port 422e, and the third write timestamp port 422f. The retirement control circuit 4111 can be the retirement control circuit 111 in the above embodiment.

[0122] In the above scheme, the register timestamp circuit 422 is configured with a ported architecture of three read timestamp ports and three write timestamp ports, realizing hardware-level parallelism of register timestamp access and trajectory data capture. While supporting the efficient execution of native instructions, it provides atomic state transition evidence for the vCPU state machine. Specifically, the three read timestamp ports read the old timestamp in the register timestamp array 4221 before the instruction to be retired, and the three write timestamp ports write the new timestamp to the register timestamp array 4221 when the instruction to be retired completes its retirement. This aligns the lifecycle data of the instruction with the instruction retirement event, ensuring the integrity of the data conversion record. At the same time, this design avoids supplementing the data required for proof through additional microinstructions, software scanning, or multi-cycle register supplementary readings while ensuring instruction execution efficiency. It provides accurate, complete, and time-consistent register state transition evidence for backend proof with extremely low intrusion, effectively supporting the efficient implementation of register dependency verification and multi-chip parallel proof.

[0123] In some embodiments, the register timestamp circuit 422 is further configured to arrange the new timestamp of the first source register, the new timestamp of the second source register, and the new timestamp of the destination register in ascending order according to the global instruction identifier and a preset offset rule.

[0124] The preset offset rule can be to increment the value of the global instruction identifier according to a preset value.

[0125] Taking a global instruction identifier of zk_CLK, a new timestamp for the first source register of rs1_read_tsp, a new timestamp for the second source register of rs2_read_tsp, and a new timestamp for the destination register of rd_write_tsp as an example, rs1_read_tsp = zk_CLK + n1, rs2_read_tsp = zk_CLK + n2, and rd_write_tsp = zk_CLK + n3, where n1 is less than n2, and n2 is less than n3. In one example, n1 = 0, n2 = 1, and n3 = 2.

[0126] Continuing with the example of a global instruction identifier of zk_CLK, a new timestamp for the first source register of rs1_read_tsp, a new timestamp for the second source register of rs2_read_tsp, and a new timestamp for the destination register of rd_write_tsp, the base_timestamp is derived from zk_CLK: rs1_read_tsp = base_timestamp + n4, rs2_read_tsp = base_timestamp + n5, rd_write_tsp = base_timestamp + n6, where n4 is less than n5, n5 is less than n6, and base_timestamp is a preset multiple of zk_CLK. In one example, n4 = 0, n5 = 1, n6 = 2, zk_CLK = 100, and base_timestamp = 400.

[0127] In the above scheme, the read-then-write register access order is encoded in a single instruction by a global instruction identifier and a preset offset rule. The backend only needs to compare the values ​​to verify the timing correctness. From the hardware level, state transition records can be generated that can be used by the backend to prove the vCPU state machine and vRAM state machine.

[0128] In some embodiments, the register timestamp circuit 422 is further configured to, when there are at least two identical register indices in the first source register, the second source register, and the destination register, write new timestamps to the registers corresponding to the at least two identical register indices according to a preset priority, at least two of the first write timestamp port, the second write timestamp port, and the third write timestamp port.

[0129] In one implementation, the preset priority is set to write a new timestamp to the first source register at a lower priority than write a new timestamp to the second source register, and write a new timestamp to the second source register at a lower priority than write a new timestamp to the destination register.

[0130] When two identical register indices exist in the first source register, second source register, and destination register, continuing with the example of a global instruction identifier of zk_CLK, a new timestamp for the first source register of rs1_read_tsp, a new timestamp for the second source register of rs2_read_tsp, and a new timestamp for the destination register of rd_write_tsp, if the index of the first source register is x1, the index of the second source register is x2, and the index of the destination register is x2, then rs1_read_tsp = zk_CLK + n1, rs2_read_tsp = zk_CLK + n3, and rd_write_tsp = zk_CLK + n3, or rs1_read_tsp = base_timestamp + n4, rs2_read_tsp = base_timestamp + n6, and rd_write_tsp = base_timestamp + n6. In one example, n1 = 0, n3 = 1 or 2, n4 = 0, and n6 = 1 or 2.

[0131] When three identical register indices exist in the first source register, second source register, and destination register, continuing with the example of a global instruction identifier of zk_CLK, a new timestamp of the first source register of rs1_read_tsp, a new timestamp of the second source register of rs2_read_tsp, and a new timestamp of the destination register of rd_write_tsp, if the indices of the first source register, second source register, and destination register are all x1, then rs1_read_tsp = zk_CLK + n3, rs2_read_tsp = zk_CLK + n3, and rd_write_tsp = zk_CLK + n3, or rs1_read_tsp = base_timestamp + n6, rs2_read_tsp = base_timestamp + n6, and rd_write_tsp = base_timestamp + n6. In one example, n3 = 0, 1, or 2, and n6 = 0, 1, or 2.

[0132] In the above scheme, when the same instruction accesses registers with the same register index, conflict resolution is performed according to the order of events within the instruction. The timestamp of the last access to the register by the instruction is retained first, eliminating the ambiguity of multiple timestamps for the same register within the same clock cycle and ensuring the reliable proof of the vCPU state machine.

[0133] Please continue reading. Figure 4The instruction status maintenance circuit 420 includes: a memory data cache circuit 423, located in the processor core 410 and connected to the instruction pipeline circuit 411, used to maintain a data conversion record corresponding to the memory event instruction when the type of the instruction to be retired is a memory event instruction; and a memory timestamp cache circuit 424, located in the processor core 410 and connected to the instruction pipeline circuit 411, used to maintain an identifier conversion record corresponding to the memory event instruction when the type of the instruction to be retired is a memory event instruction.

[0134] The memory data cache circuit 423 can be a level-one data cache in the processor 400, used to store data or the mapping relationship between memory addresses and corresponding data. The memory timestamp cache circuit 424 can be a dedicated storage circuit located in the processor core 410, used to store timestamps or the mapping relationship between memory addresses and corresponding timestamps.

[0135] In one implementation, the memory data cache circuit 423 maintains a corresponding data conversion record when the type of the instruction to be retired is a memory event instruction. For example, when the instruction pipeline circuit 411 identifies the type of the instruction to be retired as a memory event instruction, the memory data cache circuit 423 retrieves the old value corresponding to the instruction to be retired, or writes a new value corresponding to the instruction to be retired. The old and new values ​​can be data conversion records, which are both retrieved and stored by the memory data cache circuit 423 and used to construct a proof trajectory record. The memory access involved in the instruction to be retired can be parsed by the instruction pipeline circuit 411; for example, the memory address can be parsed by the instruction pipeline circuit 411.

[0136] In one implementation, the memory timestamp cache circuit 424 is used to maintain a corresponding identifier conversion record when the type of the instruction to be retired is a memory event instruction. For example, when the instruction pipeline circuit 411 identifies the type of the instruction to be retired as a memory event instruction, it obtains the old timestamp corresponding to the instruction to be retired through the memory timestamp cache circuit 424, and writes a new timestamp corresponding to the instruction to be retired through the memory timestamp cache circuit 424. The old and new timestamps can be identifier conversion records, which are both obtained and stored through the memory timestamp cache circuit 424 and used to construct proof trajectory records. The old and new timestamps corresponding to the memory accesses involved in the instruction to be retired can be parsed by the instruction pipeline circuit 411; for example, the memory address corresponding to the old timestamp and the memory address corresponding to the new timestamp can be parsed by the instruction pipeline circuit 411.

[0137] In one implementation, the memory data cache circuit 423 and the memory timestamp cache circuit 424 correspond to each other. For example, the memory data cache circuit 423 and the memory timestamp cache circuit 424 establish a one-to-one mapping relationship through physical address indices. In one example, the physical address index corresponding to cache line A in the memory data cache circuit 423 is AddrX, and the physical address index corresponding to the timestamp storage unit TS Entry B in the memory timestamp cache circuit 424 is also AddrX. Furthermore, for the aforementioned example, the correspondence between the memory data cache circuit 423 and the memory timestamp cache circuit 424 is also reflected in the following: when reading memory data (old value) from cache line A, the corresponding old timestamp can be read from the timestamp storage unit TS Entry B; when writing new memory data (new value) to cache line A, the new timestamp can be written to the timestamp storage unit TS Entry B.

[0138] In the above scheme, the memory data cache circuit 423 is used to maintain data conversion records, and the memory timestamp cache circuit 424 is used to maintain identifier conversion records, generating state transition records that can be proven by the vRAM state machine at the hardware level. Furthermore, the memory data cache circuit 423 and the memory timestamp cache circuit 424 correspond to each other, ensuring that the data conversion records and identifier conversion records correspond to the same instruction, avoiding mismatches in proof trajectory records, and providing accurate register state transition basis for backend proof.

[0139] In some embodiments, the memory event instruction includes a load instruction and a store instruction; the memory data cache circuit 423 is further configured to, in response to the load instruction, read the old memory value from the memory data address region, and the memory timestamp cache circuit 424 is further configured to, in response to the load instruction, read the old memory timestamp from the memory timestamp address region and write the new memory timestamp to the memory timestamp address region; or the memory data cache circuit 423 is further configured to, in response to the store instruction, read the old memory value from the memory data address region and write the new memory value to the memory data address region, and the memory timestamp cache circuit 424 is further configured to, in response to the store instruction, read the old memory timestamp from the memory timestamp address region and write the new memory timestamp to the memory timestamp address region; wherein, the old memory value is used to form a data conversion record, and the old memory timestamp and the new memory timestamp are used to form an identifier conversion record; or the old memory value and the new memory value are used to form a data conversion record, and the old memory timestamp and the new memory timestamp are used to form the identifier conversion record.

[0140] In one implementation, the memory data cache circuit 423 and the memory timestamp cache circuit 424 are used to cache frequently accessed memory data and memory timestamps. When a cache miss occurs, data is retrieved or written to a target storage device via an external bus. The target storage device can be an external storage device connected to the processor 400. For example, the memory data address region and / or the memory timestamp address region can be mapped to DRAM (Dynamic Random Access Memory). Figure 5 As shown. In one example, the memory data cache circuit 423 and the memory timestamp cache circuit 424 are connected to the memory access section of the instruction pipeline circuit 411.

[0141] In one implementation, the memory data cache circuit 423, in response to a load instruction, reads a memory data value (old memory value) from the memory data address region to construct a data transformation record. For example, when the instruction pipeline circuit 411 identifies the instruction type as a load instruction, it accesses the memory data address region through the memory data cache circuit 423 and reads the old memory value.

[0142] The process of reading the old memory value from the memory data address area can be executed by the instruction pipeline circuit 411. For example, the instruction pipeline circuit 411 is a five-stage pipeline circuit. The decoding part parses the base address register (first source register) index and immediate value from the instruction code. In the execution part, the instruction pipeline circuit 411 reads the value of the base address register from the general-purpose register circuit 421 according to the base address register index, and calculates the memory access address based on the value of the base address register and the immediate value. Then, the memory access address is accessed from the memory data address area through the memory data cache circuit 423 to read the old memory value. Furthermore, the old memory value can also be written to the register corresponding to the destination register index in the register file 4211 through the write port 421d of the general-purpose register circuit 421.

[0143] In one implementation, the memory data cache circuit 423, in response to a store instruction, reads the old memory value from the memory data address area and writes the new memory value to that area to construct a data conversion record. For example, when the instruction pipeline circuit 411 identifies the instruction type as a store instruction, the memory data cache circuit 423 accesses the memory data address area, first reads the current data from the memory data address area as the old memory value, and then writes the data to be stored as the new memory value into the memory data address area.

[0144] The read and write operations described above can be executed by the instruction pipeline circuit 411. For example, the instruction pipeline circuit 411 is a five-stage pipeline circuit. The decoding part parses the base address register (such as the first source register) index, the data source register (such as the second source register) index, and the immediate value from the instruction code. In the execution part, the instruction pipeline circuit 411 reads the value of the base address register from the general-purpose register circuit 421 according to the base address register index, reads the data value to be stored from the general-purpose register circuit 421 according to the data source register index, and calculates the memory access address based on the value of the base address register and the immediate value. Then, the memory access address is accessed from the memory data address area through the memory data cache circuit 423. The old memory value is read first, and then the data value to be stored is written as the new memory value to the memory access address.

[0145] In one implementation, the memory timestamp cache circuit 424, in response to a load instruction, reads the old memory timestamp from the memory timestamp address region and writes a new memory timestamp into the memory timestamp address region to construct an identifier conversion record. For example, when the instruction pipeline circuit 411 identifies the instruction type as a load instruction, the memory timestamp cache circuit 424 accesses the memory timestamp address region and reads the old memory timestamp, and then writes a new memory timestamp into the memory timestamp address region.

[0146] The process of reading the old memory timestamp from the memory timestamp address area can be executed by the instruction pipeline circuit 411. For example, the instruction pipeline circuit 411 is a five-stage pipeline circuit. In the memory access section, the instruction pipeline circuit 411 accesses the memory access address through the memory data cache circuit 423, reads the old memory value, and at the same time accesses the address corresponding to the memory access address from the memory timestamp address area through the read timestamp port of the memory timestamp cache circuit 424, reads the old memory timestamp, and then writes the new memory timestamp to the address corresponding to the memory access address in the memory timestamp address area through the write timestamp port of the memory timestamp cache circuit 424.

[0147] In one implementation, the memory timestamp cache circuit 424, in response to a store instruction, reads the old memory timestamp from the memory timestamp address region and writes the new memory timestamp to that region to construct an identifier conversion record. For example, when the instruction pipeline circuit 411 identifies the instruction type as a store instruction, the memory timestamp cache circuit 424 first reads the old memory timestamp from the memory timestamp address region, writes the new memory value, and then writes the new memory timestamp to the memory timestamp address region.

[0148] The aforementioned read and write operations can be executed through the instruction pipeline circuit 411. For example, the instruction pipeline circuit 411 is a five-stage pipeline circuit. In the memory access section, the instruction pipeline circuit 411 accesses the memory access address through the memory data cache circuit 423, reads the current data at that address as the old memory value, and accesses the address corresponding to the memory access address from the memory timestamp address area through the read timestamp port of the memory timestamp cache circuit 424 to obtain the old memory timestamp. When the memory data cache circuit 423 writes a new memory value to the memory access address, the new memory timestamp is written to the address corresponding to the memory access address in the memory timestamp address area through the write timestamp port of the memory timestamp cache circuit 424.

[0149] In the above scheme, the memory data cache circuit 423 and the memory timestamp cache circuit 424 realize the parallel capture and synchronous update of memory business data and metadata (timestamp) at the hardware level, providing a complete state transition record for the vRAM state machine, ensuring the traceability of memory state migration, eliminating the complex alignment and reasoning logic of the back-end software layer, and improving the reliability of back-end proof.

[0150] In some embodiments, the memory timestamp cache circuit 424 is further configured to arrange the old memory timestamp and the new memory timestamp in ascending order according to the global instruction identifier and the preset offset rule.

[0151] The preset offset rule can be to increment the value of the global instruction identifier according to a preset value.

[0152] Taking a global instruction identifier of zk_CLK, an old memory timestamp of mem_read_tsp, and a new memory timestamp of mem_write_tsp as an example, mem_read_tsp = zk_CLK + m1, mem_write_tsp = zk_CLK + m2, where m1 is less than m2. In one example, m1 = 0 and m2 = 1. This offset setting strictly corresponds to the execution sequence of memory event instructions, which read the old value first and then write the new value, ensuring that the timestamp order is consistent with the operation semantics.

[0153] Continuing with the example of a global instruction identifier of zk_CLK, an old memory timestamp of mem_read_tsp, and a new memory timestamp of mem_write_tsp, we derive base_timestamp from zk_CLK: mem_read_tsp = base_timestamp + m3, mem_write_tsp = base_timestamp + m4, where m3 is less than m4, and base_timestamp is a preset multiple of zk_CLK. In one example, m3 = 0, m4 = 1, zk_CLK = 100, and base_timestamp = 400.

[0154] In the above scheme, the read-then-write memory access order is encoded in a single instruction by a global instruction identifier and a preset offset rule. The backend only needs to compare the values ​​to verify the timing correctness. A state transition record that can be used by the backend for vRAM state machine verification is generated from the hardware level.

[0155] In some embodiments, the memory timestamp cache circuit 424 is further configured to obtain a memory timestamp address region according to a preset address mapping rule, so as to read the old memory timestamp from the memory timestamp address region and write the new memory timestamp to the memory timestamp address region.

[0156] The preset address mapping rule can be an address conversion formula between the user data area and the memory timestamp address area.

[0157] For example, tspByteAddr=tspMemBase+((dataAddr-userMemBase)<<1).

[0158] Wherein, userMemBase is the base address of the user data area, dataAddr is the memory access address, tspMemBase is the base address of the memory timestamp, tspByteAddr is the memory timestamp access address, dataAddr-userMemBase represents the byte offset of the user data area base address corresponding to the memory access address, and <<1 indicates a left shift operation of 1 bit on this offset to ensure that every 4 bytes of user data corresponds to 8 bytes of memory timestamp.

[0159] In one example, the memory data address region is the memory data space starting from userMemBase, and the memory timestamp address region is the memory timestamp space starting from tspMemBase.

[0160] In one embodiment, the memory data cache circuit 423 and the memory timestamp cache circuit 424 are implemented by the memory controller to map the target storage device (such as DRAM) into two independent memory address regions. For example, the memory controller located in the processor 400 is connected between the memory data cache circuit 423 and the DRAM, and is also connected between the memory timestamp cache circuit 424 and the DRAM, so that the DRAM is mapped into a memory data address region and a memory timestamp address region.

[0161] In the above scheme, address mapping is used to physically isolate the memory data address area and the memory timestamp address area, thereby improving the hit rate of memory data read / write and memory timestamp read / write. In particular, it enables the division of the same storage device into independent memory data address areas and memory timestamp address areas, thereby reducing costs.

[0162] Please see Figure 6-9 , Figure 6 This is a schematic diagram of the structure of a zero-knowledge proof system according to some embodiments of this application. Figure 1 , Figure 7 This is a schematic diagram of the structure of a zero-knowledge proof system according to some embodiments of this application. Figure 2 , Figure 8 This is a schematic diagram of the zero-knowledge proof process for some embodiments of this application. Figure 1 , Figure 9 This is a schematic diagram of the zero-knowledge proof process for some embodiments of this application. Figure 2 ,in, Figures 8-9 These are two examples of numerous zero-knowledge proof process embodiments in this application. The zero-knowledge proof system 600 includes: a host 610, used to provide a program, input parameters, and configuration data, the program including at least one instruction; an on-chip system 620, used to acquire the program, input parameters, and configuration data, and generate a proof trajectory record corresponding to at least one instruction; and a proof circuit 630, used to acquire the proof trajectory record, and after generating proof data corresponding to the proof trajectory record, return the proof data to the host.

[0163] The host 610 can be a control-side electronic device in the zero-knowledge proof system 600 responsible for controlling and managing the proof task. In one embodiment, the host 610 includes, but is not limited to, a host CPU, host DDR (Double Data Rate Synchronous Dynamic Random-Access Memory), an operating system, a ZKTrace application, a PCIe driver, a task scheduling module, and a shared memory management module.

[0164] The program can be a user program, that is, a program to be proven, which includes at least one instruction. In one implementation, the host 610 compiles the program into a preset format file, such as a RISC-V ELF format file.

[0165] Input parameters can be a collective term for program input data provided by the host that the program to be proven depends on when executing zero-knowledge proof. In one implementation, input parameters include, but are not limited to, common proof inputs and nondeterministic inputs.

[0166] Configuration data can be data used to initialize and manage the hardware resources of the zero-knowledge proof system. In one implementation, the configuration data includes configuring multiple regions. For example, the configuration data includes, but is not limited to: the base address and size of the user program area, the base address and size of the memory timestamp area, the base address and length of the proof trajectory record output area, and other system configuration parameters.

[0167] The system-on-a-chip 620 includes, but is not limited to, the processor 100 or processor 400 in the above embodiments.

[0168] In one implementation, the system-on-chip 620 is connected to a host 610 to obtain programs, input parameters, and configuration data from the host 610. Further, the system-on-chip 620 generates a proof trajectory record corresponding to at least one instruction. The proof trajectory record can be used for zero-knowledge proofs. The number of proof trajectory records can be equal to or less than the number of at least one instruction. For details on how to generate the proof trajectory records, please refer to the above embodiments; further details will not be repeated here.

[0169] The proof circuit 630 can be an integrated circuit in the zero-knowledge proof system 600 responsible for proving the proof trajectory record to generate proof data.

[0170] In one implementation, the proof circuit 630 includes, but is not limited to, a GPU (Graphics Processing Unit), an FPGA (Field-Programmable Gate Array), an ASIC (Application-Specific Integrated Circuit), or other programmable parallel computing devices.

[0171] In one implementation, the proof circuit 630 acquires proof trajectory records. For example, the proof circuit 630 is connected to the system-on-a-chip 620 to acquire proof trajectory records from the system-on-a-chip 620. Another example is that the proof circuit 630 reads proof trajectory records from a preset storage area, where the preset storage area can be the storage area of ​​a storage device in the host 610, i.e., the proof circuit 630 is connected to the host 610. Figure 6 As shown. The preset storage area can also be the storage area of ​​an independent storage device, where the on-chip system 620 outputs the proof trajectory record to the storage area after generating the proof trajectory record.

[0172] In one implementation, the proof circuit 630 generates proof data based on the proof trajectory record and returns the proof data to the host 610, such as... Figure 6 As shown, the proof circuit 630 is connected to the host 610. The proof circuit 630 directly transmits the proof data to the host 610, or the proof circuit 630 outputs the proof data to a storage area in an independent storage device accessible to the host 610, so that the host 610 can read the proof data from that storage area. Furthermore, the proof circuit 630 can notify the host 610 via MSI-X (Extended Message Signaled Interrupts). When handling this interrupt, the host 610 can perform buffer refresh operations and memory cache invalidation operations to read the latest proof data.

[0173] In one embodiment, the proof circuit 630 performs a preset proof data generation operation to generate proof data. The preset proof data generation operation includes, but is not limited to, columnarizing, sorting, calculating permutation parameters, calculating search parameters, and calculating polynomial commitments on the proof trajectory record according to the constraints in the proof circuit 630.

[0174] In the above solution, the efficient flow of the entire process from the issuance to the generation of zero-knowledge proof tasks is realized through a three-level collaborative architecture of host 610, system-on-chip 620 and proof circuit 630. At the same time, the output proof trajectory record has completeness, order and semantic compliance, taking into account both execution efficiency and proof reliability, and providing feasible hardware support for the large-scale implementation of zero-knowledge proof.

[0175] In some embodiments, the host 610 is also configured to write the program, input parameters, and configuration data to shared memory, and perform a cache refresh operation after the writing is complete.

[0176] The shared memory can be a storage area accessible and writable by the host 610 and / or the system-on-chip 620 and / or the verification circuit 630. For example, the shared memory includes at least one of the following: a storage area within the host 610, a storage area within the system-on-chip 620, a storage area in the verification circuit 630, and an external storage device (such as DRAM).

[0177] In one example, the shared memory includes at least a separate input data area, a trajectory result collection area, and a proof data area. The input data area is used to store the program, input parameters, and configuration data provided by the host 610; the trajectory result collection area is used to store the proof trajectory records generated by the system-on-chip 620; and the proof data area is used to store the proof data generated by the proof circuit 630.

[0178] The trajectory result collection area can be further subdivided into multiple result collection areas. For example, it may include a result collection area for storing proof trajectory records, a result collection area for storing final state auxiliary trajectory records, and a result collection area for storing timestamp final state and result header information. The specific design can be based on the structure of the data related to the proof task that the System-on-Chip 620 can generate. The final state auxiliary trajectory records may include a memory final state data set and a register final state data set.

[0179] Furthermore, after the host 610 writes the program, input data, and configuration data to the shared memory, it performs a cache refresh operation to ensure that the latest data is written back to the shared memory from the host 610's cache. This ensures that the subsequent system-on-chip 620 accurately retrieves the program, input parameters, and configuration data from the shared memory. Additionally, after performing the cache refresh operation, a memory barrier operation can be performed to ensure that the program, input parameters, and configuration data are globally visible to the system-on-chip 620.

[0180] In the above solution, shared memory balances cross-device interaction efficiency and reliability, and in conjunction with the host 610 cache refresh mechanism, it prevents data from becoming outdated and is compatible with various certifications.

[0181] In some embodiments, the host 610 is further configured to send a trajectory generation start signal to the system-on-chip 620; the system-on-chip 620 is further configured to, upon receiving the trajectory generation start signal, acquire the program, input parameters and configuration data, and generate a proof trajectory record corresponding to at least one instruction.

[0182] In some implementations, after performing a preset operation (such as a cache refresh operation and / or a memory barrier operation), the host 610 sends a trace generation start signal to the system-on-chip 620, for example, by notifying the system-on-chip 620 to start via a PCIe doorbell or control register.

[0183] In some implementations, the system-on-chip 620 acquires the program, input parameters, and configuration data according to a preset reading method. For example, the read interface of the system-on-chip 620 is configured in a non-buffered or strongly ordered mode to directly read the program, input parameters, and configuration data, bypassing obsolete caches. Furthermore, a proof trajectory record corresponding to at least one instruction is generated, as described in the above embodiments, and will not be repeated here.

[0184] In the above scheme, the host 610 triggers the transmission of the trajectory generation start signal only after performing a preset operation. The on-chip system 620 responds to the signal and starts data acquisition and proof trajectory record generation. This establishes a cross-device task triggering timing between the host 610 and the on-chip system 620. Furthermore, the host 610 sends the trajectory generation start signal only after performing the preset operation, which avoids the on-chip system 620 starting prematurely before the data is ready, thus preventing the reading of outdated data and ensuring the accuracy and completeness of the proof trajectory record generation.

[0185] In some embodiments, the system-on-chip 620 is further configured to send a trajectory generation end signal to the host 610 after generating a proof trajectory record corresponding to at least one instruction, so as to start the proof circuit 630 through the host 610.

[0186] In one implementation, after generating a proof trace record corresponding to at least one instruction, the on-chip system 620 generates an end signal via a PCIe MSI-X interrupt, completion register, or doorbell to notify the host 610 that a proof trace record corresponding to at least one instruction has been generated. Subsequently, the host 610 starts the proof circuit 630 to generate proof data based on the proof trace record.

[0187] In the above scheme, the closed-loop mechanism of the host 610 starting the proof circuit 630 is triggered by the end signal generated by the on-chip system 620, which further reduces the system idle waiting time and eliminates the computing power overhead of the host 610 polling the state. At the same time, the timing boundary from trajectory readiness to proof start is strictly locked by hardware signals to ensure that the data obtained by the proof circuit 630 is complete and valid.

[0188] In some embodiments, the host 610 is further configured to perform a memory barrier operation after receiving a trajectory generation end signal, and send a proof start signal to the proof circuit 630 after performing the memory barrier operation to start the proof circuit 630.

[0189] The memory barrier operation is used to ensure that the proof trajectory record is globally visible to the proof circuit 630.

[0190] In one implementation, the read interface of the proof circuit 630 is configured in an unbuffered or strongly ordered mode to directly read the complete proof trajectory record, for example, by reading the proof trajectory record from the trajectory result collection area.

[0191] In the above scheme, after receiving the trajectory generation end signal, the host 610 executes a memory barrier to ensure that the proof trajectory record output by the on-chip system 620 has been completely written to the shared memory, avoiding the risk of out-of-order transmission where the proof start signal is globally visible before the proof trajectory record. Furthermore, with the non-cached / strongly ordered read configuration of the proof circuit 630, there is no need to deploy a complex cross-device cache consistency protocol, which reduces the complexity of hardware implementation and avoids proof verification failure caused by incomplete or out-of-order trajectory data from the source, further improving the reliability of system operation and the success rate of tasks.

[0192] In some embodiments, the proof circuit 630 is further configured to write the proof data into shared memory after generating proof data corresponding to the proof trajectory record, and send a proof completion signal to the host 610.

[0193] As described in the above embodiments, the proof data can be written to the proof data area in shared memory. Then, after the proof data writing is complete, a proof completion signal is sent to the host 610, so that the host 610 can read the latest proof data.

[0194] In the above scheme, the task progress is precisely synchronized by hardware signals, avoiding host polling overhead and ensuring that the host can read the latest valid content only after the proof data is completely written to disk. Furthermore, the unified shared memory interface is compatible with various proof devices, further improving the closed loop of heterogeneous collaborative zero-knowledge proof tasks.

[0195] Please see Figure 10 and combined Figure 11-13 , Figure 10 This is a flowchart illustrating the proof state generation method of some embodiments of this application. Figure 11 This is a flowchart illustrating the global instruction identifier and timestamp maintenance mechanism of some embodiments of this application. Figure 12 This is a flowchart illustrating the consistency proof of the vCPU state machine and vRAM state machine in some embodiments of this application. Figure 13 This is a schematic diagram illustrating the memory timestamp address mapping process in some embodiments of this application, wherein, Figures 11-13These are three examples from numerous embodiments of the proof state generation process in this application. This method can be applied to processors, systems-on-a-chip (SoCs), electronic devices, etc., for example, to processor 100, processor 400, or SoC 620. Specifically, the relevant steps in this method can be executed by specific circuits in processor 100, processor 400, or SoC 620. The processor can be a CPU, specifically implemented based on a reduced instruction set architecture (RISC). In one specific embodiment, the processor can be a RISC-V-based processor configured to execute a user program and generate corresponding proof states to construct a proof trajectory record. The processor can be integrated into an SoC or located in an electronic device, and the SoC can also be located in an electronic device. The electronic device can be a computer, and the electronic device can execute the method through a processor or SoC, or it can implement the method through a program. In the method steps, the processor or SoC is used as the execution subject for description. The method includes the following steps: Step S101: Execute the instruction and obtain the retirement instruction.

[0196] A pending retirement instruction can be an instruction that is being executed in a user program but has not yet been retired. For example, a pending retirement instruction could be an instruction that has entered the write-back phase and is waiting to retire.

[0197] Step S102: When the retirement instruction is completed, generate a unique and monotonically increasing global instruction identifier, and maintain the data conversion record and identifier conversion record of the retirement instruction.

[0198] Global instruction identifiers include, but are not limited to, unique and monotonically increasing data such as counters, timestamps, and sequence numbers. Furthermore, global instruction identifiers possess system-level global visibility, for example, global visibility in heterogeneous systems.

[0199] Taking the sequential retrieval and execution of instructions A, B, and C from the user program as an example, when instruction A retires, a global instruction identifier id1 corresponding to instruction A is generated; when instruction B retires, a global instruction identifier id2 corresponding to instruction B is generated; and when instruction C retires, a global instruction identifier id3 corresponding to instruction C is generated. Instruction A retires before instruction B, instruction B retires before instruction C, and id1 < id2 < id3.

[0200] A data transformation record can include a record of the data transformations corresponding to an instruction generated by its execution. For example, if the original data is V1, executing the instruction transforms the original data V1 into V2. The original data V1 is different from the transformed data V2; that is, the data transformation record can include both the original data V1 and the transformed data V2. In one example, the data transformation record includes register data and / or memory data.

[0201] An identifier translation record may include a record of identifier translations corresponding to an instruction generated by the execution of that instruction. For example, if the original identifier is D1, executing the instruction will transform the original identifier D1 into D2. The original identifier D1 is different from the transformed identifier D2. That is to say, the identifier translation record may include both the original identifier D1 and the transformed identifier D2. In one example, the identifier translation record includes register identifiers and / or memory identifiers. More specifically, the identifier translation record may include register timestamps and / or memory timestamps.

[0202] In one embodiment, a data conversion record and an identifier conversion record correspond. For example, the data conversion record includes register data and / or memory data, and the identifier conversion record may include an identifier corresponding to the register data and / or an identifier corresponding to the memory data. In one example, the register data includes register read values ​​and register write values, and the identifier conversion record includes a timestamp corresponding to the register read value and another timestamp corresponding to the register write value. In another example, the memory data includes memory read values ​​and memory write values, and the identifier conversion record includes a timestamp corresponding to the memory read value and another timestamp corresponding to the memory write value.

[0203] Step S103: Construct a proof trajectory record based on the global instruction identifier, data conversion record, and identifier conversion record.

[0204] The global instruction identifier, data conversion record, and identifier conversion record are used to construct the proof trajectory record. The proof trajectory record can be a data form of instruction execution evidence structure, including a data set automatically captured and constructed from relevant data generated by the executed instruction, used to record and prove the instruction execution process and results. In different implementations or application scenarios, the proof trajectory record can also be called a trajectory record, operation log, execution total, verification data packet, etc.

[0205] The proof trajectory record includes, but is not limited to, global instruction identifiers, data conversion records, and identifier conversion records, which can be added according to design requirements. For example, the proof trajectory record may also include the following trajectory fields: valid, used to indicate whether this proof trajectory record is valid; pc, used to record the program counter address of the instruction; inst, used to record the opcode and operand encoding of the instruction.

[0206] In the above scheme, generating a unique and monotonically increasing global instruction identifier consistent with the instruction retirement semantics ensures that the update of the architecture state by the instruction and the generation of the proof trajectory record are inseparable atomic events, guaranteeing that the proof trajectory record is completely consistent with the actual execution semantics of the program. Furthermore, by establishing a globally unique timing benchmark, the strong order of the trajectory is guaranteed, providing a unified timing reference for the vCPU state machine and vRAM state machine, satisfying consistency proof. Simultaneously, by generating explicit global instruction identifiers, the global order of instructions remains strictly controllable even under complex backend proof logic, reducing the additional overhead caused by software-layer timestamp alignment, improving the overall throughput and response speed of the system, and meeting the urgent need for high-performance proof systems in blockchain scaling and decentralized computing. Maintaining data conversion records and identifier conversion records corresponding to the instructions records the details of state changes during instruction execution, solving the problem of proof failure due to the lack of traceable timing evidence, and providing indispensable data support for register consistency proof of the vCPU state machine and memory consistency proof of the vRAM state machine. Thus, it is proven that the global instruction identifier, data conversion record, and identifier conversion record in the trajectory record provide reliable, ordered, and semantically consistent execution witness data for the backend proof.

[0207] In some embodiments, generating a unique and monotonically increasing global instruction identifier when the instruction to be retired completes retirement includes: causing the instruction to be retired to complete retirement when the instruction to be retired meets preset retirement conditions, and generating a unique and monotonically increasing global instruction identifier.

[0208] The pre-set retirement conditions can be at least one of the following.

[0209] In one implementation, the preset retirement conditions are set according to the instruction retirement semantics. For example, when the instruction to be retired meets the conditions of instruction validity, no relapse, and no exception, the instruction to be retired is retired and a unique and monotonically increasing global instruction identifier is generated.

[0210] In one implementation, preset retirement conditions are set based on information related to the instruction. For example, it is determined whether the address of the instruction to be retired is located in a preset address region. If the instruction to be retired is located in the preset address region, the instruction to be retired is retired, and a unique and monotonically increasing global instruction identifier is generated. In one example, the preset address region may be a preset user program address region. The program counter address of the instruction to be retired is obtained, and it is determined whether the program counter address belongs to the preset user program address region. The size of the preset user program address region can be adjusted according to design requirements.

[0211] In one implementation, the preset retirement conditions are set based on data conversion records and / or identifier conversion records. For example, for load instructions, if the old value and / or timestamp corresponding to the memory access address is not read, the instruction to be retired cannot be retired; for store instructions, if the old value and / or timestamp corresponding to the memory write address is not read, the instruction to be retired cannot be retired.

[0212] In one implementation, the preset retirement conditions are set based on the consumption status of the consumer. For example, if the consumer continuously consumes proof trajectory records, and if the consumer can no longer consume a new proof trajectory record, the retirement instruction cannot be retired, and the transmission of the proof trajectory record for that retirement instruction to the consumer will cease. In one example, when the consumer can no longer consume a new proof trajectory record, it continuously sends a signal to pause the transmission of proof trajectory records, indicating that the transmission of proof trajectory records can continue without receiving this signal, and will stop upon receiving this signal.

[0213] The above scheme achieves deep coupling and refined control between instruction retirement and trajectory generation through multi-dimensional preset retirement conditions. Determining whether an instruction is to be retired based on retirement semantics ensures the compliance and security of the trajectory; determining whether an instruction is to be retired based on its address ensures that instructions within the legitimate user address space are allowed to retire and generate proof trajectory records, preventing illegal proofs and information leaks; determining whether an instruction is to be retired based on the data in the proof trajectory records avoids ghost instructions or incomplete trajectory issues caused by missing key data, ensuring that each output proof trajectory record has complete data support, meeting the stringent requirements of backend proof for input determinism; determining whether an instruction is to be retired based on the consumption status at the consumer end effectively prevents data overflow, packet loss, or state machine crashes caused by mismatched upstream and downstream processing rates, ensuring the continuous and stable operation of the system under long-term operation or high-load scenarios. Simultaneously, the multi-level judgment logic provides extremely high flexibility for the processor architecture, meeting diverse needs and adapting to various proof scenarios.

[0214] In some embodiments, maintaining data conversion records and identifier conversion records for retirement instructions includes: maintaining data conversion records and identifier conversion records corresponding to the type of retirement instruction, based on the type of retirement instruction.

[0215] The data conversion record can include read values ​​and write-back values, and the identifier conversion record can include old timestamps and new timestamps. For example, read values ​​and write values ​​during instruction execution, as well as old timestamps and new timestamps during instruction execution. The timestamp corresponding to the read value can be the old timestamp, and the timestamp corresponding to the write value can be the new timestamp. In one example, the read value can be the value stored in a register or the value corresponding to a memory address; the write value can be the value that needs to be written to the register or memory address; the old timestamp can be the timestamp corresponding to the last write operation performed on the register or memory address; and the new timestamp can be the timestamp corresponding to the read or write operation on the register or memory address.

[0216] For different instruction types, the corresponding data conversion records and identifier conversion records are different. For example, for register event instructions (such as ordinary arithmetic instructions), only register read and write operations are involved, and the old timestamp and new timestamp are only related to register read and write operations. For memory event instructions (such as load instructions and store instructions), both register read operations, or read and write operations, and memory address read or write operations are involved.

[0217] In the above scheme, data conversion records and identifier conversion records are maintained differently according to the type of instruction to be retired, achieving precise matching between trajectory records and instruction execution semantics, and providing accurate verification basis for state changes of vCPU state machine and vRAM state machine. Meanwhile, the structured and typed records are naturally adapted to different verification logics such as backend arithmetic constraints, memory consistency constraints, and control flow constraints, eliminating the overhead of instruction parsing and field extraction in the backend software layer, and can efficiently support the implementation of complex scenarios such as permutation proof and multi-chip parallel proof. Furthermore, this design reserves extended adaptation interfaces for instruction types, flexibly supporting the record generation needs of various standard extensions or custom instruction sets without modifying the core architecture, significantly improving the processor's architectural compatibility and scenario adaptability.

[0218] In some embodiments, depending on the type of the retirement instruction, maintaining a data conversion record and an identifier conversion record corresponding to the type of the retirement instruction includes: maintaining a data conversion record and an identifier conversion record corresponding to the register event instruction in response to the type of the retirement instruction being a register event instruction; or maintaining a data conversion record and an identifier conversion record corresponding to the memory event instruction in response to the type of the retirement instruction being a memory event instruction.

[0219] Take the register event instruction as an example, which is a normal arithmetic instruction.

[0220] When the instruction to be retired is a normal arithmetic instruction, the data conversion record corresponding to the normal arithmetic instruction should include at least the old value of source register 1, the old value of source register 2, the old value of the destination register, and the write-back value of the destination register; the identifier conversion record corresponding to the normal arithmetic instruction should include at least the old timestamp of source register 1, the old timestamp of source register 2, the old timestamp of the destination register, and the new timestamp of source register 1, the new timestamp of source register 2, and the new timestamp of the destination register. The old timestamp can be the timestamp corresponding to the last time source register 1 / source register 2 / destination register was written to, and the new timestamp can be the timestamp corresponding to the time the normal arithmetic instruction reads / writes to source register 1 / source register 2 / destination register.

[0221] Taking memory event instructions as an example, which are load and store instructions.

[0222] When the instruction to be retired is a load instruction, the data translation record corresponding to the load instruction should include at least the old value of source register 1, the read value of the memory access address, the old value of the destination register, and the write-back value. The identifier translation record corresponding to the load instruction should include at least the old timestamp of source register 1, the old timestamp of the memory access address, the old timestamp of the destination register, and the new timestamps of source register 1, the memory access address, and the destination register. The old timestamp can be the timestamp corresponding to the last time source register 1 / memory access address / destination register was written, and the new timestamp can be the timestamp corresponding to when the load instruction reads / writes to source register 1, memory access address, and destination register. In one example, source register 1 is the base address register.

[0223] When the instruction to be retired is a store instruction, the data translation record corresponding to the store instruction should include at least the old value of source register 1, the old value of source register 2, the old value of the memory write address, and the written value. The identifier translation record corresponding to the store instruction should include at least the old timestamp of source register 1, the old timestamp of source register 2, the old timestamp of the memory write address, and the new timestamps of source register 1, source register 2, and the memory write address. The old timestamp can be the timestamp corresponding to the last time source register 1 / source register 2 / memory write address was written, and the new timestamp can be the timestamp corresponding to when the store instruction reads / writes to source register 1, source register 2, and the memory write address. In one example, source register 1 is a base address register.

[0224] In the above scheme, data conversion records and identifier conversion records are maintained in a refined manner according to the type of instruction to be retired. This translates the differentiated record rules into verifiable semantics field by field, achieving precise matching between records and the semantics of various instruction executions. This provides a complete and traceable verification basis for the state transitions of the vCPU state machine and vRAM state machine. Simultaneously, the fully structured, typed records naturally adapt to multi-dimensional verification logic such as backend register read / write dependency verification, memory consistency constraints, and control flow jump verification. This eliminates the overhead of instruction parsing, field completion, and alignment in the backend software layer, efficiently supporting low-latency implementation in complex scenarios such as permutation arguments and multi-chip parallel proofs. Furthermore, this design reserves an instruction type extension mapping interface, allowing seamless adaptation to the record generation needs of various standard extensions or custom instruction sets without modifying the core architecture, significantly improving the processor's architectural compatibility and multi-scenario adaptability.

[0225] In some embodiments, in response to the type of the instruction to be retired being a register event instruction, maintaining a data conversion record and an identifier conversion record corresponding to the register event instruction includes: reading a first source register value, a second source register value, and an old value of the destination register from the register file before the instruction to be retired, and writing a new value of the destination register to the register file when the instruction to be retired is completed, wherein the first source register value, the second source register value, the old value of the destination register, and the new value of the destination register are used to form a data conversion record; and reading a first source register timestamp, a second source register timestamp, and an old timestamp of the destination register from the register timestamp array before the instruction to be retired, and writing a new timestamp of the first source register, a new timestamp of the second source register, and a new timestamp of the destination register to the register timestamp array when the instruction to be retired is completed, wherein the first source register timestamp, the second source register timestamp, the old timestamp of the destination register, and the new timestamp of the first source register, the new timestamp of the second source register, and the new timestamp of the destination register are used to form an identifier conversion record.

[0226] A register file can include multiple registers, for example, 32 registers. Each register stores register-related business data, such as data that is instruction-dependent and can be fetched and / or modified by instructions.

[0227] In one implementation, the register file has multiple registers configured with three read ports and one write port to update the register file while maintaining data conversion records. Taking 32 registers (x0 to x31) as an example, the first read port reads the first source register value from a register (e.g., register x1) in registers x0 to x31 before the retirement of the instruction to be retired. The second read port reads the second source register value from a register (e.g., register x2) in registers x0 to x31 before the retirement of the instruction to be retired. The third read port reads the old value of the destination register from a register (e.g., register x3) in registers x0 to x31 before the retirement of the instruction to be retired. The write port writes the new value (e.g., the value calculated based on the value of register x1 and register x2) to a register (e.g., register x3) in registers x0 to x31 when the retirement of the instruction to be retired is completed.

[0228] The first source register value, the second source register value, the old value of the destination register, and the new value of the destination register are used to form a data conversion record.

[0229] A register timestamp array may include multiple registers or memory locations, for example, 32 registers. Each register can be used to store a register timestamp, such as an instruction-related timestamp that can be fetched and / or overwritten by an instruction. Furthermore, each register may correspond to a register in a register file; for example, the 32 registers in the register timestamp array may each correspond to a register in a register file.

[0230] In one implementation, the register timestamp array is configured with three read timestamp ports and three write timestamp ports to update the timestamp array while maintaining identifier conversion records. Taking registers x32~x63 as an example, the first read timestamp port reads the first source register timestamp from a register in the register timestamp array (such as register x33) before the instruction to be retired; the second read timestamp port reads the second source register timestamp from a register in the register timestamp array (such as register x34) before the instruction to be retired; the third read timestamp port reads the old timestamp of the destination register from a register in the register timestamp array (such as register x35) before the instruction to be retired; the first write timestamp port writes the new timestamp (such as the timestamp corresponding to the reading of the first source register value) to the first source register (such as register x33) when the instruction to be retired is completed; the second write timestamp port writes the new timestamp (such as the timestamp corresponding to the reading of the second source register value) to the second source register (such as register x34) when the instruction to be retired is completed; the third write timestamp port writes the new timestamp (such as the timestamp corresponding to writing the new value to the destination register) to the destination register (such as register x35) when the instruction to be retired is completed.

[0231] The timestamps of the first source register, the second source register, the old timestamp of the destination register, the new timestamps of the first source register, the new timestamps of the second source register, and the new timestamps of the destination register are used to form the identifier conversion record.

[0232] The above scheme achieves hardware-level parallelism in register business data access and register timestamp access with trajectory data capture. While supporting efficient execution of native instructions, it provides atomic state transition evidence for the vCPU state machine. The lifecycle data of instructions is aligned with instruction retirement events, ensuring the integrity of data conversion records and identifier conversion records. At the same time, while ensuring instruction execution efficiency, this design avoids supplementing the data required for proof through additional microinstructions, software scanning, or multi-cycle register reads. It provides accurate, complete, and time-consistent register state transition evidence for backend proof with extremely low intrusion, effectively supporting the efficient implementation of register dependency verification and multi-chip parallel proof.

[0233] In some embodiments, the new timestamp of the first source register, the new timestamp of the second source register, and the new timestamp of the destination register are arranged in ascending order according to the global instruction identifier and a preset offset rule.

[0234] The preset offset rule can be to increment the value of the global instruction identifier according to a preset value.

[0235] Taking a global instruction identifier of zk_CLK, a new timestamp for the first source register of rs1_read_tsp, a new timestamp for the second source register of rs2_read_tsp, and a new timestamp for the destination register of rd_write_tsp as an example, rs1_read_tsp = zk_CLK + n1, rs2_read_tsp = zk_CLK + n2, and rd_write_tsp = zk_CLK + n3, where n1 is less than n2, and n2 is less than n3. In one example, n1 = 0, n2 = 1, and n3 = 2.

[0236] Continuing with the example of a global instruction identifier of zk_CLK, a new timestamp for the first source register of rs1_read_tsp, a new timestamp for the second source register of rs2_read_tsp, and a new timestamp for the destination register of rd_write_tsp, the base_timestamp is derived from zk_CLK: rs1_read_tsp = base_timestamp + n4, rs2_read_tsp = base_timestamp + n5, rd_write_tsp = base_timestamp + n6, where n4 is less than n5, n5 is less than n6, and base_timestamp is a preset multiple of zk_CLK. In one example, n4 = 0, n5 = 1, n6 = 2, zk_CLK = 100, and base_timestamp = 400.

[0237] In the above scheme, the read-then-write register access order is encoded in a single instruction by a global instruction identifier and a preset offset rule. The backend only needs to compare the values ​​to verify the timing correctness. From the hardware level, state transition records can be generated that can be used by the backend to prove the vCPU state machine and vRAM state machine.

[0238] In some embodiments, when there are at least two identical register indices corresponding to the new timestamp in the first source register, the new timestamp in the second source register, and the new timestamp in the destination register, a new timestamp is written to the registers corresponding to the at least two identical register indices according to a preset priority.

[0239] In one implementation, the preset priority is set to write a new timestamp to the first source register at a lower priority than write a new timestamp to the second source register, and write a new timestamp to the second source register at a lower priority than write a new timestamp to the destination register.

[0240] When two identical register indices exist in the first source register, second source register, and destination register, continuing with the example of a global instruction identifier of zk_CLK, a new timestamp for the first source register of rs1_read_tsp, a new timestamp for the second source register of rs2_read_tsp, and a new timestamp for the destination register of rd_write_tsp, if the index of the first source register is x1, the index of the second source register is x2, and the index of the destination register is x2, then rs1_read_tsp = zk_CLK + n1, rs2_read_tsp = zk_CLK + n3, and rd_write_tsp = zk_CLK + n3, or rs1_read_tsp = base_timestamp + n4, rs2_read_tsp = base_timestamp + n6, and rd_write_tsp = base_timestamp + n6. In one example, n1 = 0, n3 = 1 or 2, n4 = 0, and n6 = 1 or 2.

[0241] When three identical register indices exist in the first source register, second source register, and destination register, continuing with the example of a global instruction identifier of zk_CLK, a new timestamp of the first source register of rs1_read_tsp, a new timestamp of the second source register of rs2_read_tsp, and a new timestamp of the destination register of rd_write_tsp, if the indices of the first source register, second source register, and destination register are all x1, then rs1_read_tsp = zk_CLK + n3, rs2_read_tsp = zk_CLK + n3, and rd_write_tsp = zk_CLK + n3, or rs1_read_tsp = base_timestamp + n6, rs2_read_tsp = base_timestamp + n6, and rd_write_tsp = base_timestamp + n6. In one example, n3 = 0, 1, or 2, and n6 = 0, 1, or 2.

[0242] In the above scheme, when the same instruction accesses registers with the same register index, conflict resolution is performed according to the order of events within the instruction. The timestamp of the last access to the register by the instruction is retained first, eliminating the ambiguity of multiple timestamps for the same register within the same clock cycle and ensuring the reliable proof of the vCPU state machine.

[0243] In some embodiments, in response to a memory event instruction being retired, maintaining a data conversion record and an identifier conversion record corresponding to the memory event instruction includes: in response to a load instruction corresponding to the memory event instruction, reading the old memory value from the memory data address region, reading the old memory timestamp from the memory timestamp address region, and writing the new memory timestamp to the memory timestamp address region; or in response to a store instruction corresponding to the memory event instruction, reading the old memory value from the memory data address region, writing the new memory value to the memory data address region, and reading the old memory timestamp from the memory timestamp address region, and writing the new memory timestamp to the memory timestamp address region; wherein the old memory value is used to form a data conversion record, and the old memory timestamp is used to form an identifier conversion record; or the old memory value and the new memory value are used to form a data conversion record, and the old memory timestamp and the new memory timestamp are used to form an identifier conversion record.

[0244] In one implementation, in response to a load instruction, an old memory value is read from a memory data address region, and an old memory timestamp is read from a memory timestamp address region. A new memory timestamp is then written to the memory timestamp address region to construct a data conversion record and an identifier conversion record. For example, the load instruction is parsed to obtain a memory access address, and the old memory value is read from the memory data address region based on the memory access address. Simultaneously, the old memory timestamp is read from the memory timestamp address region at the address corresponding to the memory access address, and the new memory timestamp corresponding to the read old memory value is written to the memory timestamp address region at the address corresponding to the memory access address.

[0245] In one implementation, in response to a store instruction, an old memory value is read from the memory data address region and a new memory value is written to the memory data address region; similarly, an old memory timestamp is read from the memory timestamp address region and a new memory timestamp is written to the memory timestamp address region to construct a data conversion record and an identifier conversion record. For example, the store instruction is parsed to obtain a memory access address, and the old memory value is read from the memory data address region based on the memory access address. Simultaneously, the old memory timestamp is read from the memory timestamp address region at the address corresponding to the memory access address. Then, the new memory value is written to the memory data address region based on the memory access address, and the new memory timestamp corresponding to this write is written to the memory timestamp address region at the address corresponding to the memory access address.

[0246] The above scheme achieves parallel capture and synchronous update of in-memory business data and metadata (timestamps), provides a complete state transition record for the vRAM state machine, ensures the traceability of in-memory state migration, eliminates the complex alignment and reasoning logic of the backend software layer, and improves the reliability of backend proof.

[0247] In some embodiments, the old memory timestamp and the new memory timestamp are arranged in ascending order according to the global instruction identifier and a preset offset rule.

[0248] The preset offset rule can be to increment the value of the global instruction identifier according to a preset value.

[0249] Taking a global instruction identifier of zk_CLK, an old memory timestamp of mem_read_tsp, and a new memory timestamp of mem_write_tsp as an example, mem_read_tsp = zk_CLK + m1, mem_write_tsp = zk_CLK + m2, where m1 is less than m2. In one example, m1 = 0 and m2 = 1. This offset setting strictly corresponds to the execution sequence of memory event instructions, which read the old value first and then write the new value, ensuring that the timestamp order is consistent with the operation semantics.

[0250] Continuing with the example of a global instruction identifier of zk_CLK, an old memory timestamp of mem_read_tsp, and a new memory timestamp of mem_write_tsp, we derive base_timestamp from zk_CLK: mem_read_tsp = base_timestamp + m3, mem_write_tsp = base_timestamp + m4, where m3 is less than m4, and base_timestamp is a preset multiple of zk_CLK. In one example, m3 = 0, m4 = 1, zk_CLK = 100, and base_timestamp = 400.

[0251] In the above scheme, the read-then-write memory access order is encoded in a single instruction by a global instruction identifier and a preset offset rule. The backend only needs to compare the values ​​to verify the timing correctness. A state transition record that can be used by the backend for vRAM state machine verification is generated from the hardware level.

[0252] In some embodiments, a memory timestamp address region is obtained according to a preset address mapping rule, so as to read the old memory timestamp from the memory timestamp address region and write the new memory timestamp to the memory timestamp address region.

[0253] The preset address mapping rule can be an address conversion formula between the user data area and the memory timestamp address area.

[0254] For example, tspByteAddr=tspMemBase+((dataAddr-userMemBase)<<1).

[0255] Wherein, userMemBase is the base address of the user data area, dataAddr is the memory access address, tspMemBase is the base address of the memory timestamp, tspByteAddr is the memory timestamp access address, dataAddr-userMemBase represents the byte offset of the user data area base address corresponding to the memory access address, and <<1 indicates a left shift operation of 1 bit on this offset to ensure that every 4 bytes of user data corresponds to 8 bytes of memory timestamp.

[0256] In one example, the memory data address region is the memory data space starting from userMemBase, and the memory timestamp address region is the memory timestamp space starting from tspMemBase.

[0257] In the above scheme, address mapping is used to physically isolate the memory data address area and the memory timestamp address area, thereby improving the hit rate of memory data read / write and memory timestamp read / write.

[0258] Please see Figure 14 , Figure 14 This is a schematic diagram of the structure of a system-on-a-chip (SoC) according to some embodiments of this application. The SoC 1400 includes a processor 1410, which may be the processor 100 or processor 400 in the above embodiments. In one example, the SoC 1400 can be used in a zero-knowledge proof system, for example, in the zero-knowledge proof system 600 in the above embodiments, to acquire a program, input parameters, and configuration data, and generate a proof trajectory record corresponding to at least one instruction.

[0259] In the above scheme, generating a unique and monotonically increasing global instruction identifier consistent with the instruction retirement semantics ensures that the update of the architecture state by the instruction and the generation of the proof trajectory record are inseparable atomic events, guaranteeing that the proof trajectory record is completely consistent with the actual execution semantics of the program. Furthermore, by establishing a globally unique timing benchmark, the strong order of the trajectory is guaranteed, providing a unified timing reference for the vCPU state machine and vRAM state machine, satisfying consistency proof. Simultaneously, by generating explicit global instruction identifiers, the global order of instructions remains strictly controllable even under complex backend proof logic, reducing the additional overhead caused by software-layer timestamp alignment, improving the overall throughput and response speed of the system, and meeting the urgent need for high-performance proof systems in blockchain scaling and decentralized computing. Maintaining data conversion records and identifier conversion records corresponding to the instructions records the details of state changes during instruction execution, solving the problem of proof failure due to the lack of traceable timing evidence, and providing indispensable data support for register consistency proof of the vCPU state machine and memory consistency proof of the vRAM state machine. Thus, it is proven that the global instruction identifier, data conversion record, and identifier conversion record in the trajectory record provide reliable, ordered, and semantically consistent execution witness data for the backend proof.

[0260] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0261] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0262] In the several embodiments provided in this application, it should be understood that the disclosed methods and apparatus can be implemented in other ways. For example, the apparatus implementations described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0263] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0264] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A processor, characterized in that, include: Instruction pipeline circuit, used to execute instructions and obtain instructions to be retired; A global instruction identifier circuit, connected to or integrated into the instruction pipeline circuit, is used to generate a unique and monotonically increasing global instruction identifier corresponding to the instruction to be retired when the instruction to be retired is retired. An instruction status maintenance circuit, connected to the instruction pipeline circuit, is used to maintain the data conversion record and identifier conversion record of the instruction to be retired; The global instruction identifier, the data conversion record, and the identifier conversion record are used to construct the proof trajectory record.

2. The processor according to claim 1, characterized in that, The instruction pipeline circuit includes: A retirement control circuit is used to enable the retirement instruction to complete retirement when the retirement instruction meets preset retirement conditions.

3. The processor according to claim 2, characterized in that, The global instruction identifier circuit is connected to the retirement control circuit through the instruction pipeline circuit. The global instruction identifier circuit is used to generate the global instruction identifier when the retirement control circuit causes the instruction to be retired to complete retirement.

4. The processor according to claim 2, characterized in that, The global instruction identifier circuit is integrated into the instruction pipeline circuit and connected to the retirement control circuit. The global instruction identifier circuit is used to generate the global instruction identifier when the retirement control circuit causes the instruction to be retired to complete retirement.

5. The processor according to claim 1, characterized in that, The instruction status maintenance circuit is also used to maintain the data conversion record and the identifier conversion record corresponding to the type of the retirement instruction, based on the type of the retirement instruction.

6. The processor according to claim 5, characterized in that, The instruction status maintenance circuit is further configured to maintain the data conversion record and the identifier conversion record corresponding to the register event instruction in response to the type of the instruction to be retired being a register event instruction; or In response to the retirement instruction being a memory event instruction, the data conversion record and the identifier conversion record corresponding to the memory event instruction are maintained.

7. The processor according to claim 6, characterized in that, The processor includes: A processor core, the processor core including the instruction pipeline circuit and the global instruction identifier circuit; The instruction status maintenance circuit includes: A general-purpose register circuit, located in the processor core and connected to the instruction pipeline circuit, is used to maintain the data conversion record corresponding to the register event instruction or the memory event instruction when the type of the instruction to be retired is the register event instruction or the memory event instruction. The register timestamp circuit, located outside the processor core and connected to the instruction pipeline circuit, is used to maintain the identifier conversion record corresponding to the register event instruction or memory event instruction when the type of the instruction to be retired is the register event instruction or memory event instruction.

8. The processor according to claim 7, characterized in that, The general-purpose register circuit includes: The register file is used to store register business data; The first read port is used to read the value of the first source register from the register file before the retirement instruction is retired; The second read port is used to read the value of the second source register from the register file before the retirement instruction is retired. The third read port is used to read the old value of the destination register from the register file before the retirement instruction is retired; A write port is used to write a new value to the destination register into the register file when the retirement instruction is completed. The values ​​read by the first and second read ports, the old value read by the third read port, and the new value written by the write port are used to form the data conversion record.

9. The processor according to claim 7, characterized in that, The register timestamp circuit includes: A register timestamp array used to store register timestamps; The first read timestamp port is used to read the timestamp of the first source register from the register timestamp array before the retirement instruction is retired; The second timestamp read port is used to read the timestamp of the second source register from the register timestamp array before the retirement instruction is retired; The third timestamp read port is used to read the old timestamp of the destination register from the register timestamp array before the retirement instruction is retired; The first write timestamp port is used to write a new timestamp of the first source register to the register timestamp array when the retirement instruction to be retired is completed. The second write timestamp port is used to write a new timestamp of the second source register to the register timestamp array when the retirement instruction to be retired is completed; The third write timestamp port is used to write a new timestamp of the destination register to the register timestamp array when the retirement instruction to be retired is completed. The timestamps read by the first and second read timestamp ports, the old timestamp read by the third read timestamp port, the new timestamps written by the first and second write timestamp ports, and the new timestamps written by the third write timestamp port are used to form the identifier conversion record.

10. The processor according to claim 9, characterized in that, The register timestamp circuit is also used to arrange the new timestamp of the first source register, the new timestamp of the second source register, and the new timestamp of the destination register in ascending order according to the global instruction identifier and the preset offset rule.

11. The processor according to claim 10, characterized in that, The register timestamp circuit is further configured to, when there are at least two identical register indices in the first source register, the second source register, and the destination register, write new timestamps to the registers corresponding to the at least two identical register indices according to a preset priority, at least two of the first write timestamp port, the second write timestamp port, and the third write timestamp port.

12. The processor according to claim 7, characterized in that, The instruction status maintenance circuit further includes: A memory data cache circuit, located in the processor core and connected to the instruction pipeline circuit, is used to maintain the data conversion record corresponding to the memory event instruction when the type of the instruction to be retired is the memory event instruction; A memory timestamp cache circuit, located in the processor core and connected to the instruction pipeline circuit, is used to maintain the identifier conversion record corresponding to the memory event instruction when the type of the instruction to be retired is the memory event instruction.

13. The processor according to claim 12, characterized in that, The memory event instructions include load instructions and store instructions; The memory data cache circuit is also used to read the old memory value from the memory data address area in response to the load instruction, and the memory timestamp cache circuit is also used to read the old memory timestamp from the memory timestamp address area in response to the load instruction, and write the new memory timestamp into the memory timestamp address area. or The memory data cache circuit is also configured to, in response to the storage instruction, read the old memory value from the memory data address area and write the new memory value into the memory data address area; the memory timestamp cache circuit is also configured to, in response to the storage instruction, read the old memory timestamp from the memory timestamp address area and write the new memory timestamp into the memory timestamp address area. Wherein, the old memory value is used to form the data conversion record, and the old memory timestamp and the new memory timestamp are used to form the identifier conversion record; Alternatively, the old memory value and the new memory value can be used to form the data conversion record, and the old memory timestamp and the new memory timestamp can be used to form the identifier conversion record.

14. The processor according to claim 13, characterized in that, The memory timestamp caching circuit is also used to arrange the old memory timestamp and the new memory timestamp in ascending order according to the global instruction identifier and the preset offset rule.

15. The processor according to claim 13, characterized in that, The memory timestamp caching circuit is also used to obtain the memory timestamp address region according to a preset address mapping rule, so as to read the old memory timestamp from the memory timestamp address region and write the new memory timestamp into the memory timestamp address region.

16. A zero-knowledge proof system, characterized in that, include: A host computer is used to provide programs, input parameters, and configuration data, wherein the program includes at least one instruction; The system-on-a-chip includes a processor as described in any one of claims 1-15, configured to acquire the program, the input parameters, and the configuration data, and generate a proof trajectory record corresponding to the at least one instruction; The proof circuit is used to acquire the proof trajectory record and, after generating proof data corresponding to the proof trajectory record, return the proof data to the host.

17. The zero-knowledge proof system according to claim 16, characterized in that, The host is also used to write the program, the input parameters and the configuration data into shared memory, and to perform a cache refresh operation after the writing is completed.

18. The zero-knowledge proof system according to claim 17, characterized in that, The host computer is also used to send a trajectory generation start signal to the on-chip system; The on-chip system is also used to, upon receiving the trajectory generation start signal, acquire the program, the input parameters, and the configuration data, and generate the proof trajectory record corresponding to the at least one instruction.

19. The zero-knowledge proof system according to claim 17, characterized in that, The on-chip system is also used to send a trajectory generation end signal to the host after generating the proof trajectory record corresponding to the at least one instruction, so as to start the proof circuit through the host.

20. The zero-knowledge proof system according to claim 19, characterized in that, The host is also configured to perform a memory barrier operation after receiving the trajectory generation end signal, and send a proof start signal to the proof circuit after performing the memory barrier operation to start the proof circuit.

21. The zero-knowledge proof system according to claim 20, characterized in that, The proof circuit is also used to write the proof data corresponding to the proof trajectory record into shared memory after generating the proof data, and send a proof completion signal to the host.

22. A method for generating a proof state, characterized in that, include: Execute the instruction and receive the retirement instruction; When the retirement instruction is completed, a unique and monotonically increasing global instruction identifier is generated, and the data conversion record and identifier conversion record of the retirement instruction are maintained. Construct a proof trajectory record based on the global instruction identifier, data conversion record, and identifier conversion record.

23. The method according to claim 22, characterized in that, The process of generating a unique and monotonically increasing global instruction identifier upon completion of the retirement instruction includes: When the retirement instruction meets the preset retirement conditions, the retirement instruction is retired, and a unique and monotonically increasing global instruction identifier is generated.

24. The method according to claim 22, characterized in that, The maintenance of the data conversion record and identifier conversion record of the pending retirement instruction includes: Based on the type of the retirement instruction, maintain the data conversion record and the identifier conversion record corresponding to the type of the retirement instruction.

25. The method according to claim 24, characterized in that, The step of maintaining the data conversion record and the identifier conversion record corresponding to the type of the retirement instruction includes: In response to the retirement instruction being a register event instruction, maintain the data conversion record and the identifier conversion record corresponding to the register event instruction; or In response to the retirement instruction being a memory event instruction, the data conversion record and the identifier conversion record corresponding to the memory event instruction are maintained.

26. The method according to claim 25, characterized in that, The response to the retirement instruction being of type register event instruction includes maintaining the data conversion record and the identifier conversion record corresponding to the register event instruction, including: Before the retirement instruction is retired, the first source register value, the second source register value, and the old value of the destination register are read from the register file, and when the retirement instruction is completed, the new value of the destination register is written to the register file, wherein the first source register value, the second source register value, the old value of the destination register, and the new value of the destination register are used to form the data conversion record; Before the instruction to be retired is retired, the first source register timestamp, the second source register timestamp, and the old timestamp of the destination register are read from the register timestamp array. When the instruction to be retired is completed, the first source register timestamp, the second source register timestamp, and the destination register timestamp are written to the register timestamp array. The first source register timestamp, the second source register timestamp, the old timestamp of the destination register, the first source register timestamp, the second source register timestamp, and the destination register timestamp are used to form the identifier conversion record.

27. The method according to claim 26, characterized in that, The new timestamp of the first source register, the new timestamp of the second source register, and the new timestamp of the destination register are arranged in ascending order according to the global instruction identifier and the preset offset rule.

28. The method according to claim 27, characterized in that, When there are at least two identical register indices corresponding to the new timestamp in the first source register, the new timestamp in the second source register, and the new timestamp in the destination register, a new timestamp is written to the registers corresponding to the at least two identical register indices according to a preset priority.

29. The method according to claim 26, characterized in that, The response to the retirement instruction being of the type of memory event instruction includes maintaining the data conversion record and the identifier conversion record corresponding to the memory event instruction, including: In response to the load instruction corresponding to the memory event instruction, the old memory value is read from the memory data address region, and the old memory timestamp is read from the memory timestamp address region, and the new memory timestamp is written to the memory timestamp address region; or In response to the memory event instruction corresponding to a store instruction, the old memory value is read from the memory data address region and the new memory value is written into the memory data address region, and the old memory timestamp is read from the memory timestamp address region and the new memory timestamp is written into the memory timestamp address region; Wherein, the old memory value is used to form the data conversion record, and the old memory timestamp and the new memory timestamp are used to form the identifier conversion record; or the old memory value and the new memory value are used to form the data conversion record, and the old memory timestamp and the new memory timestamp are used to form the identifier conversion record.

30. The method according to claim 29, characterized in that, The old memory timestamp and the new memory timestamp are arranged in ascending order according to the global instruction identifier and the preset offset rule.

31. The method according to claim 29, characterized in that, The memory timestamp address region is obtained according to the preset address mapping rules, so as to read the old memory timestamp from the memory timestamp address region and write the new memory timestamp into the memory timestamp address region.

32. A system-on-a-chip, characterized in that, Includes the processor as described in any one of claims 1-15, or for performing the method as described in any one of claims 22-31.

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