Processor pipeline depth control method and device based on information processing efficiency quantification and resource matching

Abstract

The application discloses a processor pipeline depth control method and device based on information processing efficiency quantization and resource matching, and relates to the chip design field. In the instruction decoding stage, the intrinsic complexity parameter β and the data dependency depth R_d of the current instruction are obtained; β and R_d are substituted into the formula α=k x log2(β) / R_d to calculate the efficiency factor α; α is compared with a preset threshold value to determine the pipeline depth level corresponding to the current instruction; the corresponding depth label is generated and is passed in the pipeline with the instruction; according to the comparison result of the depth label and the current level number, the current clock gate switch state and the data path gating state are independently decided by each level pipeline, so that the current instruction exits the pipeline through the bypass write-back path at the termination level. The application can realize nanosecond instruction pipeline depth adaptive scheduling, cooperatively plan the instruction emission arrangement through the depth label and the reordering buffer, reduce resource idling and power consumption waste, and realize significant power consumption reduction under typical load.

Description

Technical Field

[0001] This invention relates to the field of chip design, specifically to a method and apparatus for processor pipeline depth control based on information processing efficiency quantification and resource matching, and is particularly applicable to central processing unit (CPU) pipeline depth control. Background Technology

[0002] 1. Existing processor pipeline architecture Traditional processor chips have a fixed pipeline depth, typically a 4- or 5-stage pipeline architecture. In this architecture, all machine instructions, regardless of their computational complexity, must pass through the same number of pipeline stages to complete processing. This architecture suffers from several underlying technical flaws: (1) Waste of hardware resources due to simple instructions. Simple arithmetic logic instructions, such as ADD, SUB, and MOV, only involve three main steps in their execution flow: instruction decoding, ALU arithmetic operation, and result write-back. At the hardware level, only a 3-stage pipeline (fetch → decode → execute) is required to complete compliant operations. However, fixed-depth pipeline architectures force simple instructions to flow through all 4-5 stages of the pipeline. The registers at the end of the pipeline continuously receive clock toggle signals but do not participate in effective operation processing, remaining in an ineffective idle state. This phenomenon, on the one hand, prolongs the inherent execution latency of simple instructions, and on the other hand, significantly increases the dynamic power consumption of pipeline registers, resulting in a double waste of chip computing power and power resources.

[0003] (2) Complex instructions have a high risk of hardware timing violations. Complex instructions, such as DIV division, MOD modulo, and BRANCH branch jump, involve multi-cycle iterative operations and multi-branch condition judgment logic during execution. At the hardware level, 5 to 6 pipeline stages are required to amortize the combinational logic delay in order to meet clock timing constraints. Taking a conventional 32-bit native divider as an example, the typical overall combinational logic delay of an unleveled native divider is 3.5ns (STA analysis results based on 28nm process, typical process corner TT). If adapted to a fixed 4-stage pipeline architecture, the division operation logic must be completed within a single execution cycle. The combinational logic transmission path is too long, directly triggering clock timing violations.

[0004] (3) The overall computing power execution efficiency is low under mixed loads. During the operation of terminal programs, lightweight simple instructions and highly complex instructions are issued serially in alternation. Fixed-depth pipelines cannot adapt to dynamic changes in instruction load and cannot adjust the number of pipeline stages as needed, resulting in long-term limitations on the overall instruction throughput and operating energy efficiency of the processor.

[0005] Similarly, in chips such as DSPs (Digital Signal Processors), there is also an energy efficiency problem caused by a fixed instruction pipeline depth.

[0006] 2. Technical limitations of existing dynamic scheduling schemes (1) Dynamic Voltage and Frequency Adjustment Technology (DVFS). Existing DVFS scheduling decisions rely on macroscopic load statistics of the chip to complete the regulation, and the scheduling response granularity is at the microsecond to millisecond level (typical value is 10μs~100ms), which cannot achieve real-time parameter switching at the nanosecond instruction level. At the same time, the DVFS regulation object is the chip operating voltage and operating frequency, and does not involve pipeline execution depth regulation.

[0007] (2) Load scheduling scheme based on queue waiting time. This type of scheme requires the hardware to build multiple independent instruction scheduling queues, resulting in large hardware register and control logic overhead, high instruction scheduling response latency, and the inability to achieve real-time configuration of nanosecond-level instruction-level pipeline depth. The core shortcoming is that this type of scheduling logic does not have a standardized instruction complexity quantification system, and cannot accurately determine instruction complexity and instruction-data coupling. Summary of the Invention

[0008] I. Technical problems to be solved To address the technical problems of existing processors where fixed pipeline depth leads to wasted power due to idle cycles after simple instructions and timing violations caused by excessively long logic paths for complex instruction combinations, this invention provides a processor pipeline depth control method and apparatus based on information processing efficiency quantification and resource matching.

[0009] II. Technical Solution The present invention provides a processor pipeline depth control method based on information processing efficiency quantification and resource matching, comprising the following steps: During the instruction decoding stage, the intrinsic complexity parameter β and data dependency depth R_d of the current instruction are obtained; β is a quantized integer value representing the instruction opcode classification space, and its value is obtained by looking up a table according to the instruction type; R_d is a quantized integer value representing the number of clock cycles that the current instruction needs to wait because the source register data is not ready, and is dynamically output by the data hazard detection unit. Bypass determination is performed based on β and R_d: If β=1, the preset shallowest pipeline depth is directly output as the final pipeline depth D_final, and the efficiency factor formula calculation, threshold comparison step and physical security verification step are skipped. If R_d=0 and β≠1, skip the efficiency factor formula calculation and output the preset shallowest pipeline depth as the calculation depth D_α to the physical security verification step. When R_d≠0 and β≠1, substituting said β and R_d into the efficiency factor formula α = k × log2(β) / R_d, the efficiency factor α is calculated by a hardware combinational logic circuit within a single decoding cycle, where k is a scaling constant greater than 0; comparing said efficiency factor α with at least two preset thresholds, and determining the pipeline depth corresponding to the current instruction as the calculation depth D_α according to the comparison result; Performing a physical security check step: taking said calculation depth D_α and the β value of the current instruction as inputs, querying a pre-stored security threshold table to obtain the minimum safe physical depth D_min of the instruction; if D_α<D_min, outputting D_min as the final pipeline depth D_final; if D_α ≥ D_min, outputting D_α as the final pipeline depth D_final; Generating a depth tag corresponding to said final pipeline depth, wherein the depth tag is a multi-bit binary code for identifying the final pipeline depth, and the depth tag is transmitted step by step along with the current instruction in the pipeline; Each stage of the pipeline independently determines the state of its own clock gating switch and the data path gating state according to the comparison result between the depth tag and the number of the current stage; After the current instruction completes the operation at the termination stage corresponding to the depth tag, it exits the pipeline through the bypass write-back path, and the clock gating of each stage of the pipeline after the termination stage is turned off.

[0010] The above solution can be specifically explained as that the present invention relates to the basic form of the efficiency factor formula α = k × log2(β) / R_d and the definition of its parameters (β is the intrinsic complexity parameter, and R_d is the resource coupling parameter). Based on this, the present invention applies the formula to the scenario of processor pipeline depth control, and provides a specific hardware implementation device and method.

[0011] The basic form of Taiyang's formula is: α = k × log2(β) / R_d In the scenario of processor pipeline: β is the intrinsic complexity parameter, which reflects the operation complexity of an instruction, specifically in the instruction opcode classification space (in this embodiment, β=8 for simple instructions, β=16 for medium instructions, and β=32 for complex instructions).

[0012] R_d is a resource coupling parameter. In the processor pipeline scenario, the resource coupling parameter R_d specifically represents the data dependency depth of the instruction—that is, the number of clock cycles that the current instruction needs to wait because the source register data is not ready. R_d is dynamically output by the data hazard detection unit, and its value is determined based on the following three aspects: (1) the pipeline stage distance between the current instruction and the preceding instruction that was recently written to its source register; (2) the pipeline stage (EX / MEM / WB) where the preceding instruction is currently located and its data ready state; (3) the inherent execution latency of the preceding instruction (producer) itself (e.g., the multiplier requires 3 cycles, and the divider requires multiple cycles). R_d=0 indicates that the source data is ready, and the instruction can be issued and executed without waiting.

[0013] α is the instruction information processing efficiency factor.

[0014] k is the scene adaptation scaling constant.

[0015] How to obtain R_d: R_d is dynamically calculated and output by the Data Hazard Detection Unit. This unit takes the source register identifier of the current instruction as input, queries the register write-back mapping table (map table) to obtain the instruction number most recently written to that source register, monitors the current pipeline stage (EX / MEM / WB) of the preceding instruction and its remaining execution cycles (if the instruction is a multi-cycle instruction), and checks the data readiness status of the preceding instruction. After comprehensive judgment, it outputs the actual number of waiting cycles required for the current instruction. The value output by the Data Hazard Detection Unit is the R_d value of the current instruction, which is directly used in the subsequent calculation of the efficiency factor α = k × log2(β) / R_d. When R_d=0, the α calculation is skipped and the physical security check is performed directly; when R_d>0, it is substituted into the formula for calculation. All judgments are completed by combinational logic within a single decoding cycle.

[0016] Physical security threshold verification mechanism: The efficiency factor α determines the optimal pipeline depth level for instructions under normal operating conditions. However, in actual processor operation, there is no fixed monotonic mapping relationship between the values ​​of β and R_d. High intrinsic complexity instructions (such as DIV and MOD) may have R_d=0 due to bypassing of the forward network, while low intrinsic complexity instructions (such as ADD) may have a large R_d due to cache misses. Under these atypical combinations, relying solely on the value of α for depth decision-making may lead to two biases: first, high β instructions may be allocated to too shallow a pipeline depth due to R_d=0, triggering timing violations; second, low β instructions may be allocated to too deep a pipeline due to extremely large R_d, resulting in wasted power.

[0017] To address this, the present invention adds a physical security verification link after the threshold comparison step, providing a hardware-level safety net for the aforementioned atypical combinations. This physical security verification step shares the same physical essence as the "optional post-processing constraint module" disclosed in the parent application—that is, based on the α decision, a secondary forced correction is applied to the resource allocation result in conjunction with the chip's physical timing boundary conditions. The present invention concretizes this into a security depth enforcement circuit in a processor pipeline scenario, constituting a complete hardware implementation scheme.

[0018] After the α calculation module outputs the calculated depth D_α, an independent SafetyDepth Forcing Circuit is added. This circuit takes D_α and the β value of the instruction as input and queries the minimum safe physical depth D_min of the instruction through another set of read-only safety threshold tables (pre-filled by STA analysis). The final output depth label D_final = max(D_α, D_min).

[0019] This mechanism is independent of the α calculation result of the Taiyang formula—α determines the "optimal depth level by a comprehensive trade-off between complexity and coupling," and D_min determines the "minimum depth level for absolute physical timing safety," with the maximum value of both being output. This circuit does not participate in the normal calculation path of α, but only performs forced correction when the α decision result deviates from the physical safety boundary, ensuring that timing violations are not triggered under any operating condition.

[0020] Distinguishing between R_d=0 and β=1: R_d=0: This indicates no prerequisite data dependency, and the instruction can be issued immediately. From a scheduling physics perspective, in the decoupled state, instructions can be executed without waiting. The optimal strategy is to directly allocate the shallowest pipeline depth to avoid unnecessary waiting delays. In this case, α calculation is skipped, and the preset shallowest pipeline depth is used as D_α input to the physical safety enforcement circuit. For instructions with high intrinsic complexity (such as DIV, β=32), the physical safety enforcement circuit queries D_min based on its β value (such as level 4) and forces the final depth to D_min to ensure timing safety; for instructions with low intrinsic complexity (such as ADD, β=8), D_min=3, and the final depth remains the shallowest to avoid unnecessary power waste.

[0021] β=1: Corresponds to no-operation instructions such as NOP, with no actual computational requirements. In this case, the preset shallowest pipeline depth is directly output, completely skipping the entire chain of α calculation, threshold comparison, and physical security verification. The β=1 bypass logic has higher priority than the R_d=0 bypass logic.

[0022] Regarding the relationship between threshold quantity and scheduling level: This invention does not limit the specific number of thresholds. When a two-level scheduling hierarchy is required, at least one threshold (Th1) is needed; when a three-level scheduling hierarchy is required, at least two thresholds (Th1, Th2) are needed; and when a four-level scheduling hierarchy is required, at least three thresholds (Th1, Th2, Th3) are needed. In this embodiment, three thresholds, Th1, Th2, and Th3, are used to achieve four pipeline depth levels. Those skilled in the art can set different numbers of thresholds according to the actual chip design requirements.

[0023] Core hardware architecture: This invention adds the following core hardware modules to the traditional assembly line: (1) α calculation module: a pure combinational logic circuit that completes the full operation from β and R_d to α in a single decoding cycle. It includes: a logarithmic approximation sub-circuit (equipped with an 8-bit input read-only LUT, pre-stores the fixed-point amplified value of log2β); a fixed-point division sub-circuit (relying on a shift subtraction divider to complete the division operation); and a parallel comparison encoding sub-circuit (multi-channel comparators synchronously compare the fixed-point value of α with a preset threshold, and the encoder outputs the calculation depth D_α).

[0024] (2) Physical safety enforcement circuit: includes a read-only safety threshold table and a comparator, takes D_α and instruction β as input, outputs D_min, and takes the maximum value of D_α.

[0025] (3) Depth encoder: used to generate the corresponding depth label D based on the final pipeline depth D_final.

[0026] (4) Depth Tag As-Pass Register: Located between each stage of the pipeline, the depth tag is embedded in the instruction control field and is passed level by level along with the instruction data stream. The depth tag also provides a feedforward control signal to notify each stage of the clock gating ICG whether the instruction needs to pass through this stage.

[0027] (5) Independent control unit for each level of pipeline: Each level is equipped with an independent digital comparator, which compares the level number N with the depth label D, and combines the effective signal of the level pipeline with the global Stall / Flush control signal to jointly decide the level ICG and MUX.

[0028] (6) Bypass Write-back MUX: Set at the execution level output, when the depth label indicates the preset shallowest pipeline depth, the execution level operation result is selected to the write-back data bus after being tagged by the pipeline register.

[0029] Joint control logic of ICG at all levels: In this invention, the clock gating (ICG) of each stage of the pipeline is not decided independently by a single stage, but is jointly determined by the three control signals shown in Table 1 below: Table 1

[0030] ICG activation conditions at each level: There is a valid instruction (valid=1) in this level OR the previous level depth label indicates that the instruction will enter this level OR the global Stall signal is valid (hold clock).

[0031] ICG shutdown conditions at each level: No valid instruction at this level AND the previous level depth tag does not point to this level AND the global Stall signal is invalid.

[0032] The three components work together through combinational logic to generate the on / off control signal for this level of ICG, ensuring that the start / stop of the clock gating is synchronized with the pipeline data flow.

[0033] Hardware implementation of the threshold: The aforementioned preset thresholds (Th1, Th2, Th3) are stored in fixed-point format in on-chip programmable registers. These registers are populated with threshold parameters by the firmware or hardware configuration module during chip initialization. The fixed-point amplified α value output by the α calculation module is compared with the values ​​in each threshold register using parallel comparators (i.e., multiple comparators simultaneously compare α with each threshold). The comparison result is directly input into the encoder to generate the corresponding computational depth D_α. The specific threshold values ​​are determined through static timing analysis (STA) and can be adapted and adjusted according to different processes and clock frequencies by updating the register configuration.

[0034] When the scene adaptation scaling constant k changes (e.g., from k_old to k_new), the preset threshold stored in the on-chip programmable register is scaled synchronously and proportionally: Th'_i = (k_new / k_old) × Th_i, to ensure that the depth level crossing point of each instruction remains unchanged.

[0035] Pipeline depth classification definition: In this invention, "pipeline depth" refers to the number of execution stages an instruction needs to pass through after decoding, i.e., the number of stages in the pipeline involved in instruction computation. Taking a depth of 3 as an example, the corresponding physical path is fetch → decode → execute (EX stage) → bypass write-back. The output pipeline register slapping at the EX stage is part of the execution stage and is not counted as an independent pipeline depth stage. Those skilled in the art will understand that the definitions of each stage may differ in different processor architectures. This invention uses the number of stages involved in computation as the depth counting standard, facilitating unified quantification of scheduling decisions. The functional definitions of each pipeline stage are shown in Table 2 below: Table 2

[0036] In this embodiment, the preset shallowest pipeline depth is 3 levels, and the corresponding physical exit level is 4 levels (IF→ID→EX→bypass WB, including EX level output pipeline register pausing).

[0037] The functional definitions of each level of the 6-level pipeline are as follows: Level 1 = Fetch (IF), Level 2 = Decode (ID), Level 3 = Execute (EX), Level 4 = Memory Access 1 (MEM1), Level 5 = Memory Access 2 (MEM2) / Write Back (WB), Level 6 = Additional Timing Buffer Level.

[0038] Those skilled in the art will understand that the mechanisms for depth tag transmission, clock gating control, and bypass write-back in this invention can also be implemented using equivalent alternatives known in the art: (1) Depth tags are not limited to being passed step by step with instructions. They can also be implemented by using a centralized depth management unit in conjunction with instruction identifiers, or by using a distributed register network, or by using the depth code carried by the instruction to be transmitted through the data path and control signals. (2) Clock gating is not limited to ICG, but can also be implemented by any means that can stop a specified pipeline from working, such as clock enable control, voltage domain shutdown, data path selection, etc. (3) Bypass write-back is not limited to the MUX at the EX stage output. It can also be achieved by any data path that can bypass the subsequent pipeline stage and write back directly. (4) Physical security verification is not limited to the security threshold table lookup method. It can also be implemented by any method that can achieve physical security verification, such as formula calculation, rule judgment, empirical value mapping or adaptive adjustment.

[0039] A standardized five-step management process across the entire domain: Step 1: Parallel parameter acquisition. During the decoding stage, β is obtained by looking up a table in ROM, and R_d is obtained in real time by the data hazard detection unit.

[0040] Step 2: Bypass determination and efficiency factor calculation.

[0041] If β=1: jump directly to step five, output the preset shallowest pipeline depth, and skip all subsequent calculations.

[0042] If R_d=0: Skip α calculation, D_α=preset shallowest pipeline depth, proceed to step three.

[0043] If R_d≠0 and β≠1: run the Taiyang formula to calculate α, compare the threshold and output D_α.

[0044] Step 3: Physical security verification. Take the maximum value between D_α and D_min, and output D_final.

[0045] Step 4: Pipeline hardware configuration. Depth tags are distributed along the path, and feedforward control signals are provided simultaneously. Each ICG level makes a joint decision on the switching state based on the depth tag feedforward, the effective signal of its own level, and the global Stall signal.

[0046] Step 5: Instruction hierarchical execution. After the instruction flows through the corresponding pipeline stage, it is output from the terminal stage, queried by the pipeline register, and then written back through the bypass MUX. The pipeline clock is then turned off to reduce power consumption.

[0047] III. Beneficial Effects Compared to the three mainstream technologies of fixed pipeline, DVFS, and queue scheduling, this invention has the following core technological advantages: First, instruction-level dynamic adaptation capability. Relying on the Taiyang formula to couple quantization parameters, it accurately matches instruction complexity and pipeline depth, enabling full-load adaptive scheduling.

[0048] Second, global chip energy efficiency optimization. Idle pipeline hardware clocks are gated and powered down, reducing the power consumption of register dynamic toggling from the source. Verification results show that approximately 85% of instructions are allocated to the first depth level (level 3 in this embodiment), and the subsequent stage clocks are turned off; compared to a fixed 6-stage pipeline, dynamic power consumption is reduced by approximately 23%, and compared to a fixed 4-stage pipeline, it is reduced by approximately 12%.

[0049] Third, nanosecond-level hardware real-time response. End-to-end decoding-level combinational logic operations, with no software scheduling delay, achieve a response granularity at the instruction-level nanosecond level.

[0050] Fourth, extremely low incremental hardware cost. The total number of newly added digital gates is approximately 2,800, accounting for about 0.047%, without requiring modifications to the original kernel dataflow, resulting in a low barrier to mass production.

[0051] Fifth, it exhibits excellent robustness across all workloads. It can stably schedule mixed workloads including simple instructions, complex instructions, and long dependency chains, and automatically reverts to traditional execution mechanisms under extreme conditions.

[0052] Sixth, proactive scheduling and guidance capabilities for the reordering buffer (ROB). By utilizing the instruction completion time T_pred carried by the depth tag, the risk of ROB storage blockage can be predicted in advance and instruction issuance can be proactively guided; the same quantization scheduling framework can be directly adapted to multiple types of processors such as CPUs and DSPs. Attached Figure Description

[0053] Figure 1 This is a flowchart of the overall technical solution of the present invention; it shows a complete five-step scheduling process, including three independent paths: β=1 full bypass, R_d=0 partial bypass, and physical security verification. Figure 2 This is a block diagram comparing the old and new hardware architectures of this invention; comparing the traditional fixed pipeline with the dynamically configured pipeline of this invention; Figure 3 is a diagram of the parameter acquisition and α operation link according to an embodiment of the present invention; which shows a dual-parameter parallel acquisition and three-level operation hardware link; Figure 4 is a schematic diagram of the shallowest depth bypass writeback path according to an embodiment of the present invention; which marks the EX-stage bypass MUX and the post-stage ICG turn-off path; Figure 5 is a dynamically configurable pipeline topology structure diagram according to an embodiment of the present invention; which shows the interconnection control relationship among multi-stage pipelines, depth labels, ICG and MUX. DETAILED DESCRIPTION

[0054] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be described clearly and completely below with reference to the accompanying drawings.

[0055] An embodiment of the present invention provides a processor pipeline depth control method based on information processing efficiency quantification and resource matching, comprising the following steps: In the instruction decoding stage, obtain the intrinsic complexity parameter β and the data dependence depth R_d of the current instruction; wherein β is a quantized integer value characterizing the instruction opcode classification space, and its value is obtained through table lookup mapping according to instruction types; R_d is a quantized integer value characterizing the number of clock cycles that the current instruction needs to wait for because the source register data is not ready, and is dynamically output by a data hazard detection unit; Perform bypass judgment according to said β and R_d: if β=1, directly output the preset shallowest pipeline depth as the final pipeline depth D_final, and skip the efficiency factor formula calculation, threshold comparison step and physical safety check step; if R_d=0 and β≠1, skip said efficiency factor formula calculation, and output the preset shallowest pipeline depth as the calculated depth D_α to the physical safety check step; when R_d≠0 and β≠1, substitute said β and R_d into the efficiency factor formula α = k × log2(β) / R_d, the efficiency factor α is calculated by the hardware combinational logic circuit within a single decoding cycle, where k is a scaling constant greater than 0; compare said efficiency factor α with at least two preset thresholds, and determine the pipeline depth corresponding to the current instruction as the calculated depth D_α according to the comparison result; Execute the physical safety check step: take said calculated depth D_α and the β value of said current instruction as input, query a pre-stored safety threshold table to obtain the minimum safe physical depth D_min of the instruction; if D_α<D_min, output D_min as the final pipeline depth D_final; if D_α ≥ D_min, output D_α as the final pipeline depth D_final; Generate a depth label corresponding to the final pipeline depth. The depth label is a multi-bit binary code used to identify the final pipeline depth. The depth label is passed step by step in the pipeline along with the current instruction. Each pipeline level independently decides on the clock gating switch state and data path selection state based on the comparison result between the depth label and the level number. After the current instruction completes its operation at the termination stage corresponding to the depth label, it exits the pipeline via a bypass write-back path, and the clock gating of each pipeline stage after the termination stage is turned off.

[0056] Specifically, the preset shallowest pipeline depth is 3 levels, and the corresponding physical exit level is 4 levels. After the instruction is slapped by the pipeline register at the execution level output end, it exits through the bypass write-back path.

[0057] The intrinsic complexity parameter β ranges from 1 to 256; the simplified arithmetic instruction β=8, the memory access comparison instruction β=16, and the branch iteration complex instruction β=32.

[0058] The value of the data dependency depth R_d is determined based on one or more of the following: the pipeline stage distance between the current instruction and the preceding instruction, the pipeline stage where the preceding instruction is currently located and its data ready state, and the remaining execution cycles of the preceding instruction; for multi-source register instructions, R_d is the maximum value of the waiting cycles corresponding to all source registers.

[0059] The depth tag uses non-continuous encoding, with illegal encoding states reserved between legal encodings; when the depth tag is detected to fall into an illegal encoding state, the hardware automatically flushes the entire pipeline stage, and the instruction is retransmitted at the bottom depth.

[0060] Specifically, this also includes the Reorder Buffer (ROB) collaborative scheduling mechanism: While generating depth labels, read the current value C_cur of the global cycle counter, generate the expected completion cycle T_pred = C_cur + D and store it in the new field of the ROB entry, where D is the pipeline depth value corresponding to the depth label; Before issuing a new command, retain the station to read the estimated completion cycle value of the ROB header command; If the remaining ROB slots are lower than the preset threshold and the expected completion period of the header instruction is greater than the sum of the current period and the preset margin, then the issuance of new instructions will be paused. When the execution unit completes the instruction, it writes the actual completion cycle into the ROB. When the deviation between the actual completion cycle and the expected completion cycle exceeds a preset threshold, the prediction failure correction mechanism is triggered.

[0061] Specifically, the termination level is the current level where the pipeline depth value D corresponding to the depth label is equal to the level number N, and D=N; when D>N, the current level is passed through; when D<N, the current level is clock-gated off.

[0062] Specifically, each level of the pipeline independent control unit includes an independent digital comparator, a clock gating ICG, and an output strobe MUX, with no feedback or state synchronization between levels; multi-cycle complex instructions are controlled by the built-in done signal of the execution unit, and if the instruction is not completed after exceeding the preset timeout counter threshold, a partial pipeline flush and instruction rescheduling are triggered.

[0063] Specifically, the processor is at least one of a central processing unit (CPU) and a digital signal processor (DSP), or the processor is a memory-based processor.

[0064] Specifically, the depth tag is also used for computing paradigm adaptation in the in-memory computing architecture. The fields of the depth tag include a depth level field, a data movement sensitivity field, and a retirement enable field. The depth level field is used to indicate the pipeline depth level or the computational paradigm type to which the instruction is adapted; The data movement sensitivity field is used to indicate the data movement sensitivity level of the instruction; The retirement enable field is used to indicate whether the execution results are allowed to be directly retained in the storage medium.

[0065] Specifically, when the data transfer sensitivity field in the depth label indicates that the data transfer sensitivity of the instruction is lower than a preset threshold, the instruction is assigned to the near-memory computing unit for execution; When the data transfer sensitivity field indicates that the data transfer sensitivity of the instruction is not lower than the preset threshold, the instruction is assigned to the traditional kernel for execution.

[0066] Specifically, when the retirement enable field in the depth label indicates that the execution result can be directly retained in the storage medium, the execution result of the instruction completed in the in-memory computing unit is directly written to the storage medium through an independent result bus without going through a bypass write-back path.

[0067] On the other hand, embodiments of the present invention also disclose a processor pipeline depth control device based on information processing efficiency quantification and resource matching, used to implement the above method, comprising: The intrinsic complexity parameter acquisition circuit is used to read the intrinsic complexity parameter β of the current instruction from the read-only instruction classification ROM during the decoding stage. The data dependency depth tracking circuit is used to calculate the data dependency depth R_d of the current instruction based on the register write-back mapping table and the global instruction counter. The efficiency factor calculation circuit includes a logarithmic lookup table sub-circuit and a fixed-point division sub-circuit. When R_d ≠ 0 and β ≠ 1, it substitutes β and R_d into α = k × log2(β) / R_d to calculate the efficiency factor α and outputs the corresponding calculation depth D_α. When R_d = 0 and β ≠ 1, the efficiency factor calculation circuit is bypassed, and the preset shallowest pipeline depth is directly output as the calculation depth D_α to the physical safety enforcement circuit. When β = 1, the efficiency factor calculation circuit is completely bypassed, and the preset shallowest pipeline depth is directly output as the final pipeline depth D_final to the depth encoder, without passing through the physical safety enforcement circuit. The physical safety enforcement circuit includes a safety threshold table and a comparator, which is used to query the minimum safe physical depth D_min of the instruction with the calculated depth D_α and the β value of the current instruction as input, and take the maximum value of D_α and D_min to output the final pipeline depth D_final; A depth encoder is used to generate a corresponding depth label based on the final pipeline depth D_final, wherein the depth label is a multi-bit binary code. The depth tag-as-you-go register is set between each stage of the pipeline and is used to carry the depth tag and move synchronously with the instructions. Each pipeline level has an independent control unit, and each level includes a level number comparator, a clock gating ICG, and an output gating MUX. These units are used to jointly decide the clock gating switch status and data path gating status of the level based on the comparison result between the depth tag and the level number, the valid signal of the pipeline level, and the global Stall / Flush control signal. The bypass write-back MUX, set at the execution level output, is used to select the execution result to the write-back data bus when the depth label indicates the preset shallowest pipeline depth.

[0068] The efficiency factor operation circuit is implemented using combinational logic, and completes the full operation from β and R_d to the computational depth D_α in a single decoding cycle.

[0069] In another aspect, the present invention also discloses a processor chip, comprising the processor pipeline depth control device based on information processing efficiency quantification and resource matching as described above.

[0070] The embodiments of the present invention will be described in detail below through specific examples.

[0071] I. Formula Calculation Examples and Grading Threshold Comparison Table This embodiment is based on 28nm process and 1GHz main frequency, and adopts three-level judgment thresholds: first / second depth level boundary Th1=1.0, second / third depth level boundary Th2=0.6, and bottom-line depth trigger Th3=0.3.

[0072] The aforementioned thresholds are not arbitrarily set, but are derived from the minimum timing requirements of various instructions within the processor core through static timing analysis (STA). Specifically, the upper bound of Th1 (log216 / 4=1.0) is derived from the minimum safe depth of MUL-type instructions as the second depth level; the upper bound of Th2 is derived from the minimum safe depth of highly iterative complex operation instructions as the third depth level (according to STA analysis, these instructions have timing violations at the second depth level and need to be allocated to the third depth level, with a corresponding α boundary of approximately 0.6); and Th3 (0.3) is derived from the minimum safe depth of ultra-long chain-dependent instructions as the fourth depth level, serving as the hard safety margin boundary. All thresholds can be re-derived and adapted based on different process technologies and clock frequencies through static timing analysis.

[0073] Methods for obtaining β and hardware implementation β is read from the read-only instruction classification ROM by the instruction decoder. After parsing the opcode of the current instruction, the decoder uses the encoded bit fields of the opcode (such as opcode[6:0] and funct3[14:12], funct7[31:25]) as the input address of the ROM, where the ROM stores the corresponding β value. The β mapping table is established according to the public specifications of the instruction set architecture (such as RISC-V, ARM, x86, etc.), and the decoder completes address decoding and ROM reading in a single cycle.

[0074] The method of obtaining R_d and its hardware implementation R_d is calculated in real time by the Data Hazard Detection Unit. This unit contains the following sub-modules: (1) Register write-back mapping table (map table): 32 entries, recording the instruction number corresponding to the most recent write-back of each general-purpose register, and maintaining a global instruction counter (instr_cnt).

[0075] (2) Pipeline level tracer: monitors the current pipeline level (EX / MEM / WB) of each instruction in the map table, and is used to determine how many cycles are left before the previous instruction is written back.

[0076] (3) Multi-cycle instruction execution status tracker: For instructions with long execution delays, such as multipliers (3 cycles) and dividers (multi-cycles), track the number of remaining execution cycles.

[0077] (4) Data ready status monitor: detects whether the data of the preceding instructions is ready.

[0078] For each source register rs of the current decoding instruction, the calculation logic of R_d is as follows: ① If map[rs] is invalid (this register has never been written to), or if the pre-instruction data is ready, then R_d = 0 (no need to wait).

[0079] ② If the pre-instruction is at the MEM level and the data is ready, then R_d = 0 (data hazard resolved).

[0080] ③ If the preceding instruction is at the MEM level but the data is not yet ready (e.g., the data has not yet been read from the cache in a Load-Use adventure), then R_d = 1~2 (waiting for the memory access to complete).

[0081] ④ If the pre-instruction is at the EX level and is a multi-cycle instruction (such as a multiplier or divider), then R_d = the number of remaining execution cycles of the pre-instruction.

[0082] ⑤ If multiple source registers have data hazards at the same time, R_d takes the maximum value of the calculated R_d values ​​of all source registers.

[0083] The calculation is performed by combinational logic within a single decoding cycle, with a combinational logic delay of <0.5ns (based on 28nm process and typical process angle TT), adapting to 1GHz single-cycle timing constraints.

[0084] When instr_cnt overflows and wraps around, the historical instruction number in the mapping table is used to synchronously perform saturation processing or full table flushing and updating to ensure that the calculation of R_d will not produce incorrect small interval values ​​due to counter overflow.

[0085] R_d=0 bypass processing: When R_d=0, the instruction has no prerequisite data dependency, does not need to calculate the efficiency factor α, and directly outputs the preset shallowest pipeline depth D_α to the physical safety enforcement circuit. At this time, the physical safety enforcement circuit of high intrinsic complexity instructions (such as DIV) will force them to a deeper depth level to ensure timing safety. This R_d=0 bypass logic runs in parallel with the β=1 bypass logic below, but the processing paths are different. The priority of R_d=0 bypass processing is lower than that of β=1 bypass processing. When β=1 and R_d=0 are both true, it is processed according to β=1, directly outputting the preset shallowest pipeline depth and completely bypassing the physical safety enforcement circuit. β=1 corresponds to no-operation instructions such as NOP, which have no actual computational requirements and do not require any pipeline depth adaptation.

[0086] β=1 bypass processing: When β=1 (corresponding to no-operation instructions such as NOP), the α operation link is also skipped, and the preset shallowest pipeline depth code is directly output by the dedicated β=1 bypass logic, while the physical safety enforcement circuit is completely bypassed. The priority of this β=1 bypass logic is higher than the α threshold decision table, and the difference between it and the R_d=0 bypass logic is that R_d=0 still needs to go through physical safety verification, while β=1 completely skips the physical safety verification.

[0087] α calculation module In the hardware implementation, the α calculation module is integrated into the decoding stage of the processor pipeline and consists of combinational logic circuits. The β value read from ROM and the R_d value output by the data hazard detection unit enter the α calculation module in parallel. After logarithmic LUT lookup (log2), fixed-point division, and threshold comparison, the calculation depth D_α is output within a single decoding cycle. This calculation depth then enters the physical security enforcement circuit, and after taking the maximum value with D_min, the final depth label is output. This label is passed along the pipeline stage by stage with the instructions. The independent control unit of each pipeline stage independently decides whether to turn the clock on / off and select the data path based on the comparison result of the depth label and its own stage number.

[0088] II. Formula Calculation Examples 1. A simplified example of ADD instruction operation is shown in Table 3. Table 3

[0089] The complete calculation formula is: α = 1 × log2(8) / 2 = 1.5>1.0, which is suitable for the first depth level (level 3 in this embodiment).

[0090] 2. Examples of complex DIV instruction operations are shown in Table 4. Table 4

[0091] The complete calculation formula is: α = 1 × log2(32) / 3 ≈ 1.67, which is adapted to the second depth level (level 4 in this embodiment) after physical security verification.

[0092] 3. Examples of DIV instruction R_d=0 (key scenarios) are shown in Table 5. Table 5

[0093] In this example, the R_d=0 bypass logic sets D_α to the preset shallowest pipeline depth, but the physical safety enforcement circuit, based on the safety threshold table stored in the STA, forces the minimum safety depth of the DIV instruction to the second depth level, ultimately outputting the second depth level to ensure timing compliance. This demonstrates the collaborative working method of R_d=0 bypass and physical safety verification—R_d=0 only skips α calculation, not physical safety verification.

[0094] 4. Examples of the β=1 case (complete bypass) are shown in Table 6. Table 6

[0095] III. Global α-Depth Level Comparison Table, as shown in Table 7 Table 7

[0096] Explanation regarding the third / fourth depth levels: Triggering the third and fourth depth levels requires a wait period condition of R_d ≥ 5 (α ≤ 0.6) or R_d ≥ 7 (α ≤ 0.3). In typical CoreMark and other benchmark tests, since the data hazard detection unit can resolve most data hazards, the R_d value is usually 0~2. Therefore, the actual trigger rate of the third / fourth depth levels in this test load is approximately 0%. This is not design redundancy—the value of the third / fourth depth levels lies in the timing guarantees in the following extreme scenarios: (1) Long dependency chain: When multi-cycle instructions (DIV) are continuously dependent, R_d can reach more than 5; (2) Load-Use hazard: Cache misses lead to prolonged waiting periods; (3) Process angle deviation: The remaining execution cycle of multi-cycle instructions increases under the SS process angle.

[0097] The third / fourth depth level is positioned as a "hard safety margin mechanism". Its value lies in "backup" rather than "common use" - ensuring that instructions can comply with timing in any extreme situation.

[0098] The overall technical solution flowchart of this invention is as follows: Figure 1 As shown, the five-step complete scheduling process is illustrated (parallel parameter acquisition → bypass determination and efficiency factor calculation → physical security verification → pipeline hardware configuration → instruction hierarchical execution), which includes three independent paths: β=1 full bypass, R_d=0 partial bypass, and physical security verification.

[0099] The difference between R_d=0 bypass logic and β=1 bypass logic: R_d=0 bypass: Skip α calculation, D_α = preset shallowest pipeline depth enters the physical safety enforcement circuit, and the maximum value of D_min is taken before output. High-complexity instructions (such as DIV) are still protected by the physical safety mechanism.

[0100] β=1 bypass: Completely skips α calculation, threshold comparison, and physical safety enforcement circuitry, directly outputting the preset shallowest pipeline depth. β=1 corresponds to no-operation instructions such as NOP, with no actual computation and no need for timing protection.

[0101] When the decoder ROM outputs β=1, log2(1)=0. If calculated according to the formula, α=0, which will trigger the deepest pipeline allocation, resulting in wasted power consumption. This invention sets a β=1 bypass comparator at the logarithmic LUT output of the α operation link. This comparator operates independently of the α operation path. When β=1 is detected, it directly outputs the preset shallowest depth code to the encoder, while shielding the output of the α operation path (tri-state gate isolation). When the data hazard detection unit outputs the zero flag signal (zero_flag), the R_d=0 bypass logic outputs D_α=the preset shallowest pipeline depth to the physical safety enforcement circuit, instead of directly outputting the final depth. The R_d=0 bypass logic and the β=1 bypass logic run in parallel but have different processing paths. Both can trigger the preset shallowest depth code output, but R_d=0 must undergo physical safety verification, while β=1 completely bypasses the physical safety verification.

[0102] IV. Fault-Tolerant Design of Depth Tag Encoding This invention employs a non-contiguous encoding mapping, leaving redundant states between legal encodings. When a soft error causes a depth label to fall into a reserved illegal encoding state, the hardware automatically identifies this and triggers a flushing mechanism. Those skilled in the art can choose different encoding schemes based on chip reliability requirements; for example, an extended encoding scheme with a larger Hamming distance can be used in space applications.

[0103] In this embodiment, 3-bit binary encoding is used to correspond to four depth levels: 011 (first depth level), 100 (second depth level), 101 (third depth level), and 110 (fourth depth level), with 000, 001, 010, and 111 reserved as illegal encoding states. Non-contiguous encoding has the following design advantages: (1) Illegal encoding reservation: Illegal encodings 000, 001, 010, and 111 will not appear during normal operation. When the depth tag falls into the illegal encoding range due to a single event flip (SEU) or hardware failure, the hardware automatically flushes the entire pipeline stage, and the instruction is re-emitted at the bottom depth. Some single-bit flips of legal encodings (such as 011→001, 011→010, 011→111, 100→000, 100→110) will fall into the illegal state and be detected, thus improving the reliability of the system in the space environment.

[0104] (2) Reduce the probability of misjudgment: Compared with continuous encoding (000, 001, 010, 011), non-continuous encoding makes the proportion of illegal encoding states in the encoding space higher (illegal states account for 50% in 3-bit encoding). Single particle flip reduces the probability of depth labels falling into legal states, thereby reducing the risk of misjudgment.

[0105] (3) Scalability: For scenarios with higher reliability requirements (such as aerospace-grade chips), those skilled in the art can adopt a more bit encoding scheme (such as 4-bit encoding) without changing the core scheme of the present invention, maintain a larger Hamming distance between legal codes, so that the single bit flip of any legal code falls into an illegal state, thereby achieving complete detection of single bit errors.

[0106] A Comparison of the Dynamic Configuration Pipeline Architecture of this Invention with the Traditional Fixed Depth Pipeline Architecture Figure 2 As shown, the left side is the traditional fixed-depth pipeline (all instructions flow through all stages), and the right side is the dynamic configuration pipeline of this invention (including depth label generation and in-path delivery, independent control of each level of ICG, and bypass write-back path).

[0107] V. Combinational Logic Hardware Architecture of the α Computation Module The entire α operation chain is a pure combinational logic circuit with no register timing overhead, and all operations are completed in a single decoding cycle.

[0108] 1. Pre-parameter acquisition circuit β is output in parallel by looking up a table in the decoder ROM; R_d is output by the combinational logic of the data hazard detection unit, with a combinational logic delay of <0.5ns (based on 28nm process and typical process corner TT), adapting to 1GHz single-cycle timing constraints. When R_d=0, the pre-parameter acquisition circuit outputs D_α=the preset shallowest pipeline depth to the physical safety enforcement circuit, without initiating subsequent division operations; when β=1, the pre-parameter acquisition circuit directly outputs the preset shallowest depth code to the encoder, while completely bypassing the physical safety enforcement circuit.

[0109] 2. Three-level serial operation submodule Logarithmic approximation sub-circuit: Equipped with an 8-bit input read-only LUT, pre-stores the fixed-point amplified value of log2β, directly reads the logarithmic value, and compensates for non-standard β values ​​by linear interpolation of adjacent points, with an interpolation error of <±3%.

[0110] Fixed-point division sub-circuit: The logarithmic result is shifted and amplified to improve the accuracy of the operation. The division operation is completed by relying on the shift subtraction divider, and the amplified fixed-point value of α is output.

[0111] Parallel comparison encoding sub-circuit: Multiple comparators synchronously compare the fixed-point value of α with the preset threshold, and the encoder directly compiles and outputs the calculated depth D_α.

[0112] The above-mentioned parallel acquisition and three-stage serial operation link for dual parameters β and R_d is as follows: Figure 3 As shown.

[0113] VI. Shallowest-level hardware implementation In a standard 5-stage pipeline (fetch → decode → execute → memory access → write-back), simple instructions like ADD, after completing ALU operations in the EX stage (stage 3), originally still needed to pass through the MEM and WB stages before being written back. This invention adds a dedicated bypass write-back MUX at the EX stage output. When the instruction depth label indicates the preset shallowest pipeline depth, this MUX selects the EX stage operation result, which, after being queried by the pipeline register, is directly connected to the write-back data bus, bypassing the subsequent MEM and WB stages. Simultaneously, the ICG clock gating of stages 4 (MEM) and 5 (WB) is pulled low by the stage depth comparator, completely shutting off the subsequent stage clock. This bypass path is pure combinational logic with no additional timing overhead.

[0114] The shallowest depth bypass write-back path mentioned above is as follows: Figure 4 As shown.

[0115] VII. Overall Incremental Hardware Engineering Architecture This invention belongs to the traditional pipeline incremental modification architecture. It does not change the original instruction fetch, decode, execute, memory access, and write-back to the native data stream. It only adds a decode-level deep prediction unit, a physical security enforcement circuit, ICG clock gating for each stage of the pipeline, and an output MUX gating unit.

[0116] 1. R_d acquisition circuit Hardware components: 32-entry 8-bit register mapping table (general purpose register write-back mapping table) and 32-entry map_cc table (condition code register write-back mapping table), 8-bit global instruction counter instr_cnt, pipeline-level tracer, multi-cycle instruction execution status tracer, data ready status monitor, and multi-channel difference comparison logic.

[0117] Overflow protection logic: When instr_cnt overflows and wraps around, it relies on the historical instruction number in the mapping table to perform saturation processing or full table flushing and updating to ensure that R_d calculation will not result in an incorrect number of waiting cycles due to counter overflow, and avoids the misjudgment that R_d=0 due to the counter returning to zero.

[0118] Execution logic: During the decoding phase, the historical write-back instruction numbers of the source register (including the condition code register) are read synchronously. The current pipeline stage (EX / MEM / WB) of the preceding instruction and its remaining execution cycles are queried. Combined with the data readiness status of the preceding instruction, a comprehensive judgment is made, and the R_d value is output. During the instruction write-back phase, the corresponding map entry number of the target register and the corresponding entry in the condition code register map_cc are updated synchronously.

[0119] When R_d=0, the difference comparison logic simultaneously outputs a zero flag signal to both the bypass logic and the physical safety enforcement circuit. Upon receiving this signal, the physical safety enforcement circuit outputs the maximum value between D_α (the preset shallowest pipeline depth) and D_min, instead of directly outputting the preset shallowest depth. This zero flag signal is a combinational logic output, valid simultaneously with the R_d value during the decoding cycle, without adding any additional timing overhead.

[0120] 2. Depth label generation and in-path delivery The result of the α operation is encoded as a lightweight depth tag, which, after being verified by a physical security enforcement circuit, is embedded in the instruction control field and passed level by level along with the instruction data stream. A 6-level pipeline requires only a 3-bit tag encoding, and the tag remains fixed throughout the process until the instruction is written back.

[0121] 3. Independent control logic for single-level pipelines Each pipeline stage is equipped with an independent digital comparator, which compares the stage number N and the instruction depth tag D, and independently controls the stage's ICG and MUX. There is no feedback or state synchronization between stages, as shown in Table 8. Table 8

[0122] The above multi-stage pipeline topology is as follows: Figure 5 As shown.

[0123] Anomaly fallback: The depth tag D is a multi-bit binary code, 3 bits in this embodiment. Valid values ​​are 011 (first depth level), 100 (second depth level), 101 (third depth level), and 110 (fourth depth level). When the tag code is an invalid reserved value (000, 001, 010, 111), the hardware automatically flushes the entire pipeline stage, and the instruction is re-emitted at the fallback depth. This mechanism also covers tag anomalies caused by soft errors such as single-event upsets (SEU).

[0124] 4. Adaptation to complex instructions across multiple cycles DIV and floating-point multi-cycle instructions rely on the built-in done function of the execution unit to complete signal linkage control. If the instruction is not completed within the preset timeout counter threshold T_timeout (64 clock cycles in this embodiment), a partial pipeline flush is triggered, and the instruction re-enters the scheduling queue to wait for re-emission.

[0125] 5. Native out-of-order execution architecture compatible with ROB collaborative scheduling Depth tags are generated during the front-end decoding stage of the retention station. Tags are stored in the retention station and the reorder buffer (ROB) along with instructions. Storage space for tags is reserved in the ROB for each instruction. The retention station reads back the corresponding depth tag using the ROB index.

[0126] ROB Cooperative Scheduling Implementation: While generating the depth label D, the depth encoder reads the current value C_cur of the global period counter, generates the estimated completion period T_pred = C_cur + D, and stores it in the new field of the ROB entry. Before issuing a new instruction, the station reads the T_pred value of the ROB header instruction. If the remaining space in the ROB is lower than a preset threshold and the estimated completion period of the header instruction is greater than the sum of the current period and the preset margin, the issuance of new instructions is paused. When the instruction is completed, the execution unit writes the actual completion period T_actual into the ROB. When the deviation between T_actual and T_pred exceeds a preset threshold, the prediction failure correction mechanism is triggered, the scheduler updates T_pred to T_actual, and exits the paused state.

[0127] 6. Hardware depth limit fallback mechanism The hardware presets a maximum pipeline stage number M_max. For extremely complex instructions that exceed the scheduling capacity, a fallback depth of M_max is uniformly allocated. Multi-cycle iterative calculations are performed based on the execution unit's built-in state machine, which is compatible with traditional multi-cycle instruction execution logic.

[0128] VIII. Extended Applications for In-Memory Computing Architectures This embodiment illustrates the extended application of the present invention in in-memory computing architectures. In in-memory computing architectures, computing units can be distributed near or inside the storage array, and the energy consumption and latency of different computing tasks executed at different locations vary significantly. The depth tag of the present invention can carry pipeline depth control information and computing paradigm adaptation information simultaneously during the decoding stage, making it suitable for scheduling decisions in in-memory computing heterogeneous computing scenarios.

[0129] 1. An Extended Interpretation of Deep Tagging in In-Memory Computing Architectures The fields of the depth tag in this invention can be further interpreted in the context of in-memory computing as shown in Table 9: Table 9

[0130] After the depth tag is generated during the decoding stage, it is not only sent to each stage of the pipeline along with the instructions, but also simultaneously delivered to the configuration register group of the in-memory computing unit via a separate feedforward control bus. This configuration register group is located at the boundary between the SM and the in-memory computing unit. The alpha_code and depth_level fields in the depth tag are mapped to control signals of the in-memory computing unit, which are then read by its internal memory array controller and compute unit configuration interface. In this embodiment, this control bus is a dedicated signal path with a width of 8 bits (covering 2 bits for depth_level, 3 bits for alpha_code, 1 bit for retire_enable, and 2 reserved bits), and does not occupy the instruction data path bandwidth.

[0131] 2. Scheduling strategy extension Based on the extended information from the depth labels, the scheduler can perform the following additional decisions: (1) Computation paradigm selection: When the alpha_code in the depth label indicates that the data movement sensitivity of the instruction is low—that is, the data required by the instruction already exists in the current storage level (such as SRAM cache, register file, HBM), or the data dependency depth R_d is less than the preset threshold R_d_th (R_d_th=4 cycles in this embodiment)—the scheduler marks the instruction as "in-memory computing adaptation" and prioritizes its allocation to the near-memory computing unit for execution, so as to shorten the data movement path and reduce access energy consumption.

[0132] The value of R_d_th=4 cycles is determined as follows: when R_d≤4, the data required by the instruction has already been hit in the L1 / L2 cache or register file, and the data transfer distance is short; when R_d>4, the instruction needs to wait for a longer memory access latency (usually an L3 cache miss or DRAM access), resulting in high data transfer costs. This threshold can be determined through static timing analysis or simulation based on the specific process and memory level latency, and can be adjusted through firmware register configuration in different implementations.

[0133] Conversely, when alpha_code indicates high data movement sensitivity (R_d is large or cross-memory access is required), the instruction is still assigned to the traditional kernel for execution.

[0134] (2) Heterogeneous retirement mechanism: The execution results of instructions completed in the in-memory computing unit can be directly retained in the storage medium. The retire_enable flag in the depth tag controls this process - when the flag is 1, the execution results of the in-memory computing unit are directly written to the storage medium through an independent result bus, without going through the EX level bypass to write back to the MUX.

[0135] It should be noted that the bypass write-back mechanism of this invention has the same physical implementation basis as the aforementioned embodiments in the in-memory computing scenario: the traditional bypass write-back MUX serves the write-back of results from the internal execution unit of the pipeline (the EX-level operation result is selected to the write-back data bus after being queried by the pipeline register), while the in-memory computing result bus serves the in-memory computing unit. The two are physically independent but logically coordinated. When the depth label indicates the traditional path, the MUX selects the EX-level operation result; when the depth label indicates the in-memory computing path, the MUX is placed in a high-impedance state, and the in-memory computing result bus takes over the write-back operation.

[0136] (3) Cross-domain collaboration and data consistency maintenance: The deep tag serves as a coordination signal between the traditional core and the in-memory computing unit, ensuring the operation sequence and data consistency between the two computing domains. Specifically, it includes: a) Operation Sequence Management: The depth tag is transmitted to the local controller of the in-memory computing unit along with the task descriptor. The local controller returns the execution results of the in-memory computing unit in the original instruction order based on the instruction sequence number and dependency markers carried in the depth tag, avoiding submission errors caused by out-of-order execution. In this embodiment, the instruction sequence number is generated during the decoding stage and encoded in a reserved field of the depth tag, without adding additional signal overhead.

[0137] b) Data consistency maintenance: Traditional cores and in-memory compute units share the same storage view. When a depth label indicates that a task has been completed in an in-memory compute unit, the local controller sends a completion signal to the system cache consistency protocol unit (such as the MESI protocol controller), triggering a status update of the corresponding cache line (from "modified" or "exclusive" to "shared"), ensuring that the traditional core can obtain the correct latest value when reading the data subsequently, without waiting for explicit memory barrier instructions.

[0138] c) Cross-domain handshake protocol: When part of an instruction's operation is executed in the traditional kernel and part in the in-memory compute unit, the depth tag serves as a handshake signal between the two compute domains. Before initiating a cross-domain operation, the traditional kernel writes the depth tag into the in-memory compute unit's configuration register; after the in-memory compute unit completes the operation, it notifies the traditional kernel via an interrupt or a status register write-back. In this embodiment, the depth tag acts as a handshake token, ensuring the atomicity of cross-domain operations—at any given time, the depth tag belongs to only one compute domain.

[0139] 3. Technical Effects This extended application demonstrates that the depth tagging mechanism of the present invention is not only applicable to traditional pipeline depth control, but can also be extended to in-memory computing architectures, serving as a unified scheduling information carrier between tasks and traditional core and near-memory computing units, providing a foundation for energy efficiency optimization in heterogeneous computing scenarios.

[0140] Those skilled in the art will understand that the above-described extended applications are based on the same deep tag generation and transmission principle as the aforementioned embodiments—deep tags are always generated at the decoding level based on α values, are always transmitted step-by-step with instructions / tasks, and always serve as a unified information carrier for backend decision-making. The only difference lies in the interpretation method of the tag field (extended from "pipeline stage" to "computation paradigm type") and the scheduling objective (extended from "deep control" to "cross-domain scheduling"). Therefore, the scope of protection of this invention is not limited to traditional pipeline architectures, but can also cover heterogeneous computing architectures such as in-memory computing and near-memory computing.

[0141] IX. Overall Hardware Overhead Statistics Taking a 10-stage standard pipelined core as an example, the details of the new hardware are shown in Table 10 below: Table 10

[0142] With the 28nm advanced process, compared to the total core area of ​​the original 10-stage pipeline (typically about 6 million gates), the total increase in hardware area is about 0.047%, and the area and power consumption overhead are negligible.

[0143] 10. Verification Results This invention was verified using the Verilator RTL simulation environment and the CoreMark benchmark program as the test load (approximately 35% simple ALU instructions, 45% medium instructions, and 10% complex instructions).

[0144] 1. Depth distribution, as shown in Table 11 Table 11

[0145] 2. Power consumption estimation, as shown in Table 12 Table 12

[0146] 3. Activity rates of each level of the production line, as shown in Table 13. Table 13

[0147] The above verification results demonstrate that the present invention can effectively achieve instruction-level pipeline depth adaptive scheduling, resulting in significant power consumption reduction under typical loads. The clock cycles of stages 4-6 are shut down for 85%-100% of the time, which is the core reason for the power consumption reduction.

[0148] It is understood that the systems, devices, and storage media provided in the embodiments of the present invention correspond to the methods provided in the embodiments of the present invention, and the explanations, examples, and beneficial effects of the relevant content can be referred to the corresponding parts of the above methods.

[0149] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0150] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A processor pipeline depth control method based on information processing efficiency quantification and resource matching, characterized in that, comprising the following steps: in the instruction decoding stage, acquiring an intrinsic complexity parameter β and a data dependency depth R_d of the current instruction; wherein β is a quantified integer value characterizing an instruction opcode classification space, and the value of β is obtained by table lookup mapping according to instruction types; R_d is a quantified integer value characterizing the number of clock cycles that the current instruction needs to wait for because source register data is not ready, and is dynamically output by a data hazard detection unit; performing bypass judgment according to the β and R_d: if β=1, directly outputting a preset shallowest pipeline depth as a final pipeline depth D_final, and skipping the efficiency factor formula calculation, threshold comparison step and physical security check step; if R_d=0 and β≠1, skipping the efficiency factor formula calculation, and outputting the preset shallowest pipeline depth as a calculation depth D_α to the physical security check step; when R_d≠0 and β≠1, substituting the β and R_d into an efficiency factor formula α = k × log2(β) / R_d, calculating an efficiency factor α by a hardware combinational logic circuit within a single decoding cycle, wherein k is a scaling constant greater than 0; comparing the efficiency factor α with at least two preset thresholds, and determining a pipeline depth corresponding to the current instruction as a calculation depth D_α according to a comparison result; executing the physical security check step: taking the calculation depth D_α and the β value of the current instruction as inputs, querying a pre-stored security threshold table to obtain a minimum safe physical depth D_min of the instruction; if D_α<D_min, outputting D_min as the final pipeline depth D_final; if D_α ≥ D_min, outputting D_α as the final pipeline depth D_final; generating a depth tag corresponding to the final pipeline depth, wherein the depth tag is a multi-bit binary code for identifying the final pipeline depth, and the depth tag is transmitted step by step along with the current instruction in the pipeline; each stage of the pipeline independently determines a clock gating switch state and a data path gating state of the current stage according to a comparison result between the depth tag and a current stage number; after the current instruction completes operation at a termination stage corresponding to the depth tag, exiting the pipeline through a bypass write-back path, and turning off clock gating of each pipeline stage after the termination stage.

2. The method according to claim 1, characterized in that, the preset shallowest pipeline depth is 3 stages, and the corresponding physical exit stage number is 4 stages; after being latched by a pipeline register at an output end of an execution stage, the instruction exits through the bypass write-back path.

3. The method according to claim 1, characterized in that, the value range of the intrinsic complexity parameter β is 1~256; β of a simple operation instruction is 8, β of a memory access comparison instruction is 16, and β of a complex branch iteration instruction is 32.

4. The method according to claim 1, characterized in that, the value of the data dependency depth R_d is determined based on one or more of the following items: a pipeline stage distance between the current instruction and a preceding instruction, a current pipeline stage of the preceding instruction and the data ready status thereof, and the number of remaining execution cycles of the preceding instruction; for a multi-source register instruction, R_d takes the maximum value of the waiting cycle numbers corresponding to all source registers.

5. The method according to claim 1, characterized in that, The depth tag uses non-continuous encoding, with illegal encoding states reserved between legal encodings; when the depth tag is detected to fall into an illegal encoding state, the hardware automatically flushes the entire pipeline stage, and the instruction is retransmitted at the bottom depth.

6. The method according to claim 1, characterized in that, It also includes the reordering buffer ROB cooperative scheduling mechanism: While generating depth labels, read the current value C_cur of the global cycle counter, generate the expected completion cycle T_pred = C_cur + D and store it in the new field of the ROB entry, where D is the pipeline depth value corresponding to the depth label; Before issuing a new command, retain the station to read the estimated completion cycle value of the ROB header command; If the remaining ROB slots are lower than the preset threshold and the expected completion period of the header instruction is greater than the sum of the current period and the preset margin, then the issuance of new instructions will be paused. When the execution unit completes the instruction, it writes the actual completion cycle into the ROB. When the deviation between the actual completion cycle and the expected completion cycle exceeds a preset threshold, the prediction failure correction mechanism is triggered.

7. The method according to claim 1, characterized in that, The termination level is the current level where the pipeline depth value D corresponding to the depth label is equal to the level number N, and D=N; when D>N, the current level is passed through, and when D<N, the current level is clock-gated off.

8. The method according to claim 1, characterized in that, Each level of the pipeline's independent control unit includes an independent digital comparator, a clock gating ICG, and an output strobe MUX. There is no feedback or state synchronization between levels. Multi-cycle complex instructions are controlled by the execution unit's built-in done signal. If the instruction is not completed after exceeding the preset timeout counter threshold, a partial pipeline flush and instruction rescheduling are triggered.

9. The method according to claim 1, characterized in that, The processor is at least one of a central processing unit (CPU) and a digital signal processor (DSP), or the processor is a memory-based processor.

10. The method according to claim 1, characterized in that, The depth tag is also used for computing paradigm adaptation in the in-memory computing architecture. The fields of the depth tag include a depth level field, a data movement sensitivity field, and a retirement enable field. The depth level field is used to indicate the pipeline depth level or the computational paradigm type to which the instruction is adapted; The data movement sensitivity field is used to indicate the data movement sensitivity level of the instruction; The retirement enable field is used to indicate whether the execution results are allowed to be directly retained in the storage medium.

11. The method according to claim 10, characterized in that, When the data transfer sensitivity field in the depth label indicates that the data transfer sensitivity of the instruction is lower than a preset threshold, the instruction is assigned to the near-memory computing unit for execution. When the data transfer sensitivity field indicates that the data transfer sensitivity of the instruction is not lower than the preset threshold, the instruction is assigned to the traditional kernel for execution.

12. The method according to claim 11, characterized in that, When the retirement enable field in the depth label indicates that the execution result can be directly retained in the storage medium, the execution result of the instruction completed in the in-memory computing unit is directly written to the storage medium through an independent result bus without going through a bypass write-back path.

13. A processor pipeline depth control device based on information processing efficiency quantification and resource matching, used to implement the method described in any one of claims 1-12, characterized in that, Include: The intrinsic complexity parameter acquisition circuit is used to read the intrinsic complexity parameter β of the current instruction from the read-only instruction classification ROM during the decoding stage. The data dependency depth tracking circuit is used to calculate the data dependency depth R_d of the current instruction based on the register write-back mapping table and the global instruction counter. The efficiency factor calculation circuit includes a logarithmic lookup table sub-circuit and a fixed-point division sub-circuit. When R_d ≠ 0 and β ≠ 1, it substitutes β and R_d into α = k × log2(β) / R_d to calculate the efficiency factor α and outputs the corresponding calculation depth D_α. When R_d = 0 and β ≠ 1, the efficiency factor calculation circuit is bypassed, and the preset shallowest pipeline depth is directly output as the calculation depth D_α to the physical safety enforcement circuit. When β = 1, the efficiency factor calculation circuit is completely bypassed, and the preset shallowest pipeline depth is directly output as the final pipeline depth D_final to the depth encoder, without passing through the physical safety enforcement circuit. The physical safety enforcement circuit includes a safety threshold table and a comparator, which is used to query the minimum safe physical depth D_min of the instruction with the calculated depth D_α and the β value of the current instruction as input, and take the maximum value of D_α and D_min to output the final pipeline depth D_final; A depth encoder is used to generate a corresponding depth label based on the final pipeline depth D_final, wherein the depth label is a multi-bit binary code. The depth tag-as-you-go register is set between each stage of the pipeline and is used to carry the depth tag and move synchronously with the instructions. Each pipeline level has an independent control unit, and each level includes a level number comparator, a clock gating ICG, and an output gating MUX. These units are used to jointly decide the clock gating switch status and data path gating status of the level based on the comparison result between the depth tag and the level number, the valid signal of the pipeline level, and the global Stall / Flush control signal. The bypass write-back MUX, set at the execution level output, is used to select the execution result to the write-back data bus when the depth label indicates the preset shallowest pipeline depth.

14. The apparatus according to claim 13, characterized in that, The efficiency factor operation circuit is implemented using combinational logic, and completes the full operation from β and R_d to the computation depth D_α in a single decoding cycle.

15. A processor chip, characterized in that, It includes a processor pipeline depth control device based on information processing efficiency quantification and resource matching as described in claim 13 or claim 14.

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