A phase-branch adaptive redundancy and fault-tolerant array and method

Abstract

The application discloses a phase branch adaptive redundancy and fault-tolerant array. The array comprises: a redundancy branch array, containing a main branch and a redundancy branch; a bad point detection circuit, detecting phase errors and current amplitudes of each branch, and outputting a failure flag; and a dynamic reconfiguration controller, dynamically switching functions of a failed main branch to an idle redundancy branch according to the failure flag, and updating an effective branch mapping table. The application replaces a failed branch with a small number of redundancy branches, significantly improves reliability and yield of a projection computer with a small area overhead, supports online reconfiguration and self-checking, and is suitable for a high-reliability parallel analog computing system.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits and parallel computing architecture technology, specifically to a general-purpose phase computing chip architecture and its control method based on parallel projection angle modulation. This invention is particularly applicable to general-purpose control chip scenarios in multi-physics field applications such as the chip-based implementation of parallel phase modulation modules, acceleration of large-scale parallel phase computing, topology material-driven array control, and optical computing / gravitational field / neural modulation. Background Technology

[0002] With the establishment of a unified geometric field theory system and the maturity of topological material manipulation technology, an increasing number of physical field applications (gravitational field manipulation, terahertz phased arrays, neural field phased arrays, optical computation matrix multiplication, etc.) require a common core capability: real-time generation and distribution of massively parallel phase signals. This requirement cannot be efficiently met in existing chip architectures. Existing chip architectures can be mainly categorized as follows: (a) General-purpose microprocessors / digital signal processors Phase control signals for each channel are generated by software programming and then output after digital-to-analog conversion. This type of scheme has the following problems: (1) The serial instruction execution mode cannot achieve true simultaneous parallel output; (2) Digital-to-analog conversion introduces delay and accuracy loss; (3) Phase calculation of a large number of channels occupies CPU resources and has poor real-time performance; (4) High power consumption, which is not suitable for implantable or portable devices. (ii) Field Programmable Gate Array Multi-channel phase signal generation is achieved through hardware parallelism. This type of scheme has the following problems: (1) complex programming and long development cycle; (2) the phase synchronization accuracy between channels is limited by the FPGA clock network; (3) the resource consumption is huge when the number of channels is large (>256); (4) the phase resolution is limited by the bit width of the internal lookup table. (iii) Application-Specific Integrated Circuits Phase control chips are customized for specific applications. This type of solution has the following problems: (1) high design and manufacturing costs and long cycle; (2) fixed functions and lack of versatility; (3) difficult to adapt to different needs of various physical field applications; (4) each technology iteration requires re-fabrication. (iv) Parallel scheme based on microcontroller array Parallel output is achieved by multiple microcontrollers working together. This type of solution has the following problems: (1) inter-chip communication delay leads to a decrease in phase synchronization accuracy; (2) system complexity increases exponentially with the number of channels; (3) power consumption and area consumption are huge. In summary, the fundamental deficiency of existing chip architectures lies in the lack of a dedicated chip architecture capable of simultaneously achieving large-scale parallel phase output, high synchronization accuracy, and programmable versatility. This invention proposes for the first time a general-purpose phase calculation chip architecture based on parallel projection angle control, realizing a direct mapping from algorithm to physical phase. Summary of the Invention

[0003] (a) Purpose of the invention This invention provides a general phase computing chip architecture and its control method based on parallel control of projection angle, aiming to solve the technical problem that existing chip architectures cannot efficiently realize large-scale parallel phase signal generation and distribution. (II) Technical Principles This invention is based on the principle of phase parallel computation. In this invention, the general-purpose phase computation chip is implemented through the following architecture: Core computing unit: The chip contains multiple phase calculation cores, each of which independently calculates a projection angle θ_i. The operations of each core are independent of each other, with no data dependency, and can be completed simultaneously on the same clock edge. Parallel distribution network: The calculation results of each phase calculation core are transmitted to the corresponding output pin within the same clock cycle through the parallel distribution network. The distribution network adopts a parallel bus structure, eliminating serialization bottlenecks. Programmable phase mapping: The chip has a built-in programmable phase mapping table that supports mapping input control data (such as frequency, amplitude, phase offset, etc.) to projection angle θ_i. The mapping table can be updated online via an external interface. Multi-chip cascading expansion: The chips support master-slave cascading mode, and multiple chips can work together through synchronous clocks and cascading interfaces to achieve a larger number of phase output channels. The fundamental difference from existing technologies: This invention is not a serial architecture of "general-purpose processor + digital-to-analog converter" nor a general-purpose hardware architecture of "FPGA + lookup table", but a dedicated chip architecture optimized for phase parallel computing, achieving the highest efficiency and lowest latency in phase computing. (III) Technical Solution A general-purpose phase calculation chip based on parallel control of projection angle, characterized in that it comprises: Multiple phase calculation cores are arranged in an array, and each core independently calculates a projection angle θ_i; The parallel distribution network connects the output terminals of each phase calculation core and is used to transmit each projection angle to the corresponding output pin within the same clock cycle. A programmable phase mapping table, connected to the phase calculation core, is used to map input control data into projection angles; The clock synchronization network is used to provide a synchronous clock signal for each phase computing core, ensuring that the calculations of each core are completed on the same clock edge; The external interface module is used to receive external control commands and programming data, as well as output chip status information. A general phase control method based on parallel projection angle modulation, characterized by the following steps: S1: Receives control commands and phase mapping data through an external interface module and programs the phase mapping table; S2: Each phase calculation core starts calculation simultaneously at the edge of the synchronous clock, and calculates its corresponding projection angle θ_i in parallel. S3: The calculation results of each core are transmitted to the corresponding output pin within the same clock cycle through the parallel distribution network; S4: Output pin drives external topological materials or actuators to achieve phase modulation of the physical field; S5: Repeat steps S2 to S4 to achieve continuous real-time phase control. (iv) Beneficial effects First, it achieves large-scale parallel phase output, with the number of channels expandable to over 1024, far exceeding existing solutions. Second, the phase synchronization accuracy of each channel is better than 100 picoseconds, meeting the requirements of high-precision phase control applications. Third, the programmable phase mapping table supports multiple physical field applications, making it a versatile chip. Fourth, multi-chip cascading supports unlimited expansion, adapting to application scenarios of different scales. Fifth, power consumption is less than 1 watt per 100 channels, making it suitable for implantable and portable devices. Detailed Implementation

[0004] Example 1 (256-channel general-purpose phase calculation chip) Step 1: Chip architecture design. The design incorporates a chip with 256 phase calculation cores arranged in a 16×16 array. Each core contains a multiplier, an adder, a phase accumulator, and a lookup table, and can independently calculate the projection angle θ_i. Step 2: Configure the programmable phase mapping table. The phase map table can be programmed into three operating modes via an external interface: direct phase output mode (θ = input data), frequency synthesis mode (θ = θ0 + ω·t), and array scanning mode (θ = θ0 + k·x + l·y). Step 3: Parallel computation and output. At a 100MHz synchronous clock, 256 cores simultaneously calculate their respective projection angles and output them to 256 pins within the same clock cycle via a parallel distribution network. The phase update rate is 100MHz, and the phase synchronization accuracy of each channel is better than 100ps. Step 4: Application verification. The chip was used to drive a topological terahertz metasurface array, a neurostimulation electrode array, and an optical computing weight array, respectively, verifying the chip's versatility in three different physical field applications. Example 2 (Multi-chip cascaded 1024-channel system) Four 256-channel chips are cascaded to achieve 1024 channels of parallel phase output through a master-slave clock synchronization mode. The master chip generates a synchronization clock signal, and the slave chips lock onto the same clock source. The system has a total of 1024 phase output channels, with synchronization accuracy of each channel better than 200ps. Example 3 (Low-power implanted version) The chip channel count has been reduced to 64, the operating voltage has been lowered to 0.8V, the clock frequency has been reduced to 10MHz, and the total power consumption is less than 5mW. The chip size is less than 2mm × 2mm, making it suitable for implantable neurostimulators and cochlear implants. Example 4 (High-speed optical computing version) The chip clock frequency was increased to 1GHz, and the number of channels was configured to 128 to drive the weight array of the optical computing chip. The phase update rate was 1GHz, supporting nanosecond-level reconfiguration of optical computing weights. Attached Figure Description

[0005] Figure 1 This is a block diagram of the overall architecture of the general phase calculation chip based on parallel control of projection angle according to the present invention. Figure 2 This is a schematic diagram of the internal structure of the phase calculation core. Figure 3 This is a schematic diagram of a parallel distribution network structure (N=8). Figure 4 This is a flowchart of the general phase control method of the present invention. Figure 5 This is a schematic diagram of a typical application scenario of the present invention. Terminology Explanation

[0006] Phase calculation core: The smallest computational unit in the chip that independently calculates a projection angle θ_i. Parallel distribution network: An on-chip interconnect network that simultaneously transmits the computation results of each core to the corresponding output pin. Programmable phase mapping table: An online programmable lookup table that maps input control data to projection angles. Multi-chip cascading: Multiple chips can work together through master-slave synchronization mode to expand the number of output channels.

Claims

1. A general phase control method based on parallel projection angle adjustment, characterized in that, Includes the following steps: S1: Receives control commands and phase mapping data through an external interface module and programs the phase mapping table; S2: Each phase calculation core starts calculation simultaneously at the edge of the synchronous clock, and calculates its corresponding projection angle θ_i in parallel. S3: The calculation results of each core are transmitted to the corresponding output pin within the same clock cycle through the parallel distribution network; S4: Output pin drives external topological materials or actuators to achieve phase modulation of the physical field; S5: Repeat steps S2 to S4 to achieve continuous real-time phase control.

2. A general-purpose phase calculation chip based on parallel control of projection angle, characterized in that, include: Multiple phase calculation cores are arranged in an array, and each core independently calculates a projection angle θ_i; The parallel distribution network connects the output terminals of each phase calculation core and is used to transmit each projection angle to the corresponding output pin within the same clock cycle. A programmable phase mapping table, connected to the phase calculation core, is used to map input control data into projection angles; A clock synchronization network is used to provide a synchronized clock signal for each phase calculation core; The external interface module is used to receive external control commands and programming data, as well as output chip status information.

3. The chip according to claim 2, characterized in that, The phase calculation core includes at least one of a multiplier, an adder, a phase accumulator, and a lookup table.

4. The chip according to claim 2, characterized in that, The parallel distribution network is a parallel bus structure, with each channel transmitting independently, eliminating serialization bottlenecks.

5. The chip according to claim 2, characterized in that, The programmable phase mapping table supports online real-time reprogramming with a programming time of less than 1 microsecond.

6. The chip according to claim 2, characterized in that, The phase synchronization accuracy of each phase calculation core is better than 100 picoseconds.

7. The chip according to claim 2, characterized in that, The chip supports multi-chip cascading expansion and achieves a larger number of phase output channels through master-slave synchronous mode.

8. The chip according to claim 2, characterized in that, The chip has at least one configuration of phase calculation cores, which is 64, 128, 256 or 1024.

9. The method according to claim 1, characterized in that, The phase mapping table supports at least one of the following operating modes: direct phase output mode, frequency synthesis mode, and array scanning mode.

10. The chip according to claim 2, characterized in that, The chip is applied in at least one of the following fields: topological terahertz phased array, neural field phased array, optical computing chip, gravitational field manipulation, and topological quantum computing.

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