Cache miss backfill method, system, computer device and storage medium

Abstract

The application relates to a cache miss backfill method, a system, computer equipment and a storage medium. The method comprises the following steps: storing a cache miss event of a cache controller in a first-level cache in a miss state holding register; a row buffer and a speculative row buffer module are arranged in the miss state holding register; storing memory data corresponding to the cache miss event in a second-level cache into the row buffer to obtain cache row data; when the cache miss event is a branch speculation event, the cache row data is transferred from the row buffer to the speculative row buffer module; when speculation context information corresponding to the branch speculation event is analyzed as safe, the data in the speculative row buffer module is stored into the first-level cache. The method can reduce the hardware cost.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a cache missing backfilling method, system, computer device, and storage medium. Background Technology

[0002] With the development of computer architecture technology, modern CPUs employ two core optimization techniques to improve speed: out-of-order execution and speculative execution. When a speculative execution error occurs, although the register state visible to the program is restored, the data changes in the CPU cache caused by it may not be completely cleared. This allows attackers to exploit these changes by measuring the time required to access different memory addresses, thereby inferring sensitive data that should not have been accessed during speculative execution.

[0003] In traditional techniques, a shadow copy is created for the entire cache and bypass translation buffer. All speculative operations are performed on this shadow copy. Only when the speculative result is confirmed to be correct is the data in the shadow copy committed to the actual cache; if an error occurs, the data in the shadow copy is discarded. However, this approach requires maintaining a shadow copy for the entire caching system, resulting in high hardware costs and significant overhead.

[0004] It is evident that existing technologies still suffer from high hardware costs and significant overhead associated with out-of-order processors. Summary of the Invention

[0005] Therefore, it is necessary to provide a cache miss backfilling method, apparatus, computer equipment, and storage medium that can reduce hardware costs and overhead in response to the above-mentioned technical problems.

[0006] Firstly, this application provides a cache missing data backfilling method, which includes:

[0007] The cache miss event of the cache controller in the first-level cache is stored in the miss status holding register; the miss status holding register is equipped with a row buffer and a speculative row buffer module;

[0008] The memory data corresponding to the cache miss event in the second-level cache is stored in the line buffer to obtain cache line data;

[0009] When the cache miss event is a branch speculation event, the cache line data is transferred from the line buffer to the speculation line buffer module;

[0010] When the speculation context information corresponding to the branch speculation event is resolved as safe, the data in the speculation line buffer module is stored in the first-level cache.

[0011] In one embodiment, the cache missing backfilling method further includes:

[0012] When the cache miss event is a normal write-back event, the memory data corresponding to the normal write-back event is stored in the first-level cache.

[0013] In one embodiment, the out-of-order processor includes a loading storage unit, and the process of storing the cached line data into the line buffer and obtaining the cached line data includes:

[0014] Obtain the speculative context information corresponding to the cache miss event of the loaded storage unit; the speculative context information includes a branch dependency mask and a storage dependency mask;

[0015] If both the branch dependency mask and the storage dependency mask are zero, then the cache miss event is a normal write-back event.

[0016] If the storage dependency mask is zero and the branch dependency mask is not zero, then the cache miss event is a branch speculation event.

[0017] In one embodiment, after storing the cached line data in the line buffer, the process further includes:

[0018] If the storage dependency mask is not zero, then after responding to the load instruction corresponding to the cache missing event based on the cache line data, the cache line data is discarded.

[0019] In one embodiment, when the cache miss event is a branch speculation event, transferring the cache line data from the line buffer to the speculation line buffer module includes:

[0020] Obtain the event flag bit corresponding to the cache missing event in the loaded storage unit;

[0021] If the event flag is not set, the cached line data and the speculative context information are transferred from the line buffer to the speculative line buffer module.

[0022] In one embodiment, the process of parsing the speculation context information corresponding to the branch speculation event into a safe judgment includes:

[0023] If the branch dependency mask is zero and the storage dependency mask is zero, then check whether there is dirty data in the cache line corresponding to the data in the speculative line buffer module.

[0024] If no dirty data exists, the speculation context information corresponding to the branch speculation event is parsed as safe.

[0025] In one embodiment, the cache missing backfilling method further includes:

[0026] During the lifetime of the missing state holding register or the speculative line buffer module, the branch resolution signal and memory address disambiguation signal of the out-of-order processor are monitored;

[0027] Update the branch dependency mask based on the branch parsing signal;

[0028] Update the storage dependency mask based on the storage address disambiguation signal.

[0029] In one embodiment, storing the memory data of the branch speculation event in the first-level cache includes: writing a reserved flag bit into the first-level cache corresponding to the first target position according to the first target position corresponding to the branch speculation event;

[0030] Before storing the memory data corresponding to the normal write-back event in the first-level cache, the method further includes: determining whether there is a reserved flag bit in the second target position corresponding to the normal write-back event in the first-level cache; if so, there is a write conflict, the normal write-back event is rejected and retried in subsequent cycles.

[0031] Secondly, this embodiment provides a cache miss filling system, which includes an out-of-order processor, a first-level cache, a second-level cache, and a miss status holding register; wherein, the out-of-order processor is communicatively connected to the first-level cache and the miss status holding register; the miss status holding register is communicatively connected to the first-level cache and the second-level cache; the miss status holding register includes a line buffer and a speculative line buffer module; wherein:

[0032] The missing state holding register is used to store cache missing events of the cache controller in the first level cache; the memory data corresponding to the cache missing event in the second level cache is stored in the line buffer to obtain cache line data; when the cache missing event is a branch speculative event, the cache line data is transferred from the line buffer to the speculative line buffer module.

[0033] The speculative line buffer module is used to store the data in the speculative line buffer module into the first-level cache when the speculative context information corresponding to the branch speculative event is parsed as safe.

[0034] Thirdly, this application provides a computer device including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the method described in any of the embodiments described above.

[0035] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the methods described in any of the above embodiments.

[0036] The aforementioned cache miss backfilling method, system, computer device, and storage medium store cache miss events of the cache controller in the first-level cache in a miss status holding register. The miss status holding register is equipped with a row buffer and a speculative row buffer module. Memory data corresponding to the cache miss event in the second-level cache is stored in the row buffer to obtain cache line data. When the cache miss event is a branch speculative event, the cache line data is transferred from the row buffer to the speculative row buffer module. When the speculative context information corresponding to the branch speculative event is resolved as safe, the data in the speculative row buffer module is stored in the first-level cache. The speculative row buffer module in the miss status holding register temporarily stores cache line data that has been returned from the second-level cache but is not allowed to be installed into the first-level cache because the branch has not yet been resolved. Since the speculative row buffer module is a small speculative row buffer structure within the miss status holding register, it avoids creating copies of the entire cache and bypass conversion buffer while ensuring security, thereby achieving the technical effect of reducing hardware costs and overhead while maintaining security. Attached Figure Description

[0037] Figure 1 This is a flowchart illustrating a cache missing data filling method in one embodiment;

[0038] Figure 2 This is a schematic diagram of the process of transferring cache line data to the speculative line buffer module in one embodiment;

[0039] Figure 3 This is a schematic diagram illustrating the process of storing data from the speculative banking buffer module to the first-level cache in one embodiment.

[0040] Figure 4 This is a hardware flowchart of a cache missing backfilling method in one embodiment;

[0041] Figure 5 This is a state transition diagram of a state machine for filling in a missing state holding register in one embodiment;

[0042] Figure 6 Here is a state transition diagram of the speculative line buffer module installation state machine in one embodiment;

[0043] Figure 7 This is an installation flowchart of the speculative line buffer module installing data into the first-level cache in one embodiment;

[0044] Figure 8 This is a structural block diagram of a cache missing data backfilling system in one embodiment;

[0045] Figure 9 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0047] In one embodiment, such as Figure 1 As shown, a cache miss backfilling method is provided, applied to out-of-order processors, including the following steps:

[0048] Step S110: Store the cache miss event of the cache controller in the first-level cache in the miss status holding register.

[0049] The first-level cache can be the cache layer closest to the processor, with the fastest access speed, but the smallest capacity. The cache controller can be a hardware logic unit inside the processor responsible for managing all cache read and write operations, maintaining data consistency, and coordinating data transfer between cache levels and memory.

[0050] The cache miss event can be a series of hardware responses and state transitions triggered when the processor attempts to access a memory address but fails to find a valid copy of the data in the L1 cache.

[0051] The missing state holding register may be an internal processor unit used to manage incomplete memory access requests initiated due to cache misses.

[0052] The missing state holding register is equipped with a row buffer and a speculative row buffer module. The row buffer can be used to temporarily store cached row data returned from the second-level cache or memory, and the speculative row buffer module can be used to temporarily store cached row data in the row buffer.

[0053] Step S120: Store the memory data corresponding to the cache missing event in the second-level cache into the row buffer to obtain cache row data.

[0054] The second-level cache can be a second-level high-speed cache, which has a larger cache capacity than the first-level cache, but a slower access speed.

[0055] To retrieve the memory data corresponding to a cache miss event from the second-level cache, the cache controller of the first-level cache can send a miss request to the second-level cache when a cache miss event occurs. The miss request contains the physical address where the required memory data is stored, and the second-level cache finds the corresponding memory data based on the physical address.

[0056] Storing memory data in a row buffer can be achieved by having a second-level cache write the cached memory data and its metadata into the row buffer; the metadata can be data used to represent the consistency information of the cached rows.

[0057] In this embodiment, cache line data may include memory data, metadata, and status information; the status information may be information indicating whether the cache line is valid, the write address of the cache line data, and the loading instruction corresponding to the cache line.

[0058] Step S130: When the cache missing event is a branch speculation event, the cache line data is transferred from the line buffer to the speculation line buffer module.

[0059] The branch speculation event can be a well-founded guessing action initiated by the processor when it encounters a branch instruction, in order to prevent the pipeline from being idle while waiting for the branch result, and its subsequent processing.

[0060] In an exemplary embodiment, when the cache miss event is not a branch speculative event, then the cache miss event is a normal write-back event. A normal write-back event can be a memory access event that is determined to occur during normal program execution, distinct from speculative events. Speculative events can include the branch speculative event and the store-load speculative event; for example, the normal write-back event can be one or more of architectural misses or regular misses.

[0061] It is understandable that when a cache miss event is within the branch speculation window but not within the store load speculation window, the cache miss event can be identified as a branch speculation event.

[0062] The cached line data is transferred from the line buffer to the speculative line buffer module. For example, the cached line data can be stored into the speculative line buffer module step by step in the order of data snapshots, and a flag bit is added to the speculative line buffer module to indicate that the data in the cached line has been completely transferred to the speculative line buffer module.

[0063] Step S140: When the speculation context information corresponding to the branch speculation event is resolved as safe, the data in the speculation line buffer module is stored in the first-level cache.

[0064] The speculative context information can be used to determine whether the branch speculative event needs to be stored in the first-level cache. For example, when a cache missing event occurs, if the rearranged buffer marks the event as a speculative event, the loading storage unit sends the speculative context information to the missing state holding register, and the missing state holding register then transfers it to the speculative line buffer module.

[0065] The speculation context information may include a branch dependency mask and a storage dependency mask. If both the branch dependency mask and the storage dependency mask are zero, and there is no dirty data in the corresponding cache line in the first-level cache, then the speculation context information corresponding to the branch speculation event can be considered to be resolved as safe.

[0066] To store data from the speculative line buffer module into the first-level cache, one can first read the consistency metadata of the corresponding cache line in the first-level cache, determine whether the current cache line can be written, and if it can be written, store the data from the speculative line buffer module into the corresponding cache line of the first-level cache and update the consistency metadata.

[0067] This embodiment provides a cache miss backfilling method. The cache miss event of the cache controller in the first-level cache is stored in a miss status holding register. The miss status holding register is equipped with a row buffer and a speculative row buffer module. The memory data corresponding to the cache miss event in the second-level cache is stored in the row buffer to obtain cache row data. When the cache miss event is a branch speculative event, the cache row data is transferred from the row buffer to the speculative row buffer module. When the speculative context information corresponding to the branch speculative event is resolved as safe, the data in the speculative row buffer module is stored in the first-level cache. The speculative row buffer module in the miss status holding register temporarily stores cache row data that has been returned from the second-level cache but is not allowed to be installed into the first-level cache because the branch has not yet been resolved. Since the speculative row buffer module is a small speculative row buffer structure within the miss status holding register, it avoids creating copies of the entire cache and bypass conversion buffer while ensuring security. This achieves the technical effect of reducing hardware costs and overhead while maintaining security.

[0068] In one embodiment, the cache missing backfilling method further includes:

[0069] When the cache miss event is a normal write-back event, the memory data corresponding to the normal write-back event is stored in the first-level cache.

[0070] The memory loading speculative event can be an event in which the processor, during out-of-order execution, allows a loading instruction to retrieve data before all earlier memory instruction addresses have been calculated.

[0071] For example, storing the memory data corresponding to the ordinary write-back event in the first-level cache may mean storing the memory data in the cache line address corresponding to the first-level cache.

[0072] This embodiment provides a cache miss backfilling method that, by distinguishing between speculative events and normal write-back events, avoids treating all cache miss events as speculative events. Since the processing of speculative events requires conservative delay, this avoids overly conservative delaying the processing of all cache miss events, thereby improving the processor's operating efficiency.

[0073] In one embodiment, the out-of-order processor includes a loading storage unit, and the process of storing the cached line data into the line buffer and obtaining the cached line data includes:

[0074] Obtain the speculative context information corresponding to the cache miss event of the loaded storage unit; the speculative context information includes a branch dependency mask and a storage dependency mask;

[0075] If both the branch dependency mask and the storage dependency mask are zero, then the cache miss event is a normal write-back event.

[0076] If the storage dependency mask is zero and the branch dependency mask is not zero, then the cache miss event is a branch speculation event.

[0077] The loading memory unit can be the core execution unit inside the processor responsible for executing all memory access instructions (loading and storing); the speculative context information can also be used to determine whether the cache miss event is a memory loading speculative event.

[0078] For example, the branch dependency mask can be used to indicate which unresolved branches the current instruction depends on, and the storage dependency mask can be used to distinguish whether the load request is a storage load speculative event, and which earlier addresses the load request depends on that have not yet been resolved.

[0079] Furthermore, the branch dependency mask can be configured such that if the rearranged buffer marks a cached missing event as a branch speculative event, the loading storage unit converts the unresolved branches that the cached missing event still depends on into a branch dependency mask, and sends the branch dependency mask to the missing state holding register when the cached missing event enters the missing state holding register.

[0080] The storage dependency mask can be, if the rearranged buffer marks a cache miss event as a storage load speculative event, the loading storage unit converts the unresolved storage instructions that the loading instructions in the cache miss event still depend on into a storage dependency mask, and sends the storage dependency mask to the miss state holding register when the cache miss event enters the miss state holding register.

[0081] Specifically, if both the branch dependency mask and the storage dependency mask are zero, it indicates that the branch resolution of the cache miss event is correct, and the load instruction in the cache event no longer depends on the storage instruction whose address was not resolved earlier than the load instruction. In other words, the cache miss event can be determined to be a normal write-back event.

[0082] Specifically, if the storage dependency mask is zero and the branch dependency mask is not zero, it indicates that the load instruction in the cache miss event no longer depends on a storage instruction whose address has not been resolved earlier than the load instruction. However, the branch resolution result is not yet clear, so it is still within the branch speculation window. Therefore, the cache miss event can be judged as a branch speculation event.

[0083] This embodiment provides a cache miss backfilling method that obtains the speculative context information of the cache miss event corresponding to the loaded storage unit, and determines whether the cache miss event is a normal write-back event or a branch speculative event based on the speculative context information. This avoids treating all cache miss events as speculative events. Since the processing of speculative events requires conservative delay, this method avoids overly conservative delaying the processing of all cache miss events, thereby improving the processor's operating efficiency.

[0084] In one embodiment, after storing the cached line data in the line buffer, the process further includes:

[0085] If the storage dependency mask is not zero, then after responding to the load instruction corresponding to the cache missing event based on the cache line data, the cache line data is discarded.

[0086] Specifically, if the storage dependency mask is not zero, it indicates that the load instruction in the cache miss event still depends on a storage instruction whose address has not been resolved earlier than the load instruction. That is, the cache miss event is still in the storage load speculation window, and the cache miss event is a storage load speculation event.

[0087] Specifically, for the storage loading speculative event, this embodiment adopts a conservative discard strategy, which discards the cache line data after responding to the loading instruction corresponding to the cache missing event based on the cache line data.

[0088] This embodiment provides a cache missing event backfilling method. By determining the type of the cache missing event, if the cache missing event is a storage loading speculative event, the cache line data is discarded after providing the necessary data response to the loading instruction, and is not installed into the first-level cache. Thus, even if it is found in subsequent processes that the loading instruction should obtain data from the storage instruction or should be replayed, no cache data that can be observed by attackers will be left in the first-level cache, thereby avoiding Spectre attacks and improving system security.

[0089] In one embodiment, such as Figure 2 As shown, when the cache miss event is a branch speculation event, the step of transferring the cache line data from the line buffer to the speculation line buffer module includes:

[0090] Obtain the event flag bit corresponding to the cache missing event in the loaded storage unit;

[0091] If the event flag is not set, the cached line data and the speculative context information are transferred from the line buffer to the speculative line buffer module.

[0092] Specifically, upon receiving a cache miss request, the miss status holding register corresponding to the row buffer transitions from the initialization state to the send fill request state, sending a fill request to the second-level cache and simultaneously entering the receive fill response state. Upon receiving the data response from the second-level cache, the miss status holding register clears the waiting request queue for the cache row data loading instruction and determines, based on the event flag, whether the cache row data and the speculative context information need to be transferred from the row buffer to the speculative row buffer module. If necessary, the cache row data and the speculative context information are transferred from the row buffer to the speculative row buffer module, a storage protocol completion message is sent, and the module enters the completion state. If not, the module directly enters the completion state, clears the cache row data, and returns to the initialization state, ready to continue processing new cache miss events. Specifically, the storage protocol completion message can be a message informing the speculative row buffer module that the cache row data has been completely transferred.

[0093] For example, the event flag can be a binary flag, specifically, the event flag can be set when one or more abnormal events such as branch prediction error or abnormal flushing occur.

[0094] Specifically, if the event flag is not set, it indicates that the above-mentioned abnormal event has not occurred in the branch speculation event, so that the cached line data and the speculation context information can be transferred from the line buffer to the speculation line buffer module.

[0095] In one exemplary embodiment, such as Figure 3 As shown, the step of transferring the cached line data from the line buffer to the speculative line buffer module may further include:

[0096] Upon receiving a request to transfer data from the missing state holding register, the speculative line buffer module creates a corresponding speculative line buffer module entry. The speculative line buffer module entry includes a metadata array and a data array. The metadata array contains a branch dependency mask and a storage dependency mask.

[0097] Store the data in the row buffer into the data array;

[0098] The branch dependency mask and storage dependency mask in the speculation context information are stored in the branch dependency mask and storage dependency mask in the metadata array, respectively.

[0099] This embodiment provides a cache miss backfilling method. By transferring the cache line data in the miss state holding register to the speculative line buffer module, the miss state holding register can return to an idle state after transferring the cache line data to the speculative line buffer module for branch speculative events, and reprocess the cache miss event. This avoids the blockage of the miss state holding register caused by waiting for branch parsing results for a long time, thereby improving the processor's operating efficiency.

[0100] In one embodiment, such as Figure 3 As shown, the process of parsing the speculative context information corresponding to the branch speculative event into a safe judgment includes:

[0101] If the branch dependency mask is zero and the storage dependency mask is zero, then check whether there is dirty data in the cache line corresponding to the data in the speculative line buffer module.

[0102] If no dirty data exists, the speculation context information corresponding to the branch speculation event is parsed as safe.

[0103] If the branch dependency mask is zero and the storage dependency mask is zero, then check whether there is dirty data in the cache line corresponding to the data in the speculative line buffer module. The dirty data may refer to the data in the cache line that needs to be written back to the second-level cache or main memory. Therefore, if there is dirty data in the cache line, the dirty data needs to be written back to the second-level cache or main memory first.

[0104] Specifically, the process of checking whether there is dirty data in the cache line corresponding to the data in the speculative line buffer module can be as follows: read the consistency metadata of the corresponding cache line. If the status of the consistency metadata is Modified, it can be considered that there is data in the cache line that has been modified but not written back to the main memory, that is, there is dirty data in the cache line.

[0105] Furthermore, in this embodiment, data in the speculative line buffer module can be discarded if dirty data exists; if no dirty data exists, the speculative context information corresponding to the branch speculative event is parsed as safe, that is, the data in the speculative line buffer module can be written into the first-level cache.

[0106] This embodiment provides a cache missing backfilling method that determines whether the speculative context information corresponding to the branch speculative event is safe by checking whether there is dirty data in the cache line. This can avoid writing data when there is dirty data in the cache line, prevent data loss, and achieve the technical effect of improving system security.

[0107] In one embodiment, the cache missing backfilling method further includes:

[0108] During the lifetime of the missing state holding register or the speculative line buffer module, the branch resolution signal and memory address disambiguation signal of the out-of-order processor are monitored;

[0109] Update the branch dependency mask based on the branch parsing signal;

[0110] Update the storage dependency mask based on the storage address disambiguation signal.

[0111] The branch resolution signal can be the decision signal for the rearranged buffer (ROB) after the actual branch result has been calculated in the execution unit. This decision signal contains the final result of the branch prediction and is used to verify whether the previous branch prediction was correct.

[0112] The address disambiguation signal can be a decision signal issued by the memory disambiguation logic in the load memory unit after comparing the complete addresses of all earlier store instructions with the addresses of the load instructions during the background verification phase. This decision signal is used to verify whether the previously performed memory load speculation was safe.

[0113] For example, while waiting for data responses from the second-level cache, the active missing state holding register can monitor the branch resolution signal and the storage address disambiguation signal of the out-of-order processor. Based on the branch resolution signal, the branch dependency mask can be updated; based on the storage address disambiguation signal, the storage dependency mask can be updated; and based on the updated branch dependency mask, storage dependency mask, and the event flag, it can be determined whether it is necessary to transfer cached line data from the line buffer to the speculative line buffer module.

[0114] For example, after transferring cache line data from the line buffer to the speculative line buffer module, the active speculative line buffer module listens to the branch resolution signal and storage address disambiguation signal of the out-of-order processor, updates the branch dependency mask according to the branch resolution signal, updates the storage dependency mask according to the storage address disambiguation signal, and determines whether the speculative context of the branch speculative event is safe based on the updated branch dependency mask, storage dependency mask, and whether there is dirty data in the corresponding cache line.

[0115] Updating the branch dependency mask can be achieved by listening to the correct parsing signal for the branch path in the branch parsing signal and resetting the binary bits corresponding to the branch path in the branch dependency mask.

[0116] The update of the storage dependency mask can be achieved by listening to the parsing signal of the address of the storage instruction before the load instruction in the storage address disambiguation signal. If there is no conflict between the address of the storage instruction and the address of the load instruction, the corresponding binary bit of the storage instruction in the storage dependency mask is reset.

[0117] This embodiment provides a cache missing backfilling method that continuously monitors the branch resolution signal and storage address disambiguation signal of the out-of-order processor and updates the branch dependency mask and storage dependency mask during the life of the missing state holding register or the speculative line buffer module. This can prevent already resolved branches from being brought back into the speculative line buffer module, or unnecessarily delayed backfilling due to already resolved storage dependencies. In this way, it can avoid misjudgments caused by the use of old snapshots in the waiting request queue of traditional techniques.

[0118] In one embodiment, storing the memory data of the branch speculation event in the first-level cache includes: writing a reserved flag bit into the first-level cache corresponding to the first target position according to the first target position corresponding to the branch speculation event;

[0119] Before storing the memory data corresponding to the normal write-back event in the first-level cache, the method further includes: determining whether there is a reserved flag bit in the second target position corresponding to the normal write-back event in the first-level cache; if so, there is a write conflict, the normal write-back event is rejected and retried in subsequent cycles.

[0120] The reserved flag can be a flag used to determine whether there is a write conflict between branch speculative events and normal write-back events.

[0121] Understandably, since branch speculative events are first transferred to the speculative line buffer module, and then the speculative line buffer module decides whether to write to the first-level cache, during this process, there may be ordinary write-back events for the same cache line. Therefore, in order to avoid write conflicts between branch speculative events and ordinary write-back events, a reserved flag can be written in the first-level cache corresponding to the first target position according to the first target position of the branch speculative event. When the speculative line buffer module is writing, if an ordinary write-back event for the same cache line occurs, and the reserved flag exists in the second target position corresponding to the ordinary write-back event, it can be determined that there is a write conflict. In this case, the ordinary write-back event will be rejected and retried in subsequent cycles.

[0122] Furthermore, while waiting for the processor's branch resolution signal, the branch speculative event will not occupy the first target location, nor will it block normal write-back events. Only when the branch speculative event is actually ready to write to the first target location will a reserved flag be written to the first target location corresponding to the first level cache. At the same time, when the processor determines the target location for write-back of other cache miss events, it will also check the reserved flag and select the target location that does not contain the reserved flag as the target location for write-back of other cache miss events. This can prevent the branch speculative event from occupying a certain target location for a long time while waiting for the branch resolution signal, thereby improving the system's operating efficiency.

[0123] This embodiment provides a cache missing backfilling method. By writing a reserved flag bit at the target location of a branch speculative event write-back, and simultaneously checking the reserved flag bit at the target location corresponding to a normal write-back event, if the reserved flag bit exists at the target location corresponding to the normal write-back event, the normal write-back event is rejected and retried in subsequent cycles. This can prevent two events from different sources from being written to the same target location at the same time, causing data loss and pollution, and achieve the technical effect of improving system security.

[0124] To more clearly illustrate the technical solution of this application, a detailed embodiment is also provided.

[0125] Modern high-performance processors typically employ out-of-order execution and speculative execution mechanisms to improve program efficiency. The processor executes subsequent instructions prematurely, before branch results or memory dependencies are fully determined. This mechanism can improve pipeline utilization and memory access parallelism, but it can also introduce microarchitectural security issues.

[0126] In out-of-order processors, when a load instruction accesses the L1 data cache, if a cache miss occurs, the Miss Status Register (MSHR) typically records the miss request and initiates an access to the next lower-level cache or memory. When the data is returned, a traditional processor loads the returned cache line into the L1 data cache and returns the data to any load instruction waiting for that cache line.

[0127] The problem is that even if load instructions on a speculative execution path are eventually revoked by the processor, the cache backfilling they trigger during execution may still alter the state of the L1 data cache. For example, in Spectre-type attacks, an attacker can induce the processor to execute secret-related memory accesses along incorrect branch paths or incorrect memory-dependent paths, causing certain cache lines to be prematurely loaded into the L1 data cache. Although instructions on incorrect paths are not committed to the architectural state, the hit / miss differences in the cache can still be observed by the attacker using timing methods, thereby revealing secret information.

[0128] Therefore, simply ensuring that speculative instructions are not ultimately committed is insufficient; it is also necessary to limit the impact of cache backfilling caused by speculative execution on the L1 data cache state. For out-of-order processors using a non-blocking cache structure, data returned by a loadmiss may eventually be loaded into the L1 data cache, thereby altering the cache state and creating observable cache traces. Therefore, appropriate safety control mechanisms need to be introduced during the cache backfilling process to prevent cache state changes caused by erroneous speculative paths from being retained.

[0129] Currently, protection methods against speculative execution side channels mainly include software barriers, speculative state cleanup, shadow caching, and speculative buffers. Software barriers reduce the risk of leakage by limiting the scope of speculative execution, but they rely on software cooperation and incur significant performance overhead. Speculative state cleanup schemes restore or clear the relevant microarchitectural state after detecting erroneous speculation, but there is still a time window that can be exploited before the cleanup action is performed.

[0130] Furthermore, hardware solutions such as shadow caching, speculative caching, and speculative buffers attempt to isolate speculative data from the actual cache state, reducing cache side-channel risk at the hardware level. However, these solutions typically require additional cache structures and control logic, increasing hardware overhead. In out-of-order processors, cache miss requests are managed uniformly by MSHR, while branch states, store-load dependency states, and abnormal rollback states continuously change during the wait for backfilling. If the protection mechanism is not tightly integrated with the MSHR backfilling path, waiting queue, and dynamic speculative state, problems such as inaccurate backfilling classification or invalid speculative context can easily occur. Some solutions only process based on the speculative state at the time the request is initiated, without considering changes in branch resolution results and memory dependencies during the cache miss wait period, which may lead to excessive delays in safe backfilling or incorrect installation of unsafe backfilling into the L1 data cache. Therefore, existing solutions still have shortcomings in combining MSHR backfilling mechanisms, dynamic speculative state tracking, and cache installation control.

[0131] To address the aforementioned issues of high hardware overhead, inaccurate backfilling classification, and invalid speculative context, one embodiment provides a cache miss backfilling method, which includes the following steps:

[0132] Step 1: Store the cache miss event of the cache controller in the first-level cache in the miss status holding register; the miss status holding register is equipped with a row buffer and a speculative row buffer module.

[0133] In one exemplary embodiment, such as Figure 4 As shown, if a cache miss event occurs when the loading storage unit executes a loading instruction, that is, there is no tag and data in the tag array and data array of the first-level cache that match the address of the loading instruction, the cache controller of the first-level cache sends an allocation request to the miss status holding register.

[0134] Specifically, the data stored in the missing state holding register includes: the missing address of this cached missing event, the cache command, the replacement path consistency metadata, the branch dependency mask, the storage dependency mask, and the event flag, which are recorded by the missing state holding register.

[0135] The missing address record contains the complete physical memory address that triggered this cache miss event;

[0136] The caching command specifies the type of memory access, for example: Load instruction: only needs to read data into the register; Store instruction: needs to read data first, modify it in the cache, and then write it; Prefetch instruction: hardware prefetch instruction, used to load data in advance;

[0137] In a set-associative cache, a cache set has multiple ways. The replacement way field records which way data should be written when it is returned from memory. This is the position selected by the replacement algorithm when a cache miss event occurs. The replacement algorithm can be the LRU algorithm or other replacement algorithms, which are not limited in this embodiment.

[0138] The LRU algorithm, or Least Recently Used algorithm, is a strategy applied to cache replacement. It is based on the assumption that if a piece of data has not been used for a long time, then the probability of it being used in the future is relatively low. When the cache space is full and space needs to be made for new data, the data that has not been accessed for the longest time is replaced first.

[0139] Logical consistency metadata is used to maintain cache consistency protocols (such as MESI) among multi-core CPUs. It records the current state of this cache line, for example: Invalid: The data is invalid and needs to be read from memory; Shared: The data is valid in the caches of multiple cores; Exclusive / Modified: Currently exclusive to the core and modifiable.

[0140] A branch dependency mask is used to indicate which unresolved branches the current instruction depends on.

[0141] A storage dependency mask is used to distinguish whether a load request is a storage load speculative event, and which earlier storage instructions the load request depends on that have not yet been resolved. For example, the storage dependency mask can be a dependency bitmap of storage instructions that occurred before the load instruction, provided by the load storage unit.

[0142] The event flag is used to indicate whether there are branch parsing errors, abnormal flushing, or other situations related to cache missing events.

[0143] Step 2: Store the memory data corresponding to the cache miss event in the second-level cache into the line buffer to obtain cache line data.

[0144] In one exemplary embodiment, such as Figure 4 As shown, the missing state holding register can initiate a request to the second-level cache, receive the returned data, and write the returned data into the missing state holding register line buffer (MSHRLine Buffer) one by one to obtain the cache line data.

[0145] Step 3: When the cache missing event is a branch speculation event, the cache line data is transferred from the line buffer to the speculation line buffer module.

[0146] Furthermore, before determining that the cache missing event is a branch speculation event, the loading requests waiting for the cache line data in the waiting request queue (RPQ) can be processed first. For each pending load request, the missing state holding register retrieves the corresponding data from the line buffer and returns it to the processor core based on the offset of the requested address within the cache line, the access size, and the sign extension information. This process only provides the data response required by the load request. At this time, the data is still in the replacement buffer, and the cache line has not yet updated the L1 tag array, L1 data array, and replacement state. Therefore, it has not yet become a formal cache line that an attacker can observe through a normal L1 hit state. The L1 tag array stores the high-order part of the physical address corresponding to each cache line, as well as the MESI consistency state of the cache line (i.e., one of Invalid, Exclusive, Shared, and Modified mentioned above). The L1 data array stores the complete cache line data retrieved from memory, which can be a continuous 64 bytes. The replacement state stores metadata, such as which way was most recently used and which has been least used.

[0147] Specifically, the process for determining whether a cache miss event is a branch speculation event includes:

[0148] Monitor the branch parsing signal and memory address disambiguation signal of the out-of-order processor;

[0149] Update the branch dependency mask based on the branch parsing signal;

[0150] Update the storage dependency mask based on the storage address disambiguation signal.

[0151] Furthermore, the aforementioned event flag can also be obtained. If the cache missing event is parsed as an error path or a flush path, the event flag can be set.

[0152] For example, if the event flag is set, it indicates that the request has belonged to an incorrect path or a flushed path. The missing status holding register does not allow the cache line to enter the first-level cache or the speculative line buffer module. Instead, it discards the backfill side effect and only completes the necessary protocol cleanup.

[0153] If the storage dependency mask is still not zero, it indicates that the cache miss event originated from a storage load speculative window, and the address relationship of the preceding storage instruction has not been fully resolved. For this type of backfilling, this embodiment adopts a conservative discard strategy: the miss status holding register can return data to the waiting load request in the line buffer, but it does not load the cache line into the first-level cache, nor does it transfer it to the speculative line buffer module. Instead, it is discarded after the response is completed. In this way, even if it is subsequently found that the load request should have been forwarded from the preceding storage instruction or should have been replayed, no trace of the cache line generated under the incorrect memory order will be left in the first-level cache.

[0154] In one exemplary embodiment, such as Figure 4 As shown, if both the branch dependency mask and the storage dependency mask are zero and the event flag is not set, it means that the backfill no longer depends on the unresolved speculative state. The missing state holding register follows the original secure installation path, reads or updates the consistency metadata, writes the cache line to the data array of the first-level cache, and completes the consistency metadata writing.

[0155] If the storage dependency mask has been cleared but the branch dependency mask is still not zero, it means that there is no longer any uncertainty in the storage load address for the backfill, but it is still within the branch speculative window. At this time, the missing state holding register does not allow it to be immediately installed into the first-level cache, but instead transfers the cache line data from the line buffer to the speculative line buffer module.

[0156] In one exemplary embodiment, such as Figure 5 As shown, the missing state holding register is equipped with an MSHR backfill state machine, and the states in the backfill state machine include:

[0157] Initial / Invalid State (s_invalid): At this point, the missing status holding register (MSHR) entry has just been allocated, but no request has been made yet. This indicates that the entry is in an "idle" or "reset" state.

[0158] Refill Request Status (s_refill_req): The Missing Status Holding Register (MSHR) has sent a memory read request to the Level 2 cache and is waiting for the data to be returned.

[0159] Refill response received status (s_refill_resp): The memory controller has returned the requested data (cache line), and the data has arrived in the line buffer.

[0160] The wait request queue is emptied (s_drain_rpq_loads). In this state, after the Missing Status Holding Register (MSHR) has finished processing the current backfill, the corresponding entry is removed from the wait request queue (RPQ), and all instructions waiting for that data are woken up, ensuring that all load instructions that depend on that data are correctly woken up.

[0161] Transfer status (s_slb_transfer). The missing status holding register transfers the cached line data from the line buffer to the speculative line buffer module.

[0162] The process of transferring the cached line data from the line buffer to the speculative line buffer module includes:

[0163] A request for entry allocation is sent to the speculative line buffer module. While waiting for the entry allocation response from the speculative line buffer module, the branch dependency mask, storage dependency mask, and event flag are checked again, because the branch may still continue to resolve in the short time while waiting for allocation from the speculative line buffer module. If the branch dependency mask is already zeroed and the event flag is not set, it means that the backfill has become a safe backfill, and the missing state holding register can bypass the speculative line buffer module and return to the original first-level cache mounting path. If a branch error, abnormal flush, or the storage dependency mask is re-resolved to a non-zero state, the missing state holding register discards the backfill side effect to avoid further transfer. If the speculative line buffer module has no free entries, the missing state holding register does not wait indefinitely, but conservatively discards the branch speculative backfill and releases the missing state holding register to avoid blocking the entire cache missing event processing path due to a full speculative line buffer.

[0164] In an exemplary embodiment, after the cached line data is transferred from the line buffer to the speculative line buffer module, the MSHR backfill state machine may also enter the following state:

[0165] Metadata read (s_meta_read) reads the tag and consistency metadata (such as MESI status) of the target cache set after the data is returned from memory, using the missing state holding register MSHR to determine the status and write position of the current cache line.

[0166] The first metadata response (s_meta_resp_1) is the first response received after reading metadata, and it may include tag information and the status of the current cache line.

[0167] The second metadata response (s_meta_resp_2) is the second response received after the metadata read. It can contain more detailed cache line status, such as whether there is dirty data or whether it is held by other cores.

[0168] If the cache line contains dirty data at this time, then proceed to:

[0169] The metadata clearing state (s_meta_clear) clears the old metadata of the target path (Way) before writing new data (e.g., setting the state to Invalid) to prepare for the writing of new data.

[0170] The write-back request status (s_wb_req) indicates that if the replaced cache line contains dirty data, it needs to be written back to the next level cache or memory. This status signifies that a write-back request has been initiated by the missing status holding register.

[0171] Upon receiving the write-back response (s_wb_resp), confirming that the dirty data has been successfully written back, the cache line can be safely released. The system then enters the commit cache line state.

[0172] If the cache line does not contain dirty data at this point, proceed directly:

[0173] The commit cache line status (s_commit_line) writes the returned data to the specified path (Way) of the first-level cache.

[0174] Empty the waiting request queue (s_drain_rpq). After processing the current backfill, remove the entry from the waiting request queue and wake up all instructions waiting for the data.

[0175] The metadata write request (s_meta_write_req) requires that, after data is written to the cache, the missing state holding register needs to write the updated metadata (such as the new MESI state) back to the cache tag array to ensure that the cache's consistency state is correctly updated. It then proceeds to the first memory completion state (s_mem_finish_1) and the second memory completion state (s_mem_finish_2). Wherein:

[0176] The first memory completion status indicates that internal resources, such as line buffers, can be synchronized or released at this time.

[0177] The second memory completion state indicates that the entire backfilling process has entered the final state. The missing state register entries have been completely released, and the state machine returns to the initial / invalid state (s_invalid).

[0178] For example, if the branch dependency mask has been cleared and the event flag has not been set, it means that the backfill has become a safe backfill. The missing state holding register can bypass the speculative line buffer module, return to the original first-level cache installation path, and enter the first memory completion state (s_mem_finish_1) and the second memory completion state (s_mem_finish_2) in sequence after installation.

[0179] When it is confirmed that a transfer is needed and the speculative line buffer module has available entries, MSHR sends a data packet to SLB carrying the cache line address, current branch dependency mask, storage dependency mask, pre-selected installation path, and consistency metadata. Upon receiving the data packet, the speculative line buffer module allocates a free entry and writes this data into that entry. Subsequently, the missing status holding register reads data from the line buffer in cache line data beat order and writes it to the speculative line buffer module's data storage array through the data write interface. Each data write includes the speculative line buffer module entry number, data beat offset, and corresponding data. When the last beat of data writing is complete, the speculative line buffer module sets the entry's completion flag (fill_done), indicating that the entry has saved a complete cache line. After the data transfer is completed, the missing state holding register sends a storage protocol completion message and then returns to the idle state, ready to continue processing new cache missing events. Thus, the data backfilled by branch speculation is transferred from the row buffer of the missing state holding register to the speculation row buffer module and no longer occupies the missing state holding register, but it is still kept outside the first-level cache, waiting for subsequent speculation parsing.

[0180] In one embodiment, such as Figure 6 As shown, the speculative line buffer module is equipped with an SLB installation state machine. The SLB installation state machine includes an initial state (slb_install_s_idle). After the above-mentioned transfer state is completed, it sequentially enters the following states: SLB metadata read (slb_meta_read), SLB first metadata response (slb_meta_resp_1), and SLB second metadata response (slb_meta_resp_2). The meanings of these three states can be referred to the meanings of the above-mentioned metadata read, first metadata response, and second metadata response, respectively. This embodiment will not elaborate on these meanings here.

[0181] Upon receiving the SLB second metadata response, check for cache line conflicts and dirty data. If any are found, discard the speculative line buffer module entry and return to the initial state (slb_install_s_idle). If none are found, proceed as follows:

[0182] The SLB metadata clearing status (slb_meta_clear), SLB commit cache line status (slb_data_install), and SLB metadata write request (slb_meta_write) are defined as follows. The meanings of these three statuses can be found in the definitions of the metadata clearing status, commit cache line status, and metadata write request mentioned above. They will not be elaborated upon in this embodiment.

[0183] After the SLB metadata write request receives a correct response, it enters the memory release state (free entry), clears the data in the data array and metadata array, releases the speculative line buffer module entry, and enters the initial state for the next use.

[0184] In one embodiment, such as Figure 7 As shown, the speculative line buffer module is located inside the missing state holding register. It is a small speculative line buffer structure, not a new cache level, and does not participate in the normal first-level tag cache hit determination. The function of the speculative line buffer module is to temporarily store branch speculative cache lines that have returned but have not yet been allowed to be installed into the first-level cache. Each speculative line buffer module entry can contain a metadata array and a data array. The metadata array stores the valid bit (valid), the completion flag (fill_done), the cache line address (addr), the target L1Way candidate (Way), metadata (metadata), the branch dependency mask (br_mask), and the store dependency mask (st_dep_mask). The data array stores the complete cache line data. The data storage of the speculative line buffer module is separated from the line buffer of the missing state holding register. Therefore, the missing state holding register can be released after the transfer is completed without waiting for branch resolution.

[0185] Furthermore, the number of entries in the speculative line buffer module can be parameterized. In one exemplary embodiment, the number of entries can be the maximum of 2 times or 4 times the number of missing state holding registers, so as to still have sufficient buffering capacity in processor configurations with a small number of missing state holding registers. When multiple missing state holding registers simultaneously request the speculative line buffer module to allocate or write data, the speculative line buffer module selects one of the requests to execute through an arbitrator, thereby ensuring that the metadata writing and data writing order is clear.

[0186] Step 4: When the speculation context information corresponding to the branch speculation event is resolved as safe, the data in the speculation line buffer module is stored in the first-level cache.

[0187] In one specific embodiment, such as Figure 7 As shown, the process of parsing the speculative context information corresponding to the branch speculative event into a safe judgment includes:

[0188] If the branch dependency mask is zero and the storage dependency mask is zero, then check whether there is dirty data in the cache line corresponding to the data in the speculative line buffer module.

[0189] If no dirty data exists, the speculation context information corresponding to the branch speculation event is parsed as safe.

[0190] The process of determining the branch dependency mask and storage dependency mask can refer to the process of determining whether a cache missing event is a branch speculation event in step three above, and will not be repeated here.

[0191] Furthermore, before checking whether there is dirty data in the cache line corresponding to the data in the speculative line buffer module, it is also necessary to check the completion flag (fill_done) of the speculative line buffer module. If the completion flag (fill_done) has been set, the consistent metadata of the set or way corresponding to the cache line is reread. The purpose of rereading the consistent metadata is to confirm whether the cache state of the target position has changed during the period when the speculative line buffer module is waiting for branch parsing, and whether writing is allowed at that position.

[0192] After the consistent metadata is returned, the system checks whether there is dirty data in the cache line corresponding to the data in the speculative line buffer module. Furthermore, while checking for dirty data, it also checks for conflicts. If an active missing state holding register or data cache request is processing the same cache address, it indicates that the state of that cache address may have been updated. To avoid old data overwriting the new state, the speculative line buffer module directly discards the entry. If the cache line corresponding to the target location is dirty data and a write-back needs to be triggered, this embodiment also conservatively discards the entry, without introducing an additional write-back process into the speculative line buffer module installation path. Since the speculative line buffer module stores branch speculative backfill data that has not yet entered the first-level cache, discarding this entry will not affect the correctness of the architecture; it will only cause the subsequent correct path to re-initiate a normal cache miss event when the cache line is needed. This strategy avoids complex coupling between the speculative line buffer module installation path and the original write-back unit, probe processing, and consistent state transition, making the speculative line buffer module installation state machine simpler and easier to verify.

[0193] Furthermore, after the speculation context information corresponding to the branch speculation event is parsed as safe, the consistency metadata is checked. If the check passes and the target location allows installation, the speculation line buffer module's installation state machine enters the data installation phase. In this phase, data is read from the speculation line buffer module's data storage array according to the data tick order of the cache line and written to the target set or way of the first-level cache data array. After all data ticks are written, the speculation line buffer module enters the consistency metadata writing phase, writing the corresponding tag, validity bit, and consistency metadata to the first-level cache. Only after both the data array and consistency metadata have been written does the cache line officially become a visible cache line in the first-level cache. Subsequently, the speculation line buffer module clears the validity bit and completion flag of the entry, releasing the entry for subsequent branch speculation backfilling.

[0194] Furthermore, if the completion flag (fill_done) has been set, the branch dependency mask (br_mask) and the store dependency mask (st_dep_mask) are both 0, there is no conflict with the missing state holding register in DCache or active, and there is no dirty data in the cache line, then the speculative line buffer module can also respond to load instructions for the cache line that are not in the store load speculative window.

[0195] In an exemplary embodiment, storing the memory data of the branch speculation event in the first-level cache includes: writing a reserved flag bit into the first-level cache corresponding to the first target position according to the first target position corresponding to the branch speculation event;

[0196] Before storing the memory data corresponding to the normal write-back event in the first-level cache, the method further includes: determining whether there is a reserved flag bit in the second target position corresponding to the normal write-back event in the first-level cache; if so, there is a write conflict, the normal write-back event is rejected and retried in subsequent cycles.

[0197] The reserved flag can be a flag used to determine whether there is a write conflict between branch speculative events and normal write-back events.

[0198] Understandably, since branch speculative events are first transferred to the speculative line buffer module, and then the speculative line buffer module decides whether to write to the first-level cache, during this process, there may be ordinary write-back events for the same cache line. Therefore, in order to avoid write conflicts between branch speculative events and ordinary write-back events, a reserved flag can be written in the first-level cache corresponding to the first target position according to the first target position of the branch speculative event. When the speculative line buffer module is writing, if an ordinary write-back event for the same cache line occurs, and the reserved flag exists in the second target position corresponding to the ordinary write-back event, it can be determined that there is a write conflict. In this case, the ordinary write-back event will be rejected and retried in subsequent cycles.

[0199] Furthermore, while waiting for the processor's branch resolution signal, the branch speculative event will not occupy the first target location, nor will it block normal write-back events. Only when the branch speculative event is actually ready to write to the first target location will a reserved flag be written to the first target location corresponding to the first level cache. At the same time, when the processor determines the target location for write-back of other cache miss events, it will also check the reserved flag and select the target location that does not contain the reserved flag as the target location for write-back of other cache miss events. This can prevent the branch speculative event from occupying a certain target location for a long time while waiting for the branch resolution signal, thereby improving the system's operating efficiency.

[0200] In one specific embodiment, the forwarding behavior of the speculative line buffer module can also be restricted. When the data storage flag of a speculative line buffer module entry is set, the branch dependency mask and storage dependency mask are both cleared, there is no ongoing installation, and there is no conflict with the active missing state holding register, subsequent normal load instructions accessing the same cache line can obtain data from the speculative line buffer module through a secure forwarding path. During this process, only the data required by the current load instruction is returned; the first-level cache tag array or the first-level cache data array is not updated. For storage instructions, atomic memory operations (AMO), load-reserved operations, and load instructions still marked as storage-load speculative, requests cannot directly obtain data from the speculative line buffer module; instead, they must wait for the speculative line buffer module to complete installation, for the entry to be discarded, or for a retry. Through this restriction, the speculative line buffer module will not become a new source of insecure speculative data, nor will it bypass storage-load dependency protection.

[0201] Furthermore, this embodiment strives to maintain the original mechanisms of the BOOM architecture in terms of replay, probe, and fence.

[0202] In one specific embodiment, for replay, the Missing State Holding Register may merge multiple requests to access the same cache line. Load instructions can receive a response after the data in the Level 2 cache is stored in the line buffer of the Missing State Holding Register. However, replays of non-load instructions such as load instructions and atomic memory operations (AMOs) cannot be silently discarded simply because the cache line is deemed speculative backfilling; otherwise, it could impact the architecture's progress. Therefore, the Missing State Holding Register needs to ensure that the work of non-load instructions that must be replayed is not lost before discarding backfilling side effects, and if necessary, follow the original safe replay path.

[0203] In one specific embodiment, for probes, since speculative line buffer module entries are not valid cache lines in the first-level cache tag array before formal installation, unresolved speculative line buffer module entries are not treated as cache lines of the normal first-level cache in response to probes; when the speculative line buffer module enters the installation phase, consistency metadata is reread, conflict checking and conservative discarding strategies are used to avoid inconsistencies with probes or other cache operations.

[0204] In one specific embodiment, for the barrier, the speculative line buffer module stores speculative load instruction backfill data that has not yet been submitted to the first-level cache state, and does not include already submitted storage instruction updates. Therefore, the unparsed speculative line buffer module entry itself does not constitute a storage instruction visibility event that must be waited for, and the storage instruction order is still maintained by the original storage instruction queue and data caching mechanism.

[0205] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0206] Based on the same inventive concept, this application also provides a cache miss filling system for implementing the cache miss filling method described above. The solution provided by this system is similar to the implementation described in the above method; therefore, the specific limitations of one or more cache miss filling system embodiments provided below can be found in the limitations of the cache miss filling method described above, and will not be repeated here.

[0207] In one embodiment, such as Figure 8 As shown, a cache miss filling system is provided, which includes an out-of-order processor 100, a first-level cache 200, a second-level cache 400, and a miss status holding register 300; wherein:

[0208] The out-of-order processor 100 is communicatively connected to the first-level cache 200 and the missing state holding register 300, respectively; the missing state holding register 300 is communicatively connected to the first-level cache 200 and the second-level cache 400, respectively; the missing state holding register 300 includes a line buffer 320 and a speculative line buffer module 310; wherein:

[0209] The missing state holding register 300 is used to store the cache missing event of the cache controller in the first level cache 200; the memory data corresponding to the cache missing event in the second level cache 400 is stored in the line buffer 320 to obtain cache line data; when the cache missing event is a branch speculative event, the cache line data is transferred from the line buffer 320 to the speculative line buffer module 310.

[0210] The speculative line buffer module 310 is used to store the data in the speculative line buffer module 310 into the first-level cache 200 when the speculative context information corresponding to the branch speculative event is parsed as safe.

[0211] In one embodiment, such as Figure 9 As shown, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the cache miss backfilling method of any of the above embodiments:

[0212] The cache miss event of the cache controller in the first-level cache is stored in the miss status holding register; the miss status holding register is equipped with a row buffer and a speculative row buffer module;

[0213] The memory data corresponding to the cache miss event in the second-level cache is stored in the line buffer to obtain cache line data;

[0214] When the cache miss event is a branch speculation event, the cache line data is transferred from the line buffer to the speculation line buffer module;

[0215] When the speculation context information corresponding to the branch speculation event is resolved as safe, the data in the speculation line buffer module is stored in the first-level cache.

[0216] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the cache miss backfilling method of any of the above embodiments:

[0217] The cache miss event of the cache controller in the first-level cache is stored in the miss status holding register; the miss status holding register is equipped with a row buffer and a speculative row buffer module;

[0218] The memory data corresponding to the cache miss event in the second-level cache is stored in the line buffer to obtain cache line data;

[0219] When the cache miss event is a branch speculation event, the cache line data is transferred from the line buffer to the speculation line buffer module;

[0220] When the speculation context information corresponding to the branch speculation event is resolved as safe, the data in the speculation line buffer module is stored in the first-level cache.

[0221] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0222] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0223] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0224] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A cache missing backfilling method, characterized in that, Applied to out-of-order processors, the cache miss backfilling method includes: The cache miss event of the cache controller in the first-level cache is stored in the miss status holding register; the miss status holding register is equipped with a row buffer and a speculative row buffer module; The memory data corresponding to the cache miss event in the second-level cache is stored in the line buffer to obtain cache line data; When the cache miss event is a branch speculation event, the cache line data is transferred from the line buffer to the speculation line buffer module; When the speculation context information corresponding to the branch speculation event is resolved as safe, the data in the speculation line buffer module is stored in the first-level cache.

2. The cache missing data filling method according to claim 1, characterized in that, The cache missing backfilling method also includes: When the cache miss event is a normal write-back event, the memory data corresponding to the normal write-back event is stored in the first-level cache.

3. The cache missing backfilling method according to claim 2, characterized in that, The out-of-order processor includes a loading storage unit, and the process of storing the data into the line buffer and obtaining the cached line data includes: Obtain the speculative context information corresponding to the cache miss event of the loaded storage unit; the speculative context information includes a branch dependency mask and a storage dependency mask; If both the branch dependency mask and the storage dependency mask are zero, then the cache miss event is a normal write-back event. If the storage dependency mask is zero and the branch dependency mask is not zero, then the cache miss event is a branch speculation event.

4. The cache missing backfilling method according to claim 3, characterized in that, After storing the cached line data in the line buffer, the process further includes: If the storage dependency mask is not zero, then after responding to the load instruction corresponding to the cache missing event based on the cache line data, the cache line data is discarded.

5. The cache missing backfilling method according to claim 3, characterized in that, When the cache miss event is a branch speculative event, the step of transferring the cached line data from the line buffer to the speculative line buffer module includes: Obtain the event flag bit corresponding to the cache missing event in the loaded storage unit; If the event flag is not set, the cached line data and the speculative context information are transferred from the line buffer to the speculative line buffer module.

6. The cache missing backfilling method according to claim 3, characterized in that, The process of parsing the speculative context information corresponding to the branch speculative event into a safe judgment includes: If the branch dependency mask is zero and the storage dependency mask is zero, then check whether there is dirty data in the cache line corresponding to the data in the speculative line buffer module. If no dirty data exists, the speculation context information corresponding to the branch speculation event is parsed as safe.

7. The cache missing backfilling method according to claim 3 or claim 6, characterized in that, The cache missing backfilling method also includes: During the lifetime of the missing state holding register or the speculative line buffer module, the branch resolution signal and memory address disambiguation signal of the out-of-order processor are monitored; Update the branch dependency mask based on the branch parsing signal; Update the storage dependency mask based on the storage address disambiguation signal.

8. The cache missing backfilling method according to claim 2, characterized in that, Storing the memory data of the branch speculation event into the first-level cache includes: writing a reserved flag bit into the first-level cache corresponding to the first target position according to the first target position corresponding to the branch speculation event; Before storing the memory data corresponding to the normal write-back event in the first-level cache, the method further includes: determining whether there is a reserved flag bit in the second target position corresponding to the normal write-back event in the first-level cache; if so, there is a write conflict, the normal write-back event is rejected and retried in subsequent cycles.

9. A cache missing backfilling system, characterized in that, The cache miss backfilling system includes an out-of-order processor, a first-level cache, a second-level cache, and a miss status holding register; wherein, the out-of-order processor is communicatively connected to both the first-level cache and the miss status holding register; the miss status holding register is communicatively connected to both the first-level cache and the second-level cache; the miss status holding register includes a line buffer and a speculative line buffer module; wherein: The missing state holding register is used to store cache missing events of the cache controller in the first level cache; the memory data corresponding to the cache missing event in the second level cache is stored in the line buffer to obtain cache line data; when the cache missing event is a branch speculative event, the cache line data is transferred from the line buffer to the speculative line buffer module. The speculative line buffer module is used to store the data in the speculative line buffer module into the first-level cache when the speculative context information corresponding to the branch speculative event is parsed as safe.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the method of any one of claims 1 to 8.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 8.

Images