Shared storage device and ualink chip

Abstract

The application discloses a shared storage device and a UALink chip, divides storage into a sending message storage area and a processing message storage area, the sending message storage area comprises a plurality of sending message storage bits, the sending message storage area is configured with at least a first read pointer and a first write pointer, the first read pointer points to a sending message storage bit where a current to-be-sent message is located, and the first write pointer points to a sending message storage bit where a to-be-sent message to be written is located; the processing message storage area comprises a plurality of processing message storage bits, the processing message storage area is configured with at least a second read pointer and a second write pointer, the second write pointer points to a processing message storage bit where a to-be-processed message to be written is located, and the second read pointer points to a processing message storage bit where a to-be-processed message is located. It can be seen that the shared storage device enables a to-be-sent message and a to-be-processed message to share one storage in the case that the to-be-sent message and the to-be-processed message can be sent, thereby improving storage space utilization.

Description

Technical Field

[0001] This invention relates to the field of chip communication technology, specifically to a shared storage device and a UALink chip. Background Technology

[0002] In high-performance AI switching chips and high-speed interconnect communication systems, UALink (Ultra AcceleratorLink, a high-performance interconnect protocol for accelerators) has attracted widespread attention as a chip / board interconnect protocol for high-speed interconnection, low latency, and high reliability due to its high bandwidth and low latency characteristics. UALink adopts a layered protocol architecture, including the UALink Protocol Level Interface (UPLI), Transaction Layer (TL), Data Link Layer (DL), and Physical Layer (PL). The UALink Protocol Level Interface serves as the entry point for the entire interconnect protocol to the upper-layer hardware, handling high-level memory access transaction definitions and interfacing with the accelerator core, cache, and memory controller. When message interaction is performed based on UALink chips, reliable message transmission relies on the buffer management of the sending and receiving queues by the Data Link Layer.

[0003] In the existing architecture, the sending end of the UALink chip needs to temporarily store messages to be sent until it receives confirmation from the target UALink chip to support packet loss retransmission; the receiving end of the UALink chip needs to temporarily store received messages that have not yet been read by upper-layer software or hardware to implement flow control and error handling. Therefore, send storage and receive storage are indispensable components of the data link layer. Currently, the send storage of the sending end and the receive storage of the receiving end of the UALink chip are generally implemented using independent storage spaces, that is, the send queue and the receive queue are set up with their own independent storage. However, in actual operation, the storage spaces corresponding to the send queue and the receive queue rarely reach their peak values ​​at the same time. This situation will cause one side's storage space to be idle for a long time, while the other side frequently triggers overflow alarms, resulting in a waste of storage resources. Summary of the Invention

[0004] The main technical problem solved by this invention is that the storage spaces corresponding to the sending queue and the receiving queue rarely reach their peak values ​​at the same time. One side's storage space is idle for a long time, while the other side frequently triggers overflow alarms, resulting in a waste of storage resources.

[0005] According to a first aspect, one embodiment provides a shared storage device, comprising:

[0006] The storage includes a message sending storage area and a message processing storage area. The message sending storage area includes several message sending storage bits and is equipped with at least a first read pointer and a first write pointer. The first read pointer points to the message sending storage bit where the current message to be sent is located, and the first write pointer points to the message sending storage bit where the current message to be written is located. The message processing storage area includes several message processing storage bits and is equipped with at least a second read pointer and a second write pointer. The second write pointer points to the message processing storage bit where the current message to be written is located, and the second read pointer points to the message processing storage bit where the current message to be processed is located.

[0007] The message sending buffer module includes multiple message sending buffer bits;

[0008] The message caching module includes multiple message caching bits.

[0009] The queue management module is used for:

[0010] When receiving a message to be sent, at least a portion of the received message to be sent is written sequentially into the plurality of message storage bits, and the first write pointer is maintained to point to the message storage bit where the current message to be written is located each time the message to be sent is written.

[0011] When sending a message to be sent, the sending message buffer module is controlled to send the message to be sent from the plurality of sending message buffer bits; wherein, the sending message buffer module releases one sending message buffer bit each time it sends a message to be sent;

[0012] In response to the release of the sending message buffer bit, the sending message buffer module is controlled to read the message to be sent stored in the sending message storage bit currently pointed to by the first read pointer, so as to fill the released sending message buffer bit; and the first read pointer is maintained so that the first read pointer points to the sending message storage bit where the current message to be sent is located;

[0013] When receiving a message to be processed, at least a portion of the received message to be processed is written sequentially into the plurality of processing message storage bits, and the second write pointer is maintained to point to the processing message storage bit where the current message to be processed is located each time the message to be processed is written.

[0014] When sending a message to be processed, the message processing cache module is controlled to send the message to be processed from the plurality of message processing cache bits; wherein, the message processing cache module releases one message processing cache bit each time it sends a message to be processed;

[0015] In response to the release of the processing message buffer bit, the processing message buffer module is controlled to read the message to be processed stored in the processing message storage bit currently pointed to by the second read pointer, so as to fill the released processing message buffer bit; and the second read pointer is maintained so that the second read pointer points to the position of the message to be sent.

[0016] In one embodiment, the message storage area is further configured with a first reread pointer, which points to the location of the message to be sent that needs to be confirmed whether it needs to be reread.

[0017] The shared storage device further includes: a message backup module, comprising multiple message backup bits, each message buffer bit corresponding to each message backup bit, wherein the message backup bits are used to store copies of messages to be sent;

[0018] The queue management module is also used for:

[0019] When each of the aforementioned message buffer bits is filled for the first time, the message to be sent that was first filled into the message buffer bit is respectively filled into the corresponding message backup bit;

[0020] The messages in the message buffer are sent sequentially. After each sending, the message buffer module is controlled to read the message to be sent from the message buffer pointed to by the first read pointer and fill it into the empty message buffer. The first read pointer keeps its current pointer.

[0021] For any one of the message backup bits: when the corresponding message to be sent is confirmed as the expected message to be sent, clear the copy of the message to be sent on the corresponding message backup bit, control the message backup module to maintain the copy of the message to be sent on the corresponding message backup bit, so that the copy of the message to be sent on the corresponding message backup bit is the current message to be sent on the corresponding message buffer bit; and maintain the first reread pointer so that the first reread pointer points to the position of the message to be sent that needs to be confirmed whether it needs to be reread, and release the message storage bit corresponding to the corresponding message backup bit;

[0022] When the corresponding message to be sent is confirmed as an unexpected message, the sending message buffer module is controlled to copy a copy of the message to be sent from any of the sending messages and fill it into the corresponding sending message buffer bit, and then resend it; and the current position pointed to by the first reread pointer is maintained.

[0023] In one embodiment, when receiving a message to be sent, at least a portion of the received message to be sent is sequentially written into the plurality of message storage bits in chronological order, including:

[0024] In the initial stage, the first N messages to be sent are sequentially filled into multiple message sending buffers, and each message sending buffer is filled with one message to be sent.

[0025] The N subsequent messages to be sent are written sequentially into the message sending storage area.

[0026] In one embodiment, the message sending storage area is provided with a first prefetch register, and the queue management module is further used to monitor the state of the first prefetch register. When the first prefetch register is in an idle state, the module controls the first prefetch register to read the message to be sent from the message sending storage bit pointed to by the first read pointer, so as to read the message to be sent from the first prefetch register when controlling the message sending buffer module to read the message to be sent; and to maintain the current pointer of the first read pointer.

[0027] In one embodiment, the plurality of message sending buffer bits constitute a first-in-first-out queue;

[0028] The step of controlling the sending message buffer module to read the message to be sent stored in the sending storage bit currently pointed to by the first read pointer in response to the release of the sending message buffer bit includes:

[0029] After the message to be sent in the first sending message buffer is read, the messages to be sent in the second to Nth sending message buffers are moved forward one position in sequence, so that the first sending message buffer is filled and the Nth sending message buffer is empty; N is the total number of the multiple sending message buffers;

[0030] After the Nth send message buffer bit is set to empty, the send message buffer module is controlled to read the message to be sent from the first prefetch register and fill it into the Nth send message buffer bit;

[0031] and / or;

[0032] The multiple message backup bits form a first-in-first-out queue;

[0033] The control of the message backup module to maintain a copy of the message to be sent at any one of the message backup bits includes:

[0034] When the message to be sent corresponding to the first message backup bit is the desired message, clear the first message backup bit;

[0035] After the copy of the message to be sent in the first message backup bit is cleared, the messages to be sent in the second to Nth message backup bits are moved forward one position in sequence, so that the first message backup bit is filled and the Nth message backup bit is empty; N is the total number of the multiple message backup bits;

[0036] After the Nth message backup bit is set to empty, the message backup module is controlled to read the message to be sent from the first prefetch register and fill it into the Nth message backup bit.

[0037] In one embodiment, the received message storage area is further configured with a second reread pointer, which points to the location of the pending message that needs to be confirmed whether it needs to be reread.

[0038] The shared storage device further includes: a message processing backup module, comprising multiple message processing backup bits, each message processing cache bit corresponding one-to-one with each message processing backup bit, wherein the message processing backup bits are used to store copies of messages to be processed;

[0039] The queue management module is also used for:

[0040] When each of the processing message buffer bits is filled for the first time, the messages to be processed that were first filled into the processing message buffer bits are respectively filled into the corresponding processing message backup bits;

[0041] The messages in the processing message buffer are sent sequentially. After each sending, the processing message buffer module is controlled to read the message to be processed from the processing message buffer pointed to by the second read pointer and fill it into the empty processing message buffer. The second read pointer keeps its current pointer.

[0042] For any processing message backup bit: when the corresponding pending message is confirmed as the expected processing message, clear the copy of the pending message on the processing message backup bit, control the processing message backup module to maintain the copy of the pending message on the processing message backup bit, so that the copy of the pending message on the processing message backup bit is the current pending message on the corresponding processing message cache bit; and maintain the second reread pointer so that the second reread pointer points to the position of the pending message that needs to be confirmed whether it needs to be reread, and release the processing message storage bit corresponding to the processing message backup bit;

[0043] When the corresponding pending message is confirmed as an undesirable message, the processing message caching module is controlled to copy a copy of the pending message on any one of the processing messages and fill it into the corresponding processing message caching bit, and then resend it; and the current position pointed to by the second reread pointer is maintained.

[0044] In one embodiment, when receiving a message to be processed, at least a portion of the received messages to be processed are sequentially written into the plurality of processing message storage bits, including:

[0045] In the initial stage, the first N messages to be processed are sequentially filled into multiple processing message cache positions, and each of the multiple processing message cache positions is filled with one message to be processed;

[0046] The N subsequent messages to be processed are written sequentially into the processing message storage area.

[0047] In one embodiment, the processing message storage area is provided with a second prefetch register, and the queue management module is further used to monitor the state of the second prefetch register. When the second prefetch register is in an idle state, the module controls the second prefetch register to read the message to be processed on the processing message storage bit pointed to by the second read pointer, so as to read the message to be processed from the second prefetch register when controlling the processing message cache module to read the message to be processed; and to maintain the current pointer of the second read pointer.

[0048] In one embodiment, the plurality of message processing buffer bits constitute a first-in-first-out queue;

[0049] The step of controlling the message processing cache module to read the message to be processed stored at the current position pointed to by the second read pointer in response to the release of the message processing cache bit includes:

[0050] When the message to be processed in the first processing buffer bit is read, the messages to be processed in the second to Nth processing buffer bits are moved forward one position in sequence, so that the first processing buffer bit is filled and the Nth processing buffer bit is empty; N is the total number of the multiple processing buffer bits.

[0051] After the Nth processing message buffer bit is set to empty, the processing message buffer module is controlled to read the message to be processed in the second prefetch register and fill it into the Nth processing message buffer bit;

[0052] and / or;

[0053] The multiple message backup bits constitute a first-in-first-out queue;

[0054] The control of the message processing backup module to maintain a copy of the message to be processed at any one of the message processing backup bits includes:

[0055] When the message to be processed corresponding to the first backup bit of the processing message is the message to be processed, clear the copy of the message to be processed in the first backup bit of the processing message;

[0056] After the copy of the message to be processed in the first processing message backup position is cleared, the copies of the data to be processed in the second to Nth processing message backup positions are moved forward one position in sequence, so that the first processing message backup position is filled and the Nth processing message backup position is empty; N is the total number of the multiple processing message backup positions;

[0057] After the Nth processing message backup bit is set to empty, the processing message backup module is controlled to read the message to be processed in the second prefetch register and fill it into the Nth processing message backup bit.

[0058] In one embodiment, the shared storage device further includes:

[0059] The configuration management module is used to obtain pre-configuration parameters, determine the address range of the sending storage area and the address range of the receiving storage area based on the pre-configuration parameters, and send them to the queue management module.

[0060] The queue management module is also used for:

[0061] Based on the address range of the sending storage area and the address range of the receiving storage area, the storage is divided into the sending message storage area and the processing message storage area.

[0062] According to a second aspect, one embodiment provides a UALink chip, including: a shared storage device as described above.

[0063] According to the shared storage device and UALink chip in the above embodiments, the storage is divided into a message sending storage area and a message processing storage area. After receiving a message to be sent, the queue management module can sequentially write at least a portion of the message to be sent into the message sending storage position in the message sending storage area. When sending messages to be sent from several message sending storage positions, the queue management module controls the message sending buffer module to send messages to be sent from the message sending buffer positions. After sending, the message to be sent is read from the message sending storage position. In this way, the message to be sent is sent. Similarly, after receiving a message to be processed, the queue management module can sequentially write at least a portion of the message to be processed into the message processing storage position in the message processing storage area. When sending messages to be processed from several message processing storage positions, the queue management module controls the message processing buffer module to send messages to be processed from the message processing buffer positions. After sending, the message to be processed is read from the message processing storage position. In this way, the message to be processed is sent. Therefore, this shared storage device enables both messages to be sent and messages to be processed to be sent to share the same storage space. Furthermore, it can divide the same storage space into corresponding message sending and message processing storage areas based on the data volume of the messages to be sent and the data volume of the messages to be processed, thereby achieving on-demand flexible allocation of storage resources and improving storage space utilization. Attached Figure Description

[0064] Figure 1 This is a schematic block diagram of a shared storage device according to one embodiment;

[0065] Figure 2 This is a schematic block diagram of a shared storage device according to another embodiment;

[0066] Figure 3 This is a flowchart illustrating the working principle of a configuration management module in one embodiment.

[0067] Figure 4 This is a flowchart illustrating the sending process of a message to be sent, according to one embodiment.

[0068] Reference numerals: 100, Queue Management Module; 200, Storage; 201, First Prefetch Register; 202, Second Prefetch Register; 300, Send Message Backup Module; 301, Send Message Backup Bit; 3011, Second Selector; 3012, First Backup Register; 400, Send Message Buffer Module; 401, Send Message Buffer Bit; 4011, First Selector; 4012, First Buffer Register; 500, Processing Message Buffer Module; 501, Processing Message Buffer Bit; 5011, Third Selector; 5012, Second Buffer Register; 600, Processing Message Backup Module; 601, Processing Message Backup Bit; 6011, Fourth Selector; 6012, Second Backup Register; 700, Configuration Management Module. Detailed Implementation

[0069] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of the invention. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present invention are not shown or described in the specification. This is to avoid obscuring the core parts of the invention with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0070] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0071] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this invention, unless otherwise specified, include both direct and indirect connections (linkages).

[0072] This application provides a shared storage device applied to a UALink chip, such as... Figure 1 As shown, it may include a storage module, a message sending cache module, a message processing cache module, a queue management module, and a configuration management module.

[0073] The storage system includes a message sending storage area and a message processing storage area. The message sending storage area includes several message sending storage bits and is configured with at least a first read pointer and a first write pointer. The first read pointer points to the message sending storage bit currently containing the message to be sent, and the first write pointer points to the message sending storage bit currently containing the message to be written. The message processing storage area includes several message processing storage bits and is configured with at least a second read pointer and a second write pointer. The second read pointer points to the message processing storage bit currently containing the message to be processed, and the second write pointer points to the message processing storage bit currently containing the message to be written. A message sending cache module includes multiple message sending cache bits used to cache messages to be sent. A message processing cache module includes multiple message processing cache bits used to cache messages to be processed.

[0074] The queue management module is used for:

[0075] When receiving a message to be sent, at least a portion of the received message to be sent is written sequentially into several message storage bits, and each time a message to be sent is written, the first write pointer is maintained to point to the message storage bit where the current message to be written is located.

[0076] When sending a message to be sent, the message sending buffer module is controlled to send the message to be sent from multiple message sending buffer bits; each time the message sending buffer module sends a message to be sent, it releases one message sending buffer bit.

[0077] In response to the release of the send message buffer bit, the send message buffer module is controlled to read the message to be sent stored in the send message storage bit currently pointed to by the first read pointer, so as to fill the released send message buffer bit; and the first read pointer is maintained so that the first read pointer points to the send message storage bit where the current message to be sent is located;

[0078] When receiving a message to be processed, at least a portion of the received message to be processed is written sequentially into several processing message storage bits, and a second write pointer is maintained to point to the processing message storage bit where the current message to be processed is located each time a message to be processed is written.

[0079] When sending pending messages, the control message processing cache module sends pending messages from multiple processing message cache bits; each time the processing message cache module sends a pending message, it releases one processing message cache bit.

[0080] In response to the release of the processing message buffer bit, the control module reads the message to be processed stored in the processing message storage bit currently pointed to by the second read pointer to fill the released processing message buffer bit; and maintains the second read pointer so that the second read pointer points to the position of the message to be sent.

[0081] In some embodiments, the storage is pre-configured as independent message sending storage area and message processing storage area, each with its own dedicated address range, and the address ranges of the two do not overlap. The sum of the queue depth of the message sending storage area and the queue depth of the message processing storage area is less than or equal to the total storage depth. In one specific embodiment, the storage depth is 0 to B-1, the queue depth of the message sending storage area is 0 to A-1, and the queue depth of the message processing storage area is A to B-1; where A is a positive integer between 0 and B-1. For example, if the storage depth is 0 to 9, the queue depth of the message sending storage area can be 0 to 4; and the queue depth of the message processing storage area can be 5 to 9; where 5 can be understood as A, and 9 can be understood as B-1. Of course, when the storage depth is 0 to 9, the queue depth of the message sending storage area can be 0 to 7, and the queue depth of the message processing storage area can be 8 to 9; where 8 can be understood as A, and 9 can be understood as B-1. Those skilled in the art can determine the specific depth according to the actual situation.

[0082] For example, with a storage depth of 0 to 31, the queue depth of the message sending storage area can be 0 to 15; the queue depth of the message processing storage area can be 16 to 31; where 15 can be understood as A, and 31 can be understood as B-1. Of course, when the storage depth is 0 to 31, the queue depth of the message sending storage area can be 0 to 18; the queue depth of the message processing storage area can be 19 to 31; where 19 can be understood as A, and 31 can be understood as B-1, and those skilled in the art can determine the specific depth according to the actual situation.

[0083] The message sending storage area comprises several message sending storage bits, which form a first-in, first-out (FIFO) array. The message sending storage area maintains at least a first read pointer and a first write pointer. The first read pointer always points to the message sending storage bit currently being read. During initialization, the first read pointer is set to the starting address of the message sending storage area (i.e., offset address 0) to point to the head of the queue (the first readable position). The first write pointer always points to the message sending storage bit currently being written. During initialization, the first write pointer is set to the starting address of the message sending storage area (i.e., offset address 0) to point to the head of the queue (the first writable position).

[0084] Specifically, after initialization, the message sending storage area has the following settings: wr_ptr = 0, rd_ptr = 0, replay_ptr = 0; the message processing storage area has the following settings: wr_ptr = A, rd_ptr = A, replay_ptr = A. When maintaining the first read pointer, second read pointer, first write pointer, and second write pointer, the pointers are incremented by 1 each time, and after reaching the maximum address, they are all circularly flipped back to the base address.

[0085] The message processing storage area comprises several message processing storage bits, which form a first-in, first-out (FIFO) array. The message processing storage area maintains at least a second read pointer and a second write pointer. The second read pointer always points to the message processing storage bit currently being read. During initialization, the second read pointer is set to the starting address of the message processing storage area (i.e., offset address A), pointing to the head of the queue (the first readable position). The second write pointer always points to the message processing storage bit currently being written. During initialization, the second write pointer is set to the starting address of the message processing storage area (i.e., offset address A), pointing to the head of the queue (the first writable position).

[0086] During the message receiving phase: The queue management module sequentially writes at least a portion of the received messages into several message storage bits in the message sending storage area. The first write pointer increments with each write, and after reaching the maximum address, it rotates to the base address. The queue management module controls the message sending buffer module to sequentially output the messages to be sent buffered in the message sending buffer bits. Each time a buffered message to be sent is output, a message sending buffer bit is released. In response to the release of the message sending buffer bit, the queue management module controls the message sending buffer module to read the message to be sent stored in the message sending storage bit currently pointed to by the first read pointer from the message sending storage area and fill it into the released message sending buffer bit. At the same time, the first read pointer is maintained so that it points to the message sending storage bit where the current message to be sent is located.

[0087] Therefore, during the message sending stage, the message sending buffer module can be controlled to output the messages to be sent from the message sending buffer positions in sequence, and at the same time, the messages in the message sending storage positions of the message sending storage area can be sequentially filled into the message sending buffer positions of the message sending buffer module, thereby realizing pipelined message sending.

[0088] During the message receiving phase: The queue management module sequentially writes at least a portion of the received messages into several processing message storage bits in the processing message storage area. The second write pointer increments with each write, and after reaching the maximum address, it rotates to the base address. The queue management module controls the processing message buffer module to sequentially output the messages to be processed cached in the processing message buffer bits. Each time a buffered message is output, a processing message buffer bit is released. In response to the release of the processing message buffer bit, the queue management module controls the processing message buffer module to read the message to be processed from the processing message storage area currently pointed to by the second read pointer and fill it into the released processing message buffer bit. At the same time, the second read pointer is maintained so that it points to the processing message storage bit where the current message to be processed is located.

[0089] Therefore, during the message sending phase, the message processing cache module can be controlled to output the messages to be processed in the message processing cache position in sequence, and at the same time, the messages in the message processing storage position of the message processing storage area can be sequentially filled into the message processing cache position of the message processing cache module, thereby realizing pipelined message sending.

[0090] Therefore, this shared storage device enables messages to be sent and messages to be processed to be sent in a pipeline manner, allowing them to share a single storage space. Furthermore, it can divide the same storage space into corresponding message sending and message processing storage areas based on the data volume of the messages to be sent and the data volume of the messages to be processed, thereby achieving on-demand elastic allocation of storage resources and improving storage space utilization.

[0091] In some instances, the message storage area also maintains a first reread pointer, which points to the location of the message to be sent that needs to be confirmed whether it needs to be reread. When it is determined that rereading is not necessary, the location of the message to be sent can be released. For example... Figure 2 As shown, the shared storage device also includes a message backup module, comprising multiple message backup bits. Each message buffer bit corresponds one-to-one with each message backup bit, and the message backup bits are used to store copies of the messages to be sent. Specifically, the number of multiple message backup bits is the same as the number of multiple message buffer bits. Each message buffer bit corresponds to one message backup bit, and each message backup bit corresponding to a message buffer bit stores a copy of the message to be sent stored in that message buffer bit.

[0092] In some embodiments, the queue management module is further configured to:

[0093] When each message buffer is filled for the first time, the messages to be sent that were first filled into the message buffer will be filled into the corresponding message backup bits.

[0094] Messages in the message buffer are sent sequentially. After each sending, the message buffer module reads the message to be sent from the message buffer pointed to by the first read pointer and fills the empty message buffer. The first read pointer keeps the current pointer.

[0095] For any message backup bit: when the corresponding message to be sent is confirmed as the expected message to be sent, clear the copy of the message to be sent on any message backup bit, control the message backup module to maintain the copy of the message to be sent on any message backup bit, so that the copy of the message to be sent on any message backup bit is the current message to be sent on the corresponding message buffer bit; and maintain the first reread pointer so that the first reread pointer points to the position of the message to be sent that needs to be confirmed whether it needs to be reread, and release the message storage bit corresponding to any message backup bit;

[0096] When the corresponding message to be sent is confirmed as an unexpected message, the sending message buffer module is controlled to copy a copy of the message to be sent from any sending message and fill it into the corresponding sending message buffer bit, and then resend it; and the current position pointed to by the first reread pointer is maintained.

[0097] Specifically, when multiple message sending cache bits on the message sending cache module are filled for the first time, the queue management module fills the multiple messages to be sent from the multiple message sending cache bits filled for the first time into multiple message sending backup bits, so that the message sending backup bits and message sending cache bits maintain the same content in the initial filling stage.

[0098] During the message sending phase, after sending the messages to be sent in the message sending buffer in sequence, the message sending buffer module is controlled to read the messages to be sent from the message sending buffer pointed to by the first read pointer and fill them into the empty message sending buffer. The first read pointer keeps its current pointer.

[0099] For any message backup bit, when the corresponding message to be sent (i.e., the currently sent message) is confirmed as the expected message, the queue management module clears the copy in the message backup bit, updates the current message to be sent in the corresponding message buffer bit to the message backup bit (this is the updated message to be sent), increments the first reread pointer (rotates in a circular fashion), and releases the message storage bit corresponding to the message backup bit, so that the message storage bit can be reused by new messages. When the corresponding message to be sent is confirmed as an unexpected message, the queue management module copies the copy in the message backup bit to the corresponding message buffer bit to perform retransmission, while keeping the current pointer of the first reread pointer unchanged.

[0100] In some embodiments, after a message to be sent is sent from the message buffer, it can be sent to the target UALink chip. The target UALink chip processes the message to be sent and performs verification to determine whether the message is the expected message. A checksum (such as CRC check or parity check) can be appended to the end or a specified field of the message to be sent. This checksum is calculated using an existing verification algorithm based on all valid data of the message to be sent. When the target UALink chip receives the message to be sent, it also recalculates a checksum based on all valid data of the message to be sent and compares the recalculated checksum with the checksum carried in the received message to be sent. If they match, it is the expected message to be sent; otherwise, it is not the expected message to be sent. The target UALink chip is the chip connected to the UALink chip connected to the local end. The target UALink chip is also connected to a peer device, which refers to an accelerator connected to the target UALink chip. This accelerator can be, but is not limited to, a GPU. For example, the accelerator can also be an NPU (Neural Processing Unit). A UALink chip refers to a chip that supports the UALink protocol and can interconnect with the accelerator via the UALink protocol.

[0101] If a message is expected to be sent, data indicating that the message to be sent is an expected message will be included when sending the message (to be processed) to the UALink chip. After the message to be processed is processed, the UALink chip on the local end generates a first feedback message (indicating that the message to be sent is an expected message). At this time, the queue management module responds to the first feedback message by updating the current message to be sent in the corresponding message buffer to a copy of the message to be sent in the message backup bit (which is the message to be sent that has been maintained). At the same time, the first reread pointer is incremented (circular flip), and the message storage bit corresponding to the message backup bit is released. Here, the local end can be understood as an accelerator connected to the UALink chip. The accelerator can be, but is not limited to, a GPU (Graphics Processing Unit). For example, the accelerator can also be an NPU (Neural Processing Unit).

[0102] If the message is not the expected message, it will carry data indicating that it is not the expected message when sending the message (pending message) to the UALink chip. After the pending message is processed, the UALink chip generates a second feedback message (indicating that the pending message is not the expected message). At this time, the queue management module responds to the second feedback message by copying the current pending message from the corresponding sending message backup bit to the sending message backup bit (which is now the maintained pending message), while keeping the first reread pointer unchanged, and controlling the sending message buffer module to retransmit the pending message. Therefore, by using the backup message buffer module, storage access is not required during retransmission, eliminating the latency caused by storage access during retransmission.

[0103] Furthermore, based on the premise that retransmission does not require access to storage, an initialization filling strategy is defined. In the initial stage, the queue management module sequentially fills the first N messages to be sent (N being the total number of message buffer positions) into multiple message buffer positions, with each buffer filled with one message to be sent. Simultaneously, the corresponding backup message positions are also filled, ensuring that all message buffer positions and backup positions are fully loaded when the pipeline starts. Subsequent messages to be sent are written sequentially to the message storage area, without being directly filled into message buffer positions. Therefore, when sending messages, continuous sending can begin from the first message buffer position after initialization, without waiting for a storage response. The pipeline achieves line-rate output from startup, reducing latency.

[0104] It should be noted that the initial stage refers to the stage when multiple message sending buffer bits are empty during the initial operation.

[0105] In some embodiments, such as Figure 1 , Figure 2As shown, the message storage area is equipped with a first prefetch register, which is located between the message storage area and the message buffer module. The first prefetch register serves as an intermediate buffer between the message storage area and the message buffer module. In practical applications, after the initial stage (after the initialization and filling strategy is completed), the queue management module continuously monitors the status of the first prefetch register. When the first prefetch register is idle, the queue management module controls the first prefetch register to read the message to be sent from the message storage position currently pointed to by the first read pointer and temporarily store it, while maintaining the first read pointer. When the message buffer module needs to fill the message to be sent, the queue management module controls the message buffer module to read the temporarily stored message to be sent from the first prefetch register and fill it into the released message buffer position. The first prefetch register is set up as an intermediate buffer to prefetch the message to be sent when reading the message to be sent. Since the register latency is lower than the storage latency, the first prefetch register further ensures the timeliness of filling the message buffer module, avoiding the situation where the message buffer position becomes empty due to latency.

[0106] In some embodiments, multiple message buffer bits form a first-in-first-out (FIFO) queue, and multiple message backup bits form a FIFO queue. The multiple message buffer bits and multiple message backup bits are kept synchronized through a shift mechanism. The queue control module can monitor the status of each message buffer bit and the status of each message backup bit.

[0107] When the queue management module responds to the release of the message buffer bit and controls the message buffer module to read the message to be sent stored in the message storage bit currently pointed to by the first read pointer, after the message to be sent in the first message buffer bit is read, the queue control module detects that the first message buffer bit has been released and further controls the messages to be sent in the second to Nth message buffer bits to move forward one position in sequence, so that the first message buffer bit is filled and the Nth message buffer bit is empty; at this time, the queue management module detects that the Nth message buffer bit is empty, and further controls the message buffer module to read the message to be sent in the first prefetch register and fill it into the Nth message buffer bit; after the message to be sent in the first prefetch register is read, the queue control module further controls the first prefetch register to read a message to be sent from the position currently pointed to by the first read pointer and fill it into the first prefetch register for the next filling; where N is the total number of multiple message buffer bits.

[0108] Meanwhile, the message backup module executes the same shift mechanism. When the queue management module responds to the release of a message backup bit and controls the message backup module to update the copy of the message to be sent at any one of the message backup bits, if the message to be sent corresponding to the first message backup bit is the desired message, the first message backup bit is cleared. The queue control module detects that the first message backup bit has been released and controls the messages to be sent in the second to Nth message backup bits to move forward one position sequentially, so that the first message backup bit is filled and the Nth message backup bit is empty. At this point, the queue management module detects that the Nth message backup bit is empty, and further controls the message processing module to read the message to be sent from the first prefetch register and fill it into the Nth message backup bit. At this point, the messages to be sent in the multiple message backup bits and the multiple message buffer bits are consistent; where N is the total number of message backup bits.

[0109] Through the aforementioned first-in-first-out queue shifting mechanism, the message sending cache module and the message sending backup module always maintain a bit-by-bit correspondence, ensuring that the backup bit stores the latest copy of the message in the corresponding cache bit at any given time. During retransmission, it can be directly restored in parallel without additional address calculation or storage access.

[0110] In some embodiments, when the message to be sent is not an expected message that needs to be retransmitted, copies of the message to be sent stored in each of the multiple message backup bits are read, and these copies are copied one-to-one into the multiple message buffer bits. This copying operation ensures that the message to be sent in the message buffer bits is consistent with the message to be sent in the message backup bits, and enables retransmission, maintaining the consistency between the message to be sent in the multiple message buffer bits and the copies of the message to be sent in the multiple message backup bits.

[0111] In some embodiments, such as Figure 1 , Figure 2 As shown, each of the multiple message sending buffer bits includes a first selector and a first buffer register. The first selector can be a multiplexer. The multiple message sending buffer bits are cascaded. For any level of message sending buffer bit, the multiplexer is connected to the queue management module, the storage, the corresponding message sending backup bit, and the output of the first prefetch register, respectively. The output of the multiplexer is connected to the input of the corresponding first buffer register. When there is a previous level message sending buffer bit, the output of the first buffer register is connected to the multiplexer on the previous level message sending buffer bit. The output of the first buffer register on the first level message sending buffer bit (i.e., the first message sending buffer bit) is used to output the message to be sent.

[0112] like Figure 2 As shown, each of the multiple message backup bits includes a second selector and a backup buffer. The second selector can be a multiplexer. The multiple message backup bits are cascaded. For any level of message backup bit, the multiplexer is connected to the output of the queue management module, the storage, and the first prefetch register, respectively. The output of the multiplexer is connected to the input of the corresponding first backup register. Specifically, the output of the first backup register in non-first-level message backup bits is connected to the previous-level multiplexer and the multiplexer on the corresponding message buffer bit. The output of the first backup register on the first-level message buffer bit is connected to the multiplexer on the corresponding message buffer bit.

[0113] In practical applications, during the initial filling phase, the queue management module controls the first selector to sequentially fill N messages to be sent into the first buffer registers on multiple message sending buffer bits. At the same time, N messages to be sent are sequentially filled into the first backup registers on multiple message sending backup bits. The first prefetch register reads the message to be sent from the position currently pointed to by the first read pointer in the sending storage area.

[0114] During the message sending phase, the first buffer register outputs the messages it has buffered. The queue management module detects that the first buffer register is empty and controls the messages to be sent in the second to the Nth buffer registers to move forward one position sequentially. The first buffer register is filled and the Nth buffer register is empty. At this time, the Nth buffer register reads the messages to be sent from the first prefetch register. In this way, the messages to be sent received by the queue management module are sent sequentially. During the process, the first read pointer is maintained so that it always points to the message to be sent that is currently being read. At the same time, the first write pointer is maintained so that it always points to the position of the message to be written.

[0115] When a message to be sent is a message to be sent, the queue management module responds to the corresponding first feedback message by clearing the copy of the message to be sent, that is, clearing the copy in the first backup register corresponding to the message to be sent. At this time, the queue management module detects that the first backup register is empty, and controls the copies of the messages to be sent in the second backup register to the Nth backup register to move forward one position in sequence. The first backup register is filled and the Nth backup register is empty. At this time, the Nth backup register is controlled to read the message to be sent from the first prefetch register. In this way, the copy in each backup register is kept consistent with the message to be sent in the corresponding message buffer bit.

[0116] When a message to be sent is not the expected message, the queue management module responds to the corresponding second feedback message by controlling all first buffer registers to copy the message to be sent from the corresponding first backup register. Since the first backup register is not cleared, the copy of the message to be sent in the corresponding first backup register is the copy before the message was sent. Therefore, after the first buffer register copies the message to be sent from the corresponding first backup register, the content of the message to be sent in the first first buffer register is consistent with the content of the message to be sent. Thus, retransmission can be achieved when an erroneous message (not the expected message) is sent.

[0117] In some embodiments, the message storage area also maintains a second reread pointer, which points to the location of the message to be processed that needs to be reread. When it is determined that rereading is not necessary, the location of the message to be processed can be released. For example... Figure 2 As shown, the shared storage device also includes a message processing backup module, comprising message processing backup bits. Each message processing cache bit corresponds one-to-one with each message processing backup bit, and the message processing backup bits are used to store copies of messages to be processed. Specifically, the number of multiple message processing backup bits is the same as the number of multiple message processing cache bits. Each message processing cache bit corresponds to one message processing backup bit, and each message processing backup bit corresponding to a message processing cache bit stores a copy of the message to be processed stored in that message processing cache bit.

[0118] In some embodiments, the queue management module is further configured to:

[0119] When each processing message buffer is filled for the first time, the messages to be processed that were first filled into the processing message buffer will be filled into the corresponding processing message backup bits respectively;

[0120] Messages in the processing message buffer are sent sequentially. After each sending, the processing message buffer module reads the message to be processed from the processing message buffer pointed to by the second read pointer and fills the empty processing message buffer. The second read pointer keeps the current pointer.

[0121] For any processing message backup bit: when the corresponding pending message is confirmed as the expected processing message, clear the copy of the pending message on any processing message backup bit, control the processing message backup module to maintain the copy of the pending message on any processing message backup bit, so that the copy of the pending message on any processing message backup bit is the current pending message on the corresponding processing message cache bit; and maintain the second reread pointer so that the second reread pointer points to the location of the pending message that needs to be confirmed whether it needs to be reread, and release the processing message storage bit corresponding to any processing message backup bit;

[0122] When the corresponding pending message is confirmed as an unexpected message, the control message processing cache module copies a copy of the pending message from any processing message and fills it into the corresponding processing message cache bit for retransmission; and maintains the current position pointed to by the second reread pointer.

[0123] Specifically, when multiple processing message cache bits on the processing message cache module are filled for the first time, the queue management module will fill the pending messages that were first filled into the processing message cache bits into the corresponding pending messages, so that the processing message backup bits and processing message cache bits maintain the same content in the initial filling stage.

[0124] During the message sending phase, after the messages to be processed in the message processing buffer are sent in sequence, the message processing buffer module is controlled to read the messages to be processed in the message processing buffer pointed to by the first read pointer and fill them into the empty message processing buffer. The second read pointer keeps pointing to the current position.

[0125] For any processing message backup bit, when the corresponding pending message (i.e., the currently sent pending message) is confirmed as the expected processing message, the queue management module clears the copy in the processing message backup bit, updates the processing message backup bit with the current pending message in the corresponding processing message cache bit (at this time, it is the pending message that has been updated in the processing message cache bit), increments the second reread pointer (circular flip), and releases the processing message storage bit corresponding to the processing message backup bit, so that the processing message storage bit can be reused by new messages. When the corresponding pending message is confirmed as an unexpected processing message, the queue management module copies the copy in the processing message backup bit to the corresponding processing message cache bit to perform retransmission, and keeps the current direction of the second reread pointer unchanged.

[0126] In some embodiments, after a message to be processed is sent from the message processing buffer, it can be sent to the upper-layer processing module in the UALink chip. The upper-layer processing module processes the message to be processed and can determine whether the corresponding message is the expected message through the message to be processed. After receiving the message to be processed, the upper-layer processing module can verify the message to see if it is the expected message. Specifically, a check code (such as CRC check or parity check) can be appended to the end of the message to be processed or a specified field. This check code is calculated and generated based on all the valid data of the message to be processed using an existing verification algorithm. When the upper-layer processing module receives the message to be processed, it also recalculates a check code based on all the valid data of the message to be processed and compares the recalculated check code with the check code carried in the received message to be processed. If the two match, it is the expected message to be processed; if they do not match, it is not the expected message to be processed.

[0127] When determining whether a message to be processed is a desired message, the address corresponding to the first desired message can be pre-configured in the upper-layer processing module. After receiving the first desired message, the address of the second desired message is determined based on the address of the first desired message. For example, if the first desired message is the message to be processed corresponding to address A, after receiving the message to be processed at address A, address A+1 is used as the address of the next desired message, and so on, until the message to be processed corresponding to address B-1 is received. Then, the message to be processed corresponding to address A is used as the desired message again. The explanation of A and B can be found in the explanation of A and B above, and will not be elaborated further here.

[0128] When the address of the message to be processed matches the address of the message to be processed, the UALink chip can generate a third feedback message (indicating that the message to be processed is the message to be processed). At this time, the queue management module responds to the third feedback message by updating the current message to be processed in the corresponding processing message cache bit to the processing message backup bit (which is now the updated message to be processed), and increments the second reread pointer (circular flip), and releases the processing message storage bit corresponding to the processing message backup bit.

[0129] If the message to be processed is not the expected message, the UALink chip can generate a fourth feedback message (indicating that the message to be processed is not the expected message). In response to this fourth feedback message, the queue management module updates the current message to be processed in the corresponding message backup bit to the message processing cache bit, while keeping the second reread pointer unchanged, and controls the message processing cache module to retransmit the message to be processed. Therefore, by using the message processing backup module, storage access is eliminated during retransmission, thus removing the latency caused by storage access during retransmission.

[0130] Furthermore, based on the premise that retransmission does not require access to storage, an initialization filling strategy is defined. In the initial stage, the queue management module sequentially fills the first N pending messages (N being the total number of processing message buffer slots) into multiple processing message buffer slots, with each buffer slot filled with one pending message. Simultaneously, the corresponding backup processing message slot is also filled, ensuring that all processing message buffer slots and backup slots are fully loaded when the pipeline starts. Subsequent pending messages are written sequentially to the processing message storage area, without being directly filled into processing message buffer slots. Therefore, when sending pending messages, continuous sending can begin after initialization from the first processing message buffer slot, without waiting for a storage response. The pipeline achieves line-rate output from startup, reducing latency.

[0131] In some embodiments, such as Figure 1 , Figure 2As shown, a second prefetch register is provided in the message processing storage area. This second prefetch register is located between the message processing storage area and the message processing cache module, serving as an intermediate buffer between them. In practical applications, after the initial phase (after the initialization and filling strategy is completed), the queue management module continuously monitors the status of the second prefetch register. When the second prefetch register is idle, the queue management module controls it to read the message to be processed from the message processing storage position currently pointed to by the second read pointer and temporarily store it, while simultaneously maintaining the second read pointer. When the message processing cache module needs to fill the message to be processed, the queue management module controls it to read the temporarily stored message to be processed from the second prefetch register and fill it into the released message processing cache position. The second prefetch register acts as an intermediate buffer to prefetch the message to be processed when reading it. Since the register's latency is lower than the storage latency, the second prefetch register further ensures the timeliness of filling the message processing cache module, avoiding empty positions in the message processing cache due to latency.

[0132] It should be noted that the initial stage refers to the stage when multiple message buffer bits are empty during the initial run.

[0133] In some embodiments, multiple message processing buffer bits form a first-in-first-out (FIFO) queue, and multiple message processing backup bits form a FIFO queue. The multiple message processing buffer bits and multiple message processing backup bits are kept synchronized through a shift mechanism. The queue control module can monitor the status of each message processing buffer bit and the status of each message processing backup bit.

[0134] When the queue management module responds to the release of the processing message buffer bit and controls the processing message buffer module to read the pending message stored in the processing message storage bit currently pointed to by the second read pointer, after the pending message in the first processing message buffer bit is read, the queue control module detects that the first processing message buffer bit has been released, and further controls the pending messages in the second to Nth processing message buffer bits to move forward one position in sequence, so that the first processing message buffer bit is filled and the Nth processing message buffer bit is empty; at this time, it detects that the Nth processing message buffer bit is empty, and the queue management module further controls the processing message buffer module to read the pending message in the second prefetch register and fill it into the Nth processing message buffer bit; after the pending message in the second prefetch register is read, the queue control module further controls the second prefetch register to read a pending message from the position currently pointed to by the second read pointer and fill it into the second prefetch register for the next filling; where N is the total number of multiple processing message buffer bits.

[0135] Meanwhile, the message backup module executes the same shift mechanism. When the queue management module, in response to the release of a message backup bit, controls the message backup module to update the copy of the message to be processed at any of the message backup bits, if the message to be processed corresponding to the first message backup bit is the desired message, the first message backup bit is cleared. The queue control module, detecting that the first message backup bit has been released, controls the messages to be processed in the second to Nth message backup bits to move forward one position sequentially, so that the first message backup bit is filled and the Nth message backup bit is empty. At this point, detecting that the Nth message backup bit is empty, the queue management module further controls the message processing module to read the message to be processed from the second prefetch register and fill it into the Nth message backup bit. At this point, the messages to be processed in the multiple message backup bits and the multiple message buffer bits are consistent; where N is the total number of message backup bits.

[0136] Through the aforementioned first-in-first-out queue shifting mechanism, the message processing cache module and the message processing backup module always maintain a bit-to-bit correspondence, ensuring that the message processing backup bit stores the latest copy of the message in the corresponding message processing cache bit at any given time. During retransmission, it can be directly restored in parallel without additional address calculation or storage access.

[0137] In some embodiments, when a message to be processed is not a message expected to be processed and needs to be retransmitted, copies of the message to be processed stored in each of the multiple message backup positions are read, and these copies are copied one-to-one into the multiple message buffer positions. This copying operation ensures that the message to be processed in the message buffer positions is consistent with the message to be processed in the message backup positions, and enables retransmission, maintaining consistency between the message to be processed in the multiple message buffer positions and the copies of the message to be processed in the multiple message backup positions.

[0138] In some embodiments, each of the multiple processing message buffer bits includes a third selector and a second buffer register, where the third selector can be a multiplexer. The multiple processing message buffer bits are cascaded. For any level of processing message buffer bit, the multiplexer is connected to the queue management module, the storage, the corresponding processing message backup bit, and the output of the second prefetch register, respectively. The output of the multiplexer is connected to the input of the corresponding second buffer register. When there is a preceding level processing message buffer bit, the output of the second buffer register is connected to the multiplexer on the preceding level processing message buffer bit. The output of the second buffer register on the first level processing message buffer bit (i.e., the first processing message buffer bit) is used to output the message to be processed.

[0139] Each of the multiple processing message backup bits includes a fourth selector and a second backup register, where the second selector can be a multiplexer. The multiple processing message backup bits are cascaded. For any level of processing message backup bit, the multiplexer is connected to the output of the queue management module, the storage, and the second prefetch register, respectively. The output of the multiplexer is connected to the input of the corresponding second backup register. Specifically, the output of the second backup register in non-first-level processing message backup bits is connected to the previous-level multiplexer and the multiplexer on the corresponding processing message buffer bit. The output of the second backup register on the first-level processing message buffer bit is connected to the multiplexer on the corresponding processing message buffer bit.

[0140] In practical applications, during the initial filling phase, the queue management module controls the third selector to sequentially fill N messages to be processed into the second cache registers on multiple processing message cache bits. At the same time, N messages to be processed are sequentially filled into the second backup registers on multiple processing message backup bits. The second prefetch register reads the message to be processed from the position currently pointed to by the second read pointer in the processing storage area.

[0141] During the message sending phase, the first second buffer register outputs the messages it has buffered. The queue management module detects that the first second buffer register is empty and controls the messages in the second second buffer register to the Nth second buffer register to move forward one position sequentially. The first second buffer register is filled and the Nth second buffer register is empty. At this time, the Nth second buffer register is controlled to read the messages in the second prefetch register. In this way, the messages received by the queue management module are sent sequentially. During the process, the second read pointer is maintained so that it always points to the message to be read. At the same time, the second write pointer is maintained so that it always points to the position of the message to be written.

[0142] When a pending message is a message to be sent, the queue management module responds to the corresponding third feedback message by clearing the copy corresponding to that pending message, that is, clearing the copy in the second backup register corresponding to that pending message. At this time, the queue management module detects that the first second backup register is empty, and controls the copies of pending messages in the second second backup register to the Nth second backup register to move forward one position in sequence. The first second backup register is filled and the Nth second backup register is empty. At this time, the Nth second backup register is controlled to read the pending message in the second prefetch register. In this way, the copy in each second backup register is kept consistent with the pending message in the corresponding processing message buffer bit.

[0143] When a pending message is not the expected message, the queue management module responds to the corresponding fourth feedback message by controlling all second buffer registers to copy the pending message in the corresponding second backup register. Since the second backup register is not cleared, the copy of the pending message in the corresponding second backup register is the copy before the pending message was sent. Therefore, after the second buffer register copies the copy of the pending message in the corresponding second backup register, the content of the pending message in the first second buffer register is consistent with the content of the pending message. Thus, retransmission can be achieved when an erroneous message (not the expected message) is sent.

[0144] In some embodiments, when dividing the sending and receiving storage areas, specifically after the system powers on, the upper-layer software writes pre-configuration parameters to the configuration management module through the configuration channel. After obtaining the pre-configuration parameters, the configuration management module calculates the queue depth of the sending message storage area and the queue depth of the processing message storage area based on the pre-configuration parameters. The sum of the queue depths of the sending message storage area and the processing message storage area is less than or equal to M, where M is the total storage depth. The pre-configuration parameters are configured in advance in the upper-layer software by the user based on the actual amount of data to be sent and processed, ensuring that the queue depth of the sending message storage area calculated by the configuration management module can meet the storage requirements of both the sending and processing message storage areas. The pre-configuration parameters also pre-define the starting position for dividing the sending and processing message storage areas, as well as the region to which the starting position belongs. In one embodiment, the starting position is the address 0, which belongs to the sending message storage area. Based on this, the configuration management module can calculate the base address of the sending message storage area as 0 and the maximum address as A-1; and the base address of the processing message storage area as A and the maximum address as B-1.

[0145] The explanations for A and B can be found in the explanations for A and B above, and will not be repeated here.

[0146] In some embodiments, such as Figure 3As shown, the configuration management module is also responsible for arbitration control of the read / write channels during runtime. When the upper layer needs to write a message to be sent, the configuration management module opens the upper layer write message channel and closes the message channel for receiving messages from the target UALink chip (the target UALink chip refers to the accelerator connected to the target UALink chip); when it needs to read a message to be sent, the configuration management module opens the UALink chip read message channel; when it needs to write messages received from the target UALink chip (messages to be processed) into the processing queue (processing message storage), the configuration management module opens the message channel for receiving messages from the target UALink chip; when the upper layer needs to read received messages (messages to be processed), the configuration management module opens the upper layer read message channel. Through the above channel switching logic, the configuration management module achieves read / write conflict isolation between the message sending storage area and the message processing storage area on the same physical storage.

[0147] Since the sending message storage area and the processing message storage area share the same storage, the upper layer can flexibly adjust the queue depth of the sending message storage area and the queue depth of the processing message storage area according to the actual business load. Under the premise that the sum of the queue depth of the sending message storage area and the queue depth of the processing message storage area does not exceed M, the sending and receiving queue depths (M is the total storage depth) are dynamically allocated, eliminating the resource waste caused by the asynchronous peak traffic when the depth processing storage of the sending message storage area and the processing message storage area are configured independently.

[0148] In some embodiments, the configuration management module can be connected to the upper-level processing module via the upper-level configuration bus, and the upper-level software runs on the upper-level processing module.

[0149] To make it easier to understand, the following explanation uses a three-level message buffer as an example.

[0150] like Figure 4 As shown, when the message buffer is empty (initial filling) and the upper layer begins writing messages to be sent, the first three messages are written to MEMORY address 0 sequentially, and simultaneously copied to SEND0 and REPLAY0 (SEND0 represents the first first buffer register, REPLAY0 represents the first backup register); the second message is written to MEMORY address 1, and simultaneously copied to SEND1 and REPLAY1 (SEND1 represents the second first buffer register, REPLAY1 represents the second backup register); the third message is written to MEMORY address 2, and simultaneously copied to SEND2 and REPLAY2 (SEND2 represents the third first buffer register, REPLAY2 represents the third backup register). After this, subsequent messages are only written to MEMORY (address 3 and onwards), and are no longer directly written to the message buffer. After initialization, SEND0~2 are all full, and reading can begin from SEND0.

[0151] Normal read and prefetch pipeline: One message to be sent is read from SEND0 each clock cycle. After reading, the second and third first buffer registers perform the following shift and prefetch operations:

[0152] (1) Shift: The content of SEND1 is shifted to SEND0, the content of SEND2 is shifted to SEND1, and SEND2 becomes empty.

[0153] (2) Prefetch trigger: As long as SEND2 is empty, the prefetch control logic immediately sends a read request to MEMORY to read the message pointed to by the current rd_ptr.

[0154] (3) Delay absorption: Due to the two-clock delay in MEMORY read, the request will return the message to be sent after two clock cycles. During this period, SEND0 and SEND1 are still available in the SEND register group for continuous reading by the message packetizer, and there will be no idle time.

[0155] (4) Message writing: Two clock cycles later, the message to be sent returned by MEMORY arrives. The prefetch control logic writes the message according to priority based on the current empty state of the SEND register: SEND0 > SEND1 > SEND2. That is: if SEND0 is empty, SEND0 is written directly; otherwise, if SEND1 is empty, SEND1 is written; otherwise, SEND2 is written.

[0156] Since reading and shifting are synchronous, the returned message to be sent is usually written to SEND2 (because SEND0 and SEND1 are often not empty), thus keeping the three-stage pipeline fully loaded.

[0157] In some embodiments, this application also provides a UALink chip, including the shared storage device as described above. Specific details are as described in the detailed embodiment of the shared storage device above, and will not be repeated here.

[0158] This document describes various exemplary embodiments with reference to them. However, those skilled in the art will recognize that changes and modifications can be made to the exemplary embodiments without departing from the scope of this document. For example, various operational steps and components for performing operational steps can be implemented in different ways depending on the specific application or considering any number of cost functions associated with the operation of the system (e.g., one or more steps can be deleted, modified, or combined with other steps).

[0159] While the principles herein have been illustrated in various embodiments, numerous modifications to the structures, arrangements, proportions, elements, materials, and components, particularly suited to specific environments and operational requirements, may be used without departing from the principles and scope of this disclosure. These modifications and other alterations or alterations will be included within the scope of this document. Those skilled in the art will recognize that many changes can be made to the details of the above embodiments without departing from the fundamental principles of the invention.

Claims

1. A shared storage device, characterized in that, The shared storage device, applied to the UALink chip, includes: The storage includes a message sending storage area and a message processing storage area. The message sending storage area includes several message sending storage bits and is equipped with at least a first read pointer and a first write pointer. The first read pointer points to the message sending storage bit where the current message to be sent is located, and the first write pointer points to the message sending storage bit where the current message to be written is located. The message processing storage area includes several message processing storage bits and is equipped with at least a second read pointer and a second write pointer. The second write pointer points to the message processing storage bit where the current message to be written is located, and the second read pointer points to the message processing storage bit where the current message to be processed is located. The message sending buffer module includes multiple message sending buffer bits; The message caching module includes multiple message caching bits. The queue management module is used for: When receiving a message to be sent, at least a portion of the received message to be sent is written sequentially into the plurality of message storage bits, and the first write pointer is maintained to point to the message storage bit where the current message to be written is located each time the message to be sent is written. When sending a message to be sent, the sending message buffer module is controlled to send the message to be sent from the plurality of sending message buffer bits; wherein, the sending message buffer module releases one sending message buffer bit each time it sends a message to be sent; In response to the release of the sending message buffer bit, the sending message buffer module is controlled to read the message to be sent stored in the sending message storage bit currently pointed to by the first read pointer, so as to fill the released sending message buffer bit; and the first read pointer is maintained so that the first read pointer points to the sending message storage bit where the current message to be sent is located; When receiving a message to be processed, at least a portion of the received message to be processed is written sequentially into the plurality of processing message storage bits, and the second write pointer is maintained to point to the processing message storage bit where the current message to be processed is located each time the message to be processed is written. When sending a message to be processed, the message processing cache module is controlled to send the message to be processed from the plurality of message processing cache bits; wherein, the message processing cache module releases one message processing cache bit each time it sends a message to be processed; In response to the release of the processing message buffer bit, the processing message buffer module is controlled to read the message to be processed stored in the processing message storage bit currently pointed to by the second read pointer, so as to fill the released processing message buffer bit; and the second read pointer is maintained so that the second read pointer points to the position of the message to be sent.

2. The shared storage device as described in claim 1, characterized in that, The message storage area is also configured with a first reread pointer, which points to the location of the message to be sent that needs to be confirmed whether it needs to be reread. The shared storage device further includes: a message backup module, comprising multiple message backup bits, each message buffer bit corresponding to each message backup bit, wherein the message backup bits are used to store copies of messages to be sent; The queue management module is also used for: When each of the aforementioned message buffer bits is filled for the first time, the message to be sent that was first filled into the message buffer bit is respectively filled into the corresponding message backup bit; The messages in the message buffer are sent sequentially. After each sending, the message buffer module is controlled to read the message to be sent from the message buffer pointed to by the first read pointer and fill it into the empty message buffer. The first read pointer keeps its current pointer. For any one of the message backup bits: when the corresponding message to be sent is confirmed as the expected message to be sent, clear the copy of the message to be sent on the corresponding message backup bit, control the message backup module to maintain the copy of the message to be sent on the corresponding message backup bit, so that the copy of the message to be sent on the corresponding message backup bit is the current message to be sent on the corresponding message buffer bit; and maintain the first reread pointer so that the first reread pointer points to the position of the message to be sent that needs to be confirmed whether it needs to be reread, and release the message storage bit corresponding to the corresponding message backup bit; When the corresponding message to be sent is confirmed as an unexpected message, the sending message buffer module is controlled to copy a copy of the message to be sent from any of the sending messages and fill it into the corresponding sending message buffer bit, and then resend it; and the current position pointed to by the first reread pointer is maintained.

3. The shared storage device as described in claim 2, characterized in that, When receiving a message to be sent, at least a portion of the received message to be sent is sequentially written into the plurality of message storage bits in chronological order, including: In the initial stage, the first N messages to be sent are sequentially filled into multiple message sending buffers, and each message sending buffer is filled with one message to be sent. The N subsequent messages to be sent are written sequentially into the message sending storage area.

4. The shared storage device as described in claim 3, characterized in that, The message sending storage area is provided with a first prefetch register. The queue management module is also used to monitor the status of the first prefetch register. When the first prefetch register is in an idle state, it controls the first prefetch register to read the message to be sent from the message sending storage bit pointed to by the first read pointer, so that when the message sending buffer module is controlled to read the message to be sent, the message to be sent is read from the first prefetch register; and to maintain the current pointer of the first read pointer.

5. The shared storage device as described in claim 4, characterized in that, The multiple message sending buffer bits form a first-in-first-out queue; The step of controlling the sending message buffer module to read the message to be sent stored in the sending storage bit currently pointed to by the first read pointer in response to the release of the sending message buffer bit includes: After the message to be sent in the first sending message buffer is read, the messages to be sent in the second to Nth sending message buffers are moved forward one position in sequence, so that the first sending message buffer is filled and the Nth sending message buffer is empty; N is the total number of the multiple sending message buffers; After the Nth send message buffer bit is set to empty, the send message buffer module is controlled to read the message to be sent from the first prefetch register and fill it into the Nth send message buffer bit; and / or; The multiple message backup bits form a first-in-first-out queue; The control of the message backup module to maintain a copy of the message to be sent at any one of the message backup bits includes: When the message to be sent corresponding to the first message backup bit is the desired message, clear the first message backup bit; After the copy of the message to be sent in the first message backup bit is cleared, the messages to be sent in the second to Nth message backup bits are moved forward one position in sequence, so that the first message backup bit is filled and the Nth message backup bit is empty; N is the total number of the multiple message backup bits; After the Nth message backup bit is set to empty, the message backup module is controlled to read the message to be sent from the first prefetch register and fill it into the Nth message backup bit.

6. The shared storage device according to any one of claims 1-5, characterized in that, The received message storage area is also configured with a second reread pointer, which points to the location of the pending message that needs to be confirmed whether it needs to be reread. The shared storage device further includes: a message processing backup module, comprising multiple message processing backup bits, each message processing cache bit corresponding one-to-one with each message processing backup bit, wherein the message processing backup bits are used to store copies of messages to be processed; The queue management module is also used for: When each of the processing message buffer bits is filled for the first time, the messages to be processed that were first filled into the processing message buffer bits are respectively filled into the corresponding processing message backup bits; The messages in the processing message buffer are sent sequentially. After each sending, the processing message buffer module is controlled to read the message to be processed from the processing message buffer pointed to by the second read pointer and fill it into the empty processing message buffer. The second read pointer keeps its current pointer. For any processing message backup bit: when the corresponding pending message is confirmed as the expected processing message, clear the copy of the pending message on the processing message backup bit, control the processing message backup module to maintain the copy of the pending message on the processing message backup bit, so that the copy of the pending message on the processing message backup bit is the current pending message on the corresponding processing message cache bit; and maintain the second reread pointer so that the second reread pointer points to the position of the pending message that needs to be confirmed whether it needs to be reread, and release the processing message storage bit corresponding to the processing message backup bit; When the corresponding pending message is confirmed as an undesirable message, the processing message caching module is controlled to copy a copy of the pending message on any one of the processing messages and fill it into the corresponding processing message caching bit, and then resend it; and the current position pointed to by the second reread pointer is maintained.

7. The shared storage device as claimed in claim 6, characterized in that, When receiving a message to be processed, at least a portion of the received message to be processed is sequentially written into the plurality of processing message storage bits, including: In the initial stage, the first N messages to be processed are sequentially filled into multiple processing message cache positions, and each of the multiple processing message cache positions is filled with one message to be processed; The N subsequent messages to be processed are written sequentially into the processing message storage area.

8. The shared storage device as claimed in claim 7, characterized in that, The processing message storage area is provided with a second prefetch register. The queue management module is also used to monitor the status of the second prefetch register. When the second prefetch register is in an idle state, it controls the second prefetch register to read the message to be processed on the processing message storage bit pointed to by the second read pointer, so as to read the message to be processed from the second prefetch register when controlling the processing message cache module to read the message to be processed; and to maintain the current pointer of the second read pointer.

9. The shared storage device as claimed in claim 8, characterized in that, The multiple message processing buffer bits form a first-in-first-out queue; The step of controlling the message processing cache module to read the message to be processed stored at the current position pointed to by the second read pointer in response to the release of the message processing cache bit includes: When the message to be processed in the first processing buffer bit is read, the messages to be processed in the second to Nth processing buffer bits are moved forward one position in sequence, so that the first processing buffer bit is filled and the Nth processing buffer bit is empty; N is the total number of the multiple processing buffer bits. After the Nth processing message buffer bit is set to empty, the processing message buffer module is controlled to read the message to be processed in the second prefetch register and fill it into the Nth processing message buffer bit; and / or; The multiple message backup bits constitute a first-in-first-out queue; The control of the message processing backup module to maintain a copy of the message to be processed at any one of the message processing backup bits includes: When the message to be processed corresponding to the first backup bit of the processing message is the message to be processed, clear the copy of the message to be processed in the first backup bit of the processing message; After the copy of the message to be processed in the first processing message backup position is cleared, the copies of the data to be processed in the second to Nth processing message backup positions are moved forward one position in sequence, so that the first processing message backup position is filled and the Nth processing message backup position is empty; N is the total number of the multiple processing message backup positions; After the Nth processing message backup bit is set to empty, the processing message backup module is controlled to read the message to be processed in the second prefetch register and fill it into the Nth processing message backup bit.

10. The shared storage device as claimed in claim 9, characterized in that, The shared storage device also includes: The configuration management module is used to obtain pre-configuration parameters, determine the address range of the sending storage area and the address range of the receiving storage area based on the pre-configuration parameters, and send them to the queue management module. The queue management module is also used for: Based on the address range of the sending storage area and the address range of the receiving storage area, the storage is divided into the sending message storage area and the processing message storage area.

11. A UALink chip, characterized in that, include: The shared storage device as described in any one of claims 1-10.

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