A reset method of a computing card, a computing card and a server

Abstract

The application relates to a reset method of a computing card, the computing card and a server, and belongs to the technical field of electronic circuits. The computing card comprises a first chip, a second chip and a switching chip, a first downlink port of the switching chip is connected with the first chip, a second downlink port of the switching chip is connected with each second chip, a management bus interface of the switching chip is connected with only the first chip, and the first chip and each second chip are directly connected. The method comprises the following steps: when a PCIe link of the second chip is abnormal, a reset request representing PCIe link abnormality of the second chip is sent to the first chip; when the reset request is received, the first chip controls the switching chip to perform a reset operation on the second chip through the management bus interface; and when a PCIe link of the first chip is abnormal, the switching chip is controlled to perform a reset operation on the first chip through the management bus interface. The application can improve the poor universality of the existing PCIe link abnormality repair scheme.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, specifically relating to a method for resetting a computing card, the computing card, and a server. Background Technology

[0002] With the development of artificial intelligence and high-performance computing, graphics processing units (GPUs) are widely used as core PCIe (Peripheral Component Interconnect express) devices in various server scenarios. However, when PCIe devices negotiate PCIe links with the server motherboard's CPU (Central Processing Unit), occasional failures sometimes occur, mainly manifested as bandwidth drops (e.g., from x16 to x8 / x4 / x1) or speed reductions (e.g., from Gen4 to Gen3 / Gen2 / Gen1). Although such problems occur with a low probability, once they do, they directly affect the computing performance of PCIe devices, leading to a decrease in the efficiency of AI training or inference tasks.

[0003] To address the aforementioned PCIe link anomalies, several remediation solutions have been proposed in related technologies. However, most of these solutions rely on the complete server system. For example, the remediation logic typically requires the use of firmware such as the BIOS (Basic Input / Output System) and BMC (Baseboard Management Controller) within the server system. Since different servers have different firmware interfaces, command sets, and implementation methods, adaptation to the underlying interfaces of different server models is necessary. Because server systems have diverse hardware and firmware sources and inconsistent interface standards, extensive customization is required for each server adaptation. This not only results in poor universality of the remediation solutions but also significantly increases deployment and maintenance costs. Summary of the Invention

[0004] Therefore, the purpose of this application is to provide a method for resetting a computing card, a computing card, and a server, so as to improve the problem of insufficient universality caused by the reliance on server systems in existing PCIe link anomaly repair solutions.

[0005] The embodiments of this application are implemented as follows: In a first aspect, embodiments of this application provide a method for resetting a computing card. The computing card includes a first chip, a second chip, and a switching chip. A first downlink port of the switching chip is connected to the first chip, and a second downlink port of the switching chip is connected to each of the second chips. The management bus interface of the switching chip is only connected to the first chip, and the first chip and each of the second chips are directly connected. The method includes: when the PCIe link of the second chip is abnormal, sending a reset request indicating that its own PCIe link is abnormal to the first chip; when the first chip receives the reset request, controlling the second downlink port of the switching chip to perform a reset operation on the second chip through the management bus interface; and when the PCIe link of the first chip is abnormal, controlling the first downlink port of the switching chip to perform a reset operation on the first chip through the management bus interface.

[0006] In the above implementation scheme, the computing card with the aforementioned structure allows for a physical connection between the management module in the first chip and its upstream bridge or port device. Therefore, when the PCIe link of the first chip malfunctions, the first chip can directly access and control the first downlink port of the switching chip via the management bus interface, thereby performing a reset operation on itself. However, due to limitations in the internal resource allocation of the computing card (e.g., the management bus interface of the switching chip is only connected to the first chip), there is no direct physical connection between the management module in the second chip and its upstream bridge or port device. However, through the collaborative cooperation between the first and second chips, a reset operation on the second chip can still be completed. This provides a reset method that does not rely on a complete server system and does not require customized adaptation for different servers. It enables the PCIe device to autonomously complete a fast and accurate reset of the malfunctioning PCIe link, improving the poor versatility of existing PCIe link anomaly repair solutions. Furthermore, since the computing card connects to at least two chips via the switching chip, it can be connected to the server system through a single PCIe slot. This allows for the accommodation of more chips within the same server space, effectively improving overall computing performance to meet the increasing demands of AI computing power.

[0007] In one possible implementation of the first aspect embodiment, the method further includes: after sending a reset request, the second chip re-detects its own PCIe link; if the PCIe link is abnormal, it sends a reset request to the first chip again, until the PCIe link of the second chip returns to normal or the number of reset requests sent reaches a first preset number.

[0008] In the above implementation scheme, the PCIe link status of the second chip is repeatedly checked. If it is still abnormal, a reset request is repeatedly sent to the first chip until the PCIe link of the second chip returns to normal or the number of reset requests sent reaches a first preset number, in order to restore the PCIe link status to normal as much as possible. At the same time, to avoid getting stuck in an infinite loop, a first preset number is set as an upper limit; when the number of reset requests exceeds this preset number, the current process exits directly.

[0009] In one possible implementation of the first aspect embodiment, the first chip and the second chip are directly connected via GPIO pins, and sending a reset request to the first chip includes: sending a reset request to the first chip by pulling up the GPIO pin.

[0010] In the above implementation scheme, the first chip and the second chip are connected through GPIO pins. When a reset request needs to be sent, the reset request can be sent to the first chip simply by pulling the GPIO pin high. This not only realizes the fast and reliable transmission of reset requests between chips, but also makes the hardware implementation simple and inexpensive.

[0011] In one possible implementation of the first aspect embodiment, the first chip and the second chip are directly connected only through a GPIO pin, and the GPIO pin on the second chip side is configured as an output and the GPIO pin on the first chip side is configured as an input; after sending a reset request to the first chip by pulling the GPIO pin high, the method further includes: if the pull-high duration of the GPIO pin is greater than a preset duration, automatically pulling the GPIO pin low.

[0012] In the above implementation scheme, if the first chip and the second chip are directly connected via only one GPIO pin, the GPIO pin on the first chip side only needs to be configured as input mode and the GPIO pin on the second chip side as output mode. When the second chip sends a reset request, it pulls the GPIO pin high and maintains it for a preset duration to ensure that the first chip can detect the reset request as much as possible; if the high duration of the GPIO pin is longer than the preset duration, it automatically pulls the GPIO pin low so that it can send a reset request to the first chip again by pulling the GPIO pin high next time.

[0013] In one possible implementation of the first aspect embodiment, the first chip and the second chip are directly connected via a first GPIO pin and a second GPIO pin, wherein the first GPIO pin on the second chip side is configured as an output and the first GPIO pin on the first chip side is configured as an input, the second GPIO pin on the second chip side is configured as an input and the second GPIO pin on the first chip side is configured as an output; after sending a reset request to the first chip by pulling the GPIO pin high, the method further includes: the second chip detecting whether the level state of the second GPIO pin is high; if the level state of the second GPIO pin is high, indicating that a reset request response sent by the first chip has been received, then pulling the first GPIO pin low.

[0014] In the above implementation scheme, if the first chip and the second chip are directly connected via two GPIO pins (first GPIO pin and second GPIO pin), after the first chip completes the reset operation on the second chip, it can send a reset request response to the second chip by pulling the second GPIO pin high. The second chip no longer pulls the first GPIO pin high for a fixed preset time and then immediately pulls it low; instead, it only pulls the first GPIO pin low after detecting that the second GPIO pin is high. By setting a feedback mechanism for the first chip's reset of the second chip, the second chip can accurately know that the reset operation has been completed, avoiding the problem of missing the detection signal due to a fixed delay in pulling the GPIO pin low, thereby improving the reliability and timeliness of the inter-chip collaborative reset.

[0015] In one possible implementation of the first aspect embodiment, the method further includes: if the level state of the second GPIO pin is low, the second chip detects again whether the level state of the second GPIO pin is high, until the level state of the second GPIO pin is detected to be high, or the number of detections reaches a second preset number.

[0016] In the above implementation scheme, if the level state of the second GPIO pin is low, the level state of the second GPIO pin is repeatedly detected until it becomes high or the second preset number of times is reached. This avoids misjudgment caused by the first chip's reset operation not yet being completed, thereby improving the reliability of the collaborative reset. At the same time, by setting the second preset number of times, the maximum number of repeated detections is limited. When the number of detections exceeds the preset number, the current process exits to prevent the second chip from entering an infinite waiting state.

[0017] In one possible implementation of the first aspect embodiment, the method further includes: after completing the reset operation on the first chip, the first chip re-detects its own PCIe link; if the PCIe link is abnormal, the first downlink port of the switching chip is controlled through the management bus interface to repeatedly perform the reset operation on the first chip until the PCIe link of the first chip returns to normal or the number of resets of the first chip is greater than a third preset number.

[0018] In the above implementation scheme, the PCIe link status of the first chip is repeatedly checked. If it is still abnormal, the reset operation of the first chip is repeatedly performed until the PCIe link of the first chip returns to normal or the number of resets of the first chip exceeds a third preset number, so as to restore the PCIe link status to normal as much as possible. At the same time, to avoid getting stuck in an infinite loop, a third preset number is set as an upper limit; when the number of reset requests exceeds this preset number, the current process is directly exited.

[0019] In one possible implementation of the first aspect embodiment, before the second downlink port of the switching chip is controlled to perform a reset operation on the second chip through the management bus interface, the method further includes: determining that the PCIe link of the first chip has returned to normal or that the number of resets of the first chip is greater than a third preset number; wherein, after determining that the PCIe link of the first chip has returned to normal or that the number of resets of the first chip is greater than the third preset number, it is only after detecting whether the reset request has been received.

[0020] In the above implementation scheme, the detection and reset operations of the PCIe link of the first chip can be repeatedly performed continuously until the PCIe link of the first chip returns to normal, or the number of resets exceeds a third preset number, before detecting whether a reset request from the second chip has been received, and then switching to the detection and reset processing of the second chip. In this way, the stability of the first chip's own link can be prioritized, avoiding the impact on its recovery efficiency due to frequent responses to the second chip's requests. At the same time, this sequential strategy is simple in logic and easy to implement, and is especially suitable for scenarios where the first chip is the main controller or where higher reliability requirements are required.

[0021] In one possible implementation of the first aspect embodiment, before controlling the second downlink port of the switching chip to perform a reset operation on the second chip through the management bus interface, the method further includes: when the PCIe link of the first chip is abnormal, controlling the first downlink port of the switching chip to perform a reset operation on the first chip through the management bus interface; after completing a reset operation on the first chip, directly detecting whether the reset request has been received.

[0022] In the above implementation scheme, when the PCIe link of the first chip is abnormal, only one reset operation is performed on the first chip. Then, instead of immediately entering the next cycle of detection or processing of the first chip, the system immediately switches to the detection and processing of the second chip. This allows the processing flow of the second chip to be entered in advance, avoiding the situation where the second chip cannot recover in time due to a long waiting time if the speed reduction or bandwidth drop problem of the first chip is relatively stubborn. This effectively shortens the overall recovery time and improves the system response efficiency.

[0023] In one possible implementation of the first aspect embodiment, before the first chip detects its own PCIe link again, the method further includes: determining that the reset request has not been detected or that the reset operation on the second chip has been completed; wherein, after the reset request has not been detected or the reset operation on the second chip has been completed, the first chip detects its own PCIe link again.

[0024] In the above implementation scheme, the PCIe link of the second chip is repeatedly detected and processed to restore it to normal as much as possible until no reset request is detected or the reset operation of the second chip is completed. Only then is the PCIe link of the first chip detected and processed. This avoids frequent switching between the first chip and the second chip, thereby reducing the overhead of state transition, simplifying the control logic, and improving the execution efficiency of the overall recovery process.

[0025] In one possible implementation of the first aspect embodiment, the method further includes: after completing the reset operation of the second chip, the first chip detects again whether the PCIe link of the second chip is abnormal; if the PCIe link of the second chip is still abnormal, the first chip controls the second downlink port of the switching chip through the management bus interface to perform the reset operation of the second chip again; until the PCIe link of the second chip returns to normal, or the number of resets of the second chip reaches a fourth preset number.

[0026] In the above implementation scheme, the first chip can continuously and repeatedly perform detection and reset operations on the PCIe link of the second chip until the PCIe link of the second chip returns to normal, or until the number of resets exceeds a fourth preset number, before exiting the process. This maximizes the chances of restoring the PCIe link of the second chip to normal operation.

[0027] In one possible implementation of the first aspect embodiment, controlling the second downlink port of the switching chip through the management bus interface to perform a reset operation on the second chip includes: configuring the bridge control register in the second downlink port of the switching chip through the management bus interface to perform a hot reset on the second chip. In the above implementation scheme, a hot reset of the second chip is achieved by configuring the bridge control register in the second downlink port of the switching chip. Specifically, the secondary bus reset bit (default value is 0) in the bridge control register is first written to 1 to generate a hot reset, and then the bit is written to 0 to exit the hot reset. This method only requires a write operation to a single control bit to trigger a hot reset, without power interruption, and the reset range is limited to the target PCIe device itself, without affecting the normal operation of other devices or systems. At the same time, the operation takes very little time (milliseconds), thus achieving rapid recovery of the link state with minimal system overhead. In a possible implementation scheme in conjunction with the first aspect embodiment, controlling the first downlink port of the switching chip to perform a reset operation on the first chip through the management bus interface includes: configuring the bridge control register in the first downlink port of the switching chip through the management bus interface to perform a hot reset on the first chip.

[0028] Secondly, embodiments of this application also provide a computing card, including: a switching chip, a first chip, and at least one second chip; the first chip and each of the second chips are directly connected; a first downlink port of the switching chip is connected to the first chip, a second downlink port of the switching chip is connected to each of the second chips, and a management bus interface of the switching chip is only connected to the first chip; when the PCIe link of the first chip is abnormal, the first chip is used to control the first downlink port of the switching chip to perform a reset operation on the first chip through the management bus interface; when the PCIe link of the second chip is abnormal, the second chip is used to send a reset request indicating its own PCIe link abnormality to the first chip; when the first chip receives the reset request, the first chip is also used to control the second downlink port of the switching chip to perform a reset operation on the second chip through the management bus interface.

[0029] In one possible implementation of the second aspect embodiment, the second chip is further configured to detect its own PCIe link again after sending a reset request; if the PCIe link is abnormal, it sends a reset request to the first chip again until the PCIe link of the second chip returns to normal or the number of reset requests sent reaches a first preset number.

[0030] In one possible implementation of the second aspect embodiment, the first chip and the second chip are directly connected via GPIO pins; specifically, the second chip is used to send a reset request to the first chip by pulling up the GPIO pin.

[0031] In one possible implementation of the second aspect embodiment, the first chip and the second chip are directly connected only through a GPIO pin, and the GPIO pin on the second chip side is configured as an output and the GPIO pin on the first chip side is configured as an input; the second chip is further configured to automatically pull the GPIO pin low if the pull-high duration of the GPIO pin is longer than a preset duration after sending a reset request to the first chip by pulling the GPIO pin high.

[0032] In one possible implementation of the second aspect embodiment, the first chip and the second chip are directly connected via a first GPIO pin and a second GPIO pin, wherein the first GPIO pin on the second chip side is configured as an output and the first GPIO pin on the first chip side is configured as an input, the second GPIO pin on the second chip side is configured as an input and the second GPIO pin on the first chip side is configured as an output; the second chip is further configured to detect whether the level state of the second GPIO pin is high after sending a reset request to the first chip by pulling the GPIO pin high; if the level state of the second GPIO pin is high, indicating that a reset request response sent by the first chip has been received, then the first GPIO pin is pulled low.

[0033] In one possible implementation of the second aspect embodiment, the second chip is further configured to detect whether the level state of the second GPIO pin is high again if the level state of the second GPIO pin is low, until the level state of the second GPIO pin is detected to be high, or the number of detections reaches a second preset number.

[0034] In one possible implementation of the second aspect embodiment, the first chip is further configured to detect its own PCIe link again after completing the reset operation of the first chip; if the PCIe link is abnormal, the first downlink port of the switching chip is controlled through the management bus interface to repeatedly perform the reset operation of the first chip until the PCIe link of the first chip returns to normal or the number of resets of the first chip is greater than a third preset number.

[0035] In a possible implementation of the second aspect embodiment, it is further configured to determine whether the PCIe link of the first chip has returned to normal or whether the number of resets of the first chip is greater than a third preset number before performing a reset operation on the second chip through the second downlink port of the control switching chip via the management bus interface; wherein, after determining that the PCIe link of the first chip has returned to normal or the number of resets of the first chip is greater than the third preset number, it is only after detecting whether the reset request has been received.

[0036] In one possible implementation of the second aspect embodiment, the first chip is further configured to, before performing a reset operation on the second chip by controlling the second downlink port of the switching chip through the management bus interface, perform a reset operation on the first chip once through the first downlink port of the switching chip when the PCIe link of the first chip is abnormal; after completing a reset operation on the first chip, directly detect whether the reset request has been received.

[0037] In one possible implementation of the second aspect embodiment, the first chip is further configured to determine, before re-detecting its own PCIe link, that the reset request or the reset operation of the second chip has not been detected; wherein, after the reset request has not been detected or the reset operation of the second chip has been completed, the first chip re-detects its own PCIe link.

[0038] In one possible implementation of the second aspect embodiment, the first chip is further configured to, after completing the reset operation of the second chip, detect again whether the PCIe link of the second chip is abnormal; if the PCIe link of the second chip is still detected to be abnormal, the first chip controls the second downlink port of the switching chip through the management bus interface to perform the reset operation of the second chip again; until the PCIe link of the second chip returns to normal, or the number of resets of the second chip reaches a fourth preset number.

[0039] Thirdly, embodiments of this application also provide a server, including: a server motherboard and a computing card provided as described in the second aspect embodiments and / or in combination with the second aspect embodiments; the uplink port of the switching chip in the computing card is connected to the PCIe slot of the server motherboard.

[0040] The technical effects of any of the implementation methods in the second to third aspects can be referred to the technical effects of the same or similar implementation methods in the first aspect, and will not be repeated here.

[0041] Other features and advantages of this application will be set forth in the following description. The objectives and other advantages of this application can be realized and obtained through the structures particularly pointed out in the written description and the accompanying drawings. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. The above and other objects, features, and advantages of this application will become clearer through the accompanying drawings.

[0043] Figure 1 A schematic diagram of the structure of a computing card provided in an embodiment of this application is shown.

[0044] Figure 2 This illustration shows a schematic diagram of a computing card containing dual GPU chips, as provided in an embodiment of this application.

[0045] Figure 3a It shows Figure 2 The diagram shows the SMBus topology of the computing card.

[0046] Figure 3b It shows Figure 3a Another connection diagram of GPU0 and GPU1 in the diagram.

[0047] Figure 4 A schematic diagram of the first reset process provided in the embodiments of this application is shown.

[0048] Figure 5 A schematic diagram of a second reset process provided in an embodiment of this application is shown.

[0049] Figure 6 A schematic diagram of a third reset process provided in an embodiment of this application is shown.

[0050] Figure 7 The diagram shows a timing sequence of the GPU0 reset time point in Scheme 1 provided in this application embodiment.

[0051] Figure 8 A flowchart illustrating a method for resetting a computing card according to an embodiment of this application is shown. Detailed Implementation

[0052] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The following embodiments are provided as examples to more clearly illustrate the technical solutions of this application, and should not be used to limit the scope of protection of this application. Those skilled in the art will understand that, without conflict, the following embodiments and features can be combined with each other.

[0053] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0054] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0055] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical term "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0056] Most current PCIe link anomaly repair solutions rely on complete server systems, leading to the need for customized adaptations for different server models (i.e., poor universality). This application provides a reset method that does not rely on a complete server system and does not require customized adaptations for different servers. It can rely on PCIe devices to autonomously complete the fast and accurate reset of abnormal PCIe links. The PCIe devices in this application include, but are not limited to, GPUs, AI chips, and other accelerator cards. In the following examples, GPUs will be used as the primary example.

[0057] To meet the increasing demand for AI computing power, this application provides a multi-chip computing card, which includes a first chip, a switching chip, and at least one second chip, such as... Figure 1 As shown. The first downlink port of the switching chip (e.g. Figure 1 Port 1 in the middle is connected to the first chip and the second downlink port of the switching chip (such as...) Figure 1Port 2) in the diagram connects to each second chip. It can be understood that a switching chip can have multiple second downlink ports, with one second downlink port connected to one second chip. In an SMBus (System Management Bus) topology, the switching chip acts as a slave device, and its management bus interface connects only to the chip acting as the master device (i.e., the first chip). The uplink port of the switching chip (e.g., port 2) connects to each second chip. Figure 1 Port 0 in the configuration is used to connect to the PCIe slot on the server motherboard, through which the computing card is connected to the server system.

[0058] Furthermore, the first chip and each of the second chips are directly connected, and each of the second chips can be connected via... Figure 1 The solid line in the middle sends a reset request to the first chip. In some optional implementations, the first chip can also send a reset request via... Figure 1 The dashed line in the middle sends a reset request response to each second chip. Figure 1 The dashed lines in the diagram represent optional lines (in some scenarios, optional lines shown by dashed lines may not be available), meaning that sending a reset request response from the first chip to the second chip is optional.

[0059] The first chip and each second chip can be directly connected via GPIO (General Purpose Input / Output) pins, or they can be directly connected in other ways. For example, the first chip and each second chip can communicate directly via serial communication interfaces such as I²C (Inter-Integrated Circuit), UART (Universal Asynchronous Receiver / Transmitter), or SPI (Serial Peripheral Interface).

[0060] The switching chip in this application can be a switch chip. In some scenarios, the switching chip can also be a customized programmable logic device (PLD). By programming the programmable logic device, the effect of a switch chip or a simulated switch function can be achieved.

[0061] In some implementations, the first chip and the second chip can be different types of chips to adapt to diverse application requirements; in other implementations, the first chip and the second chip can be the same type of chip, such as both being GPUs.

[0062] In one possible implementation, the computing card can be a product containing dual GPU chips; in the following examples, GPU0 will represent the first chip and GPU1 will represent the second chip, such as... Figure 2 As shown. Figure 2 The computing card shown is a single-slot dual-GPU card. This card connects to the server system via a single PCIe slot, allowing for a greater number of GPUs to be accommodated within the same server space. Understandably, in some scenarios... Figure 2 The number of GPU1s in the system can be greater than one.

[0063] The "PCIe 4.0 x16" designation indicates that the link supports PCIe Gen4 (fourth generation) speeds and has 16 lanes of bandwidth. Specifically, PCIe 4.0 refers to the fourth generation PCIe interface standard, with a single lane speed of 16 GT / s (gigabits per second); x16 indicates that the link consists of 16 physical lanes.

[0064] To ensure dual GPUs can operate independently at full speed, the two identical GPU chips are connected via a Switch chip. Specifically, the Switch chip's upstream port connects to the host CPU via an x16 link, occupying one Root Port; the Switch chip's downstream port provides two x16 ports, each connecting to one GPU. Thus, the compute card only requires one PCIe slot and one Root Port, while each GPU still receives full-speed PCIe Gen4 x16 bandwidth. It's important to note that the Switch chip itself does not increase bandwidth. When the upstream port is only an x16 link, even with both GPUs operating at full capacity simultaneously, the total bandwidth is still limited to approximately 32 GB / s (corresponding to the theoretical bandwidth of PCIe Gen4 x16). However, because the peak burst bandwidth and independent address space of each GPU are preserved, the overall computing power of the compute card can still be doubled.

[0065] It is understandable that the aforementioned computing card may also include other peripheral chips or modules, such as temperature sensors for detecting temperature, and power management integrated circuits (PMICs) for detecting power consumption and other data. Temperature sensors and PMICs are used in... Figure 2 Not shown in the image.

[0066] Figure 3a It shows Figure 2The diagram shows the SMBus topology of the compute card. In this topology, both GPUs act as slave devices, accessible to the host (e.g., CPU). Simultaneously, the slave pins of various modules (e.g., temperature sensors, power management chips) independently configured for each GPU on the compute card are connected to the corresponding master pins of the GPU, enabling each GPU to actively read data from these modules and obtain information such as temperature and power consumption. However, the compute card has only one switch chip, which can only be accessed as a slave device by one of the GPUs.

[0067] The two GPU chips are not hierarchically designated as primary or secondary. For ease of distinction, the GPU connected to the Switch chip's SMBus interface is designated GPU0, and the other is designated GPU1. Each GPU's GPIO1 pin ( Figure 3a IO1 (short for GPIO1) is initialized to a pull-up or pull-down input state via an external power supply to distinguish between GPU0 and GPU1. Specifically, if the GPIO1 pin is in a pull-down state (or pulled low or set low, at which point the GPIO1 pin level is low), the corresponding GPU is GPU0, and its GPIO0 pin is set to input mode; if the GPIO1 pin is in a pull-up state (or pulled high or set high, at which point the GPIO1 pin level is high), the corresponding GPU is GPU1, and its GPIO0 pin is set to output mode.

[0068] The GPU's integrated management module (such as the SCPU (System Control Processing Unit) or MCU (Micro-Controller Unit)) can distinguish itself as GPU0 or GPU1 based on the GPIO1 input value after power-on. Furthermore, the management module can also distinguish itself as GPU0 or GPU1 based on the GPU ID after power-on.

[0069] Figure 3a This shows that GPU0 and GPU1 are connected via only one GPIO pin ( Figure 3a In the case of a direct connection (where IO0 is short for GPIO0), in one possible implementation, GPU0 and GPU1 can also be directly connected via more GPIO pins, for example, such as... Figure 3b As shown, GPU0 and GPU1 are connected via the first GPIO pin ( Figure 3b IO0 in the middle), the second GPIO pin ( Figure 3b(IO2 in this context is short for GPIO2) Direct connection. The first GPIO pin on the GPU1 side is configured as output, the first GPIO pin on the GPU0 side is configured as input, the second GPIO pin on the GPU1 side is configured as input, and the second GPIO pin on the GPU0 side is configured as output.

[0070] It is understandable that GPU0 and GPU1 can communicate directly in various ways besides through GPIO pins, such as through various serial communication interfaces, like I²C, UART, SPI, etc.

[0071] In the above architecture, due to the limitations of resource allocation within the computing card (for example, the SMBus interface of the Switch chip can only be directly accessed by GPU0), when a PCIe link failure occurs on GPU1, although it cannot directly control the Switch chip to perform a reset operation, it can complete the reset through the collaborative mechanism between the two GPUs.

[0072] After introducing the architecture of the computing card shown in this application, the reset process of the computing card will be explained below.

[0073] When the PCIe link of the first chip malfunctions, the first chip controls the first downlink port of the switching chip to perform a reset operation on the first chip via the management bus interface. The reset operation shown in this application can be a hot reset. For example, the first chip configures the bridge control register in the first downlink port of the switching chip through the management bus interface to perform a hot reset on the first chip. Specifically, the first chip can be hot reset by configuring the Secondary BusReset bit in the bridge control register. First, the Secondary BusReset bit is written to 1 (the default value is 0) to generate a hot reset, and then the Secondary BusReset bit is written to 0 to exit the hot reset.

[0074] When the PCIe link of the second chip malfunctions, the second chip sends a reset request indicating its own PCIe link malfunction to the first chip. Upon receiving the reset request, the first chip also controls the second downlink port of the switch chip to perform a reset operation on the second chip via the management bus interface. For example, the first chip configures the bridge control register in the second downlink port of the switch chip via the management bus interface to perform a hot reset on the second chip, a process similar to performing a hot reset on the first chip.

[0075] Specifically, if the current bandwidth of the PCIe link is lower than the expected bandwidth and / or the current rate of the PCIe link is lower than the expected rate, the PCIe link is considered abnormal. If the current bandwidth of the PCIe link is the expected bandwidth and the current rate of the PCIe link is the expected rate, the PCIe link is normal or meets expectations.

[0076] In some possible implementations, the second chip is also used to re-check its own PCIe link after sending a reset request; if the PCIe link is abnormal, it sends a reset request to the first chip again, until the second chip's PCIe link returns to normal or the number of reset requests sent reaches a first preset number (configurable, such as 3 times). This can maximize the recovery of the second chip's PCIe link. In this implementation, the second chip can also be used to count the number of reset requests sent. Before each reset request is sent, it first determines whether the number of reset requests sent is greater than the first preset number. If not, a reset request is sent to the first chip; otherwise, no reset request is sent to the first chip, thus avoiding an infinite loop.

[0077] In some possible implementations, when the first chip and the second chip are directly connected via GPIO pins, the second chip is specifically used to send a reset request to the first chip by pulling the GPIO pin high. It is understood that if the first chip and the second chip are directly connected via other means (such as UART, SPI, etc.), the second chip can send a reset request to the first chip by sending messages or data packets through the corresponding communication protocol.

[0078] If the first chip and the second chip are directly connected through only one GPIO pin, and the GPIO pin on the second chip side is configured as an output and the GPIO pin on the first chip side is configured as an input, then the second chip is also used to automatically pull the GPIO pin low after sending a reset request to the first chip by pulling the GPIO pin high, if the pull-high duration of the GPIO pin is greater than a preset duration (configurable, such as 20ms).

[0079] If the first chip and the second chip are directly connected via a first GPIO pin and a second GPIO pin, and the first GPIO pin on the second chip side is configured as an output and the first GPIO pin on the first chip side is configured as an input, and the second GPIO pin on the second chip side is configured as an input and the second GPIO pin on the first chip side is configured as an output, then the second chip is further configured to, after sending a reset request to the first chip by pulling the GPIO pin high, detect whether the level of the second GPIO pin is high (i.e., detect whether the level of the second GPIO pin is high); if the level of the second GPIO pin is high, indicating that a reset request response sent by the first chip has been received, then pull the first GPIO pin low. If the level of the second GPIO pin is low, detect whether the level of the second GPIO pin is high again, until the level of the second GPIO pin is detected to be high, or the number of detections reaches a second preset number (configurable, such as 60 times). In this implementation, the second chip can also be used to count the number of detections. Before detecting whether the level of the second GPIO pin is high again, it first determines whether the number of detections is greater than a second preset number. If not, detection is performed; otherwise, detection is stopped.

[0080] In some implementation scenarios, a fixed time interval (such as 0.5ms) can be set between two consecutive detections.

[0081] In some possible implementations, after completing the reset operation on the first chip, the first chip can also re-detect its PCIe link. If the PCIe link is abnormal, the first downlink port of the switching chip is controlled through the management bus interface to repeatedly execute the reset operation on the first chip until the PCIe link of the first chip returns to normal or the number of resets of the first chip exceeds a third preset number (configurable, such as 3 times). By repeatedly detecting and resetting, the PCIe link can be restored to normal as much as possible. At the same time, a maximum number of resets is set to avoid infinite loops. In this implementation, the first chip can also be used to count the number of resets of the first chip. Before each reset operation on the first chip, it is first determined whether the number of resets of the first chip exceeds the third preset number. If not, the reset operation on the first chip is executed; otherwise, the reset operation on the first chip is not executed.

[0082] In one possible implementation, the PCIe link detection and reset operation of the first chip can be repeatedly performed continuously without intervening in the processing of the second chip by the first chip. That is, before controlling the second downlink port of the switching chip to perform a reset operation on the second chip via the management bus interface, one of the following conditions must be met: the PCIe link of the first chip has returned to normal, or the number of resets of the first chip is greater than a third preset number. In this implementation, the detection of whether a reset request has been received is only performed after it is determined that the PCIe link of the first chip has returned to normal or the number of resets of the first chip is greater than the third preset number.

[0083] In some other possible implementations, the processing of the second chip by the first chip can be interspersed during the PCIe link detection and reset operation of the first chip. For example, before the reset operation of the second chip is performed on the second downlink port of the switch chip via the management bus interface, a reset operation of the first chip can be performed on the first downlink port of the switch chip via the management bus interface when the PCIe link of the first chip is abnormal. After completing the reset operation of the first chip, it is directly checked whether a reset request has been received, instead of continuing to detect the PCIe link of the first chip. If a reset request is detected, the second chip is reset.

[0084] For example, after completing a reset operation on the first chip, the system directly switches to the detection and processing of the second chip. The detection and processing of the second chip can be performed only once; after completing the reset process for the second chip, the PCIe link detection and reset operation for the first chip are performed again.

[0085] The detection and processing of the second chip can be repeated multiple times (the detection and processing of the first chip can be interspersed between these processes). For example, after the first chip completes a link detection and reset operation on the second chip, it performs a PCIe link detection and reset operation on the first chip again; then, it performs the PCIe link detection and reset operation on the second chip again. In this implementation, the link detection and reset operations of the first chip and the link detection and reset operations of the second chip are performed alternately. The detection and reset timing in this implementation can be: GPU0→GPU1→GPU0→GPU1…

[0086] In some other implementations, the detection and processing of the second chip can be repeated multiple times (without interleaving the detection and processing of the first chip). For example, after the first chip completes a link detection and reset operation on the second chip, it performs the PCIe link detection and reset operation on the second chip again until the PCIe link of the second chip returns to normal, or the reset operation on the second chip is completed. Then, the PCIe link detection and reset operation on the first chip is performed again. In other words, before the first chip detects its own PCIe link again, one of the following conditions must be met: no reset request is detected (indicating that the PCIe link of the second chip is normal) or the reset operation on the second chip is completed. In this implementation, the first chip only detects its own PCIe link again after no reset request is detected or the reset operation on the second chip is completed.

[0087] In one possible approach, resetting the second chip may involve resetting the second chip a fourth preset number of times (configurable, such as 3 times). In this implementation, after resetting the second chip, the first chip further checks whether the PCIe link of the second chip is abnormal. If the PCIe link is still abnormal, the first chip controls the second downlink port of the switching chip through the management bus interface to perform the reset operation on the second chip again until the PCIe link of the second chip returns to normal, or the number of resets reaches the fourth preset number. The first chip can determine whether the PCIe link of the second chip is abnormal by detecting whether a reset request is received. If a reset request is received, it indicates that the PCIe link of the second chip is abnormal. In this implementation, the first chip can also count the number of resets of the second chip. Before each reset operation on the second chip, it first checks whether the number of resets is greater than the fourth preset number. If not, the reset operation is performed; otherwise, it is not performed.

[0088] It is understandable that the functions of the first chip and the second chip described above can be combined to generate more embodiments. To better understand the reset process described above, several typical embodiments will be used for illustration below.

[0089] Example 1 by Figure 3a Taking the topology shown as an example, in one possible implementation, the reset procedure for the computing card can be as follows: Figure 4As shown. After power-on, the two GPU chips begin initializing their relevant hardware or configurations; and set GPIO1, which distinguishes GPU0 and GPU1, to input mode. The SCPU of the two chips reads the pull-up or pull-down state of GPIO1 to distinguish whether it is GPU0 or GPU1. If the GPIO1 pin is in a pull-up state (high or pulled high), the GPU is GPU0; if the GPIO1 pin is in a pull-down state (low or pulled low), the GPU is GPU1.

[0090] GPU0's perspective: Step 1. Set the maximum number of allowed attempts for GPU0's SCPU (e.g., allow_time = 3, corresponding to the third or fourth preset number of attempts mentioned above) to constrain the maximum number of recovery attempts for each GPU to 3.

[0091] Step 2. Set the current number of attempts for GPU0 to retry_time_0 = 0, and the current number of attempts for GPU1 to retry_time_1 = 0.

[0092] Step 3. The SCPU of GPU0 reads its own PCIe link status register. If the current link speed or width does not meet the expected value, it enters the recovery process of GPU0: The SCPU of GPU0 accesses the configuration space register of the PCIe Switch chip through the I²C interface (one of the management bus interfaces), finds the corresponding upper-level bridge device or port of GPU0, and writes 1 (default value is 0) to the Secondary Bus Reset bit in its configuration space (bridge control register) to generate a hot reset, and then writes 0 to exit the hot reset. After receiving the hot reset, GPU0's Link Training State Machine (LTSSM) enters the Recovery and Hot Reset state, then returns to the Detect state, and restarts the link initialization training. At this time, all state machines, hardware logic, port states, and registers in the configuration space of GPU0 are restored to their default values. The current number of attempts, retry_time_0, of GPU0 is incremented by 1, and then a delay of T1 = 20ms (it takes several milliseconds from the hot reset to the link re-establishment) is set to wait for the GPU0 chip to restore the relevant configuration. Return to step 3 until retry_time_0 exceeds 3 times (i.e., greater than allow_time) or the PCIe link status meets the expected value.

[0093] Step 4. If the link status meets the expected value, delay T0 = 2ms (ensuring a lag behind GPU1 for easy detection of GPU1's reset signal). Then, GPU0's SCPU reads the status of GPIO0. If GPIO0 is high, it indicates that GPU1 has experienced a link status abnormality, and GPU1 enters its recovery process: GPU0's SCPU accesses the PCIe Switch chip's configuration space through the I²C interface, finds the corresponding upper-level bridge device or port of GPU1, writes 1 (default value is 0) to the secondary bus reset bit in its configuration space to generate a hot reset, and then writes 0 to exit the hot reset. Increment GPU1's current number of attempts, retry_time_1, by 1, and delay T1 = 20ms. Return to step 4 until retry_time_1 exceeds 3 times or GPIO0 goes low.

[0094] Step 5. End and exit.

[0095] GPU1's perspective: Step 6. Set the maximum allowed number of attempts for GPU1's SCPU (allow_time = 6, corresponding to the first preset number mentioned above). The purpose is: if the maximum number of recovery attempts per GPU is 3, then considering the worst-case scenario (both GPUs need to perform 3 reset operations), in order to ensure that GPU1 gets 3 valid recovery opportunities, its maximum allowed number of attempts needs to be set to 6.

[0096] Step 7. Set the current number of attempts for GPU1 to retry_time = 0.

[0097] Step 8. The SCPU of GPU1 reads its own PCIe link status register. If the current link speed or width does not meet the expected value, it enters the GPU1 recovery process: The SCPU of GPU1 sets the GPIO0 pin to a high level, then waits for a delay T1 = 20ms to allow the GPU1 chip to recover the relevant configuration, and then sets the GPIO0 pin to a low level. The current number of attempts, retry_time, is incremented by 1. It returns to step 8 until retry_time exceeds 6 times (i.e., greater than allow_time) or the link status meets the expected value.

[0098] Step 9. End and exit.

[0099] Example 2 by Figure 3a Taking the topology shown as an example, in one possible implementation, the reset procedure for the computing card can be as follows: Figure 5 As shown. Due to Figure 5 Implementation principle and Figure 4 The implementation principle is similar. Figure 5 For anything not covered, please refer to [link / reference]. Figure 4 The corresponding content in [the document / document].

[0100] Figure 5 (Hereinafter referred to as Option 2) and Figure 4 The main difference between Scheme 1 and Scheme 2 is that when the SCPU of GPU0 detects an anomaly in the PCIe link of GPU0, it first performs a reset operation on GPU0. Then, instead of immediately entering the next loop of detection or processing for GPU0, it immediately switches to detecting and processing GPU1. After completing all operations on GPU1, it returns to continue detecting and processing GPU0. From a timing perspective, in the worst-case scenario, the reset sequence of Scheme 1 is: GPU0→GPU0→GPU0→GPU1→GPU1→GPU1; while the reset sequence of Scheme 2 is: GPU0→GPU1→GPU1→GPU1→GPU0→GPU0. This allows for earlier processing of GPU1 when the GPU0 slowdown or bandwidth loss problem is persistent. The interleaved processing of GPU0 and GPU1 effectively reduces overall time overhead. Simultaneously, the maximum number of recovery attempts for GPU1 can be reduced to 3, further reducing system risk.

[0101] Scenario 1: In stubborn scenarios where GPU0 is difficult to recover, Scheme 2 can reduce the time overhead and number of retries for GPU1. Example: Assume GPU0 requires 3 recovery cycles, and GPU1 requires 1 recovery cycle.

[0102] Option 1 is adopted: GPU0 actually occupies 4 recovery cycles (of which the 4th cycle is used to process GPU1, but the operation is performed by GPU0); GPU1 also occupies 4 recovery cycles (the first 3 cycles are wasted by waiting in vain). During this period, GPU1 performs a total of 4 recovery operations (including 1 hot reset and 4 configuration recoveries).

[0103] Option 2 is adopted: GPU0 actually occupies 4 recovery cycles; GPU1 only requires 2 recovery cycles, and performs a total of 2 recovery operations (including 1 hot reset and 2 configuration recovery).

[0104] Scenario 2: In stubborn scenarios where both GPU0 and GPU1 are difficult to recover, Solution 2 can also reduce the time overhead and number of retries for GPU1. Example: Assume that GPU0 requires 3 recovery cycles and GPU1 requires 3 recovery cycles.

[0105] Option 1 is adopted: GPU0 actually occupies 6 recovery cycles (the last 3 cycles are used to process GPU1, but the operations are performed by GPU0); GPU1 also occupies 6 recovery cycles (the first 3 cycles are wasted by waiting in vain). During this period, GPU1 performs a total of 6 recovery operations (including 3 hot resets and 6 configuration recoveries).

[0106] Option 2 is adopted: GPU0 actually occupies 6 recovery cycles; GPU1 only requires 4 recovery cycles, and performs a total of 4 recovery operations (including 3 hot resets and 4 configuration recoveries).

[0107] Understandably, in one implementation, the reset timing of Scheme 1 can be modified by alternating the detection and processing of GPU0 with the detection and processing of GPU1. In the worst case, the modified reset sequence of Scheme 1 is as follows: GPU0→GPU1→GPU0→GPU1→GPU0→GPU1.

[0108] Example 3 by Figure 3b Taking the topology shown as an example, in one possible implementation, the reset procedure for the computing card can be as follows: Figure 6 As shown in the diagram (hereinafter referred to as Scheme 3), this scheme (Scheme 3) uses two GPIO pins of the chip as collaborative pins. Compared with Scheme 1, it adds a feedback mechanism for GPU0 to reset GPU1 (for example, after GPU0's SCPU completes the reset of GPU1, it will pull up the GPIO2 pin to send a reset request response to GPU1), thus realizing true collaborative processing. Scheme 1 has limitations: the timing of GPU1 is fixed and it cannot perceive the reset time initiated by GPU0. Therefore, in some special cases, the recovery time after reset may not meet the basic cycle requirement, or even the number of resets may be lost.

[0109] like Figure 7 As shown, under normal circumstances, the time node for GPU0 to issue a reset should be at position 1. However, in Scheme 1, if GPU0 itself also experiences problems such as slowdown, the time node for it to issue a reset may be moved to position 2, resulting in the recovery time interval between the reset and GPU1 being insufficient to meet the basic requirements, thus causing the reset to fail; or the time node may be moved to position 3, causing the detection signal to be missed, resulting in one retry being lost, failing to meet the preset standard of 3 times.

[0110] In this solution, the GPU is guaranteed to meet the recovery time requirements after each reset, ensuring controllable recovery time and security. Furthermore, the number of resets for GPU1 is no longer jointly constrained by GPU0 and GPU1, but solely controlled by GPU1 itself. Additionally, this solution reduces the maximum allowed number of attempts (allow_time) for GPU1, thus decreasing the number of recovery attempts. The recovery operation for GPU1 is consistent with that of GPU0, with each recovery including both a reset operation and a configuration recovery, preventing wasted resources such as configuration recovery without a reset operation and avoiding invalid operations.

[0111] because Figure 6 Implementation principle and Figure 4 as well as Figure 5 The implementation principle is similar. Figure 6 For anything not covered, please refer to [link / reference]. Figure 4 as well as Figure 5 The relevant content in [the document]. The following only addresses [the relevant content]. Figure 6 The actions of GPU1 are explained (from the GPU's perspective): Step 1. Set the maximum allowed number of attempts for GPU1's SCPU to allow_time = 3, which limits the maximum number of recovery attempts for GPU1 to 3 (thus avoiding situations where there is only configuration recovery without reset operation).

[0112] Step 2. Set the current number of attempts for GPU1 to retry_time = 0.

[0113] Step 3. The SCPU of GPU1 reads its own PCIe link status register. If the current link speed or width does not meet the expected value, it enters the GPU1 recovery process: The SCPU of GPU1 sets the GPIO0 pin to a high level, and then starts polling the status of the GPIO2 pin at 0.5ms intervals. If GPIO2 is high, it means that GPU1 has started to reset. At this time, GPIO0 is set to low, and a delay of T1 = 20ms is waited for GPU1 to restore the relevant configuration. If GPIO2 is low, it is determined whether the number of polling (or detection) has reached the second preset number (60 times in this example, about 30ms, to ensure that GPU0 can detect the status of GPIO0). If the polling limit (second preset number) has not been reached, the polling count is incremented by 1 (I++), and the status of GPIO2 continues to be polled at 0.5ms intervals until GPIO2 becomes high or the polling limit is exceeded, and then it exits. After a delay of T1 = 20ms, retry_time is incremented by 1. Return to step 3 until retry_time exceeds 3 times (i.e., greater than allow_time) or the PCIe link status meets the expected value.

[0114] Step 4. End and exit.

[0115] Understandable, Figure 6 In the reset procedure shown, the reset logic of the first chip can also adopt a similar approach. Figure 5 or Figure 4 The reset logic for the first chip can be simplified by adding a "set GPIO2 high" action to the GPU1 reset process, thus enabling more implementations. Similarly, Figure 4 or Figure 5 The reset logic of the first chip can also adopt a similar approach. Figure 6 The reset logic of the first chip can be improved simply by removing the "set GPIO2 high" action from the process of resetting GPU1, thereby generating more embodiments.

[0116] Figures 4 to 6 The embodiments shown are only a part of the many embodiments described in this application. Based on this, those skilled in the art can derive more variations by adding or removing steps, changing the order of steps, or adjusting the start or end points of repeated steps.

[0117] It is understandable that when there are multiple secondary chips (such as GPU1), each secondary chip can have the same function, as described above. Figures 4 to 6 The role of GPU1 in the reset process; similarly, the processing flow of the first chip (GPU0) for each second chip is the same, similar to... Figures 4 to 6 The processing flow of GPU0 to GPU1. The processing timing can have various combinations. It can be that after completing multiple link detection and reset processes of GPU0, the link detection and reset processes of each GPU1 are processed separately. Alternatively, the link detection and reset processes of each GPU can be executed alternately. For example, after completing one link detection and reset process of GPU0, the link detection and reset processes of each GPU1 are processed, and then the process switches back to the link detection and reset processes of GPU0.

[0118] After explaining the roles of the first and second chips in the computing card during the reset process, the following will combine... Figure 8 The method for resetting the computing card provided in the embodiments of this application will be briefly described.

[0119] Step S1: The second chip detects its own PCIe link.

[0120] The second chip can obtain the current PCIe link status. If the current PCIe link bandwidth is lower than the expected bandwidth, and / or the current PCIe link rate is lower than the expected rate, then the PCIe link is considered abnormal.

[0121] Step S2: When the PCIe link of the second chip is abnormal, a reset request is sent to the first chip.

[0122] When the PCIe link of the second chip fails, it sends a reset request indicating that its own PCIe link is faulty to the first chip.

[0123] In some possible implementations, if the first chip and the second chip are directly connected via GPIO pins, the second chip may send a reset request to the first chip by pulling up the GPIO pin.

[0124] Optionally, after the second chip pulls the GPIO pin high, the method may further include pulling the GPIO pin low.

[0125] If the first chip and the second chip are directly connected through only one GPIO pin, and the GPIO pin on the second chip side is configured as an output and the GPIO pin on the first chip side is configured as an input, then after sending a reset request to the first chip by pulling the GPIO pin high, the method may further include: if the pull-high duration of the GPIO pin is greater than a preset duration, automatically pulling the GPIO pin low.

[0126] If the first chip and the second chip are directly connected via a first GPIO pin and a second GPIO pin, and the first GPIO pin on the second chip side is configured as an output and the first GPIO pin on the first chip side is configured as an input, and the second GPIO pin on the second chip side is configured as an input and the second GPIO pin on the first chip side is configured as an output; then after sending a reset request to the first chip by pulling the GPIO pin high, the method may further include: the second chip detecting whether the level state of the second GPIO pin is high; if the level state of the second GPIO pin is high, indicating that a reset request response sent by the first chip has been received, then pulling the first GPIO pin low.

[0127] Optionally, if the level of the second GPIO pin is low, the second chip will detect whether the level of the second GPIO pin is high again, until the level of the second GPIO pin is detected to be high, or the detection count reaches a second preset number, then the detection will stop.

[0128] Step S3: The second downlink port of the first chip control switching chip performs a reset operation on the second chip.

[0129] When the first chip receives a reset request, it controls the second downlink port of the switching chip through the management bus interface to perform a reset operation on the second chip. Optionally, the second chip can be hot-reset by configuring the bridge control register in the second downlink port of the switching chip through the management bus interface.

[0130] The first chip can determine whether it has received a reset request from the second chip by detecting whether the level of the GPIO pin connected to the second chip is high. If the GPIO pin is high, it indicates that the PCIe link of the second chip is abnormal, and then the first chip will perform a reset operation on the second chip.

[0131] Optionally, after the first chip completes the reset operation on the second chip, the method further includes: the first chip sending a reset request response to the second chip to indicate that the reset request sent by the second chip has been received and that the reset operation on the second chip has been performed.

[0132] It is understandable that if the first chip and the second chip are directly connected through two GPIO pins, the first chip can send a reset request response to the second chip by pulling one of the GPIO pins (the second GPIO pin) high.

[0133] Step S4: The first chip detects its own PCIe link.

[0134] Step S5: The first chip controls the first downlink port of the switching chip to perform a reset operation on the first chip.

[0135] When the PCIe link of the second chip malfunctions, the first chip controls the first downlink port of the switching chip to perform a reset operation on the first chip through the management bus interface. Optionally, the bridge control register in the first downlink port of the switching chip can be configured through the management bus interface to perform a hot reset of the first chip.

[0136] Understandably, the PCIe link detection and reset process for the first and second chips can be performed only once, or in some scenarios, it can be repeated multiple times to restore the abnormal PCIe link as much as possible.

[0137] Optionally, the above method further includes: after sending a reset request, the second chip checks its own PCIe link again; if the PCIe link is abnormal, it sends a reset request to the first chip again, until the PCIe link of the second chip returns to normal or the number of reset requests sent reaches a first preset number.

[0138] Optionally, after the first chip completes the reset operation on the second chip, the method further includes: the first chip detecting again whether the PCIe link of the second chip is abnormal; if the PCIe link of the second chip is still detected to be abnormal, the first chip controls the second downlink port of the switching chip through the management bus interface to perform the reset operation on the second chip again; until the PCIe link of the second chip returns to normal, or the number of resets of the second chip reaches a fourth preset number.

[0139] Optionally, the above method may further include: after completing the reset operation of the first chip, the first chip detects its own PCIe link again; if the PCIe link is abnormal, the first downlink port of the switching chip is controlled through the management bus interface to repeatedly perform the reset operation of the first chip until the PCIe link of the first chip returns to normal or the number of resets of the first chip is greater than a third preset number.

[0140] It is understood that the various optional implementation methods described above can exist independently or can be combined in part or in whole to generate more implementation methods. For example, the method by which the second chip re-detects its own PCIe link after sending a reset request can be combined with the method by which the first chip re-detects its own PCIe link; other combinations will not be exemplified.

[0141] Since the first chip can be involved in multiple detection and reset processes of its own PCIe link, it can also be involved in multiple detection and reset processes of the second chip's PCIe link. Therefore, there can be multiple combinations of timing between different transactions.

[0142] In one possible implementation, before controlling the second downlink port of the switching chip to perform a reset operation on the second chip via the management bus interface, the method further includes: determining that the PCIe link of the first chip has returned to normal or that the number of resets of the first chip is greater than a third preset number; wherein, only after determining that the PCIe link of the first chip has returned to normal or that the number of resets of the first chip is greater than the third preset number, is it detected whether a reset request has been received. The processing timing can be referred to the above. Figure 4 .

[0143] In one possible implementation, before controlling the second downlink port of the switching chip to perform a reset operation on the second chip via the management bus interface, the method further includes: when the PCIe link of the first chip is abnormal, controlling the first downlink port of the switching chip to perform a reset operation on the first chip via the management bus interface; after completing the reset operation on the first chip, directly detecting whether a reset request has been received. The processing timing can be referred to the above. Figure 5 .

[0144] Optionally, before the first chip re-detects its own PCIe link, the method further includes: determining that no reset request has been detected or that a reset operation on the second chip has been completed; wherein, after no reset request has been detected or a reset operation on the second chip has been completed, the first chip re-detects its own PCIe link. The processing timing can be referred to the above. Figure 5 .

[0145] The reset method for the computing card provided in this application embodiment has the same implementation principle and technical effect as the aforementioned computing card embodiment. For the sake of brevity, any parts not mentioned in the method embodiment can be referred to the corresponding content in the aforementioned computing card embodiment. This application also provides a server, which includes the aforementioned computing card and a server motherboard, wherein the server motherboard is the core component of the server system and includes a PCIe slot. The computing card is inserted and removed into the PCIe slot via its gold fingers, thereby connecting to the server system and establishing a connection and communication with the CPU on the server motherboard.

[0146] The aforementioned servers include, but are not limited to, general-purpose servers, dedicated servers, cloud servers, edge servers, data center servers, network servers, database servers, and computer equipment, workstations, and mainframes with similar computing and management capabilities. Any computing device capable of deploying the aforementioned computing cards and capable of detecting and repairing PCIe device anomalies during power-on self-test (POST) is suitable for the methods described in this application.

[0147] The server provided in this application embodiment has the same implementation principle and technical effect as the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the server embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0148] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0149] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0150] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A computing card, characterized in that, include: A first chip and at least one second chip; the first chip and each of the second chips are directly connected; A switching chip, wherein a first downlink port of the switching chip is connected to a first chip, a second downlink port of the switching chip is connected to each of the second chips, and the management bus interface of the switching chip is only connected to the first chip; When the PCIe link of the first chip is abnormal, the first chip is used to control the first downlink port of the switching chip to perform a reset operation on the first chip through the management bus interface. When the PCIe link of the second chip is abnormal, the second chip is used to send a reset request indicating that its own PCIe link is abnormal to the first chip. When the first chip receives the reset request, the first chip is also configured to control the second downlink port of the switching chip to perform a reset operation on the second chip through the management bus interface.

2. The computing card according to claim 1, characterized in that, The second chip is also used to re-detect its own PCIe link after sending a reset request; if the PCIe link is abnormal, it sends a reset request to the first chip again until the PCIe link of the second chip returns to normal or the number of reset requests sent reaches a first preset number.

3. The computing card according to claim 1 or 2, characterized in that, The first chip and the second chip are directly connected via GPIO pins; the second chip is specifically used to send a reset request to the first chip by pulling up the GPIO pin.

4. The computing card according to claim 3, characterized in that, The first chip and the second chip are directly connected only through a GPIO pin, and the GPIO pin on the second chip side is configured as an output and the GPIO pin on the first chip side is configured as an input; The second chip is also configured to automatically pull the GPIO pin low if the pull-high duration of the GPIO pin exceeds a preset duration after sending a reset request to the first chip by pulling the GPIO pin high.

5. The computing card according to claim 3, characterized in that, The first chip and the second chip are directly connected through a first GPIO pin and a second GPIO pin, and the first GPIO pin on the second chip side is configured as an output and the first GPIO pin on the first chip side is configured as an input, the second GPIO pin on the second chip side is configured as an input and the second GPIO pin on the first chip side is configured as an output; The second chip is further configured to detect whether the level state of the second GPIO pin is high after sending a reset request to the first chip by pulling the GPIO pin high; if the level state of the second GPIO pin is high, indicating that a reset request response sent by the first chip has been received, then pull the first GPIO pin low.

6. The computing card according to claim 5, characterized in that, The second chip is further configured to detect whether the level of the second GPIO pin is high again if the level of the second GPIO pin is low, until the level of the second GPIO pin is detected to be high, or the number of detections reaches a second preset number.

7. The computing card according to any one of claims 1-6, characterized in that, The first chip is also used to re-detect its own PCIe link after completing the reset operation of the first chip; if the PCIe link is abnormal, the first downlink port of the switching chip is controlled through the management bus interface to repeatedly execute the reset operation of the first chip until the PCIe link of the first chip returns to normal or the number of resets of the first chip is greater than a third preset number.

8. The computing card according to claim 7, characterized in that, The first chip is further configured to determine, before performing a reset operation on the second chip via the second downlink port of the switching chip through the management bus interface, whether the PCIe link of the first chip has returned to normal or the number of resets of the first chip is greater than a third preset number. Specifically, the system detects whether the reset request has been received only after determining that the PCIe link of the first chip has returned to normal or the number of resets of the first chip has exceeded a third preset number.

9. The computing card according to claim 7, characterized in that, The first chip is further configured to, before performing a reset operation on the second chip by controlling the second downlink port of the switching chip through the management bus interface, perform a reset operation on the first chip once through the first downlink port of the switching chip when the PCIe link of the first chip is abnormal, in the event of an abnormality in the first chip's PCIe link. After completing a reset operation on the first chip, directly check whether the reset request has been received.

10. The computing card according to claim 9, characterized in that, The first chip is also configured to determine, before re-detecting its own PCIe link, that no reset request or a reset operation paired with the second chip has been detected; If no reset request is detected or the reset operation on the second chip is completed, the first chip will then check its own PCIe link again.

11. The computing card according to any one of claims 1-10, characterized in that, The first chip is also used to detect whether the PCIe link of the second chip is abnormal after the reset operation of the second chip is completed. If the PCIe link of the second chip is still detected to be abnormal, the first chip controls the second downlink port of the switching chip to perform a reset operation on the second chip again through the management bus interface; Until the PCIe link of the second chip returns to normal, or until the number of resets of the second chip reaches the fourth preset number.

12. A server, characterized in that, include: Server motherboard and computing card as described in any one of claims 1-11; The uplink port of the switching chip in the computing card is connected to the PCIe slot of the server motherboard.

13. A method for resetting a computing card, characterized in that, The computing card includes a first chip, a second chip, and a switching chip. The first downlink port of the switching chip is connected to the first chip, and the second downlink port of the switching chip is connected to each of the second chips. The management bus interface of the switching chip is only connected to the first chip, and the first chip and each of the second chips are directly connected. The method includes: When the PCIe link of the second chip is abnormal, a reset request indicating that its own PCIe link is abnormal is sent to the first chip. When the first chip receives the reset request, it controls the second downlink port of the switching chip to perform a reset operation on the second chip through the management bus interface; When the PCIe link of the first chip fails, the first downlink port of the switching chip is controlled through the management bus interface to perform a reset operation on the first chip.

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